1 #ifndef _ASM_X86_MICROCODE_H
2 #define _ASM_X86_MICROCODE_H
4 #include <linux/earlycpio.h>
6 #define native_rdmsr(msr, val1, val2) \
8 u64 __val = native_read_msr((msr)); \
9 (void)((val1) = (u32)__val); \
10 (void)((val2) = (u32)(__val >> 32)); \
13 #define native_wrmsr(msr, low, high) \
14 native_write_msr(msr, low, high)
16 #define native_wrmsrl(msr, val) \
17 native_write_msr((msr), \
19 (u32)((u64)(val) >> 32))
21 struct cpu_signature
{
29 enum ucode_state
{ UCODE_ERROR
, UCODE_OK
, UCODE_NFOUND
};
30 extern bool dis_ucode_ldr
;
32 struct microcode_ops
{
33 enum ucode_state (*request_microcode_user
) (int cpu
,
34 const void __user
*buf
, size_t size
);
36 enum ucode_state (*request_microcode_fw
) (int cpu
, struct device
*,
39 void (*microcode_fini_cpu
) (int cpu
);
42 * The generic 'microcode_core' part guarantees that
43 * the callbacks below run on a target cpu when they
45 * See also the "Synchronization" section in microcode_core.c.
47 int (*apply_microcode
) (int cpu
);
48 int (*collect_cpu_info
) (int cpu
, struct cpu_signature
*csig
);
51 struct ucode_cpu_info
{
52 struct cpu_signature cpu_sig
;
56 extern struct ucode_cpu_info ucode_cpu_info
[];
58 #ifdef CONFIG_MICROCODE_INTEL
59 extern struct microcode_ops
* __init
init_intel_microcode(void);
61 static inline struct microcode_ops
* __init
init_intel_microcode(void)
65 #endif /* CONFIG_MICROCODE_INTEL */
67 #ifdef CONFIG_MICROCODE_AMD
68 extern struct microcode_ops
* __init
init_amd_microcode(void);
69 extern void __exit
exit_amd_microcode(void);
71 static inline struct microcode_ops
* __init
init_amd_microcode(void)
75 static inline void __exit
exit_amd_microcode(void) {}
78 #ifdef CONFIG_MICROCODE_EARLY
79 #define MAX_UCODE_COUNT 128
81 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
82 #define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
83 #define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
84 #define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
85 #define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
86 #define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
87 #define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
89 #define CPUID_IS(a, b, c, ebx, ecx, edx) \
90 (!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
93 * In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
94 * x86_vendor() gets vendor id for BSP.
96 * In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
97 * coding, we still use x86_vendor() to get vendor id for AP.
99 * x86_vendor() gets vendor information directly from CPUID.
101 static inline int x86_vendor(void)
103 u32 eax
= 0x00000000;
104 u32 ebx
, ecx
= 0, edx
;
106 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
108 if (CPUID_IS(CPUID_INTEL1
, CPUID_INTEL2
, CPUID_INTEL3
, ebx
, ecx
, edx
))
109 return X86_VENDOR_INTEL
;
111 if (CPUID_IS(CPUID_AMD1
, CPUID_AMD2
, CPUID_AMD3
, ebx
, ecx
, edx
))
112 return X86_VENDOR_AMD
;
114 return X86_VENDOR_UNKNOWN
;
117 static inline unsigned int __x86_family(unsigned int sig
)
121 x86
= (sig
>> 8) & 0xf;
124 x86
+= (sig
>> 20) & 0xff;
129 static inline unsigned int x86_family(void)
131 u32 eax
= 0x00000001;
132 u32 ebx
, ecx
= 0, edx
;
134 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
136 return __x86_family(eax
);
139 static inline unsigned int x86_model(unsigned int sig
)
141 unsigned int x86
, model
;
143 x86
= __x86_family(sig
);
145 model
= (sig
>> 4) & 0xf;
147 if (x86
== 0x6 || x86
== 0xf)
148 model
+= ((sig
>> 16) & 0xf) << 4;
153 extern void __init
load_ucode_bsp(void);
154 extern void load_ucode_ap(void);
155 extern int __init
save_microcode_in_initrd(void);
156 void reload_early_microcode(void);
157 extern bool get_builtin_firmware(struct cpio_data
*cd
, const char *name
);
159 static inline void __init
load_ucode_bsp(void) {}
160 static inline void load_ucode_ap(void) {}
161 static inline int __init
save_microcode_in_initrd(void)
165 static inline void reload_early_microcode(void) {}
166 static inline bool get_builtin_firmware(struct cpio_data
*cd
, const char *name
)
171 #endif /* _ASM_X86_MICROCODE_H */