arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/err.h>
  31 #include <linux/irqflags.h>
  32
  33 /*
  34  * We handle most unaligned accesses in hardware.  On the other hand
  35  * unaligned DMA can be quite expensive on some Nehalem processors.
  36  *
  37  * Based on this we disable the IP header alignment in network drivers.
  38  */
  39 #define NET_IP_ALIGN    0
  40
  41 #define HBP_NUM 4
  42 /*
  43  * Default implementation of macro that returns current
  44  * instruction pointer ("program counter").
  45  */
  46 static inline void *current_text_addr(void)
  47 {
  48         void *pc;
  49
  50         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  51
  52         return pc;
  53 }
  54
  55 #ifdef CONFIG_X86_VSMP
  56 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  57 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  58 #else
  59 # define ARCH_MIN_TASKALIGN             16
  60 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  61 #endif
  62
  63 enum tlb_infos {
  64         ENTRIES,
  65         NR_INFO
  66 };
  67
  68 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  69 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  70 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  71 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  72 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  73 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  74 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  75
  76 /*
  77  *  CPU type and hardware bug flags. Kept separately for each CPU.
  78  *  Members of this structure are referenced in head.S, so think twice
  79  *  before touching them. [mj]
  80  */
  81
  82 struct cpuinfo_x86 {
  83         __u8                    x86;            /* CPU family */
  84         __u8                    x86_vendor;     /* CPU vendor */
  85         __u8                    x86_model;
  86         __u8                    x86_mask;
  87 #ifdef CONFIG_X86_32
  88         char                    wp_works_ok;    /* It doesn't on 386's */
  89
  90         /* Problems on some 486Dx4's and old 386's: */
  91         char                    rfu;
  92         char                    pad0;
  93         char                    pad1;
  94 #else
  95         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  96         int                     x86_tlbsize;
  97 #endif
  98         __u8                    x86_virt_bits;
  99         __u8                    x86_phys_bits;
 100         /* CPUID returned core id bits: */
 101         __u8                    x86_coreid_bits;
 102         /* Max extended CPUID function supported: */
 103         __u32                   extended_cpuid_level;
 104         /* Maximum supported CPUID level, -1=no CPUID: */
 105         int                     cpuid_level;
 106         __u32                   x86_capability[NCAPINTS + NBUGINTS];
 107         char                    x86_vendor_id[16];
 108         char                    x86_model_id[64];
 109         /* in KB - valid for CPUS which support this call: */
 110         int                     x86_cache_size;
 111         int                     x86_cache_alignment;    /* In bytes */
 112         int                     x86_power;
 113         unsigned long           loops_per_jiffy;
 114         /* cpuid returned max cores value: */
 115         u16                      x86_max_cores;
 116         u16                     apicid;
 117         u16                     initial_apicid;
 118         u16                     x86_clflush_size;
 119         /* number of cores as seen by the OS: */
 120         u16                     booted_cores;
 121         /* Physical processor id: */
 122         u16                     phys_proc_id;
 123         /* Core id: */
 124         u16                     cpu_core_id;
 125         /* Compute unit id */
 126         u8                      compute_unit_id;
 127         /* Index into per_cpu list: */
 128         u16                     cpu_index;
 129         u32                     microcode;
 130 };
 131
 132 #define X86_VENDOR_INTEL        0
 133 #define X86_VENDOR_CYRIX        1
 134 #define X86_VENDOR_AMD          2
 135 #define X86_VENDOR_UMC          3
 136 #define X86_VENDOR_CENTAUR      5
 137 #define X86_VENDOR_TRANSMETA    7
 138 #define X86_VENDOR_NSC          8
 139 #define X86_VENDOR_NUM          9
 140
 141 #define X86_VENDOR_UNKNOWN      0xff
 142
 143 /*
 144  * capabilities of CPUs
 145  */
 146 extern struct cpuinfo_x86       boot_cpu_data;
 147 extern struct cpuinfo_x86       new_cpu_data;
 148
 149 extern struct tss_struct        doublefault_tss;
 150 extern __u32                    cpu_caps_cleared[NCAPINTS];
 151 extern __u32                    cpu_caps_set[NCAPINTS];
 152
 153 #ifdef CONFIG_SMP
 154 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 155 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 156 #else
 157 #define cpu_info                boot_cpu_data
 158 #define cpu_data(cpu)           boot_cpu_data
 159 #endif
 160
 161 extern const struct seq_operations cpuinfo_op;
 162
 163 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 164
 165 extern void cpu_detect(struct cpuinfo_x86 *c);
 166 extern void fpu_detect(struct cpuinfo_x86 *c);
 167
 168 extern void early_cpu_init(void);
 169 extern void identify_boot_cpu(void);
 170 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 171 extern void print_cpu_info(struct cpuinfo_x86 *);
 172 void print_cpu_msr(struct cpuinfo_x86 *);
 173 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 174 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 175 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 176
 177 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 178 extern void detect_ht(struct cpuinfo_x86 *c);
 179
 180 #ifdef CONFIG_X86_32
 181 extern int have_cpuid_p(void);
 182 #else
 183 static inline int have_cpuid_p(void)
 184 {
 185         return 1;
 186 }
 187 #endif
 188 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 189                                 unsigned int *ecx, unsigned int *edx)
 190 {
 191         /* ecx is often an input as well as an output. */
 192         asm volatile("cpuid"
 193             : "=a" (*eax),
 194               "=b" (*ebx),
 195               "=c" (*ecx),
 196               "=d" (*edx)
 197             : "0" (*eax), "2" (*ecx)
 198             : "memory");
 199 }
 200
 201 static inline void load_cr3(pgd_t *pgdir)
 202 {
 203         write_cr3(__pa(pgdir));
 204 }
 205
 206 #ifdef CONFIG_X86_32
 207 /* This is the TSS defined by the hardware. */
 208 struct x86_hw_tss {
 209         unsigned short          back_link, __blh;
 210         unsigned long           sp0;
 211         unsigned short          ss0, __ss0h;
 212         unsigned long           sp1;
 213         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 214         unsigned short          ss1, __ss1h;
 215         unsigned long           sp2;
 216         unsigned short          ss2, __ss2h;
 217         unsigned long           __cr3;
 218         unsigned long           ip;
 219         unsigned long           flags;
 220         unsigned long           ax;
 221         unsigned long           cx;
 222         unsigned long           dx;
 223         unsigned long           bx;
 224         unsigned long           sp;
 225         unsigned long           bp;
 226         unsigned long           si;
 227         unsigned long           di;
 228         unsigned short          es, __esh;
 229         unsigned short          cs, __csh;
 230         unsigned short          ss, __ssh;
 231         unsigned short          ds, __dsh;
 232         unsigned short          fs, __fsh;
 233         unsigned short          gs, __gsh;
 234         unsigned short          ldt, __ldth;
 235         unsigned short          trace;
 236         unsigned short          io_bitmap_base;
 237
 238 } __attribute__((packed));
 239 #else
 240 struct x86_hw_tss {
 241         u32                     reserved1;
 242         u64                     sp0;
 243         u64                     sp1;
 244         u64                     sp2;
 245         u64                     reserved2;
 246         u64                     ist[7];
 247         u32                     reserved3;
 248         u32                     reserved4;
 249         u16                     reserved5;
 250         u16                     io_bitmap_base;
 251
 252 } __attribute__((packed)) ____cacheline_aligned;
 253 #endif
 254
 255 /*
 256  * IO-bitmap sizes:
 257  */
 258 #define IO_BITMAP_BITS                  65536
 259 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 260 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 261 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 262 #define INVALID_IO_BITMAP_OFFSET        0x8000
 263
 264 struct tss_struct {
 265         /*
 266          * The hardware state:
 267          */
 268         struct x86_hw_tss       x86_tss;
 269
 270         /*
 271          * The extra 1 is there because the CPU will access an
 272          * additional byte beyond the end of the IO permission
 273          * bitmap. The extra byte must be all 1 bits, and must
 274          * be within the limit.
 275          */
 276         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 277
 278         /*
 279          * .. and then another 0x100 bytes for the emergency kernel stack:
 280          */
 281         unsigned long           stack[64];
 282
 283 } ____cacheline_aligned;
 284
 285 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
 286
 287 #ifdef CONFIG_X86_32
 288 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
 289 #endif
 290
 291 /*
 292  * Save the original ist values for checking stack pointers during debugging
 293  */
 294 struct orig_ist {
 295         unsigned long           ist[7];
 296 };
 297
 298 #define MXCSR_DEFAULT           0x1f80
 299
 300 struct i387_fsave_struct {
 301         u32                     cwd;    /* FPU Control Word             */
 302         u32                     swd;    /* FPU Status Word              */
 303         u32                     twd;    /* FPU Tag Word                 */
 304         u32                     fip;    /* FPU IP Offset                */
 305         u32                     fcs;    /* FPU IP Selector              */
 306         u32                     foo;    /* FPU Operand Pointer Offset   */
 307         u32                     fos;    /* FPU Operand Pointer Selector */
 308
 309         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 310         u32                     st_space[20];
 311
 312         /* Software status information [not touched by FSAVE ]:         */
 313         u32                     status;
 314 };
 315
 316 struct i387_fxsave_struct {
 317         u16                     cwd; /* Control Word                    */
 318         u16                     swd; /* Status Word                     */
 319         u16                     twd; /* Tag Word                        */
 320         u16                     fop; /* Last Instruction Opcode         */
 321         union {
 322                 struct {
 323                         u64     rip; /* Instruction Pointer             */
 324                         u64     rdp; /* Data Pointer                    */
 325                 };
 326                 struct {
 327                         u32     fip; /* FPU IP Offset                   */
 328                         u32     fcs; /* FPU IP Selector                 */
 329                         u32     foo; /* FPU Operand Offset              */
 330                         u32     fos; /* FPU Operand Selector            */
 331                 };
 332         };
 333         u32                     mxcsr;          /* MXCSR Register State */
 334         u32                     mxcsr_mask;     /* MXCSR Mask           */
 335
 336         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 337         u32                     st_space[32];
 338
 339         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 340         u32                     xmm_space[64];
 341
 342         u32                     padding[12];
 343
 344         union {
 345                 u32             padding1[12];
 346                 u32             sw_reserved[12];
 347         };
 348
 349 } __attribute__((aligned(16)));
 350
 351 struct i387_soft_struct {
 352         u32                     cwd;
 353         u32                     swd;
 354         u32                     twd;
 355         u32                     fip;
 356         u32                     fcs;
 357         u32                     foo;
 358         u32                     fos;
 359         /* 8*10 bytes for each FP-reg = 80 bytes: */
 360         u32                     st_space[20];
 361         u8                      ftop;
 362         u8                      changed;
 363         u8                      lookahead;
 364         u8                      no_update;
 365         u8                      rm;
 366         u8                      alimit;
 367         struct math_emu_info    *info;
 368         u32                     entry_eip;
 369 };
 370
 371 struct ymmh_struct {
 372         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 373         u32 ymmh_space[64];
 374 };
 375
 376 /* We don't support LWP yet: */
 377 struct lwp_struct {
 378         u8 reserved[128];
 379 };
 380
 381 struct bndreg {
 382         u64 lower_bound;
 383         u64 upper_bound;
 384 } __packed;
 385
 386 struct bndcsr {
 387         u64 bndcfgu;
 388         u64 bndstatus;
 389 } __packed;
 390
 391 struct xsave_hdr_struct {
 392         u64 xstate_bv;
 393         u64 xcomp_bv;
 394         u64 reserved[6];
 395 } __attribute__((packed));
 396
 397 struct xsave_struct {
 398         struct i387_fxsave_struct i387;
 399         struct xsave_hdr_struct xsave_hdr;
 400         struct ymmh_struct ymmh;
 401         struct lwp_struct lwp;
 402         struct bndreg bndreg[4];
 403         struct bndcsr bndcsr;
 404         /* new processor state extensions will go here */
 405 } __attribute__ ((packed, aligned (64)));
 406
 407 union thread_xstate {
 408         struct i387_fsave_struct        fsave;
 409         struct i387_fxsave_struct       fxsave;
 410         struct i387_soft_struct         soft;
 411         struct xsave_struct             xsave;
 412 };
 413
 414 struct fpu {
 415         unsigned int last_cpu;
 416         unsigned int has_fpu;
 417         union thread_xstate *state;
 418 };
 419
 420 #ifdef CONFIG_X86_64
 421 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 422
 423 union irq_stack_union {
 424         char irq_stack[IRQ_STACK_SIZE];
 425         /*
 426          * GCC hardcodes the stack canary as %gs:40.  Since the
 427          * irq_stack is the object at %gs:0, we reserve the bottom
 428          * 48 bytes of the irq stack for the canary.
 429          */
 430         struct {
 431                 char gs_base[40];
 432                 unsigned long stack_canary;
 433         };
 434 };
 435
 436 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
 437 DECLARE_INIT_PER_CPU(irq_stack_union);
 438
 439 DECLARE_PER_CPU(char *, irq_stack_ptr);
 440 DECLARE_PER_CPU(unsigned int, irq_count);
 441 extern asmlinkage void ignore_sysret(void);
 442 #else   /* X86_64 */
 443 #ifdef CONFIG_CC_STACKPROTECTOR
 444 /*
 445  * Make sure stack canary segment base is cached-aligned:
 446  *   "For Intel Atom processors, avoid non zero segment base address
 447  *    that is not aligned to cache line boundary at all cost."
 448  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 449  */
 450 struct stack_canary {
 451         char __pad[20];         /* canary at %gs:20 */
 452         unsigned long canary;
 453 };
 454 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 455 #endif
 456 /*
 457  * per-CPU IRQ handling stacks
 458  */
 459 struct irq_stack {
 460         u32                     stack[THREAD_SIZE/sizeof(u32)];
 461 } __aligned(THREAD_SIZE);
 462
 463 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
 464 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
 465 #endif  /* X86_64 */
 466
 467 extern unsigned int xstate_size;
 468 extern void free_thread_xstate(struct task_struct *);
 469 extern struct kmem_cache *task_xstate_cachep;
 470
 471 struct perf_event;
 472
 473 struct thread_struct {
 474         /* Cached TLS descriptors: */
 475         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 476         unsigned long           sp0;
 477         unsigned long           sp;
 478 #ifdef CONFIG_X86_32
 479         unsigned long           sysenter_cs;
 480 #else
 481         unsigned long           usersp; /* Copy from PDA */
 482         unsigned short          es;
 483         unsigned short          ds;
 484         unsigned short          fsindex;
 485         unsigned short          gsindex;
 486 #endif
 487 #ifdef CONFIG_X86_32
 488         unsigned long           ip;
 489 #endif
 490 #ifdef CONFIG_X86_64
 491         unsigned long           fs;
 492 #endif
 493         unsigned long           gs;
 494         /* Save middle states of ptrace breakpoints */
 495         struct perf_event       *ptrace_bps[HBP_NUM];
 496         /* Debug status used for traps, single steps, etc... */
 497         unsigned long           debugreg6;
 498         /* Keep track of the exact dr7 value set by the user */
 499         unsigned long           ptrace_dr7;
 500         /* Fault info: */
 501         unsigned long           cr2;
 502         unsigned long           trap_nr;
 503         unsigned long           error_code;
 504         /* floating point and extended processor state */
 505         struct fpu              fpu;
 506 #ifdef CONFIG_X86_32
 507         /* Virtual 86 mode info */
 508         struct vm86_struct __user *vm86_info;
 509         unsigned long           screen_bitmap;
 510         unsigned long           v86flags;
 511         unsigned long           v86mask;
 512         unsigned long           saved_sp0;
 513         unsigned int            saved_fs;
 514         unsigned int            saved_gs;
 515 #endif
 516         /* IO permissions: */
 517         unsigned long           *io_bitmap_ptr;
 518         unsigned long           iopl;
 519         /* Max allowed port in the bitmap, in bytes: */
 520         unsigned                io_bitmap_max;
 521         /*
 522          * fpu_counter contains the number of consecutive context switches
 523          * that the FPU is used. If this is over a threshold, the lazy fpu
 524          * saving becomes unlazy to save the trap. This is an unsigned char
 525          * so that after 256 times the counter wraps and the behavior turns
 526          * lazy again; this to deal with bursty apps that only use FPU for
 527          * a short time
 528          */
 529         unsigned char fpu_counter;
 530 };
 531
 532 /*
 533  * Set IOPL bits in EFLAGS from given mask
 534  */
 535 static inline void native_set_iopl_mask(unsigned mask)
 536 {
 537 #ifdef CONFIG_X86_32
 538         unsigned int reg;
 539
 540         asm volatile ("pushfl;"
 541                       "popl %0;"
 542                       "andl %1, %0;"
 543                       "orl %2, %0;"
 544                       "pushl %0;"
 545                       "popfl"
 546                       : "=&r" (reg)
 547                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 548 #endif
 549 }
 550
 551 static inline void
 552 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 553 {
 554         tss->x86_tss.sp0 = thread->sp0;
 555 #ifdef CONFIG_X86_32
 556         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 557         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 558                 tss->x86_tss.ss1 = thread->sysenter_cs;
 559                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 560         }
 561 #endif
 562 }
 563
 564 static inline void native_swapgs(void)
 565 {
 566 #ifdef CONFIG_X86_64
 567         asm volatile("swapgs" ::: "memory");
 568 #endif
 569 }
 570
 571 static inline unsigned long current_top_of_stack(void)
 572 {
 573 #ifdef CONFIG_X86_64
 574         return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
 575 #else
 576         /* sp0 on x86_32 is special in and around vm86 mode. */
 577         return this_cpu_read_stable(cpu_current_top_of_stack);
 578 #endif
 579 }
 580
 581 #ifdef CONFIG_PARAVIRT
 582 #include <asm/paravirt.h>
 583 #else
 584 #define __cpuid                 native_cpuid
 585 #define paravirt_enabled()      0
 586
 587 static inline void load_sp0(struct tss_struct *tss,
 588                             struct thread_struct *thread)
 589 {
 590         native_load_sp0(tss, thread);
 591 }
 592
 593 #define set_iopl_mask native_set_iopl_mask
 594 #endif /* CONFIG_PARAVIRT */
 595
 596 typedef struct {
 597         unsigned long           seg;
 598 } mm_segment_t;
 599
 600
 601 /* Free all resources held by a thread. */
 602 extern void release_thread(struct task_struct *);
 603
 604 unsigned long get_wchan(struct task_struct *p);
 605
 606 /*
 607  * Generic CPUID function
 608  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 609  * resulting in stale register contents being returned.
 610  */
 611 static inline void cpuid(unsigned int op,
 612                          unsigned int *eax, unsigned int *ebx,
 613                          unsigned int *ecx, unsigned int *edx)
 614 {
 615         *eax = op;
 616         *ecx = 0;
 617         __cpuid(eax, ebx, ecx, edx);
 618 }
 619
 620 /* Some CPUID calls want 'count' to be placed in ecx */
 621 static inline void cpuid_count(unsigned int op, int count,
 622                                unsigned int *eax, unsigned int *ebx,
 623                                unsigned int *ecx, unsigned int *edx)
 624 {
 625         *eax = op;
 626         *ecx = count;
 627         __cpuid(eax, ebx, ecx, edx);
 628 }
 629
 630 /*
 631  * CPUID functions returning a single datum
 632  */
 633 static inline unsigned int cpuid_eax(unsigned int op)
 634 {
 635         unsigned int eax, ebx, ecx, edx;
 636
 637         cpuid(op, &eax, &ebx, &ecx, &edx);
 638
 639         return eax;
 640 }
 641
 642 static inline unsigned int cpuid_ebx(unsigned int op)
 643 {
 644         unsigned int eax, ebx, ecx, edx;
 645
 646         cpuid(op, &eax, &ebx, &ecx, &edx);
 647
 648         return ebx;
 649 }
 650
 651 static inline unsigned int cpuid_ecx(unsigned int op)
 652 {
 653         unsigned int eax, ebx, ecx, edx;
 654
 655         cpuid(op, &eax, &ebx, &ecx, &edx);
 656
 657         return ecx;
 658 }
 659
 660 static inline unsigned int cpuid_edx(unsigned int op)
 661 {
 662         unsigned int eax, ebx, ecx, edx;
 663
 664         cpuid(op, &eax, &ebx, &ecx, &edx);
 665
 666         return edx;
 667 }
 668
 669 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 670 static inline void rep_nop(void)
 671 {
 672         asm volatile("rep; nop" ::: "memory");
 673 }
 674
 675 static inline void cpu_relax(void)
 676 {
 677         rep_nop();
 678 }
 679
 680 #define cpu_relax_lowlatency() cpu_relax()
 681
 682 /* Stop speculative execution and prefetching of modified code. */
 683 static inline void sync_core(void)
 684 {
 685         int tmp;
 686
 687 #ifdef CONFIG_M486
 688         /*
 689          * Do a CPUID if available, otherwise do a jump.  The jump
 690          * can conveniently enough be the jump around CPUID.
 691          */
 692         asm volatile("cmpl %2,%1\n\t"
 693                      "jl 1f\n\t"
 694                      "cpuid\n"
 695                      "1:"
 696                      : "=a" (tmp)
 697                      : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
 698                      : "ebx", "ecx", "edx", "memory");
 699 #else
 700         /*
 701          * CPUID is a barrier to speculative execution.
 702          * Prefetched instructions are automatically
 703          * invalidated when modified.
 704          */
 705         asm volatile("cpuid"
 706                      : "=a" (tmp)
 707                      : "0" (1)
 708                      : "ebx", "ecx", "edx", "memory");
 709 #endif
 710 }
 711
 712 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 713 extern void init_amd_e400_c1e_mask(void);
 714
 715 extern unsigned long            boot_option_idle_override;
 716 extern bool                     amd_e400_c1e_detected;
 717
 718 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 719                          IDLE_POLL};
 720
 721 extern void enable_sep_cpu(void);
 722 extern int sysenter_setup(void);
 723
 724 extern void early_trap_init(void);
 725 void early_trap_pf_init(void);
 726
 727 /* Defined in head.S */
 728 extern struct desc_ptr          early_gdt_descr;
 729
 730 extern void cpu_set_gdt(int);
 731 extern void switch_to_new_gdt(int);
 732 extern void load_percpu_segment(int);
 733 extern void cpu_init(void);
 734
 735 static inline unsigned long get_debugctlmsr(void)
 736 {
 737         unsigned long debugctlmsr = 0;
 738
 739 #ifndef CONFIG_X86_DEBUGCTLMSR
 740         if (boot_cpu_data.x86 < 6)
 741                 return 0;
 742 #endif
 743         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 744
 745         return debugctlmsr;
 746 }
 747
 748 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 749 {
 750 #ifndef CONFIG_X86_DEBUGCTLMSR
 751         if (boot_cpu_data.x86 < 6)
 752                 return;
 753 #endif
 754         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 755 }
 756
 757 extern void set_task_blockstep(struct task_struct *task, bool on);
 758
 759 /*
 760  * from system description table in BIOS. Mostly for MCA use, but
 761  * others may find it useful:
 762  */
 763 extern unsigned int             machine_id;
 764 extern unsigned int             machine_submodel_id;
 765 extern unsigned int             BIOS_revision;
 766
 767 /* Boot loader type from the setup header: */
 768 extern int                      bootloader_type;
 769 extern int                      bootloader_version;
 770
 771 extern char                     ignore_fpu_irq;
 772
 773 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 774 #define ARCH_HAS_PREFETCHW
 775 #define ARCH_HAS_SPINLOCK_PREFETCH
 776
 777 #ifdef CONFIG_X86_32
 778 # define BASE_PREFETCH          ""
 779 # define ARCH_HAS_PREFETCH
 780 #else
 781 # define BASE_PREFETCH          "prefetcht0 %P1"
 782 #endif
 783
 784 /*
 785  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 786  *
 787  * It's not worth to care about 3dnow prefetches for the K6
 788  * because they are microcoded there and very slow.
 789  */
 790 static inline void prefetch(const void *x)
 791 {
 792         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
 793                           X86_FEATURE_XMM,
 794                           "m" (*(const char *)x));
 795 }
 796
 797 /*
 798  * 3dnow prefetch to get an exclusive cache line.
 799  * Useful for spinlocks to avoid one state transition in the
 800  * cache coherency protocol:
 801  */
 802 static inline void prefetchw(const void *x)
 803 {
 804         alternative_input(BASE_PREFETCH, "prefetchw %P1",
 805                           X86_FEATURE_3DNOWPREFETCH,
 806                           "m" (*(const char *)x));
 807 }
 808
 809 static inline void spin_lock_prefetch(const void *x)
 810 {
 811         prefetchw(x);
 812 }
 813
 814 #ifdef CONFIG_X86_32
 815 /*
 816  * User space process size: 3GB (default).
 817  */
 818 #define TASK_SIZE               PAGE_OFFSET
 819 #define TASK_SIZE_MAX           TASK_SIZE
 820 #define STACK_TOP               TASK_SIZE
 821 #define STACK_TOP_MAX           STACK_TOP
 822
 823 #define INIT_THREAD  {                                                    \
 824         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 825         .vm86_info              = NULL,                                   \
 826         .sysenter_cs            = __KERNEL_CS,                            \
 827         .io_bitmap_ptr          = NULL,                                   \
 828 }
 829
 830 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 831
 832 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 833 #define KSTK_TOP(info)                                                 \
 834 ({                                                                     \
 835        unsigned long *__ptr = (unsigned long *)(info);                 \
 836        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 837 })
 838
 839 /*
 840  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 841  * This is necessary to guarantee that the entire "struct pt_regs"
 842  * is accessible even if the CPU haven't stored the SS/ESP registers
 843  * on the stack (interrupt gate does not save these registers
 844  * when switching to the same priv ring).
 845  * Therefore beware: accessing the ss/esp fields of the
 846  * "struct pt_regs" is possible, but they may contain the
 847  * completely wrong values.
 848  */
 849 #define task_pt_regs(task)                                             \
 850 ({                                                                     \
 851        struct pt_regs *__regs__;                                       \
 852        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task)) - \
 853                                      TOP_OF_KERNEL_STACK_PADDING);     \
 854        __regs__ - 1;                                                   \
 855 })
 856
 857 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 858
 859 #else
 860 /*
 861  * User space process size. 47bits minus one guard page.  The guard
 862  * page is necessary on Intel CPUs: if a SYSCALL instruction is at
 863  * the highest possible canonical userspace address, then that
 864  * syscall will enter the kernel with a non-canonical return
 865  * address, and SYSRET will explode dangerously.  We avoid this
 866  * particular problem by preventing anything from being mapped
 867  * at the maximum canonical address.
 868  */
 869 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 870
 871 /* This decides where the kernel will search for a free chunk of vm
 872  * space during mmap's.
 873  */
 874 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 875                                         0xc0000000 : 0xFFFFe000)
 876
 877 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 878                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 879 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 880                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 881
 882 #define STACK_TOP               TASK_SIZE
 883 #define STACK_TOP_MAX           TASK_SIZE_MAX
 884
 885 #define INIT_THREAD  { \
 886         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 887 }
 888
 889 /*
 890  * Return saved PC of a blocked thread.
 891  * What is this good for? it will be always the scheduler or ret_from_fork.
 892  */
 893 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 894
 895 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 896 extern unsigned long KSTK_ESP(struct task_struct *task);
 897
 898 /*
 899  * User space RSP while inside the SYSCALL fast path
 900  */
 901 DECLARE_PER_CPU(unsigned long, old_rsp);
 902
 903 #endif /* CONFIG_X86_64 */
 904
 905 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 906                                                unsigned long new_sp);
 907
 908 /*
 909  * This decides where the kernel will search for a free chunk of vm
 910  * space during mmap's.
 911  */
 912 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 913
 914 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 915
 916 /* Get/set a process' ability to use the timestamp counter instruction */
 917 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 918 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 919
 920 extern int get_tsc_mode(unsigned long adr);
 921 extern int set_tsc_mode(unsigned int val);
 922
 923 /* Register/unregister a process' MPX related resource */
 924 #define MPX_ENABLE_MANAGEMENT(tsk)      mpx_enable_management((tsk))
 925 #define MPX_DISABLE_MANAGEMENT(tsk)     mpx_disable_management((tsk))
 926
 927 #ifdef CONFIG_X86_INTEL_MPX
 928 extern int mpx_enable_management(struct task_struct *tsk);
 929 extern int mpx_disable_management(struct task_struct *tsk);
 930 #else
 931 static inline int mpx_enable_management(struct task_struct *tsk)
 932 {
 933         return -EINVAL;
 934 }
 935 static inline int mpx_disable_management(struct task_struct *tsk)
 936 {
 937         return -EINVAL;
 938 }
 939 #endif /* CONFIG_X86_INTEL_MPX */
 940
 941 extern u16 amd_get_nb_id(int cpu);
 942
 943 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 944 {
 945         uint32_t base, eax, signature[3];
 946
 947         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 948                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 949
 950                 if (!memcmp(sig, signature, 12) &&
 951                     (leaves == 0 || ((eax - base) >= leaves)))
 952                         return base;
 953         }
 954
 955         return 0;
 956 }
 957
 958 extern unsigned long arch_align_stack(unsigned long sp);
 959 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 960
 961 void default_idle(void);
 962 #ifdef  CONFIG_XEN
 963 bool xen_set_default_idle(void);
 964 #else
 965 #define xen_set_default_idle 0
 966 #endif
 967
 968 void stop_this_cpu(void *dummy);
 969 void df_debug(struct pt_regs *regs, long error_code);
 970 #endif /* _ASM_X86_PROCESSOR_H */