arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32 #include <linux/irqflags.h>
  33
  34 /*
  35  * We handle most unaligned accesses in hardware.  On the other hand
  36  * unaligned DMA can be quite expensive on some Nehalem processors.
  37  *
  38  * Based on this we disable the IP header alignment in network drivers.
  39  */
  40 #define NET_IP_ALIGN    0
  41
  42 #define HBP_NUM 4
  43 /*
  44  * Default implementation of macro that returns current
  45  * instruction pointer ("program counter").
  46  */
  47 static inline void *current_text_addr(void)
  48 {
  49         void *pc;
  50
  51         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  52
  53         return pc;
  54 }
  55
  56 #ifdef CONFIG_X86_VSMP
  57 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  58 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  59 #else
  60 # define ARCH_MIN_TASKALIGN             16
  61 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  62 #endif
  63
  64 enum tlb_infos {
  65         ENTRIES,
  66         NR_INFO
  67 };
  68
  69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  75 extern s8  __read_mostly tlb_flushall_shift;
  76
  77 /*
  78  *  CPU type and hardware bug flags. Kept separately for each CPU.
  79  *  Members of this structure are referenced in head.S, so think twice
  80  *  before touching them. [mj]
  81  */
  82
  83 struct cpuinfo_x86 {
  84         __u8                    x86;            /* CPU family */
  85         __u8                    x86_vendor;     /* CPU vendor */
  86         __u8                    x86_model;
  87         __u8                    x86_mask;
  88 #ifdef CONFIG_X86_32
  89         char                    wp_works_ok;    /* It doesn't on 386's */
  90
  91         /* Problems on some 486Dx4's and old 386's: */
  92         char                    hlt_works_ok;
  93         char                    hard_math;
  94         char                    rfu;
  95         char                    fdiv_bug;
  96         char                    f00f_bug;
  97         char                    coma_bug;
  98         char                    pad0;
  99 #else
 100         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
 101         int                     x86_tlbsize;
 102 #endif
 103         __u8                    x86_virt_bits;
 104         __u8                    x86_phys_bits;
 105         /* CPUID returned core id bits: */
 106         __u8                    x86_coreid_bits;
 107         /* Max extended CPUID function supported: */
 108         __u32                   extended_cpuid_level;
 109         /* Maximum supported CPUID level, -1=no CPUID: */
 110         int                     cpuid_level;
 111         __u32                   x86_capability[NCAPINTS];
 112         char                    x86_vendor_id[16];
 113         char                    x86_model_id[64];
 114         /* in KB - valid for CPUS which support this call: */
 115         int                     x86_cache_size;
 116         int                     x86_cache_alignment;    /* In bytes */
 117         int                     x86_power;
 118         unsigned long           loops_per_jiffy;
 119         /* cpuid returned max cores value: */
 120         u16                      x86_max_cores;
 121         u16                     apicid;
 122         u16                     initial_apicid;
 123         u16                     x86_clflush_size;
 124         /* number of cores as seen by the OS: */
 125         u16                     booted_cores;
 126         /* Physical processor id: */
 127         u16                     phys_proc_id;
 128         /* Core id: */
 129         u16                     cpu_core_id;
 130         /* Compute unit id */
 131         u8                      compute_unit_id;
 132         /* Index into per_cpu list: */
 133         u16                     cpu_index;
 134         u32                     microcode;
 135 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 136
 137 #define X86_VENDOR_INTEL        0
 138 #define X86_VENDOR_CYRIX        1
 139 #define X86_VENDOR_AMD          2
 140 #define X86_VENDOR_UMC          3
 141 #define X86_VENDOR_CENTAUR      5
 142 #define X86_VENDOR_TRANSMETA    7
 143 #define X86_VENDOR_NSC          8
 144 #define X86_VENDOR_NUM          9
 145
 146 #define X86_VENDOR_UNKNOWN      0xff
 147
 148 /*
 149  * capabilities of CPUs
 150  */
 151 extern struct cpuinfo_x86       boot_cpu_data;
 152 extern struct cpuinfo_x86       new_cpu_data;
 153
 154 extern struct tss_struct        doublefault_tss;
 155 extern __u32                    cpu_caps_cleared[NCAPINTS];
 156 extern __u32                    cpu_caps_set[NCAPINTS];
 157
 158 #ifdef CONFIG_SMP
 159 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 160 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 161 #else
 162 #define cpu_info                boot_cpu_data
 163 #define cpu_data(cpu)           boot_cpu_data
 164 #endif
 165
 166 extern const struct seq_operations cpuinfo_op;
 167
 168 static inline int hlt_works(int cpu)
 169 {
 170 #ifdef CONFIG_X86_32
 171         return cpu_data(cpu).hlt_works_ok;
 172 #else
 173         return 1;
 174 #endif
 175 }
 176
 177 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 178
 179 extern void cpu_detect(struct cpuinfo_x86 *c);
 180
 181 extern struct pt_regs *idle_regs(struct pt_regs *);
 182
 183 extern void early_cpu_init(void);
 184 extern void identify_boot_cpu(void);
 185 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 186 extern void print_cpu_info(struct cpuinfo_x86 *);
 187 void print_cpu_msr(struct cpuinfo_x86 *);
 188 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 189 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 190 extern unsigned short num_cache_leaves;
 191
 192 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 193 extern void detect_ht(struct cpuinfo_x86 *c);
 194
 195 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 196                                 unsigned int *ecx, unsigned int *edx)
 197 {
 198         /* ecx is often an input as well as an output. */
 199         asm volatile("cpuid"
 200             : "=a" (*eax),
 201               "=b" (*ebx),
 202               "=c" (*ecx),
 203               "=d" (*edx)
 204             : "0" (*eax), "2" (*ecx)
 205             : "memory");
 206 }
 207
 208 static inline void load_cr3(pgd_t *pgdir)
 209 {
 210         write_cr3(__pa(pgdir));
 211 }
 212
 213 #ifdef CONFIG_X86_32
 214 /* This is the TSS defined by the hardware. */
 215 struct x86_hw_tss {
 216         unsigned short          back_link, __blh;
 217         unsigned long           sp0;
 218         unsigned short          ss0, __ss0h;
 219         unsigned long           sp1;
 220         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 221         unsigned short          ss1, __ss1h;
 222         unsigned long           sp2;
 223         unsigned short          ss2, __ss2h;
 224         unsigned long           __cr3;
 225         unsigned long           ip;
 226         unsigned long           flags;
 227         unsigned long           ax;
 228         unsigned long           cx;
 229         unsigned long           dx;
 230         unsigned long           bx;
 231         unsigned long           sp;
 232         unsigned long           bp;
 233         unsigned long           si;
 234         unsigned long           di;
 235         unsigned short          es, __esh;
 236         unsigned short          cs, __csh;
 237         unsigned short          ss, __ssh;
 238         unsigned short          ds, __dsh;
 239         unsigned short          fs, __fsh;
 240         unsigned short          gs, __gsh;
 241         unsigned short          ldt, __ldth;
 242         unsigned short          trace;
 243         unsigned short          io_bitmap_base;
 244
 245 } __attribute__((packed));
 246 #else
 247 struct x86_hw_tss {
 248         u32                     reserved1;
 249         u64                     sp0;
 250         u64                     sp1;
 251         u64                     sp2;
 252         u64                     reserved2;
 253         u64                     ist[7];
 254         u32                     reserved3;
 255         u32                     reserved4;
 256         u16                     reserved5;
 257         u16                     io_bitmap_base;
 258
 259 } __attribute__((packed)) ____cacheline_aligned;
 260 #endif
 261
 262 /*
 263  * IO-bitmap sizes:
 264  */
 265 #define IO_BITMAP_BITS                  65536
 266 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 267 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 268 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 269 #define INVALID_IO_BITMAP_OFFSET        0x8000
 270
 271 struct tss_struct {
 272         /*
 273          * The hardware state:
 274          */
 275         struct x86_hw_tss       x86_tss;
 276
 277         /*
 278          * The extra 1 is there because the CPU will access an
 279          * additional byte beyond the end of the IO permission
 280          * bitmap. The extra byte must be all 1 bits, and must
 281          * be within the limit.
 282          */
 283         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 284
 285         /*
 286          * .. and then another 0x100 bytes for the emergency kernel stack:
 287          */
 288         unsigned long           stack[64];
 289
 290 } ____cacheline_aligned;
 291
 292 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 293
 294 /*
 295  * Save the original ist values for checking stack pointers during debugging
 296  */
 297 struct orig_ist {
 298         unsigned long           ist[7];
 299 };
 300
 301 #define MXCSR_DEFAULT           0x1f80
 302
 303 struct i387_fsave_struct {
 304         u32                     cwd;    /* FPU Control Word             */
 305         u32                     swd;    /* FPU Status Word              */
 306         u32                     twd;    /* FPU Tag Word                 */
 307         u32                     fip;    /* FPU IP Offset                */
 308         u32                     fcs;    /* FPU IP Selector              */
 309         u32                     foo;    /* FPU Operand Pointer Offset   */
 310         u32                     fos;    /* FPU Operand Pointer Selector */
 311
 312         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 313         u32                     st_space[20];
 314
 315         /* Software status information [not touched by FSAVE ]:         */
 316         u32                     status;
 317 };
 318
 319 struct i387_fxsave_struct {
 320         u16                     cwd; /* Control Word                    */
 321         u16                     swd; /* Status Word                     */
 322         u16                     twd; /* Tag Word                        */
 323         u16                     fop; /* Last Instruction Opcode         */
 324         union {
 325                 struct {
 326                         u64     rip; /* Instruction Pointer             */
 327                         u64     rdp; /* Data Pointer                    */
 328                 };
 329                 struct {
 330                         u32     fip; /* FPU IP Offset                   */
 331                         u32     fcs; /* FPU IP Selector                 */
 332                         u32     foo; /* FPU Operand Offset              */
 333                         u32     fos; /* FPU Operand Selector            */
 334                 };
 335         };
 336         u32                     mxcsr;          /* MXCSR Register State */
 337         u32                     mxcsr_mask;     /* MXCSR Mask           */
 338
 339         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 340         u32                     st_space[32];
 341
 342         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 343         u32                     xmm_space[64];
 344
 345         u32                     padding[12];
 346
 347         union {
 348                 u32             padding1[12];
 349                 u32             sw_reserved[12];
 350         };
 351
 352 } __attribute__((aligned(16)));
 353
 354 struct i387_soft_struct {
 355         u32                     cwd;
 356         u32                     swd;
 357         u32                     twd;
 358         u32                     fip;
 359         u32                     fcs;
 360         u32                     foo;
 361         u32                     fos;
 362         /* 8*10 bytes for each FP-reg = 80 bytes: */
 363         u32                     st_space[20];
 364         u8                      ftop;
 365         u8                      changed;
 366         u8                      lookahead;
 367         u8                      no_update;
 368         u8                      rm;
 369         u8                      alimit;
 370         struct math_emu_info    *info;
 371         u32                     entry_eip;
 372 };
 373
 374 struct ymmh_struct {
 375         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 376         u32 ymmh_space[64];
 377 };
 378
 379 struct xsave_hdr_struct {
 380         u64 xstate_bv;
 381         u64 reserved1[2];
 382         u64 reserved2[5];
 383 } __attribute__((packed));
 384
 385 struct xsave_struct {
 386         struct i387_fxsave_struct i387;
 387         struct xsave_hdr_struct xsave_hdr;
 388         struct ymmh_struct ymmh;
 389         /* new processor state extensions will go here */
 390 } __attribute__ ((packed, aligned (64)));
 391
 392 union thread_xstate {
 393         struct i387_fsave_struct        fsave;
 394         struct i387_fxsave_struct       fxsave;
 395         struct i387_soft_struct         soft;
 396         struct xsave_struct             xsave;
 397 };
 398
 399 struct fpu {
 400         unsigned int last_cpu;
 401         unsigned int has_fpu;
 402         union thread_xstate *state;
 403 };
 404
 405 #ifdef CONFIG_X86_64
 406 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 407
 408 union irq_stack_union {
 409         char irq_stack[IRQ_STACK_SIZE];
 410         /*
 411          * GCC hardcodes the stack canary as %gs:40.  Since the
 412          * irq_stack is the object at %gs:0, we reserve the bottom
 413          * 48 bytes of the irq stack for the canary.
 414          */
 415         struct {
 416                 char gs_base[40];
 417                 unsigned long stack_canary;
 418         };
 419 };
 420
 421 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 422 DECLARE_INIT_PER_CPU(irq_stack_union);
 423
 424 DECLARE_PER_CPU(char *, irq_stack_ptr);
 425 DECLARE_PER_CPU(unsigned int, irq_count);
 426 extern asmlinkage void ignore_sysret(void);
 427 #else   /* X86_64 */
 428 #ifdef CONFIG_CC_STACKPROTECTOR
 429 /*
 430  * Make sure stack canary segment base is cached-aligned:
 431  *   "For Intel Atom processors, avoid non zero segment base address
 432  *    that is not aligned to cache line boundary at all cost."
 433  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 434  */
 435 struct stack_canary {
 436         char __pad[20];         /* canary at %gs:20 */
 437         unsigned long canary;
 438 };
 439 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 440 #endif
 441 #endif  /* X86_64 */
 442
 443 extern unsigned int xstate_size;
 444 extern void free_thread_xstate(struct task_struct *);
 445 extern struct kmem_cache *task_xstate_cachep;
 446
 447 struct perf_event;
 448
 449 struct thread_struct {
 450         /* Cached TLS descriptors: */
 451         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 452         unsigned long           sp0;
 453         unsigned long           sp;
 454 #ifdef CONFIG_X86_32
 455         unsigned long           sysenter_cs;
 456 #else
 457         unsigned long           usersp; /* Copy from PDA */
 458         unsigned short          es;
 459         unsigned short          ds;
 460         unsigned short          fsindex;
 461         unsigned short          gsindex;
 462 #endif
 463 #ifdef CONFIG_X86_32
 464         unsigned long           ip;
 465 #endif
 466 #ifdef CONFIG_X86_64
 467         unsigned long           fs;
 468 #endif
 469         unsigned long           gs;
 470         /* Save middle states of ptrace breakpoints */
 471         struct perf_event       *ptrace_bps[HBP_NUM];
 472         /* Debug status used for traps, single steps, etc... */
 473         unsigned long           debugreg6;
 474         /* Keep track of the exact dr7 value set by the user */
 475         unsigned long           ptrace_dr7;
 476         /* Fault info: */
 477         unsigned long           cr2;
 478         unsigned long           trap_nr;
 479         unsigned long           error_code;
 480         /* floating point and extended processor state */
 481         struct fpu              fpu;
 482 #ifdef CONFIG_X86_32
 483         /* Virtual 86 mode info */
 484         struct vm86_struct __user *vm86_info;
 485         unsigned long           screen_bitmap;
 486         unsigned long           v86flags;
 487         unsigned long           v86mask;
 488         unsigned long           saved_sp0;
 489         unsigned int            saved_fs;
 490         unsigned int            saved_gs;
 491 #endif
 492         /* IO permissions: */
 493         unsigned long           *io_bitmap_ptr;
 494         unsigned long           iopl;
 495         /* Max allowed port in the bitmap, in bytes: */
 496         unsigned                io_bitmap_max;
 497 };
 498
 499 /*
 500  * Set IOPL bits in EFLAGS from given mask
 501  */
 502 static inline void native_set_iopl_mask(unsigned mask)
 503 {
 504 #ifdef CONFIG_X86_32
 505         unsigned int reg;
 506
 507         asm volatile ("pushfl;"
 508                       "popl %0;"
 509                       "andl %1, %0;"
 510                       "orl %2, %0;"
 511                       "pushl %0;"
 512                       "popfl"
 513                       : "=&r" (reg)
 514                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 515 #endif
 516 }
 517
 518 static inline void
 519 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 520 {
 521         tss->x86_tss.sp0 = thread->sp0;
 522 #ifdef CONFIG_X86_32
 523         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 524         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 525                 tss->x86_tss.ss1 = thread->sysenter_cs;
 526                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 527         }
 528 #endif
 529 }
 530
 531 static inline void native_swapgs(void)
 532 {
 533 #ifdef CONFIG_X86_64
 534         asm volatile("swapgs" ::: "memory");
 535 #endif
 536 }
 537
 538 #ifdef CONFIG_PARAVIRT
 539 #include <asm/paravirt.h>
 540 #else
 541 #define __cpuid                 native_cpuid
 542 #define paravirt_enabled()      0
 543
 544 static inline void load_sp0(struct tss_struct *tss,
 545                             struct thread_struct *thread)
 546 {
 547         native_load_sp0(tss, thread);
 548 }
 549
 550 #define set_iopl_mask native_set_iopl_mask
 551 #endif /* CONFIG_PARAVIRT */
 552
 553 /*
 554  * Save the cr4 feature set we're using (ie
 555  * Pentium 4MB enable and PPro Global page
 556  * enable), so that any CPU's that boot up
 557  * after us can get the correct flags.
 558  */
 559 extern unsigned long mmu_cr4_features;
 560 extern u32 *trampoline_cr4_features;
 561
 562 static inline void set_in_cr4(unsigned long mask)
 563 {
 564         unsigned long cr4;
 565
 566         mmu_cr4_features |= mask;
 567         if (trampoline_cr4_features)
 568                 *trampoline_cr4_features = mmu_cr4_features;
 569         cr4 = read_cr4();
 570         cr4 |= mask;
 571         write_cr4(cr4);
 572 }
 573
 574 static inline void clear_in_cr4(unsigned long mask)
 575 {
 576         unsigned long cr4;
 577
 578         mmu_cr4_features &= ~mask;
 579         if (trampoline_cr4_features)
 580                 *trampoline_cr4_features = mmu_cr4_features;
 581         cr4 = read_cr4();
 582         cr4 &= ~mask;
 583         write_cr4(cr4);
 584 }
 585
 586 typedef struct {
 587         unsigned long           seg;
 588 } mm_segment_t;
 589
 590
 591 /* Free all resources held by a thread. */
 592 extern void release_thread(struct task_struct *);
 593
 594 unsigned long get_wchan(struct task_struct *p);
 595
 596 /*
 597  * Generic CPUID function
 598  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 599  * resulting in stale register contents being returned.
 600  */
 601 static inline void cpuid(unsigned int op,
 602                          unsigned int *eax, unsigned int *ebx,
 603                          unsigned int *ecx, unsigned int *edx)
 604 {
 605         *eax = op;
 606         *ecx = 0;
 607         __cpuid(eax, ebx, ecx, edx);
 608 }
 609
 610 /* Some CPUID calls want 'count' to be placed in ecx */
 611 static inline void cpuid_count(unsigned int op, int count,
 612                                unsigned int *eax, unsigned int *ebx,
 613                                unsigned int *ecx, unsigned int *edx)
 614 {
 615         *eax = op;
 616         *ecx = count;
 617         __cpuid(eax, ebx, ecx, edx);
 618 }
 619
 620 /*
 621  * CPUID functions returning a single datum
 622  */
 623 static inline unsigned int cpuid_eax(unsigned int op)
 624 {
 625         unsigned int eax, ebx, ecx, edx;
 626
 627         cpuid(op, &eax, &ebx, &ecx, &edx);
 628
 629         return eax;
 630 }
 631
 632 static inline unsigned int cpuid_ebx(unsigned int op)
 633 {
 634         unsigned int eax, ebx, ecx, edx;
 635
 636         cpuid(op, &eax, &ebx, &ecx, &edx);
 637
 638         return ebx;
 639 }
 640
 641 static inline unsigned int cpuid_ecx(unsigned int op)
 642 {
 643         unsigned int eax, ebx, ecx, edx;
 644
 645         cpuid(op, &eax, &ebx, &ecx, &edx);
 646
 647         return ecx;
 648 }
 649
 650 static inline unsigned int cpuid_edx(unsigned int op)
 651 {
 652         unsigned int eax, ebx, ecx, edx;
 653
 654         cpuid(op, &eax, &ebx, &ecx, &edx);
 655
 656         return edx;
 657 }
 658
 659 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 660 static inline void rep_nop(void)
 661 {
 662         asm volatile("rep; nop" ::: "memory");
 663 }
 664
 665 static inline void cpu_relax(void)
 666 {
 667         rep_nop();
 668 }
 669
 670 /* Stop speculative execution and prefetching of modified code. */
 671 static inline void sync_core(void)
 672 {
 673         int tmp;
 674
 675 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 676         if (boot_cpu_data.x86 < 5)
 677                 /* There is no speculative execution.
 678                  * jmp is a barrier to prefetching. */
 679                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 680         else
 681 #endif
 682                 /* cpuid is a barrier to speculative execution.
 683                  * Prefetched instructions are automatically
 684                  * invalidated when modified. */
 685                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 686                              : "ebx", "ecx", "edx", "memory");
 687 }
 688
 689 static inline void __monitor(const void *eax, unsigned long ecx,
 690                              unsigned long edx)
 691 {
 692         /* "monitor %eax, %ecx, %edx;" */
 693         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 694                      :: "a" (eax), "c" (ecx), "d"(edx));
 695 }
 696
 697 static inline void __mwait(unsigned long eax, unsigned long ecx)
 698 {
 699         /* "mwait %eax, %ecx;" */
 700         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 701                      :: "a" (eax), "c" (ecx));
 702 }
 703
 704 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 705 {
 706         trace_hardirqs_on();
 707         /* "mwait %eax, %ecx;" */
 708         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 709                      :: "a" (eax), "c" (ecx));
 710 }
 711
 712 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 713 extern void init_amd_e400_c1e_mask(void);
 714
 715 extern unsigned long            boot_option_idle_override;
 716 extern bool                     amd_e400_c1e_detected;
 717
 718 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 719                          IDLE_POLL, IDLE_FORCE_MWAIT};
 720
 721 extern void enable_sep_cpu(void);
 722 extern int sysenter_setup(void);
 723
 724 extern void early_trap_init(void);
 725
 726 /* Defined in head.S */
 727 extern struct desc_ptr          early_gdt_descr;
 728
 729 extern void cpu_set_gdt(int);
 730 extern void switch_to_new_gdt(int);
 731 extern void load_percpu_segment(int);
 732 extern void cpu_init(void);
 733
 734 static inline unsigned long get_debugctlmsr(void)
 735 {
 736         unsigned long debugctlmsr = 0;
 737
 738 #ifndef CONFIG_X86_DEBUGCTLMSR
 739         if (boot_cpu_data.x86 < 6)
 740                 return 0;
 741 #endif
 742         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 743
 744         return debugctlmsr;
 745 }
 746
 747 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 748 {
 749 #ifndef CONFIG_X86_DEBUGCTLMSR
 750         if (boot_cpu_data.x86 < 6)
 751                 return;
 752 #endif
 753         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 754 }
 755
 756 extern void set_task_blockstep(struct task_struct *task, bool on);
 757
 758 /*
 759  * from system description table in BIOS. Mostly for MCA use, but
 760  * others may find it useful:
 761  */
 762 extern unsigned int             machine_id;
 763 extern unsigned int             machine_submodel_id;
 764 extern unsigned int             BIOS_revision;
 765
 766 /* Boot loader type from the setup header: */
 767 extern int                      bootloader_type;
 768 extern int                      bootloader_version;
 769
 770 extern char                     ignore_fpu_irq;
 771
 772 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 773 #define ARCH_HAS_PREFETCHW
 774 #define ARCH_HAS_SPINLOCK_PREFETCH
 775
 776 #ifdef CONFIG_X86_32
 777 # define BASE_PREFETCH          ASM_NOP4
 778 # define ARCH_HAS_PREFETCH
 779 #else
 780 # define BASE_PREFETCH          "prefetcht0 (%1)"
 781 #endif
 782
 783 /*
 784  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 785  *
 786  * It's not worth to care about 3dnow prefetches for the K6
 787  * because they are microcoded there and very slow.
 788  */
 789 static inline void prefetch(const void *x)
 790 {
 791         alternative_input(BASE_PREFETCH,
 792                           "prefetchnta (%1)",
 793                           X86_FEATURE_XMM,
 794                           "r" (x));
 795 }
 796
 797 /*
 798  * 3dnow prefetch to get an exclusive cache line.
 799  * Useful for spinlocks to avoid one state transition in the
 800  * cache coherency protocol:
 801  */
 802 static inline void prefetchw(const void *x)
 803 {
 804         alternative_input(BASE_PREFETCH,
 805                           "prefetchw (%1)",
 806                           X86_FEATURE_3DNOW,
 807                           "r" (x));
 808 }
 809
 810 static inline void spin_lock_prefetch(const void *x)
 811 {
 812         prefetchw(x);
 813 }
 814
 815 #ifdef CONFIG_X86_32
 816 /*
 817  * User space process size: 3GB (default).
 818  */
 819 #define TASK_SIZE               PAGE_OFFSET
 820 #define TASK_SIZE_MAX           TASK_SIZE
 821 #define STACK_TOP               TASK_SIZE
 822 #define STACK_TOP_MAX           STACK_TOP
 823
 824 #define INIT_THREAD  {                                                    \
 825         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 826         .vm86_info              = NULL,                                   \
 827         .sysenter_cs            = __KERNEL_CS,                            \
 828         .io_bitmap_ptr          = NULL,                                   \
 829 }
 830
 831 /*
 832  * Note that the .io_bitmap member must be extra-big. This is because
 833  * the CPU will access an additional byte beyond the end of the IO
 834  * permission bitmap. The extra byte must be all 1 bits, and must
 835  * be within the limit.
 836  */
 837 #define INIT_TSS  {                                                       \
 838         .x86_tss = {                                                      \
 839                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 840                 .ss0            = __KERNEL_DS,                            \
 841                 .ss1            = __KERNEL_CS,                            \
 842                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 843          },                                                               \
 844         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 845 }
 846
 847 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 848
 849 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 850 #define KSTK_TOP(info)                                                 \
 851 ({                                                                     \
 852        unsigned long *__ptr = (unsigned long *)(info);                 \
 853        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 854 })
 855
 856 /*
 857  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 858  * This is necessary to guarantee that the entire "struct pt_regs"
 859  * is accessible even if the CPU haven't stored the SS/ESP registers
 860  * on the stack (interrupt gate does not save these registers
 861  * when switching to the same priv ring).
 862  * Therefore beware: accessing the ss/esp fields of the
 863  * "struct pt_regs" is possible, but they may contain the
 864  * completely wrong values.
 865  */
 866 #define task_pt_regs(task)                                             \
 867 ({                                                                     \
 868        struct pt_regs *__regs__;                                       \
 869        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 870        __regs__ - 1;                                                   \
 871 })
 872
 873 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 874
 875 #else
 876 /*
 877  * User space process size. 47bits minus one guard page.
 878  */
 879 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 880
 881 /* This decides where the kernel will search for a free chunk of vm
 882  * space during mmap's.
 883  */
 884 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 885                                         0xc0000000 : 0xFFFFe000)
 886
 887 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 888                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 889 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 890                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 891
 892 #define STACK_TOP               TASK_SIZE
 893 #define STACK_TOP_MAX           TASK_SIZE_MAX
 894
 895 #define INIT_THREAD  { \
 896         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 897 }
 898
 899 #define INIT_TSS  { \
 900         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 901 }
 902
 903 /*
 904  * Return saved PC of a blocked thread.
 905  * What is this good for? it will be always the scheduler or ret_from_fork.
 906  */
 907 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 908
 909 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 910 extern unsigned long KSTK_ESP(struct task_struct *task);
 911
 912 /*
 913  * User space RSP while inside the SYSCALL fast path
 914  */
 915 DECLARE_PER_CPU(unsigned long, old_rsp);
 916
 917 #endif /* CONFIG_X86_64 */
 918
 919 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 920                                                unsigned long new_sp);
 921
 922 /*
 923  * This decides where the kernel will search for a free chunk of vm
 924  * space during mmap's.
 925  */
 926 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 927
 928 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 929
 930 /* Get/set a process' ability to use the timestamp counter instruction */
 931 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 932 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 933
 934 extern int get_tsc_mode(unsigned long adr);
 935 extern int set_tsc_mode(unsigned int val);
 936
 937 extern int amd_get_nb_id(int cpu);
 938
 939 struct aperfmperf {
 940         u64 aperf, mperf;
 941 };
 942
 943 static inline void get_aperfmperf(struct aperfmperf *am)
 944 {
 945         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 946
 947         rdmsrl(MSR_IA32_APERF, am->aperf);
 948         rdmsrl(MSR_IA32_MPERF, am->mperf);
 949 }
 950
 951 #define APERFMPERF_SHIFT 10
 952
 953 static inline
 954 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 955                                     struct aperfmperf *new)
 956 {
 957         u64 aperf = new->aperf - old->aperf;
 958         u64 mperf = new->mperf - old->mperf;
 959         unsigned long ratio = aperf;
 960
 961         mperf >>= APERFMPERF_SHIFT;
 962         if (mperf)
 963                 ratio = div64_u64(aperf, mperf);
 964
 965         return ratio;
 966 }
 967
 968 /*
 969  * AMD errata checking
 970  */
 971 #ifdef CONFIG_CPU_SUP_AMD
 972 extern const int amd_erratum_383[];
 973 extern const int amd_erratum_400[];
 974 extern bool cpu_has_amd_erratum(const int *);
 975
 976 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
 977 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
 978 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
 979         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
 980 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
 981 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
 982 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
 983
 984 #else
 985 #define cpu_has_amd_erratum(x)  (false)
 986 #endif /* CONFIG_CPU_SUP_AMD */
 987
 988 extern unsigned long arch_align_stack(unsigned long sp);
 989 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 990
 991 void default_idle(void);
 992 bool set_pm_idle_to_default(void);
 993
 994 void stop_this_cpu(void *dummy);
 995
 996 #endif /* _ASM_X86_PROCESSOR_H */