arch/x86/include/asm/tsc.h

   1 /*
   2  * x86 TSC related functions
   3  */
   4 #ifndef _ASM_X86_TSC_H
   5 #define _ASM_X86_TSC_H
   6
   7 #include <asm/processor.h>
   8
   9 #define NS_SCALE        10 /* 2^10, carefully chosen */
  10 #define US_SCALE        32 /* 2^32, arbitralrily chosen */
  11
  12 /*
  13  * Standard way to access the cycle counter.
  14  */
  15 typedef unsigned long long cycles_t;
  16
  17 extern unsigned int cpu_khz;
  18 extern unsigned int tsc_khz;
  19
  20 extern void disable_TSC(void);
  21
  22 static inline cycles_t get_cycles(void)
  23 {
  24         unsigned long long ret = 0;
  25
  26 #ifndef CONFIG_X86_TSC
  27         if (!cpu_has_tsc)
  28                 return 0;
  29 #endif
  30         rdtscll(ret);
  31
  32         return ret;
  33 }
  34
  35 static __always_inline cycles_t vget_cycles(void)
  36 {
  37         cycles_t cycles;
  38
  39         /*
  40          * We only do VDSOs on TSC capable CPUs, so this shouldnt
  41          * access boot_cpu_data (which is not VDSO-safe):
  42          */
  43 #ifndef CONFIG_X86_TSC
  44         if (!cpu_has_tsc)
  45                 return 0;
  46 #endif
  47         rdtsc_barrier();
  48         cycles = (cycles_t)__native_read_tsc();
  49         rdtsc_barrier();
  50
  51         return cycles;
  52 }
  53
  54 extern void tsc_init(void);
  55 extern void mark_tsc_unstable(char *reason);
  56 extern int unsynchronized_tsc(void);
  57 int check_tsc_unstable(void);
  58
  59 /*
  60  * Boot-time check whether the TSCs are synchronized across
  61  * all CPUs/cores:
  62  */
  63 extern void check_tsc_sync_source(int cpu);
  64 extern void check_tsc_sync_target(void);
  65
  66 extern int notsc_setup(char *);
  67
  68 #endif /* _ASM_X86_TSC_H */