projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
x86/amd-iommu: Use check_device for amd_iommu_dma_supported
[deliverable/linux.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
61 struct unity_map_entry *e);
62 static struct dma_ops_domain *find_protection_domain(u16 devid);
63 static u64 *alloc_pte(struct protection_domain *domain,
64 unsigned long address, int end_lvl,
65 u64 **pte_page, gfp_t gfp);
66 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
67 unsigned long start_page,
68 unsigned int pages);
69 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
70 static u64 *fetch_pte(struct protection_domain *domain,
71 unsigned long address, int map_size);
72 static void update_domain(struct protection_domain *domain);
73
74 #ifdef CONFIG_AMD_IOMMU_STATS
75
76 /*
77 * Initialization code for statistics collection
78 */
79
80 DECLARE_STATS_COUNTER(compl_wait);
81 DECLARE_STATS_COUNTER(cnt_map_single);
82 DECLARE_STATS_COUNTER(cnt_unmap_single);
83 DECLARE_STATS_COUNTER(cnt_map_sg);
84 DECLARE_STATS_COUNTER(cnt_unmap_sg);
85 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
86 DECLARE_STATS_COUNTER(cnt_free_coherent);
87 DECLARE_STATS_COUNTER(cross_page);
88 DECLARE_STATS_COUNTER(domain_flush_single);
89 DECLARE_STATS_COUNTER(domain_flush_all);
90 DECLARE_STATS_COUNTER(alloced_io_mem);
91 DECLARE_STATS_COUNTER(total_map_requests);
92
93 static struct dentry *stats_dir;
94 static struct dentry *de_isolate;
95 static struct dentry *de_fflush;
96
97 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
98 {
99 if (stats_dir == NULL)
100 return;
101
102 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
103 &cnt->value);
104 }
105
106 static void amd_iommu_stats_init(void)
107 {
108 stats_dir = debugfs_create_dir("amd-iommu", NULL);
109 if (stats_dir == NULL)
110 return;
111
112 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
113 (u32 *)&amd_iommu_isolate);
114
115 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
116 (u32 *)&amd_iommu_unmap_flush);
117
118 amd_iommu_stats_add(&compl_wait);
119 amd_iommu_stats_add(&cnt_map_single);
120 amd_iommu_stats_add(&cnt_unmap_single);
121 amd_iommu_stats_add(&cnt_map_sg);
122 amd_iommu_stats_add(&cnt_unmap_sg);
123 amd_iommu_stats_add(&cnt_alloc_coherent);
124 amd_iommu_stats_add(&cnt_free_coherent);
125 amd_iommu_stats_add(&cross_page);
126 amd_iommu_stats_add(&domain_flush_single);
127 amd_iommu_stats_add(&domain_flush_all);
128 amd_iommu_stats_add(&alloced_io_mem);
129 amd_iommu_stats_add(&total_map_requests);
130 }
131
132 #endif
133
134 /****************************************************************************
135 *
136 * Interrupt handling functions
137 *
138 ****************************************************************************/
139
140 static void dump_dte_entry(u16 devid)
141 {
142 int i;
143
144 for (i = 0; i < 8; ++i)
145 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
146 amd_iommu_dev_table[devid].data[i]);
147 }
148
149 static void dump_command(unsigned long phys_addr)
150 {
151 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
152 int i;
153
154 for (i = 0; i < 4; ++i)
155 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
156 }
157
158 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
159 {
160 u32 *event = __evt;
161 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
162 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
163 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
164 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
165 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
166
167 printk(KERN_ERR "AMD-Vi: Event logged [");
168
169 switch (type) {
170 case EVENT_TYPE_ILL_DEV:
171 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
172 "address=0x%016llx flags=0x%04x]\n",
173 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
174 address, flags);
175 dump_dte_entry(devid);
176 break;
177 case EVENT_TYPE_IO_FAULT:
178 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
179 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 domid, address, flags);
182 break;
183 case EVENT_TYPE_DEV_TAB_ERR:
184 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 address, flags);
188 break;
189 case EVENT_TYPE_PAGE_TAB_ERR:
190 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
191 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
192 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
193 domid, address, flags);
194 break;
195 case EVENT_TYPE_ILL_CMD:
196 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
197 reset_iommu_command_buffer(iommu);
198 dump_command(address);
199 break;
200 case EVENT_TYPE_CMD_HARD_ERR:
201 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
202 "flags=0x%04x]\n", address, flags);
203 break;
204 case EVENT_TYPE_IOTLB_INV_TO:
205 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
206 "address=0x%016llx]\n",
207 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
208 address);
209 break;
210 case EVENT_TYPE_INV_DEV_REQ:
211 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
212 "address=0x%016llx flags=0x%04x]\n",
213 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
214 address, flags);
215 break;
216 default:
217 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
218 }
219 }
220
221 static void iommu_poll_events(struct amd_iommu *iommu)
222 {
223 u32 head, tail;
224 unsigned long flags;
225
226 spin_lock_irqsave(&iommu->lock, flags);
227
228 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
229 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
230
231 while (head != tail) {
232 iommu_print_event(iommu, iommu->evt_buf + head);
233 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
234 }
235
236 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
237
238 spin_unlock_irqrestore(&iommu->lock, flags);
239 }
240
241 irqreturn_t amd_iommu_int_handler(int irq, void *data)
242 {
243 struct amd_iommu *iommu;
244
245 for_each_iommu(iommu)
246 iommu_poll_events(iommu);
247
248 return IRQ_HANDLED;
249 }
250
251 /****************************************************************************
252 *
253 * IOMMU command queuing functions
254 *
255 ****************************************************************************/
256
257 /*
258 * Writes the command to the IOMMUs command buffer and informs the
259 * hardware about the new command. Must be called with iommu->lock held.
260 */
261 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
262 {
263 u32 tail, head;
264 u8 *target;
265
266 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
267 target = iommu->cmd_buf + tail;
268 memcpy_toio(target, cmd, sizeof(*cmd));
269 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
270 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
271 if (tail == head)
272 return -ENOMEM;
273 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
274
275 return 0;
276 }
277
278 /*
279 * General queuing function for commands. Takes iommu->lock and calls
280 * __iommu_queue_command().
281 */
282 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
283 {
284 unsigned long flags;
285 int ret;
286
287 spin_lock_irqsave(&iommu->lock, flags);
288 ret = __iommu_queue_command(iommu, cmd);
289 if (!ret)
290 iommu->need_sync = true;
291 spin_unlock_irqrestore(&iommu->lock, flags);
292
293 return ret;
294 }
295
296 /*
297 * This function waits until an IOMMU has completed a completion
298 * wait command
299 */
300 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
301 {
302 int ready = 0;
303 unsigned status = 0;
304 unsigned long i = 0;
305
306 INC_STATS_COUNTER(compl_wait);
307
308 while (!ready && (i < EXIT_LOOP_COUNT)) {
309 ++i;
310 /* wait for the bit to become one */
311 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
312 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
313 }
314
315 /* set bit back to zero */
316 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
317 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
318
319 if (unlikely(i == EXIT_LOOP_COUNT)) {
320 spin_unlock(&iommu->lock);
321 reset_iommu_command_buffer(iommu);
322 spin_lock(&iommu->lock);
323 }
324 }
325
326 /*
327 * This function queues a completion wait command into the command
328 * buffer of an IOMMU
329 */
330 static int __iommu_completion_wait(struct amd_iommu *iommu)
331 {
332 struct iommu_cmd cmd;
333
334 memset(&cmd, 0, sizeof(cmd));
335 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
336 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
337
338 return __iommu_queue_command(iommu, &cmd);
339 }
340
341 /*
342 * This function is called whenever we need to ensure that the IOMMU has
343 * completed execution of all commands we sent. It sends a
344 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
345 * us about that by writing a value to a physical address we pass with
346 * the command.
347 */
348 static int iommu_completion_wait(struct amd_iommu *iommu)
349 {
350 int ret = 0;
351 unsigned long flags;
352
353 spin_lock_irqsave(&iommu->lock, flags);
354
355 if (!iommu->need_sync)
356 goto out;
357
358 ret = __iommu_completion_wait(iommu);
359
360 iommu->need_sync = false;
361
362 if (ret)
363 goto out;
364
365 __iommu_wait_for_completion(iommu);
366
367 out:
368 spin_unlock_irqrestore(&iommu->lock, flags);
369
370 return 0;
371 }
372
373 static void iommu_flush_complete(struct protection_domain *domain)
374 {
375 int i;
376
377 for (i = 0; i < amd_iommus_present; ++i) {
378 if (!domain->dev_iommu[i])
379 continue;
380
381 /*
382 * Devices of this domain are behind this IOMMU
383 * We need to wait for completion of all commands.
384 */
385 iommu_completion_wait(amd_iommus[i]);
386 }
387 }
388
389 /*
390 * Command send function for invalidating a device table entry
391 */
392 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
393 {
394 struct iommu_cmd cmd;
395 int ret;
396
397 BUG_ON(iommu == NULL);
398
399 memset(&cmd, 0, sizeof(cmd));
400 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
401 cmd.data[0] = devid;
402
403 ret = iommu_queue_command(iommu, &cmd);
404
405 return ret;
406 }
407
408 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
409 u16 domid, int pde, int s)
410 {
411 memset(cmd, 0, sizeof(*cmd));
412 address &= PAGE_MASK;
413 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
414 cmd->data[1] |= domid;
415 cmd->data[2] = lower_32_bits(address);
416 cmd->data[3] = upper_32_bits(address);
417 if (s) /* size bit - we flush more than one 4kb page */
418 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
419 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
420 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
421 }
422
423 /*
424 * Generic command send function for invalidaing TLB entries
425 */
426 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
427 u64 address, u16 domid, int pde, int s)
428 {
429 struct iommu_cmd cmd;
430 int ret;
431
432 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
433
434 ret = iommu_queue_command(iommu, &cmd);
435
436 return ret;
437 }
438
439 /*
440 * TLB invalidation function which is called from the mapping functions.
441 * It invalidates a single PTE if the range to flush is within a single
442 * page. Otherwise it flushes the whole TLB of the IOMMU.
443 */
444 static void __iommu_flush_pages(struct protection_domain *domain,
445 u64 address, size_t size, int pde)
446 {
447 int s = 0, i;
448 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
449
450 address &= PAGE_MASK;
451
452 if (pages > 1) {
453 /*
454 * If we have to flush more than one page, flush all
455 * TLB entries for this domain
456 */
457 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
458 s = 1;
459 }
460
461
462 for (i = 0; i < amd_iommus_present; ++i) {
463 if (!domain->dev_iommu[i])
464 continue;
465
466 /*
467 * Devices of this domain are behind this IOMMU
468 * We need a TLB flush
469 */
470 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
471 domain->id, pde, s);
472 }
473
474 return;
475 }
476
477 static void iommu_flush_pages(struct protection_domain *domain,
478 u64 address, size_t size)
479 {
480 __iommu_flush_pages(domain, address, size, 0);
481 }
482
483 /* Flush the whole IO/TLB for a given protection domain */
484 static void iommu_flush_tlb(struct protection_domain *domain)
485 {
486 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
487 }
488
489 /* Flush the whole IO/TLB for a given protection domain - including PDE */
490 static void iommu_flush_tlb_pde(struct protection_domain *domain)
491 {
492 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
493 }
494
495 /*
496 * This function flushes all domains that have devices on the given IOMMU
497 */
498 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
499 {
500 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
501 struct protection_domain *domain;
502 unsigned long flags;
503
504 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
505
506 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
507 if (domain->dev_iommu[iommu->index] == 0)
508 continue;
509
510 spin_lock(&domain->lock);
511 iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1);
512 iommu_flush_complete(domain);
513 spin_unlock(&domain->lock);
514 }
515
516 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
517 }
518
519 /*
520 * This function uses heavy locking and may disable irqs for some time. But
521 * this is no issue because it is only called during resume.
522 */
523 void amd_iommu_flush_all_domains(void)
524 {
525 struct protection_domain *domain;
526 unsigned long flags;
527
528 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
529
530 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
531 spin_lock(&domain->lock);
532 iommu_flush_tlb_pde(domain);
533 iommu_flush_complete(domain);
534 spin_unlock(&domain->lock);
535 }
536
537 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
538 }
539
540 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
541 {
542 int i;
543
544 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
545 if (iommu != amd_iommu_rlookup_table[i])
546 continue;
547
548 iommu_queue_inv_dev_entry(iommu, i);
549 iommu_completion_wait(iommu);
550 }
551 }
552
553 static void flush_devices_by_domain(struct protection_domain *domain)
554 {
555 struct amd_iommu *iommu;
556 int i;
557
558 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
559 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
560 (amd_iommu_pd_table[i] != domain))
561 continue;
562
563 iommu = amd_iommu_rlookup_table[i];
564 if (!iommu)
565 continue;
566
567 iommu_queue_inv_dev_entry(iommu, i);
568 iommu_completion_wait(iommu);
569 }
570 }
571
572 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
573 {
574 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
575
576 if (iommu->reset_in_progress)
577 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
578
579 iommu->reset_in_progress = true;
580
581 amd_iommu_reset_cmd_buffer(iommu);
582 flush_all_devices_for_iommu(iommu);
583 flush_all_domains_on_iommu(iommu);
584
585 iommu->reset_in_progress = false;
586 }
587
588 void amd_iommu_flush_all_devices(void)
589 {
590 flush_devices_by_domain(NULL);
591 }
592
593 /****************************************************************************
594 *
595 * The functions below are used the create the page table mappings for
596 * unity mapped regions.
597 *
598 ****************************************************************************/
599
600 /*
601 * Generic mapping functions. It maps a physical address into a DMA
602 * address space. It allocates the page table pages if necessary.
603 * In the future it can be extended to a generic mapping function
604 * supporting all features of AMD IOMMU page tables like level skipping
605 * and full 64 bit address spaces.
606 */
607 static int iommu_map_page(struct protection_domain *dom,
608 unsigned long bus_addr,
609 unsigned long phys_addr,
610 int prot,
611 int map_size)
612 {
613 u64 __pte, *pte;
614
615 bus_addr = PAGE_ALIGN(bus_addr);
616 phys_addr = PAGE_ALIGN(phys_addr);
617
618 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
619 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
620
621 if (!(prot & IOMMU_PROT_MASK))
622 return -EINVAL;
623
624 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
625
626 if (IOMMU_PTE_PRESENT(*pte))
627 return -EBUSY;
628
629 __pte = phys_addr | IOMMU_PTE_P;
630 if (prot & IOMMU_PROT_IR)
631 __pte |= IOMMU_PTE_IR;
632 if (prot & IOMMU_PROT_IW)
633 __pte |= IOMMU_PTE_IW;
634
635 *pte = __pte;
636
637 update_domain(dom);
638
639 return 0;
640 }
641
642 static void iommu_unmap_page(struct protection_domain *dom,
643 unsigned long bus_addr, int map_size)
644 {
645 u64 *pte = fetch_pte(dom, bus_addr, map_size);
646
647 if (pte)
648 *pte = 0;
649 }
650
651 /*
652 * This function checks if a specific unity mapping entry is needed for
653 * this specific IOMMU.
654 */
655 static int iommu_for_unity_map(struct amd_iommu *iommu,
656 struct unity_map_entry *entry)
657 {
658 u16 bdf, i;
659
660 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
661 bdf = amd_iommu_alias_table[i];
662 if (amd_iommu_rlookup_table[bdf] == iommu)
663 return 1;
664 }
665
666 return 0;
667 }
668
669 /*
670 * Init the unity mappings for a specific IOMMU in the system
671 *
672 * Basically iterates over all unity mapping entries and applies them to
673 * the default domain DMA of that IOMMU if necessary.
674 */
675 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
676 {
677 struct unity_map_entry *entry;
678 int ret;
679
680 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
681 if (!iommu_for_unity_map(iommu, entry))
682 continue;
683 ret = dma_ops_unity_map(iommu->default_dom, entry);
684 if (ret)
685 return ret;
686 }
687
688 return 0;
689 }
690
691 /*
692 * This function actually applies the mapping to the page table of the
693 * dma_ops domain.
694 */
695 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
696 struct unity_map_entry *e)
697 {
698 u64 addr;
699 int ret;
700
701 for (addr = e->address_start; addr < e->address_end;
702 addr += PAGE_SIZE) {
703 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
704 PM_MAP_4k);
705 if (ret)
706 return ret;
707 /*
708 * if unity mapping is in aperture range mark the page
709 * as allocated in the aperture
710 */
711 if (addr < dma_dom->aperture_size)
712 __set_bit(addr >> PAGE_SHIFT,
713 dma_dom->aperture[0]->bitmap);
714 }
715
716 return 0;
717 }
718
719 /*
720 * Inits the unity mappings required for a specific device
721 */
722 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
723 u16 devid)
724 {
725 struct unity_map_entry *e;
726 int ret;
727
728 list_for_each_entry(e, &amd_iommu_unity_map, list) {
729 if (!(devid >= e->devid_start && devid <= e->devid_end))
730 continue;
731 ret = dma_ops_unity_map(dma_dom, e);
732 if (ret)
733 return ret;
734 }
735
736 return 0;
737 }
738
739 /****************************************************************************
740 *
741 * The next functions belong to the address allocator for the dma_ops
742 * interface functions. They work like the allocators in the other IOMMU
743 * drivers. Its basically a bitmap which marks the allocated pages in
744 * the aperture. Maybe it could be enhanced in the future to a more
745 * efficient allocator.
746 *
747 ****************************************************************************/
748
749 /*
750 * The address allocator core functions.
751 *
752 * called with domain->lock held
753 */
754
755 /*
756 * This function checks if there is a PTE for a given dma address. If
757 * there is one, it returns the pointer to it.
758 */
759 static u64 *fetch_pte(struct protection_domain *domain,
760 unsigned long address, int map_size)
761 {
762 int level;
763 u64 *pte;
764
765 level = domain->mode - 1;
766 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
767
768 while (level > map_size) {
769 if (!IOMMU_PTE_PRESENT(*pte))
770 return NULL;
771
772 level -= 1;
773
774 pte = IOMMU_PTE_PAGE(*pte);
775 pte = &pte[PM_LEVEL_INDEX(level, address)];
776
777 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
778 pte = NULL;
779 break;
780 }
781 }
782
783 return pte;
784 }
785
786 /*
787 * This function is used to add a new aperture range to an existing
788 * aperture in case of dma_ops domain allocation or address allocation
789 * failure.
790 */
791 static int alloc_new_range(struct amd_iommu *iommu,
792 struct dma_ops_domain *dma_dom,
793 bool populate, gfp_t gfp)
794 {
795 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
796 int i;
797
798 #ifdef CONFIG_IOMMU_STRESS
799 populate = false;
800 #endif
801
802 if (index >= APERTURE_MAX_RANGES)
803 return -ENOMEM;
804
805 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
806 if (!dma_dom->aperture[index])
807 return -ENOMEM;
808
809 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
810 if (!dma_dom->aperture[index]->bitmap)
811 goto out_free;
812
813 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
814
815 if (populate) {
816 unsigned long address = dma_dom->aperture_size;
817 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
818 u64 *pte, *pte_page;
819
820 for (i = 0; i < num_ptes; ++i) {
821 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
822 &pte_page, gfp);
823 if (!pte)
824 goto out_free;
825
826 dma_dom->aperture[index]->pte_pages[i] = pte_page;
827
828 address += APERTURE_RANGE_SIZE / 64;
829 }
830 }
831
832 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
833
834 /* Intialize the exclusion range if necessary */
835 if (iommu->exclusion_start &&
836 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
837 iommu->exclusion_start < dma_dom->aperture_size) {
838 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
839 int pages = iommu_num_pages(iommu->exclusion_start,
840 iommu->exclusion_length,
841 PAGE_SIZE);
842 dma_ops_reserve_addresses(dma_dom, startpage, pages);
843 }
844
845 /*
846 * Check for areas already mapped as present in the new aperture
847 * range and mark those pages as reserved in the allocator. Such
848 * mappings may already exist as a result of requested unity
849 * mappings for devices.
850 */
851 for (i = dma_dom->aperture[index]->offset;
852 i < dma_dom->aperture_size;
853 i += PAGE_SIZE) {
854 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
855 if (!pte || !IOMMU_PTE_PRESENT(*pte))
856 continue;
857
858 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
859 }
860
861 update_domain(&dma_dom->domain);
862
863 return 0;
864
865 out_free:
866 update_domain(&dma_dom->domain);
867
868 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
869
870 kfree(dma_dom->aperture[index]);
871 dma_dom->aperture[index] = NULL;
872
873 return -ENOMEM;
874 }
875
876 static unsigned long dma_ops_area_alloc(struct device *dev,
877 struct dma_ops_domain *dom,
878 unsigned int pages,
879 unsigned long align_mask,
880 u64 dma_mask,
881 unsigned long start)
882 {
883 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
884 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
885 int i = start >> APERTURE_RANGE_SHIFT;
886 unsigned long boundary_size;
887 unsigned long address = -1;
888 unsigned long limit;
889
890 next_bit >>= PAGE_SHIFT;
891
892 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
893 PAGE_SIZE) >> PAGE_SHIFT;
894
895 for (;i < max_index; ++i) {
896 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
897
898 if (dom->aperture[i]->offset >= dma_mask)
899 break;
900
901 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
902 dma_mask >> PAGE_SHIFT);
903
904 address = iommu_area_alloc(dom->aperture[i]->bitmap,
905 limit, next_bit, pages, 0,
906 boundary_size, align_mask);
907 if (address != -1) {
908 address = dom->aperture[i]->offset +
909 (address << PAGE_SHIFT);
910 dom->next_address = address + (pages << PAGE_SHIFT);
911 break;
912 }
913
914 next_bit = 0;
915 }
916
917 return address;
918 }
919
920 static unsigned long dma_ops_alloc_addresses(struct device *dev,
921 struct dma_ops_domain *dom,
922 unsigned int pages,
923 unsigned long align_mask,
924 u64 dma_mask)
925 {
926 unsigned long address;
927
928 #ifdef CONFIG_IOMMU_STRESS
929 dom->next_address = 0;
930 dom->need_flush = true;
931 #endif
932
933 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
934 dma_mask, dom->next_address);
935
936 if (address == -1) {
937 dom->next_address = 0;
938 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
939 dma_mask, 0);
940 dom->need_flush = true;
941 }
942
943 if (unlikely(address == -1))
944 address = DMA_ERROR_CODE;
945
946 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
947
948 return address;
949 }
950
951 /*
952 * The address free function.
953 *
954 * called with domain->lock held
955 */
956 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
957 unsigned long address,
958 unsigned int pages)
959 {
960 unsigned i = address >> APERTURE_RANGE_SHIFT;
961 struct aperture_range *range = dom->aperture[i];
962
963 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
964
965 #ifdef CONFIG_IOMMU_STRESS
966 if (i < 4)
967 return;
968 #endif
969
970 if (address >= dom->next_address)
971 dom->need_flush = true;
972
973 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
974
975 iommu_area_free(range->bitmap, address, pages);
976
977 }
978
979 /****************************************************************************
980 *
981 * The next functions belong to the domain allocation. A domain is
982 * allocated for every IOMMU as the default domain. If device isolation
983 * is enabled, every device get its own domain. The most important thing
984 * about domains is the page table mapping the DMA address space they
985 * contain.
986 *
987 ****************************************************************************/
988
989 /*
990 * This function adds a protection domain to the global protection domain list
991 */
992 static void add_domain_to_list(struct protection_domain *domain)
993 {
994 unsigned long flags;
995
996 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
997 list_add(&domain->list, &amd_iommu_pd_list);
998 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
999 }
1000
1001 /*
1002 * This function removes a protection domain to the global
1003 * protection domain list
1004 */
1005 static void del_domain_from_list(struct protection_domain *domain)
1006 {
1007 unsigned long flags;
1008
1009 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1010 list_del(&domain->list);
1011 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1012 }
1013
1014 static u16 domain_id_alloc(void)
1015 {
1016 unsigned long flags;
1017 int id;
1018
1019 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1020 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1021 BUG_ON(id == 0);
1022 if (id > 0 && id < MAX_DOMAIN_ID)
1023 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1024 else
1025 id = 0;
1026 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1027
1028 return id;
1029 }
1030
1031 static void domain_id_free(int id)
1032 {
1033 unsigned long flags;
1034
1035 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1036 if (id > 0 && id < MAX_DOMAIN_ID)
1037 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1038 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1039 }
1040
1041 /*
1042 * Used to reserve address ranges in the aperture (e.g. for exclusion
1043 * ranges.
1044 */
1045 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1046 unsigned long start_page,
1047 unsigned int pages)
1048 {
1049 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1050
1051 if (start_page + pages > last_page)
1052 pages = last_page - start_page;
1053
1054 for (i = start_page; i < start_page + pages; ++i) {
1055 int index = i / APERTURE_RANGE_PAGES;
1056 int page = i % APERTURE_RANGE_PAGES;
1057 __set_bit(page, dom->aperture[index]->bitmap);
1058 }
1059 }
1060
1061 static void free_pagetable(struct protection_domain *domain)
1062 {
1063 int i, j;
1064 u64 *p1, *p2, *p3;
1065
1066 p1 = domain->pt_root;
1067
1068 if (!p1)
1069 return;
1070
1071 for (i = 0; i < 512; ++i) {
1072 if (!IOMMU_PTE_PRESENT(p1[i]))
1073 continue;
1074
1075 p2 = IOMMU_PTE_PAGE(p1[i]);
1076 for (j = 0; j < 512; ++j) {
1077 if (!IOMMU_PTE_PRESENT(p2[j]))
1078 continue;
1079 p3 = IOMMU_PTE_PAGE(p2[j]);
1080 free_page((unsigned long)p3);
1081 }
1082
1083 free_page((unsigned long)p2);
1084 }
1085
1086 free_page((unsigned long)p1);
1087
1088 domain->pt_root = NULL;
1089 }
1090
1091 /*
1092 * Free a domain, only used if something went wrong in the
1093 * allocation path and we need to free an already allocated page table
1094 */
1095 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1096 {
1097 int i;
1098
1099 if (!dom)
1100 return;
1101
1102 del_domain_from_list(&dom->domain);
1103
1104 free_pagetable(&dom->domain);
1105
1106 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1107 if (!dom->aperture[i])
1108 continue;
1109 free_page((unsigned long)dom->aperture[i]->bitmap);
1110 kfree(dom->aperture[i]);
1111 }
1112
1113 kfree(dom);
1114 }
1115
1116 /*
1117 * Allocates a new protection domain usable for the dma_ops functions.
1118 * It also intializes the page table and the address allocator data
1119 * structures required for the dma_ops interface
1120 */
1121 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1122 {
1123 struct dma_ops_domain *dma_dom;
1124
1125 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1126 if (!dma_dom)
1127 return NULL;
1128
1129 spin_lock_init(&dma_dom->domain.lock);
1130
1131 dma_dom->domain.id = domain_id_alloc();
1132 if (dma_dom->domain.id == 0)
1133 goto free_dma_dom;
1134 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1135 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1136 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1137 dma_dom->domain.priv = dma_dom;
1138 if (!dma_dom->domain.pt_root)
1139 goto free_dma_dom;
1140
1141 dma_dom->need_flush = false;
1142 dma_dom->target_dev = 0xffff;
1143
1144 add_domain_to_list(&dma_dom->domain);
1145
1146 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1147 goto free_dma_dom;
1148
1149 /*
1150 * mark the first page as allocated so we never return 0 as
1151 * a valid dma-address. So we can use 0 as error value
1152 */
1153 dma_dom->aperture[0]->bitmap[0] = 1;
1154 dma_dom->next_address = 0;
1155
1156
1157 return dma_dom;
1158
1159 free_dma_dom:
1160 dma_ops_domain_free(dma_dom);
1161
1162 return NULL;
1163 }
1164
1165 /*
1166 * little helper function to check whether a given protection domain is a
1167 * dma_ops domain
1168 */
1169 static bool dma_ops_domain(struct protection_domain *domain)
1170 {
1171 return domain->flags & PD_DMA_OPS_MASK;
1172 }
1173
1174 /*
1175 * Find out the protection domain structure for a given PCI device. This
1176 * will give us the pointer to the page table root for example.
1177 */
1178 static struct protection_domain *domain_for_device(u16 devid)
1179 {
1180 struct protection_domain *dom;
1181 unsigned long flags;
1182
1183 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1184 dom = amd_iommu_pd_table[devid];
1185 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1186
1187 return dom;
1188 }
1189
1190 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1191 {
1192 u64 pte_root = virt_to_phys(domain->pt_root);
1193
1194 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1195 << DEV_ENTRY_MODE_SHIFT;
1196 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1197
1198 amd_iommu_dev_table[devid].data[2] = domain->id;
1199 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1200 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1201
1202 amd_iommu_pd_table[devid] = domain;
1203 }
1204
1205 /*
1206 * If a device is not yet associated with a domain, this function does
1207 * assigns it visible for the hardware
1208 */
1209 static void __attach_device(struct amd_iommu *iommu,
1210 struct protection_domain *domain,
1211 u16 devid)
1212 {
1213 /* lock domain */
1214 spin_lock(&domain->lock);
1215
1216 /* update DTE entry */
1217 set_dte_entry(devid, domain);
1218
1219 /* Do reference counting */
1220 domain->dev_iommu[iommu->index] += 1;
1221 domain->dev_cnt += 1;
1222
1223 /* ready */
1224 spin_unlock(&domain->lock);
1225 }
1226
1227 /*
1228 * If a device is not yet associated with a domain, this function does
1229 * assigns it visible for the hardware
1230 */
1231 static void attach_device(struct amd_iommu *iommu,
1232 struct protection_domain *domain,
1233 u16 devid)
1234 {
1235 unsigned long flags;
1236
1237 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1238 __attach_device(iommu, domain, devid);
1239 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1240
1241 /*
1242 * We might boot into a crash-kernel here. The crashed kernel
1243 * left the caches in the IOMMU dirty. So we have to flush
1244 * here to evict all dirty stuff.
1245 */
1246 iommu_queue_inv_dev_entry(iommu, devid);
1247 iommu_flush_tlb_pde(domain);
1248 }
1249
1250 /*
1251 * Removes a device from a protection domain (unlocked)
1252 */
1253 static void __detach_device(struct protection_domain *domain, u16 devid)
1254 {
1255 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1256
1257 BUG_ON(!iommu);
1258
1259 /* lock domain */
1260 spin_lock(&domain->lock);
1261
1262 /* remove domain from the lookup table */
1263 amd_iommu_pd_table[devid] = NULL;
1264
1265 /* remove entry from the device table seen by the hardware */
1266 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1267 amd_iommu_dev_table[devid].data[1] = 0;
1268 amd_iommu_dev_table[devid].data[2] = 0;
1269
1270 amd_iommu_apply_erratum_63(devid);
1271
1272 /* decrease reference counters */
1273 domain->dev_iommu[iommu->index] -= 1;
1274 domain->dev_cnt -= 1;
1275
1276 /* ready */
1277 spin_unlock(&domain->lock);
1278
1279 /*
1280 * If we run in passthrough mode the device must be assigned to the
1281 * passthrough domain if it is detached from any other domain
1282 */
1283 if (iommu_pass_through) {
1284 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1285 __attach_device(iommu, pt_domain, devid);
1286 }
1287 }
1288
1289 /*
1290 * Removes a device from a protection domain (with devtable_lock held)
1291 */
1292 static void detach_device(struct protection_domain *domain, u16 devid)
1293 {
1294 unsigned long flags;
1295
1296 /* lock device table */
1297 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1298 __detach_device(domain, devid);
1299 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1300 }
1301
1302 static int device_change_notifier(struct notifier_block *nb,
1303 unsigned long action, void *data)
1304 {
1305 struct device *dev = data;
1306 struct pci_dev *pdev = to_pci_dev(dev);
1307 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1308 struct protection_domain *domain;
1309 struct dma_ops_domain *dma_domain;
1310 struct amd_iommu *iommu;
1311 unsigned long flags;
1312
1313 if (devid > amd_iommu_last_bdf)
1314 goto out;
1315
1316 devid = amd_iommu_alias_table[devid];
1317
1318 iommu = amd_iommu_rlookup_table[devid];
1319 if (iommu == NULL)
1320 goto out;
1321
1322 domain = domain_for_device(devid);
1323
1324 if (domain && !dma_ops_domain(domain))
1325 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1326 "to a non-dma-ops domain\n", dev_name(dev));
1327
1328 switch (action) {
1329 case BUS_NOTIFY_UNBOUND_DRIVER:
1330 if (!domain)
1331 goto out;
1332 if (iommu_pass_through)
1333 break;
1334 detach_device(domain, devid);
1335 break;
1336 case BUS_NOTIFY_ADD_DEVICE:
1337 /* allocate a protection domain if a device is added */
1338 dma_domain = find_protection_domain(devid);
1339 if (dma_domain)
1340 goto out;
1341 dma_domain = dma_ops_domain_alloc(iommu);
1342 if (!dma_domain)
1343 goto out;
1344 dma_domain->target_dev = devid;
1345
1346 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1347 list_add_tail(&dma_domain->list, &iommu_pd_list);
1348 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1349
1350 break;
1351 default:
1352 goto out;
1353 }
1354
1355 iommu_queue_inv_dev_entry(iommu, devid);
1356 iommu_completion_wait(iommu);
1357
1358 out:
1359 return 0;
1360 }
1361
1362 static struct notifier_block device_nb = {
1363 .notifier_call = device_change_notifier,
1364 };
1365
1366 /*****************************************************************************
1367 *
1368 * The next functions belong to the dma_ops mapping/unmapping code.
1369 *
1370 *****************************************************************************/
1371
1372 /*
1373 * This function checks if the driver got a valid device from the caller to
1374 * avoid dereferencing invalid pointers.
1375 */
1376 static bool check_device(struct device *dev)
1377 {
1378 u16 bdf;
1379 struct pci_dev *pcidev;
1380
1381 if (!dev || !dev->dma_mask)
1382 return false;
1383
1384 /* No device or no PCI device */
1385 if (!dev || dev->bus != &pci_bus_type)
1386 return false;
1387
1388 pcidev = to_pci_dev(dev);
1389
1390 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1391
1392 /* Out of our scope? */
1393 if (bdf > amd_iommu_last_bdf)
1394 return false;
1395
1396 if (amd_iommu_rlookup_table[bdf] == NULL)
1397 return false;
1398
1399 return true;
1400 }
1401
1402 /*
1403 * In this function the list of preallocated protection domains is traversed to
1404 * find the domain for a specific device
1405 */
1406 static struct dma_ops_domain *find_protection_domain(u16 devid)
1407 {
1408 struct dma_ops_domain *entry, *ret = NULL;
1409 unsigned long flags;
1410
1411 if (list_empty(&iommu_pd_list))
1412 return NULL;
1413
1414 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1415
1416 list_for_each_entry(entry, &iommu_pd_list, list) {
1417 if (entry->target_dev == devid) {
1418 ret = entry;
1419 break;
1420 }
1421 }
1422
1423 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1424
1425 return ret;
1426 }
1427
1428 /*
1429 * In the dma_ops path we only have the struct device. This function
1430 * finds the corresponding IOMMU, the protection domain and the
1431 * requestor id for a given device.
1432 * If the device is not yet associated with a domain this is also done
1433 * in this function.
1434 */
1435 static int get_device_resources(struct device *dev,
1436 struct amd_iommu **iommu,
1437 struct protection_domain **domain,
1438 u16 *bdf)
1439 {
1440 struct dma_ops_domain *dma_dom;
1441 struct pci_dev *pcidev;
1442 u16 _bdf;
1443
1444 *iommu = NULL;
1445 *domain = NULL;
1446 *bdf = 0xffff;
1447
1448 if (dev->bus != &pci_bus_type)
1449 return 0;
1450
1451 pcidev = to_pci_dev(dev);
1452 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1453
1454 /* device not translated by any IOMMU in the system? */
1455 if (_bdf > amd_iommu_last_bdf)
1456 return 0;
1457
1458 *bdf = amd_iommu_alias_table[_bdf];
1459
1460 *iommu = amd_iommu_rlookup_table[*bdf];
1461 if (*iommu == NULL)
1462 return 0;
1463 *domain = domain_for_device(*bdf);
1464 if (*domain == NULL) {
1465 dma_dom = find_protection_domain(*bdf);
1466 if (!dma_dom)
1467 dma_dom = (*iommu)->default_dom;
1468 *domain = &dma_dom->domain;
1469 attach_device(*iommu, *domain, *bdf);
1470 DUMP_printk("Using protection domain %d for device %s\n",
1471 (*domain)->id, dev_name(dev));
1472 }
1473
1474 if (domain_for_device(_bdf) == NULL)
1475 attach_device(*iommu, *domain, _bdf);
1476
1477 return 1;
1478 }
1479
1480 static void update_device_table(struct protection_domain *domain)
1481 {
1482 unsigned long flags;
1483 int i;
1484
1485 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1486 if (amd_iommu_pd_table[i] != domain)
1487 continue;
1488 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1489 set_dte_entry(i, domain);
1490 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1491 }
1492 }
1493
1494 static void update_domain(struct protection_domain *domain)
1495 {
1496 if (!domain->updated)
1497 return;
1498
1499 update_device_table(domain);
1500 flush_devices_by_domain(domain);
1501 iommu_flush_tlb_pde(domain);
1502
1503 domain->updated = false;
1504 }
1505
1506 /*
1507 * This function is used to add another level to an IO page table. Adding
1508 * another level increases the size of the address space by 9 bits to a size up
1509 * to 64 bits.
1510 */
1511 static bool increase_address_space(struct protection_domain *domain,
1512 gfp_t gfp)
1513 {
1514 u64 *pte;
1515
1516 if (domain->mode == PAGE_MODE_6_LEVEL)
1517 /* address space already 64 bit large */
1518 return false;
1519
1520 pte = (void *)get_zeroed_page(gfp);
1521 if (!pte)
1522 return false;
1523
1524 *pte = PM_LEVEL_PDE(domain->mode,
1525 virt_to_phys(domain->pt_root));
1526 domain->pt_root = pte;
1527 domain->mode += 1;
1528 domain->updated = true;
1529
1530 return true;
1531 }
1532
1533 static u64 *alloc_pte(struct protection_domain *domain,
1534 unsigned long address,
1535 int end_lvl,
1536 u64 **pte_page,
1537 gfp_t gfp)
1538 {
1539 u64 *pte, *page;
1540 int level;
1541
1542 while (address > PM_LEVEL_SIZE(domain->mode))
1543 increase_address_space(domain, gfp);
1544
1545 level = domain->mode - 1;
1546 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1547
1548 while (level > end_lvl) {
1549 if (!IOMMU_PTE_PRESENT(*pte)) {
1550 page = (u64 *)get_zeroed_page(gfp);
1551 if (!page)
1552 return NULL;
1553 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1554 }
1555
1556 level -= 1;
1557
1558 pte = IOMMU_PTE_PAGE(*pte);
1559
1560 if (pte_page && level == end_lvl)
1561 *pte_page = pte;
1562
1563 pte = &pte[PM_LEVEL_INDEX(level, address)];
1564 }
1565
1566 return pte;
1567 }
1568
1569 /*
1570 * This function fetches the PTE for a given address in the aperture
1571 */
1572 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1573 unsigned long address)
1574 {
1575 struct aperture_range *aperture;
1576 u64 *pte, *pte_page;
1577
1578 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1579 if (!aperture)
1580 return NULL;
1581
1582 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1583 if (!pte) {
1584 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1585 GFP_ATOMIC);
1586 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1587 } else
1588 pte += PM_LEVEL_INDEX(0, address);
1589
1590 update_domain(&dom->domain);
1591
1592 return pte;
1593 }
1594
1595 /*
1596 * This is the generic map function. It maps one 4kb page at paddr to
1597 * the given address in the DMA address space for the domain.
1598 */
1599 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1600 struct dma_ops_domain *dom,
1601 unsigned long address,
1602 phys_addr_t paddr,
1603 int direction)
1604 {
1605 u64 *pte, __pte;
1606
1607 WARN_ON(address > dom->aperture_size);
1608
1609 paddr &= PAGE_MASK;
1610
1611 pte = dma_ops_get_pte(dom, address);
1612 if (!pte)
1613 return DMA_ERROR_CODE;
1614
1615 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1616
1617 if (direction == DMA_TO_DEVICE)
1618 __pte |= IOMMU_PTE_IR;
1619 else if (direction == DMA_FROM_DEVICE)
1620 __pte |= IOMMU_PTE_IW;
1621 else if (direction == DMA_BIDIRECTIONAL)
1622 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1623
1624 WARN_ON(*pte);
1625
1626 *pte = __pte;
1627
1628 return (dma_addr_t)address;
1629 }
1630
1631 /*
1632 * The generic unmapping function for on page in the DMA address space.
1633 */
1634 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1635 struct dma_ops_domain *dom,
1636 unsigned long address)
1637 {
1638 struct aperture_range *aperture;
1639 u64 *pte;
1640
1641 if (address >= dom->aperture_size)
1642 return;
1643
1644 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1645 if (!aperture)
1646 return;
1647
1648 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1649 if (!pte)
1650 return;
1651
1652 pte += PM_LEVEL_INDEX(0, address);
1653
1654 WARN_ON(!*pte);
1655
1656 *pte = 0ULL;
1657 }
1658
1659 /*
1660 * This function contains common code for mapping of a physically
1661 * contiguous memory region into DMA address space. It is used by all
1662 * mapping functions provided with this IOMMU driver.
1663 * Must be called with the domain lock held.
1664 */
1665 static dma_addr_t __map_single(struct device *dev,
1666 struct amd_iommu *iommu,
1667 struct dma_ops_domain *dma_dom,
1668 phys_addr_t paddr,
1669 size_t size,
1670 int dir,
1671 bool align,
1672 u64 dma_mask)
1673 {
1674 dma_addr_t offset = paddr & ~PAGE_MASK;
1675 dma_addr_t address, start, ret;
1676 unsigned int pages;
1677 unsigned long align_mask = 0;
1678 int i;
1679
1680 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1681 paddr &= PAGE_MASK;
1682
1683 INC_STATS_COUNTER(total_map_requests);
1684
1685 if (pages > 1)
1686 INC_STATS_COUNTER(cross_page);
1687
1688 if (align)
1689 align_mask = (1UL << get_order(size)) - 1;
1690
1691 retry:
1692 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1693 dma_mask);
1694 if (unlikely(address == DMA_ERROR_CODE)) {
1695 /*
1696 * setting next_address here will let the address
1697 * allocator only scan the new allocated range in the
1698 * first run. This is a small optimization.
1699 */
1700 dma_dom->next_address = dma_dom->aperture_size;
1701
1702 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1703 goto out;
1704
1705 /*
1706 * aperture was sucessfully enlarged by 128 MB, try
1707 * allocation again
1708 */
1709 goto retry;
1710 }
1711
1712 start = address;
1713 for (i = 0; i < pages; ++i) {
1714 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1715 if (ret == DMA_ERROR_CODE)
1716 goto out_unmap;
1717
1718 paddr += PAGE_SIZE;
1719 start += PAGE_SIZE;
1720 }
1721 address += offset;
1722
1723 ADD_STATS_COUNTER(alloced_io_mem, size);
1724
1725 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1726 iommu_flush_tlb(&dma_dom->domain);
1727 dma_dom->need_flush = false;
1728 } else if (unlikely(amd_iommu_np_cache))
1729 iommu_flush_pages(&dma_dom->domain, address, size);
1730
1731 out:
1732 return address;
1733
1734 out_unmap:
1735
1736 for (--i; i >= 0; --i) {
1737 start -= PAGE_SIZE;
1738 dma_ops_domain_unmap(iommu, dma_dom, start);
1739 }
1740
1741 dma_ops_free_addresses(dma_dom, address, pages);
1742
1743 return DMA_ERROR_CODE;
1744 }
1745
1746 /*
1747 * Does the reverse of the __map_single function. Must be called with
1748 * the domain lock held too
1749 */
1750 static void __unmap_single(struct amd_iommu *iommu,
1751 struct dma_ops_domain *dma_dom,
1752 dma_addr_t dma_addr,
1753 size_t size,
1754 int dir)
1755 {
1756 dma_addr_t i, start;
1757 unsigned int pages;
1758
1759 if ((dma_addr == DMA_ERROR_CODE) ||
1760 (dma_addr + size > dma_dom->aperture_size))
1761 return;
1762
1763 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1764 dma_addr &= PAGE_MASK;
1765 start = dma_addr;
1766
1767 for (i = 0; i < pages; ++i) {
1768 dma_ops_domain_unmap(iommu, dma_dom, start);
1769 start += PAGE_SIZE;
1770 }
1771
1772 SUB_STATS_COUNTER(alloced_io_mem, size);
1773
1774 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1775
1776 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1777 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1778 dma_dom->need_flush = false;
1779 }
1780 }
1781
1782 /*
1783 * The exported map_single function for dma_ops.
1784 */
1785 static dma_addr_t map_page(struct device *dev, struct page *page,
1786 unsigned long offset, size_t size,
1787 enum dma_data_direction dir,
1788 struct dma_attrs *attrs)
1789 {
1790 unsigned long flags;
1791 struct amd_iommu *iommu;
1792 struct protection_domain *domain;
1793 u16 devid;
1794 dma_addr_t addr;
1795 u64 dma_mask;
1796 phys_addr_t paddr = page_to_phys(page) + offset;
1797
1798 INC_STATS_COUNTER(cnt_map_single);
1799
1800 if (!check_device(dev))
1801 return DMA_ERROR_CODE;
1802
1803 dma_mask = *dev->dma_mask;
1804
1805 get_device_resources(dev, &iommu, &domain, &devid);
1806
1807 if (iommu == NULL || domain == NULL)
1808 /* device not handled by any AMD IOMMU */
1809 return (dma_addr_t)paddr;
1810
1811 if (!dma_ops_domain(domain))
1812 return DMA_ERROR_CODE;
1813
1814 spin_lock_irqsave(&domain->lock, flags);
1815 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1816 dma_mask);
1817 if (addr == DMA_ERROR_CODE)
1818 goto out;
1819
1820 iommu_flush_complete(domain);
1821
1822 out:
1823 spin_unlock_irqrestore(&domain->lock, flags);
1824
1825 return addr;
1826 }
1827
1828 /*
1829 * The exported unmap_single function for dma_ops.
1830 */
1831 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1832 enum dma_data_direction dir, struct dma_attrs *attrs)
1833 {
1834 unsigned long flags;
1835 struct amd_iommu *iommu;
1836 struct protection_domain *domain;
1837 u16 devid;
1838
1839 INC_STATS_COUNTER(cnt_unmap_single);
1840
1841 if (!check_device(dev) ||
1842 !get_device_resources(dev, &iommu, &domain, &devid))
1843 /* device not handled by any AMD IOMMU */
1844 return;
1845
1846 if (!dma_ops_domain(domain))
1847 return;
1848
1849 spin_lock_irqsave(&domain->lock, flags);
1850
1851 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1852
1853 iommu_flush_complete(domain);
1854
1855 spin_unlock_irqrestore(&domain->lock, flags);
1856 }
1857
1858 /*
1859 * This is a special map_sg function which is used if we should map a
1860 * device which is not handled by an AMD IOMMU in the system.
1861 */
1862 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1863 int nelems, int dir)
1864 {
1865 struct scatterlist *s;
1866 int i;
1867
1868 for_each_sg(sglist, s, nelems, i) {
1869 s->dma_address = (dma_addr_t)sg_phys(s);
1870 s->dma_length = s->length;
1871 }
1872
1873 return nelems;
1874 }
1875
1876 /*
1877 * The exported map_sg function for dma_ops (handles scatter-gather
1878 * lists).
1879 */
1880 static int map_sg(struct device *dev, struct scatterlist *sglist,
1881 int nelems, enum dma_data_direction dir,
1882 struct dma_attrs *attrs)
1883 {
1884 unsigned long flags;
1885 struct amd_iommu *iommu;
1886 struct protection_domain *domain;
1887 u16 devid;
1888 int i;
1889 struct scatterlist *s;
1890 phys_addr_t paddr;
1891 int mapped_elems = 0;
1892 u64 dma_mask;
1893
1894 INC_STATS_COUNTER(cnt_map_sg);
1895
1896 if (!check_device(dev))
1897 return 0;
1898
1899 dma_mask = *dev->dma_mask;
1900
1901 get_device_resources(dev, &iommu, &domain, &devid);
1902
1903 if (!iommu || !domain)
1904 return map_sg_no_iommu(dev, sglist, nelems, dir);
1905
1906 if (!dma_ops_domain(domain))
1907 return 0;
1908
1909 spin_lock_irqsave(&domain->lock, flags);
1910
1911 for_each_sg(sglist, s, nelems, i) {
1912 paddr = sg_phys(s);
1913
1914 s->dma_address = __map_single(dev, iommu, domain->priv,
1915 paddr, s->length, dir, false,
1916 dma_mask);
1917
1918 if (s->dma_address) {
1919 s->dma_length = s->length;
1920 mapped_elems++;
1921 } else
1922 goto unmap;
1923 }
1924
1925 iommu_flush_complete(domain);
1926
1927 out:
1928 spin_unlock_irqrestore(&domain->lock, flags);
1929
1930 return mapped_elems;
1931 unmap:
1932 for_each_sg(sglist, s, mapped_elems, i) {
1933 if (s->dma_address)
1934 __unmap_single(iommu, domain->priv, s->dma_address,
1935 s->dma_length, dir);
1936 s->dma_address = s->dma_length = 0;
1937 }
1938
1939 mapped_elems = 0;
1940
1941 goto out;
1942 }
1943
1944 /*
1945 * The exported map_sg function for dma_ops (handles scatter-gather
1946 * lists).
1947 */
1948 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1949 int nelems, enum dma_data_direction dir,
1950 struct dma_attrs *attrs)
1951 {
1952 unsigned long flags;
1953 struct amd_iommu *iommu;
1954 struct protection_domain *domain;
1955 struct scatterlist *s;
1956 u16 devid;
1957 int i;
1958
1959 INC_STATS_COUNTER(cnt_unmap_sg);
1960
1961 if (!check_device(dev) ||
1962 !get_device_resources(dev, &iommu, &domain, &devid))
1963 return;
1964
1965 if (!dma_ops_domain(domain))
1966 return;
1967
1968 spin_lock_irqsave(&domain->lock, flags);
1969
1970 for_each_sg(sglist, s, nelems, i) {
1971 __unmap_single(iommu, domain->priv, s->dma_address,
1972 s->dma_length, dir);
1973 s->dma_address = s->dma_length = 0;
1974 }
1975
1976 iommu_flush_complete(domain);
1977
1978 spin_unlock_irqrestore(&domain->lock, flags);
1979 }
1980
1981 /*
1982 * The exported alloc_coherent function for dma_ops.
1983 */
1984 static void *alloc_coherent(struct device *dev, size_t size,
1985 dma_addr_t *dma_addr, gfp_t flag)
1986 {
1987 unsigned long flags;
1988 void *virt_addr;
1989 struct amd_iommu *iommu;
1990 struct protection_domain *domain;
1991 u16 devid;
1992 phys_addr_t paddr;
1993 u64 dma_mask = dev->coherent_dma_mask;
1994
1995 INC_STATS_COUNTER(cnt_alloc_coherent);
1996
1997 if (!check_device(dev))
1998 return NULL;
1999
2000 if (!get_device_resources(dev, &iommu, &domain, &devid))
2001 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2002
2003 flag |= __GFP_ZERO;
2004 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2005 if (!virt_addr)
2006 return NULL;
2007
2008 paddr = virt_to_phys(virt_addr);
2009
2010 if (!iommu || !domain) {
2011 *dma_addr = (dma_addr_t)paddr;
2012 return virt_addr;
2013 }
2014
2015 if (!dma_ops_domain(domain))
2016 goto out_free;
2017
2018 if (!dma_mask)
2019 dma_mask = *dev->dma_mask;
2020
2021 spin_lock_irqsave(&domain->lock, flags);
2022
2023 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
2024 size, DMA_BIDIRECTIONAL, true, dma_mask);
2025
2026 if (*dma_addr == DMA_ERROR_CODE) {
2027 spin_unlock_irqrestore(&domain->lock, flags);
2028 goto out_free;
2029 }
2030
2031 iommu_flush_complete(domain);
2032
2033 spin_unlock_irqrestore(&domain->lock, flags);
2034
2035 return virt_addr;
2036
2037 out_free:
2038
2039 free_pages((unsigned long)virt_addr, get_order(size));
2040
2041 return NULL;
2042 }
2043
2044 /*
2045 * The exported free_coherent function for dma_ops.
2046 */
2047 static void free_coherent(struct device *dev, size_t size,
2048 void *virt_addr, dma_addr_t dma_addr)
2049 {
2050 unsigned long flags;
2051 struct amd_iommu *iommu;
2052 struct protection_domain *domain;
2053 u16 devid;
2054
2055 INC_STATS_COUNTER(cnt_free_coherent);
2056
2057 if (!check_device(dev))
2058 return;
2059
2060 get_device_resources(dev, &iommu, &domain, &devid);
2061
2062 if (!iommu || !domain)
2063 goto free_mem;
2064
2065 if (!dma_ops_domain(domain))
2066 goto free_mem;
2067
2068 spin_lock_irqsave(&domain->lock, flags);
2069
2070 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2071
2072 iommu_flush_complete(domain);
2073
2074 spin_unlock_irqrestore(&domain->lock, flags);
2075
2076 free_mem:
2077 free_pages((unsigned long)virt_addr, get_order(size));
2078 }
2079
2080 /*
2081 * This function is called by the DMA layer to find out if we can handle a
2082 * particular device. It is part of the dma_ops.
2083 */
2084 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2085 {
2086 return check_device(dev);
2087 }
2088
2089 /*
2090 * The function for pre-allocating protection domains.
2091 *
2092 * If the driver core informs the DMA layer if a driver grabs a device
2093 * we don't need to preallocate the protection domains anymore.
2094 * For now we have to.
2095 */
2096 static void prealloc_protection_domains(void)
2097 {
2098 struct pci_dev *dev = NULL;
2099 struct dma_ops_domain *dma_dom;
2100 struct amd_iommu *iommu;
2101 u16 devid, __devid;
2102
2103 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2104 __devid = devid = calc_devid(dev->bus->number, dev->devfn);
2105 if (devid > amd_iommu_last_bdf)
2106 continue;
2107 devid = amd_iommu_alias_table[devid];
2108 if (domain_for_device(devid))
2109 continue;
2110 iommu = amd_iommu_rlookup_table[devid];
2111 if (!iommu)
2112 continue;
2113 dma_dom = dma_ops_domain_alloc(iommu);
2114 if (!dma_dom)
2115 continue;
2116 init_unity_mappings_for_device(dma_dom, devid);
2117 dma_dom->target_dev = devid;
2118
2119 attach_device(iommu, &dma_dom->domain, devid);
2120 if (__devid != devid)
2121 attach_device(iommu, &dma_dom->domain, __devid);
2122
2123 list_add_tail(&dma_dom->list, &iommu_pd_list);
2124 }
2125 }
2126
2127 static struct dma_map_ops amd_iommu_dma_ops = {
2128 .alloc_coherent = alloc_coherent,
2129 .free_coherent = free_coherent,
2130 .map_page = map_page,
2131 .unmap_page = unmap_page,
2132 .map_sg = map_sg,
2133 .unmap_sg = unmap_sg,
2134 .dma_supported = amd_iommu_dma_supported,
2135 };
2136
2137 /*
2138 * The function which clues the AMD IOMMU driver into dma_ops.
2139 */
2140 int __init amd_iommu_init_dma_ops(void)
2141 {
2142 struct amd_iommu *iommu;
2143 int ret;
2144
2145 /*
2146 * first allocate a default protection domain for every IOMMU we
2147 * found in the system. Devices not assigned to any other
2148 * protection domain will be assigned to the default one.
2149 */
2150 for_each_iommu(iommu) {
2151 iommu->default_dom = dma_ops_domain_alloc(iommu);
2152 if (iommu->default_dom == NULL)
2153 return -ENOMEM;
2154 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2155 ret = iommu_init_unity_mappings(iommu);
2156 if (ret)
2157 goto free_domains;
2158 }
2159
2160 /*
2161 * If device isolation is enabled, pre-allocate the protection
2162 * domains for each device.
2163 */
2164 if (amd_iommu_isolate)
2165 prealloc_protection_domains();
2166
2167 iommu_detected = 1;
2168 swiotlb = 0;
2169 #ifdef CONFIG_GART_IOMMU
2170 gart_iommu_aperture_disabled = 1;
2171 gart_iommu_aperture = 0;
2172 #endif
2173
2174 /* Make the driver finally visible to the drivers */
2175 dma_ops = &amd_iommu_dma_ops;
2176
2177 register_iommu(&amd_iommu_ops);
2178
2179 bus_register_notifier(&pci_bus_type, &device_nb);
2180
2181 amd_iommu_stats_init();
2182
2183 return 0;
2184
2185 free_domains:
2186
2187 for_each_iommu(iommu) {
2188 if (iommu->default_dom)
2189 dma_ops_domain_free(iommu->default_dom);
2190 }
2191
2192 return ret;
2193 }
2194
2195 /*****************************************************************************
2196 *
2197 * The following functions belong to the exported interface of AMD IOMMU
2198 *
2199 * This interface allows access to lower level functions of the IOMMU
2200 * like protection domain handling and assignement of devices to domains
2201 * which is not possible with the dma_ops interface.
2202 *
2203 *****************************************************************************/
2204
2205 static void cleanup_domain(struct protection_domain *domain)
2206 {
2207 unsigned long flags;
2208 u16 devid;
2209
2210 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2211
2212 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2213 if (amd_iommu_pd_table[devid] == domain)
2214 __detach_device(domain, devid);
2215
2216 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2217 }
2218
2219 static void protection_domain_free(struct protection_domain *domain)
2220 {
2221 if (!domain)
2222 return;
2223
2224 del_domain_from_list(domain);
2225
2226 if (domain->id)
2227 domain_id_free(domain->id);
2228
2229 kfree(domain);
2230 }
2231
2232 static struct protection_domain *protection_domain_alloc(void)
2233 {
2234 struct protection_domain *domain;
2235
2236 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2237 if (!domain)
2238 return NULL;
2239
2240 spin_lock_init(&domain->lock);
2241 domain->id = domain_id_alloc();
2242 if (!domain->id)
2243 goto out_err;
2244
2245 add_domain_to_list(domain);
2246
2247 return domain;
2248
2249 out_err:
2250 kfree(domain);
2251
2252 return NULL;
2253 }
2254
2255 static int amd_iommu_domain_init(struct iommu_domain *dom)
2256 {
2257 struct protection_domain *domain;
2258
2259 domain = protection_domain_alloc();
2260 if (!domain)
2261 goto out_free;
2262
2263 domain->mode = PAGE_MODE_3_LEVEL;
2264 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2265 if (!domain->pt_root)
2266 goto out_free;
2267
2268 dom->priv = domain;
2269
2270 return 0;
2271
2272 out_free:
2273 protection_domain_free(domain);
2274
2275 return -ENOMEM;
2276 }
2277
2278 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2279 {
2280 struct protection_domain *domain = dom->priv;
2281
2282 if (!domain)
2283 return;
2284
2285 if (domain->dev_cnt > 0)
2286 cleanup_domain(domain);
2287
2288 BUG_ON(domain->dev_cnt != 0);
2289
2290 free_pagetable(domain);
2291
2292 domain_id_free(domain->id);
2293
2294 kfree(domain);
2295
2296 dom->priv = NULL;
2297 }
2298
2299 static void amd_iommu_detach_device(struct iommu_domain *dom,
2300 struct device *dev)
2301 {
2302 struct protection_domain *domain = dom->priv;
2303 struct amd_iommu *iommu;
2304 struct pci_dev *pdev;
2305 u16 devid;
2306
2307 if (dev->bus != &pci_bus_type)
2308 return;
2309
2310 pdev = to_pci_dev(dev);
2311
2312 devid = calc_devid(pdev->bus->number, pdev->devfn);
2313
2314 if (devid > 0)
2315 detach_device(domain, devid);
2316
2317 iommu = amd_iommu_rlookup_table[devid];
2318 if (!iommu)
2319 return;
2320
2321 iommu_queue_inv_dev_entry(iommu, devid);
2322 iommu_completion_wait(iommu);
2323 }
2324
2325 static int amd_iommu_attach_device(struct iommu_domain *dom,
2326 struct device *dev)
2327 {
2328 struct protection_domain *domain = dom->priv;
2329 struct protection_domain *old_domain;
2330 struct amd_iommu *iommu;
2331 struct pci_dev *pdev;
2332 u16 devid;
2333
2334 if (dev->bus != &pci_bus_type)
2335 return -EINVAL;
2336
2337 pdev = to_pci_dev(dev);
2338
2339 devid = calc_devid(pdev->bus->number, pdev->devfn);
2340
2341 if (devid >= amd_iommu_last_bdf ||
2342 devid != amd_iommu_alias_table[devid])
2343 return -EINVAL;
2344
2345 iommu = amd_iommu_rlookup_table[devid];
2346 if (!iommu)
2347 return -EINVAL;
2348
2349 old_domain = domain_for_device(devid);
2350 if (old_domain)
2351 detach_device(old_domain, devid);
2352
2353 attach_device(iommu, domain, devid);
2354
2355 iommu_completion_wait(iommu);
2356
2357 return 0;
2358 }
2359
2360 static int amd_iommu_map_range(struct iommu_domain *dom,
2361 unsigned long iova, phys_addr_t paddr,
2362 size_t size, int iommu_prot)
2363 {
2364 struct protection_domain *domain = dom->priv;
2365 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2366 int prot = 0;
2367 int ret;
2368
2369 if (iommu_prot & IOMMU_READ)
2370 prot |= IOMMU_PROT_IR;
2371 if (iommu_prot & IOMMU_WRITE)
2372 prot |= IOMMU_PROT_IW;
2373
2374 iova &= PAGE_MASK;
2375 paddr &= PAGE_MASK;
2376
2377 for (i = 0; i < npages; ++i) {
2378 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2379 if (ret)
2380 return ret;
2381
2382 iova += PAGE_SIZE;
2383 paddr += PAGE_SIZE;
2384 }
2385
2386 return 0;
2387 }
2388
2389 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2390 unsigned long iova, size_t size)
2391 {
2392
2393 struct protection_domain *domain = dom->priv;
2394 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2395
2396 iova &= PAGE_MASK;
2397
2398 for (i = 0; i < npages; ++i) {
2399 iommu_unmap_page(domain, iova, PM_MAP_4k);
2400 iova += PAGE_SIZE;
2401 }
2402
2403 iommu_flush_tlb_pde(domain);
2404 }
2405
2406 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2407 unsigned long iova)
2408 {
2409 struct protection_domain *domain = dom->priv;
2410 unsigned long offset = iova & ~PAGE_MASK;
2411 phys_addr_t paddr;
2412 u64 *pte;
2413
2414 pte = fetch_pte(domain, iova, PM_MAP_4k);
2415
2416 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2417 return 0;
2418
2419 paddr = *pte & IOMMU_PAGE_MASK;
2420 paddr |= offset;
2421
2422 return paddr;
2423 }
2424
2425 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2426 unsigned long cap)
2427 {
2428 return 0;
2429 }
2430
2431 static struct iommu_ops amd_iommu_ops = {
2432 .domain_init = amd_iommu_domain_init,
2433 .domain_destroy = amd_iommu_domain_destroy,
2434 .attach_dev = amd_iommu_attach_device,
2435 .detach_dev = amd_iommu_detach_device,
2436 .map = amd_iommu_map_range,
2437 .unmap = amd_iommu_unmap_range,
2438 .iova_to_phys = amd_iommu_iova_to_phys,
2439 .domain_has_cap = amd_iommu_domain_has_cap,
2440 };
2441
2442 /*****************************************************************************
2443 *
2444 * The next functions do a basic initialization of IOMMU for pass through
2445 * mode
2446 *
2447 * In passthrough mode the IOMMU is initialized and enabled but not used for
2448 * DMA-API translation.
2449 *
2450 *****************************************************************************/
2451
2452 int __init amd_iommu_init_passthrough(void)
2453 {
2454 struct pci_dev *dev = NULL;
2455 u16 devid, devid2;
2456
2457 /* allocate passthroug domain */
2458 pt_domain = protection_domain_alloc();
2459 if (!pt_domain)
2460 return -ENOMEM;
2461
2462 pt_domain->mode |= PAGE_MODE_NONE;
2463
2464 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2465 struct amd_iommu *iommu;
2466
2467 devid = calc_devid(dev->bus->number, dev->devfn);
2468 if (devid > amd_iommu_last_bdf)
2469 continue;
2470
2471 devid2 = amd_iommu_alias_table[devid];
2472
2473 iommu = amd_iommu_rlookup_table[devid2];
2474 if (!iommu)
2475 continue;
2476
2477 __attach_device(iommu, pt_domain, devid);
2478 __attach_device(iommu, pt_domain, devid2);
2479 }
2480
2481 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2482
2483 return 0;
2484 }
Linux kernel - Deliverables
This page took 0.208637 seconds and 6 git commands to generate.