2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN 0x00
53 #define IVHD_FLAG_PASSPW_EN 0x01
54 #define IVHD_FLAG_RESPASSPW_EN 0x02
55 #define IVHD_FLAG_ISOC_EN 0x03
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed
));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed
));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed
));
118 static int __initdata amd_iommu_detected
;
120 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
122 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order
= 26; /* size of aperture in power of 2 */
125 int amd_iommu_isolate
= 1; /* if 1, device isolation is enabled */
126 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
128 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
132 * Pointer to the device table which is shared by all AMD IOMMUs
133 * it is indexed by the PCI device id or the HT unit id and contains
134 * information about the domain the device belongs to as well as the
135 * page table root pointer.
137 struct dev_table_entry
*amd_iommu_dev_table
;
140 * The alias table is a driver specific data structure which contains the
141 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
142 * More than one device can share the same requestor id.
144 u16
*amd_iommu_alias_table
;
147 * The rlookup table is used to find the IOMMU which is responsible
148 * for a specific device. It is also indexed by the PCI device id.
150 struct amd_iommu
**amd_iommu_rlookup_table
;
153 * The pd table (protection domain table) is used to find the protection domain
154 * data structure a device belongs to. Indexed with the PCI device id too.
156 struct protection_domain
**amd_iommu_pd_table
;
159 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
160 * to know which ones are already in use.
162 unsigned long *amd_iommu_pd_alloc_bitmap
;
164 static u32 dev_table_size
; /* size of the device table */
165 static u32 alias_table_size
; /* size of the alias table */
166 static u32 rlookup_table_size
; /* size if the rlookup table */
168 static inline void update_last_devid(u16 devid
)
170 if (devid
> amd_iommu_last_bdf
)
171 amd_iommu_last_bdf
= devid
;
174 static inline unsigned long tbl_size(int entry_size
)
176 unsigned shift
= PAGE_SHIFT
+
177 get_order(amd_iommu_last_bdf
* entry_size
);
182 /****************************************************************************
184 * AMD IOMMU MMIO register space handling functions
186 * These functions are used to program the IOMMU device registers in
187 * MMIO space required for that driver.
189 ****************************************************************************/
192 * This function set the exclusion range in the IOMMU. DMA accesses to the
193 * exclusion range are passed through untranslated
195 static void __init
iommu_set_exclusion_range(struct amd_iommu
*iommu
)
197 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
198 u64 limit
= (start
+ iommu
->exclusion_length
) & PAGE_MASK
;
201 if (!iommu
->exclusion_start
)
204 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
205 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
206 &entry
, sizeof(entry
));
209 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
210 &entry
, sizeof(entry
));
213 /* Programs the physical address of the device table into the IOMMU hardware */
214 static void __init
iommu_set_device_table(struct amd_iommu
*iommu
)
218 BUG_ON(iommu
->mmio_base
== NULL
);
220 entry
= virt_to_phys(amd_iommu_dev_table
);
221 entry
|= (dev_table_size
>> 12) - 1;
222 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
223 &entry
, sizeof(entry
));
226 /* Generic functions to enable/disable certain features of the IOMMU. */
227 static void __init
iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
231 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
233 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
236 static void __init
iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
240 ctrl
= readl(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
242 writel(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
245 /* Function to enable the hardware */
246 void __init
iommu_enable(struct amd_iommu
*iommu
)
248 printk(KERN_INFO
"AMD IOMMU: Enabling IOMMU "
249 "at %02x:%02x.%x cap 0x%hx\n",
250 iommu
->dev
->bus
->number
,
251 PCI_SLOT(iommu
->dev
->devfn
),
252 PCI_FUNC(iommu
->dev
->devfn
),
255 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
258 /* Function to enable IOMMU event logging and event interrupts */
259 void __init
iommu_enable_event_logging(struct amd_iommu
*iommu
)
261 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
262 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
266 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
267 * the system has one.
269 static u8
* __init
iommu_map_mmio_space(u64 address
)
273 if (!request_mem_region(address
, MMIO_REGION_LENGTH
, "amd_iommu"))
276 ret
= ioremap_nocache(address
, MMIO_REGION_LENGTH
);
280 release_mem_region(address
, MMIO_REGION_LENGTH
);
285 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
287 if (iommu
->mmio_base
)
288 iounmap(iommu
->mmio_base
);
289 release_mem_region(iommu
->mmio_phys
, MMIO_REGION_LENGTH
);
292 /****************************************************************************
294 * The functions below belong to the first pass of AMD IOMMU ACPI table
295 * parsing. In this pass we try to find out the highest device id this
296 * code has to handle. Upon this information the size of the shared data
297 * structures is determined later.
299 ****************************************************************************/
302 * This function calculates the length of a given IVHD entry
304 static inline int ivhd_entry_length(u8
*ivhd
)
306 return 0x04 << (*ivhd
>> 6);
310 * This function reads the last device id the IOMMU has to handle from the PCI
311 * capability header for this IOMMU
313 static int __init
find_last_devid_on_pci(int bus
, int dev
, int fn
, int cap_ptr
)
317 cap
= read_pci_config(bus
, dev
, fn
, cap_ptr
+MMIO_RANGE_OFFSET
);
318 update_last_devid(calc_devid(MMIO_GET_BUS(cap
), MMIO_GET_LD(cap
)));
324 * After reading the highest device id from the IOMMU PCI capability header
325 * this function looks if there is a higher device id defined in the ACPI table
327 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
329 u8
*p
= (void *)h
, *end
= (void *)h
;
330 struct ivhd_entry
*dev
;
335 find_last_devid_on_pci(PCI_BUS(h
->devid
),
341 dev
= (struct ivhd_entry
*)p
;
343 case IVHD_DEV_SELECT
:
344 case IVHD_DEV_RANGE_END
:
346 case IVHD_DEV_EXT_SELECT
:
347 /* all the above subfield types refer to device ids */
348 update_last_devid(dev
->devid
);
353 p
+= ivhd_entry_length(p
);
362 * Iterate over all IVHD entries in the ACPI table and find the highest device
363 * id which we need to handle. This is the first of three functions which parse
364 * the ACPI table. So we check the checksum here.
366 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
369 u8 checksum
= 0, *p
= (u8
*)table
, *end
= (u8
*)table
;
370 struct ivhd_header
*h
;
373 * Validate checksum here so we don't need to do it when
374 * we actually parse the table
376 for (i
= 0; i
< table
->length
; ++i
)
379 /* ACPI table corrupt */
382 p
+= IVRS_HEADER_LENGTH
;
384 end
+= table
->length
;
386 h
= (struct ivhd_header
*)p
;
389 find_last_devid_from_ivhd(h
);
401 /****************************************************************************
403 * The following functions belong the the code path which parses the ACPI table
404 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
405 * data structures, initialize the device/alias/rlookup table and also
406 * basically initialize the hardware.
408 ****************************************************************************/
411 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
412 * write commands to that buffer later and the IOMMU will execute them
415 static u8
* __init
alloc_command_buffer(struct amd_iommu
*iommu
)
417 u8
*cmd_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
418 get_order(CMD_BUFFER_SIZE
));
424 iommu
->cmd_buf_size
= CMD_BUFFER_SIZE
;
426 entry
= (u64
)virt_to_phys(cmd_buf
);
427 entry
|= MMIO_CMD_SIZE_512
;
428 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
429 &entry
, sizeof(entry
));
431 /* set head and tail to zero manually */
432 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
433 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
435 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
440 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
442 free_pages((unsigned long)iommu
->cmd_buf
,
443 get_order(iommu
->cmd_buf_size
));
446 /* allocates the memory where the IOMMU will log its events to */
447 static u8
* __init
alloc_event_buffer(struct amd_iommu
*iommu
)
450 iommu
->evt_buf
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
451 get_order(EVT_BUFFER_SIZE
));
453 if (iommu
->evt_buf
== NULL
)
456 entry
= (u64
)virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
457 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
458 &entry
, sizeof(entry
));
460 iommu
->evt_buf_size
= EVT_BUFFER_SIZE
;
462 return iommu
->evt_buf
;
465 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
467 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
470 /* sets a specific bit in the device table entry. */
471 static void set_dev_entry_bit(u16 devid
, u8 bit
)
473 int i
= (bit
>> 5) & 0x07;
474 int _bit
= bit
& 0x1f;
476 amd_iommu_dev_table
[devid
].data
[i
] |= (1 << _bit
);
479 /* Writes the specific IOMMU for a device into the rlookup table */
480 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
482 amd_iommu_rlookup_table
[devid
] = iommu
;
486 * This function takes the device specific flags read from the ACPI
487 * table and sets up the device table entry with that information
489 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
490 u16 devid
, u32 flags
, u32 ext_flags
)
492 if (flags
& ACPI_DEVFLAG_INITPASS
)
493 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
494 if (flags
& ACPI_DEVFLAG_EXTINT
)
495 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
496 if (flags
& ACPI_DEVFLAG_NMI
)
497 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
498 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
499 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
500 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
501 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
502 if (flags
& ACPI_DEVFLAG_LINT0
)
503 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
504 if (flags
& ACPI_DEVFLAG_LINT1
)
505 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
507 set_iommu_for_device(iommu
, devid
);
511 * Reads the device exclusion range from ACPI and initialize IOMMU with
514 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
516 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
518 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
523 * We only can configure exclusion ranges per IOMMU, not
524 * per device. But we can enable the exclusion range per
525 * device. This is done here
527 set_dev_entry_bit(m
->devid
, DEV_ENTRY_EX
);
528 iommu
->exclusion_start
= m
->range_start
;
529 iommu
->exclusion_length
= m
->range_length
;
534 * This function reads some important data from the IOMMU PCI space and
535 * initializes the driver data structure with it. It reads the hardware
536 * capabilities and the first/last device entries
538 static void __init
init_iommu_from_pci(struct amd_iommu
*iommu
)
540 int cap_ptr
= iommu
->cap_ptr
;
543 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
545 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
547 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
550 iommu
->first_device
= calc_devid(MMIO_GET_BUS(range
),
552 iommu
->last_device
= calc_devid(MMIO_GET_BUS(range
),
554 iommu
->evt_msi_num
= MMIO_MSI_NUM(misc
);
558 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
559 * initializes the hardware and our data structures with it.
561 static void __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
562 struct ivhd_header
*h
)
565 u8
*end
= p
, flags
= 0;
566 u16 dev_i
, devid
= 0, devid_start
= 0, devid_to
= 0;
569 struct ivhd_entry
*e
;
572 * First set the recommended feature enable bits from ACPI
573 * into the IOMMU control registers
575 h
->flags
& IVHD_FLAG_HT_TUN_EN
?
576 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
577 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
579 h
->flags
& IVHD_FLAG_PASSPW_EN
?
580 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
581 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
583 h
->flags
& IVHD_FLAG_RESPASSPW_EN
?
584 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
585 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
587 h
->flags
& IVHD_FLAG_ISOC_EN
?
588 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
589 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
592 * make IOMMU memory accesses cache coherent
594 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
597 * Done. Now parse the device entries
599 p
+= sizeof(struct ivhd_header
);
603 e
= (struct ivhd_entry
*)p
;
606 for (dev_i
= iommu
->first_device
;
607 dev_i
<= iommu
->last_device
; ++dev_i
)
608 set_dev_entry_from_acpi(iommu
, dev_i
,
611 case IVHD_DEV_SELECT
:
613 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
615 case IVHD_DEV_SELECT_RANGE_START
:
616 devid_start
= e
->devid
;
623 devid_to
= e
->ext
>> 8;
624 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
625 amd_iommu_alias_table
[devid
] = devid_to
;
627 case IVHD_DEV_ALIAS_RANGE
:
628 devid_start
= e
->devid
;
630 devid_to
= e
->ext
>> 8;
634 case IVHD_DEV_EXT_SELECT
:
636 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
639 case IVHD_DEV_EXT_SELECT_RANGE
:
640 devid_start
= e
->devid
;
645 case IVHD_DEV_RANGE_END
:
647 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
649 amd_iommu_alias_table
[dev_i
] = devid_to
;
650 set_dev_entry_from_acpi(iommu
,
651 amd_iommu_alias_table
[dev_i
],
659 p
+= ivhd_entry_length(p
);
663 /* Initializes the device->iommu mapping for the driver */
664 static int __init
init_iommu_devices(struct amd_iommu
*iommu
)
668 for (i
= iommu
->first_device
; i
<= iommu
->last_device
; ++i
)
669 set_iommu_for_device(iommu
, i
);
674 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
676 free_command_buffer(iommu
);
677 free_event_buffer(iommu
);
678 iommu_unmap_mmio_space(iommu
);
681 static void __init
free_iommu_all(void)
683 struct amd_iommu
*iommu
, *next
;
685 list_for_each_entry_safe(iommu
, next
, &amd_iommu_list
, list
) {
686 list_del(&iommu
->list
);
687 free_iommu_one(iommu
);
693 * This function clues the initialization function for one IOMMU
694 * together and also allocates the command buffer and programs the
695 * hardware. It does NOT enable the IOMMU. This is done afterwards.
697 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
699 spin_lock_init(&iommu
->lock
);
700 list_add_tail(&iommu
->list
, &amd_iommu_list
);
703 * Copy data from ACPI table entry to the iommu struct
705 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS(h
->devid
), h
->devid
& 0xff);
709 iommu
->cap_ptr
= h
->cap_ptr
;
710 iommu
->pci_seg
= h
->pci_seg
;
711 iommu
->mmio_phys
= h
->mmio_phys
;
712 iommu
->mmio_base
= iommu_map_mmio_space(h
->mmio_phys
);
713 if (!iommu
->mmio_base
)
716 iommu_set_device_table(iommu
);
717 iommu
->cmd_buf
= alloc_command_buffer(iommu
);
721 iommu
->evt_buf
= alloc_event_buffer(iommu
);
725 iommu
->int_enabled
= false;
727 init_iommu_from_pci(iommu
);
728 init_iommu_from_acpi(iommu
, h
);
729 init_iommu_devices(iommu
);
731 return pci_enable_device(iommu
->dev
);
735 * Iterates over all IOMMU entries in the ACPI table, allocates the
736 * IOMMU structure and initializes it with init_iommu_one()
738 static int __init
init_iommu_all(struct acpi_table_header
*table
)
740 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
741 struct ivhd_header
*h
;
742 struct amd_iommu
*iommu
;
745 end
+= table
->length
;
746 p
+= IVRS_HEADER_LENGTH
;
749 h
= (struct ivhd_header
*)p
;
752 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
755 ret
= init_iommu_one(iommu
, h
);
770 /****************************************************************************
772 * The following functions initialize the MSI interrupts for all IOMMUs
773 * in the system. Its a bit challenging because there could be multiple
774 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
777 ****************************************************************************/
779 static int __init
iommu_setup_msix(struct amd_iommu
*iommu
)
781 struct amd_iommu
*curr
;
782 struct msix_entry entries
[32]; /* only 32 supported by AMD IOMMU */
785 list_for_each_entry(curr
, &amd_iommu_list
, list
) {
786 if (curr
->dev
== iommu
->dev
) {
787 entries
[nvec
].entry
= curr
->evt_msi_num
;
788 entries
[nvec
].vector
= 0;
789 curr
->int_enabled
= true;
794 if (pci_enable_msix(iommu
->dev
, entries
, nvec
)) {
795 pci_disable_msix(iommu
->dev
);
799 for (i
= 0; i
< nvec
; ++i
) {
800 int r
= request_irq(entries
->vector
, amd_iommu_int_handler
,
811 for (i
-= 1; i
>= 0; --i
)
812 free_irq(entries
->vector
, NULL
);
814 pci_disable_msix(iommu
->dev
);
819 static int __init
iommu_setup_msi(struct amd_iommu
*iommu
)
822 struct amd_iommu
*curr
;
824 list_for_each_entry(curr
, &amd_iommu_list
, list
) {
825 if (curr
->dev
== iommu
->dev
)
826 curr
->int_enabled
= true;
830 if (pci_enable_msi(iommu
->dev
))
833 r
= request_irq(iommu
->dev
->irq
, amd_iommu_int_handler
,
839 pci_disable_msi(iommu
->dev
);
846 static int __init
iommu_init_msi(struct amd_iommu
*iommu
)
848 if (iommu
->int_enabled
)
851 if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSIX
))
852 return iommu_setup_msix(iommu
);
853 else if (pci_find_capability(iommu
->dev
, PCI_CAP_ID_MSI
))
854 return iommu_setup_msi(iommu
);
859 /****************************************************************************
861 * The next functions belong to the third pass of parsing the ACPI
862 * table. In this last pass the memory mapping requirements are
863 * gathered (like exclusion and unity mapping reanges).
865 ****************************************************************************/
867 static void __init
free_unity_maps(void)
869 struct unity_map_entry
*entry
, *next
;
871 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
872 list_del(&entry
->list
);
877 /* called when we find an exclusion range definition in ACPI */
878 static int __init
init_exclusion_range(struct ivmd_header
*m
)
884 set_device_exclusion_range(m
->devid
, m
);
886 case ACPI_IVMD_TYPE_ALL
:
887 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
888 set_device_exclusion_range(i
, m
);
890 case ACPI_IVMD_TYPE_RANGE
:
891 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
892 set_device_exclusion_range(i
, m
);
901 /* called for unity map ACPI definition */
902 static int __init
init_unity_map_range(struct ivmd_header
*m
)
904 struct unity_map_entry
*e
= 0;
906 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
913 e
->devid_start
= e
->devid_end
= m
->devid
;
915 case ACPI_IVMD_TYPE_ALL
:
917 e
->devid_end
= amd_iommu_last_bdf
;
919 case ACPI_IVMD_TYPE_RANGE
:
920 e
->devid_start
= m
->devid
;
921 e
->devid_end
= m
->aux
;
924 e
->address_start
= PAGE_ALIGN(m
->range_start
);
925 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
926 e
->prot
= m
->flags
>> 1;
928 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
933 /* iterates over all memory definitions we find in the ACPI table */
934 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
936 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
937 struct ivmd_header
*m
;
939 end
+= table
->length
;
940 p
+= IVRS_HEADER_LENGTH
;
943 m
= (struct ivmd_header
*)p
;
944 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
945 init_exclusion_range(m
);
946 else if (m
->flags
& IVMD_FLAG_UNITY_MAP
)
947 init_unity_map_range(m
);
956 * Init the device table to not allow DMA access for devices and
957 * suppress all page faults
959 static void init_device_table(void)
963 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
964 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
965 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
970 * This function finally enables all IOMMUs found in the system after
971 * they have been initialized
973 static void __init
enable_iommus(void)
975 struct amd_iommu
*iommu
;
977 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
978 iommu_set_exclusion_range(iommu
);
979 iommu_init_msi(iommu
);
980 iommu_enable_event_logging(iommu
);
986 * Suspend/Resume support
987 * disable suspend until real resume implemented
990 static int amd_iommu_resume(struct sys_device
*dev
)
995 static int amd_iommu_suspend(struct sys_device
*dev
, pm_message_t state
)
1000 static struct sysdev_class amd_iommu_sysdev_class
= {
1001 .name
= "amd_iommu",
1002 .suspend
= amd_iommu_suspend
,
1003 .resume
= amd_iommu_resume
,
1006 static struct sys_device device_amd_iommu
= {
1008 .cls
= &amd_iommu_sysdev_class
,
1012 * This is the core init function for AMD IOMMU hardware in the system.
1013 * This function is called from the generic x86 DMA layer initialization
1016 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1019 * 1 pass) Find the highest PCI device id the driver has to handle.
1020 * Upon this information the size of the data structures is
1021 * determined that needs to be allocated.
1023 * 2 pass) Initialize the data structures just allocated with the
1024 * information in the ACPI table about available AMD IOMMUs
1025 * in the system. It also maps the PCI devices in the
1026 * system to specific IOMMUs
1028 * 3 pass) After the basic data structures are allocated and
1029 * initialized we update them with information about memory
1030 * remapping requirements parsed out of the ACPI table in
1033 * After that the hardware is initialized and ready to go. In the last
1034 * step we do some Linux specific things like registering the driver in
1035 * the dma_ops interface and initializing the suspend/resume support
1036 * functions. Finally it prints some information about AMD IOMMUs and
1037 * the driver state and enables the hardware.
1039 int __init
amd_iommu_init(void)
1045 printk(KERN_INFO
"AMD IOMMU disabled by kernel command line\n");
1049 if (!amd_iommu_detected
)
1053 * First parse ACPI tables to find the largest Bus/Dev/Func
1054 * we need to handle. Upon this information the shared data
1055 * structures for the IOMMUs in the system will be allocated
1057 if (acpi_table_parse("IVRS", find_last_devid_acpi
) != 0)
1060 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
1061 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
1062 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
1066 /* Device table - directly used by all IOMMUs */
1067 amd_iommu_dev_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1068 get_order(dev_table_size
));
1069 if (amd_iommu_dev_table
== NULL
)
1073 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1074 * IOMMU see for that device
1076 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
1077 get_order(alias_table_size
));
1078 if (amd_iommu_alias_table
== NULL
)
1081 /* IOMMU rlookup table - find the IOMMU for a specific device */
1082 amd_iommu_rlookup_table
= (void *)__get_free_pages(
1083 GFP_KERNEL
| __GFP_ZERO
,
1084 get_order(rlookup_table_size
));
1085 if (amd_iommu_rlookup_table
== NULL
)
1089 * Protection Domain table - maps devices to protection domains
1090 * This table has the same size as the rlookup_table
1092 amd_iommu_pd_table
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
1093 get_order(rlookup_table_size
));
1094 if (amd_iommu_pd_table
== NULL
)
1097 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
1098 GFP_KERNEL
| __GFP_ZERO
,
1099 get_order(MAX_DOMAIN_ID
/8));
1100 if (amd_iommu_pd_alloc_bitmap
== NULL
)
1103 /* init the device table */
1104 init_device_table();
1107 * let all alias entries point to itself
1109 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1110 amd_iommu_alias_table
[i
] = i
;
1113 * never allocate domain 0 because its used as the non-allocated and
1114 * error value placeholder
1116 amd_iommu_pd_alloc_bitmap
[0] = 1;
1119 * now the data structures are allocated and basically initialized
1120 * start the real acpi table scan
1123 if (acpi_table_parse("IVRS", init_iommu_all
) != 0)
1126 if (acpi_table_parse("IVRS", init_memory_definitions
) != 0)
1129 ret
= sysdev_class_register(&amd_iommu_sysdev_class
);
1133 ret
= sysdev_register(&device_amd_iommu
);
1137 ret
= amd_iommu_init_dma_ops();
1143 printk(KERN_INFO
"AMD IOMMU: aperture size is %d MB\n",
1144 (1 << (amd_iommu_aperture_order
-20)));
1146 printk(KERN_INFO
"AMD IOMMU: device isolation ");
1147 if (amd_iommu_isolate
)
1148 printk("enabled\n");
1150 printk("disabled\n");
1152 if (amd_iommu_unmap_flush
)
1153 printk(KERN_INFO
"AMD IOMMU: IO/TLB flush on unmap enabled\n");
1155 printk(KERN_INFO
"AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1161 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
1162 get_order(MAX_DOMAIN_ID
/8));
1164 free_pages((unsigned long)amd_iommu_pd_table
,
1165 get_order(rlookup_table_size
));
1167 free_pages((unsigned long)amd_iommu_rlookup_table
,
1168 get_order(rlookup_table_size
));
1170 free_pages((unsigned long)amd_iommu_alias_table
,
1171 get_order(alias_table_size
));
1173 free_pages((unsigned long)amd_iommu_dev_table
,
1174 get_order(dev_table_size
));
1183 /****************************************************************************
1185 * Early detect code. This code runs at IOMMU detection time in the DMA
1186 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1189 ****************************************************************************/
1190 static int __init
early_amd_iommu_detect(struct acpi_table_header
*table
)
1195 void __init
amd_iommu_detect(void)
1197 if (swiotlb
|| no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
1200 if (acpi_table_parse("IVRS", early_amd_iommu_detect
) == 0) {
1202 amd_iommu_detected
= 1;
1203 #ifdef CONFIG_GART_IOMMU
1204 gart_iommu_aperture_disabled
= 1;
1205 gart_iommu_aperture
= 0;
1210 /****************************************************************************
1212 * Parsing functions for the AMD IOMMU specific kernel command line
1215 ****************************************************************************/
1217 static int __init
parse_amd_iommu_options(char *str
)
1219 for (; *str
; ++str
) {
1220 if (strncmp(str
, "isolate", 7) == 0)
1221 amd_iommu_isolate
= 1;
1222 if (strncmp(str
, "share", 5) == 0)
1223 amd_iommu_isolate
= 0;
1224 if (strncmp(str
, "fullflush", 9) == 0)
1225 amd_iommu_unmap_flush
= true;
1231 static int __init
parse_amd_iommu_size_options(char *str
)
1233 unsigned order
= PAGE_SHIFT
+ get_order(memparse(str
, &str
));
1235 if ((order
> 24) && (order
< 31))
1236 amd_iommu_aperture_order
= order
;
1241 __setup("amd_iommu=", parse_amd_iommu_options
);
1242 __setup("amd_iommu_size=", parse_amd_iommu_size_options
);