2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/smp.h>
37 #include <asm/perf_event.h>
38 #include <asm/x86_init.h>
39 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 #include <asm/kvm_para.h>
55 unsigned int num_processors
;
57 unsigned disabled_cpus __cpuinitdata
;
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid
= -1U;
63 * The highest APIC ID seen during enumeration.
65 unsigned int max_physical_apicid
;
68 * Bitmask of physically existing CPUs:
70 physid_mask_t phys_cpu_present_map
;
73 * Map cpu index to physical APIC ID
75 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
76 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
77 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
82 * Knob to control our willingness to enable the local APIC.
86 static int force_enable_local_apic
;
88 * APIC command line parameters
90 static int __init
parse_lapic(char *arg
)
92 force_enable_local_apic
= 1;
95 early_param("lapic", parse_lapic
);
96 /* Local APIC was disabled by the BIOS and enabled by the kernel */
97 static int enabled_via_apicbase
;
100 * Handle interrupt mode configuration register (IMCR).
101 * This register controls whether the interrupt signals
102 * that reach the BSP come from the master PIC or from the
103 * local APIC. Before entering Symmetric I/O Mode, either
104 * the BIOS or the operating system must switch out of
105 * PIC Mode by changing the IMCR.
107 static inline void imcr_pic_to_apic(void)
109 /* select IMCR register */
111 /* NMI and 8259 INTR go through APIC */
115 static inline void imcr_apic_to_pic(void)
117 /* select IMCR register */
119 /* NMI and 8259 INTR go directly to BSP */
125 static int apic_calibrate_pmtmr __initdata
;
126 static __init
int setup_apicpmtimer(char *s
)
128 apic_calibrate_pmtmr
= 1;
132 __setup("apicpmtimer", setup_apicpmtimer
);
136 #ifdef CONFIG_X86_X2APIC
137 /* x2apic enabled before OS handover */
138 static int x2apic_preenabled
;
139 static __init
int setup_nox2apic(char *str
)
141 if (x2apic_enabled()) {
142 pr_warning("Bios already enabled x2apic, "
143 "can't enforce nox2apic");
147 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
150 early_param("nox2apic", setup_nox2apic
);
153 unsigned long mp_lapic_addr
;
155 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
156 static int disable_apic_timer __cpuinitdata
;
157 /* Local APIC timer works in C2 */
158 int local_apic_timer_c2_ok
;
159 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
161 int first_system_vector
= 0xfe;
164 * Debug level, exported for io_apic.c
166 unsigned int apic_verbosity
;
170 /* Have we found an MP table */
171 int smp_found_config
;
173 static struct resource lapic_resource
= {
174 .name
= "Local APIC",
175 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
178 static unsigned int calibration_result
;
180 static int lapic_next_event(unsigned long delta
,
181 struct clock_event_device
*evt
);
182 static void lapic_timer_setup(enum clock_event_mode mode
,
183 struct clock_event_device
*evt
);
184 static void lapic_timer_broadcast(const struct cpumask
*mask
);
185 static void apic_pm_activate(void);
188 * The local apic timer can be used for any function which is CPU local.
190 static struct clock_event_device lapic_clockevent
= {
192 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
193 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
195 .set_mode
= lapic_timer_setup
,
196 .set_next_event
= lapic_next_event
,
197 .broadcast
= lapic_timer_broadcast
,
201 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
203 static unsigned long apic_phys
;
206 * Get the LAPIC version
208 static inline int lapic_get_version(void)
210 return GET_APIC_VERSION(apic_read(APIC_LVR
));
214 * Check, if the APIC is integrated or a separate chip
216 static inline int lapic_is_integrated(void)
221 return APIC_INTEGRATED(lapic_get_version());
226 * Check, whether this is a modern or a first generation APIC
228 static int modern_apic(void)
230 /* AMD systems use old APIC versions, so check the CPU */
231 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
232 boot_cpu_data
.x86
>= 0xf)
234 return lapic_get_version() >= 0x14;
238 * right after this call apic become NOOP driven
239 * so apic->write/read doesn't do anything
241 void apic_disable(void)
243 pr_info("APIC: switched to apic NOOP\n");
247 void native_apic_wait_icr_idle(void)
249 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
253 u32
native_safe_apic_wait_icr_idle(void)
260 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
264 } while (timeout
++ < 1000);
269 void native_apic_icr_write(u32 low
, u32 id
)
271 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
272 apic_write(APIC_ICR
, low
);
275 u64
native_apic_icr_read(void)
279 icr2
= apic_read(APIC_ICR2
);
280 icr1
= apic_read(APIC_ICR
);
282 return icr1
| ((u64
)icr2
<< 32);
286 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
288 void __cpuinit
enable_NMI_through_LVT0(void)
292 /* unmask and set to NMI */
295 /* Level triggered for 82489DX (32bit mode) */
296 if (!lapic_is_integrated())
297 v
|= APIC_LVT_LEVEL_TRIGGER
;
299 apic_write(APIC_LVT0
, v
);
304 * get_physical_broadcast - Get number of physical broadcast IDs
306 int get_physical_broadcast(void)
308 return modern_apic() ? 0xff : 0xf;
313 * lapic_get_maxlvt - get the maximum number of local vector table entries
315 int lapic_get_maxlvt(void)
319 v
= apic_read(APIC_LVR
);
321 * - we always have APIC integrated on 64bit mode
322 * - 82489DXs do not report # of LVT entries
324 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
332 #define APIC_DIVISOR 16
335 * This function sets up the local APIC timer, with a timeout of
336 * 'clocks' APIC bus clock. During calibration we actually call
337 * this function twice on the boot CPU, once with a bogus timeout
338 * value, second time for real. The other (noncalibrating) CPUs
339 * call this function only once, with the real, calibrated value.
341 * We do reads before writes even if unnecessary, to get around the
342 * P5 APIC double write bug.
344 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
346 unsigned int lvtt_value
, tmp_value
;
348 lvtt_value
= LOCAL_TIMER_VECTOR
;
350 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
351 if (!lapic_is_integrated())
352 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
355 lvtt_value
|= APIC_LVT_MASKED
;
357 apic_write(APIC_LVTT
, lvtt_value
);
362 tmp_value
= apic_read(APIC_TDCR
);
363 apic_write(APIC_TDCR
,
364 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
368 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
372 * Setup extended LVT, AMD specific
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
391 static atomic_t eilvt_offsets
[APIC_EILVT_NR_MAX
];
393 static inline int eilvt_entry_is_changeable(unsigned int old
, unsigned int new)
395 return (old
& APIC_EILVT_MASKED
)
396 || (new == APIC_EILVT_MASKED
)
397 || ((new & ~APIC_EILVT_MASKED
) == old
);
400 static unsigned int reserve_eilvt_offset(int offset
, unsigned int new)
402 unsigned int rsvd
; /* 0: uninitialized */
404 if (offset
>= APIC_EILVT_NR_MAX
)
407 rsvd
= atomic_read(&eilvt_offsets
[offset
]) & ~APIC_EILVT_MASKED
;
410 !eilvt_entry_is_changeable(rsvd
, new))
411 /* may not change if vectors are different */
413 rsvd
= atomic_cmpxchg(&eilvt_offsets
[offset
], rsvd
, new);
414 } while (rsvd
!= new);
420 * If mask=1, the LVT entry does not generate interrupts while mask=0
421 * enables the vector. See also the BKDGs.
424 int setup_APIC_eilvt(u8 offset
, u8 vector
, u8 msg_type
, u8 mask
)
426 unsigned long reg
= APIC_EILVTn(offset
);
427 unsigned int new, old
, reserved
;
429 new = (mask
<< 16) | (msg_type
<< 8) | vector
;
430 old
= apic_read(reg
);
431 reserved
= reserve_eilvt_offset(offset
, new);
433 if (reserved
!= new) {
434 pr_err(FW_BUG
"cpu %d, try to setup vector 0x%x, but "
435 "vector 0x%x was already reserved by another core, "
437 smp_processor_id(), new, reserved
, reg
, old
);
441 if (!eilvt_entry_is_changeable(old
, new)) {
442 pr_err(FW_BUG
"cpu %d, try to setup vector 0x%x but "
443 "register already in use, APIC%lX=0x%x\n",
444 smp_processor_id(), new, reg
, old
);
448 apic_write(reg
, new);
452 EXPORT_SYMBOL_GPL(setup_APIC_eilvt
);
455 * Program the next event, relative to now
457 static int lapic_next_event(unsigned long delta
,
458 struct clock_event_device
*evt
)
460 apic_write(APIC_TMICT
, delta
);
465 * Setup the lapic timer in periodic or oneshot mode
467 static void lapic_timer_setup(enum clock_event_mode mode
,
468 struct clock_event_device
*evt
)
473 /* Lapic used as dummy for broadcast ? */
474 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
477 local_irq_save(flags
);
480 case CLOCK_EVT_MODE_PERIODIC
:
481 case CLOCK_EVT_MODE_ONESHOT
:
482 __setup_APIC_LVTT(calibration_result
,
483 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
485 case CLOCK_EVT_MODE_UNUSED
:
486 case CLOCK_EVT_MODE_SHUTDOWN
:
487 v
= apic_read(APIC_LVTT
);
488 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
489 apic_write(APIC_LVTT
, v
);
490 apic_write(APIC_TMICT
, 0);
492 case CLOCK_EVT_MODE_RESUME
:
493 /* Nothing to do here */
497 local_irq_restore(flags
);
501 * Local APIC timer broadcast function
503 static void lapic_timer_broadcast(const struct cpumask
*mask
)
506 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
511 * Setup the local APIC timer for this CPU. Copy the initialized values
512 * of the boot CPU and register the clock event in the framework.
514 static void __cpuinit
setup_APIC_timer(void)
516 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
518 if (cpu_has(¤t_cpu_data
, X86_FEATURE_ARAT
)) {
519 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_C3STOP
;
520 /* Make LAPIC timer preferrable over percpu HPET */
521 lapic_clockevent
.rating
= 150;
524 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
525 levt
->cpumask
= cpumask_of(smp_processor_id());
527 clockevents_register_device(levt
);
531 * In this functions we calibrate APIC bus clocks to the external timer.
533 * We want to do the calibration only once since we want to have local timer
534 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
537 * This was previously done by reading the PIT/HPET and waiting for a wrap
538 * around to find out, that a tick has elapsed. I have a box, where the PIT
539 * readout is broken, so it never gets out of the wait loop again. This was
540 * also reported by others.
542 * Monitoring the jiffies value is inaccurate and the clockevents
543 * infrastructure allows us to do a simple substitution of the interrupt
546 * The calibration routine also uses the pm_timer when possible, as the PIT
547 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
548 * back to normal later in the boot process).
551 #define LAPIC_CAL_LOOPS (HZ/10)
553 static __initdata
int lapic_cal_loops
= -1;
554 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
555 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
556 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
557 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
560 * Temporary interrupt handler.
562 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
564 unsigned long long tsc
= 0;
565 long tapic
= apic_read(APIC_TMCCT
);
566 unsigned long pm
= acpi_pm_read_early();
571 switch (lapic_cal_loops
++) {
573 lapic_cal_t1
= tapic
;
574 lapic_cal_tsc1
= tsc
;
576 lapic_cal_j1
= jiffies
;
579 case LAPIC_CAL_LOOPS
:
580 lapic_cal_t2
= tapic
;
581 lapic_cal_tsc2
= tsc
;
582 if (pm
< lapic_cal_pm1
)
583 pm
+= ACPI_PM_OVRRUN
;
585 lapic_cal_j2
= jiffies
;
591 calibrate_by_pmtimer(long deltapm
, long *delta
, long *deltatsc
)
593 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
594 const long pm_thresh
= pm_100ms
/ 100;
598 #ifndef CONFIG_X86_PM_TIMER
602 apic_printk(APIC_VERBOSE
, "... PM-Timer delta = %ld\n", deltapm
);
604 /* Check, if the PM timer is available */
608 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
610 if (deltapm
> (pm_100ms
- pm_thresh
) &&
611 deltapm
< (pm_100ms
+ pm_thresh
)) {
612 apic_printk(APIC_VERBOSE
, "... PM-Timer result ok\n");
616 res
= (((u64
)deltapm
) * mult
) >> 22;
617 do_div(res
, 1000000);
618 pr_warning("APIC calibration not consistent "
619 "with PM-Timer: %ldms instead of 100ms\n",(long)res
);
621 /* Correct the lapic counter value */
622 res
= (((u64
)(*delta
)) * pm_100ms
);
623 do_div(res
, deltapm
);
624 pr_info("APIC delta adjusted to PM-Timer: "
625 "%lu (%ld)\n", (unsigned long)res
, *delta
);
628 /* Correct the tsc counter value */
630 res
= (((u64
)(*deltatsc
)) * pm_100ms
);
631 do_div(res
, deltapm
);
632 apic_printk(APIC_VERBOSE
, "TSC delta adjusted to "
633 "PM-Timer: %lu (%ld)\n",
634 (unsigned long)res
, *deltatsc
);
635 *deltatsc
= (long)res
;
641 static int __init
calibrate_APIC_clock(void)
643 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
644 void (*real_handler
)(struct clock_event_device
*dev
);
645 unsigned long deltaj
;
646 long delta
, deltatsc
;
647 int pm_referenced
= 0;
651 /* Replace the global interrupt handler */
652 real_handler
= global_clock_event
->event_handler
;
653 global_clock_event
->event_handler
= lapic_cal_handler
;
656 * Setup the APIC counter to maximum. There is no way the lapic
657 * can underflow in the 100ms detection time frame
659 __setup_APIC_LVTT(0xffffffff, 0, 0);
661 /* Let the interrupts run */
664 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
669 /* Restore the real event handler */
670 global_clock_event
->event_handler
= real_handler
;
672 /* Build delta t1-t2 as apic timer counts down */
673 delta
= lapic_cal_t1
- lapic_cal_t2
;
674 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
676 deltatsc
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
678 /* we trust the PM based calibration if possible */
679 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
682 /* Calculate the scaled math multiplication factor */
683 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
684 lapic_clockevent
.shift
);
685 lapic_clockevent
.max_delta_ns
=
686 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
687 lapic_clockevent
.min_delta_ns
=
688 clockevent_delta2ns(0xF, &lapic_clockevent
);
690 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
692 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
693 apic_printk(APIC_VERBOSE
, "..... mult: %u\n", lapic_clockevent
.mult
);
694 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
698 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
700 (deltatsc
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
701 (deltatsc
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
704 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
706 calibration_result
/ (1000000 / HZ
),
707 calibration_result
% (1000000 / HZ
));
710 * Do a sanity check on the APIC calibration result
712 if (calibration_result
< (1000000 / HZ
)) {
714 pr_warning("APIC frequency too slow, disabling apic timer\n");
718 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
721 * PM timer calibration failed or not turned on
722 * so lets try APIC timer based calibration
724 if (!pm_referenced
) {
725 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
728 * Setup the apic timer manually
730 levt
->event_handler
= lapic_cal_handler
;
731 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
732 lapic_cal_loops
= -1;
734 /* Let the interrupts run */
737 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
740 /* Stop the lapic timer */
741 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
744 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
745 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
747 /* Check, if the jiffies result is consistent */
748 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
749 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
751 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
755 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
756 pr_warning("APIC timer disabled due to verification failure\n");
764 * Setup the boot APIC
766 * Calibrate and verify the result.
768 void __init
setup_boot_APIC_clock(void)
771 * The local apic timer can be disabled via the kernel
772 * commandline or from the CPU detection code. Register the lapic
773 * timer as a dummy clock event source on SMP systems, so the
774 * broadcast mechanism is used. On UP systems simply ignore it.
776 if (disable_apic_timer
) {
777 pr_info("Disabling APIC timer\n");
778 /* No broadcast on UP ! */
779 if (num_possible_cpus() > 1) {
780 lapic_clockevent
.mult
= 1;
786 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
787 "calibrating APIC timer ...\n");
789 if (calibrate_APIC_clock()) {
790 /* No broadcast on UP ! */
791 if (num_possible_cpus() > 1)
797 * If nmi_watchdog is set to IO_APIC, we need the
798 * PIT/HPET going. Otherwise register lapic as a dummy
801 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
803 /* Setup the lapic or request the broadcast */
807 void __cpuinit
setup_secondary_APIC_clock(void)
813 * The guts of the apic timer interrupt
815 static void local_apic_timer_interrupt(void)
817 int cpu
= smp_processor_id();
818 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
821 * Normally we should not be here till LAPIC has been initialized but
822 * in some cases like kdump, its possible that there is a pending LAPIC
823 * timer interrupt from previous kernel's context and is delivered in
824 * new kernel the moment interrupts are enabled.
826 * Interrupts are enabled early and LAPIC is setup much later, hence
827 * its possible that when we get here evt->event_handler is NULL.
828 * Check for event_handler being NULL and discard the interrupt as
831 if (!evt
->event_handler
) {
832 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
834 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
839 * the NMI deadlock-detector uses this.
841 inc_irq_stat(apic_timer_irqs
);
843 evt
->event_handler(evt
);
847 * Local APIC timer interrupt. This is the most natural way for doing
848 * local interrupts, but local timer interrupts can be emulated by
849 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
851 * [ if a single-CPU system runs an SMP kernel then we call the local
852 * interrupt as well. Thus we cannot inline the local irq ... ]
854 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
856 struct pt_regs
*old_regs
= set_irq_regs(regs
);
859 * NOTE! We'd better ACK the irq immediately,
860 * because timer handling can be slow.
864 * update_process_times() expects us to have done irq_enter().
865 * Besides, if we don't timer interrupts ignore the global
866 * interrupt lock, which is the WrongThing (tm) to do.
870 local_apic_timer_interrupt();
873 set_irq_regs(old_regs
);
876 int setup_profiling_timer(unsigned int multiplier
)
882 * Local APIC start and shutdown
886 * clear_local_APIC - shutdown the local APIC
888 * This is called, when a CPU is disabled and before rebooting, so the state of
889 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
890 * leftovers during boot.
892 void clear_local_APIC(void)
897 /* APIC hasn't been mapped yet */
898 if (!x2apic_mode
&& !apic_phys
)
901 maxlvt
= lapic_get_maxlvt();
903 * Masking an LVT entry can trigger a local APIC error
904 * if the vector is zero. Mask LVTERR first to prevent this.
907 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
908 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
911 * Careful: we have to set masks only first to deassert
912 * any level-triggered sources.
914 v
= apic_read(APIC_LVTT
);
915 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
916 v
= apic_read(APIC_LVT0
);
917 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
918 v
= apic_read(APIC_LVT1
);
919 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
921 v
= apic_read(APIC_LVTPC
);
922 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
925 /* lets not touch this if we didn't frob it */
926 #ifdef CONFIG_X86_THERMAL_VECTOR
928 v
= apic_read(APIC_LVTTHMR
);
929 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
932 #ifdef CONFIG_X86_MCE_INTEL
934 v
= apic_read(APIC_LVTCMCI
);
935 if (!(v
& APIC_LVT_MASKED
))
936 apic_write(APIC_LVTCMCI
, v
| APIC_LVT_MASKED
);
941 * Clean APIC state for other OSs:
943 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
944 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
945 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
947 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
949 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
951 /* Integrated APIC (!82489DX) ? */
952 if (lapic_is_integrated()) {
954 /* Clear ESR due to Pentium errata 3AP and 11AP */
955 apic_write(APIC_ESR
, 0);
961 * disable_local_APIC - clear and disable the local APIC
963 void disable_local_APIC(void)
967 /* APIC hasn't been mapped yet */
968 if (!x2apic_mode
&& !apic_phys
)
974 * Disable APIC (implies clearing of registers
977 value
= apic_read(APIC_SPIV
);
978 value
&= ~APIC_SPIV_APIC_ENABLED
;
979 apic_write(APIC_SPIV
, value
);
983 * When LAPIC was disabled by the BIOS and enabled by the kernel,
984 * restore the disabled state.
986 if (enabled_via_apicbase
) {
989 rdmsr(MSR_IA32_APICBASE
, l
, h
);
990 l
&= ~MSR_IA32_APICBASE_ENABLE
;
991 wrmsr(MSR_IA32_APICBASE
, l
, h
);
997 * If Linux enabled the LAPIC against the BIOS default disable it down before
998 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
999 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1000 * for the case where Linux didn't enable the LAPIC.
1002 void lapic_shutdown(void)
1004 unsigned long flags
;
1006 if (!cpu_has_apic
&& !apic_from_smp_config())
1009 local_irq_save(flags
);
1011 #ifdef CONFIG_X86_32
1012 if (!enabled_via_apicbase
)
1016 disable_local_APIC();
1019 local_irq_restore(flags
);
1023 * This is to verify that we're looking at a real local APIC.
1024 * Check these against your board if the CPUs aren't getting
1025 * started for no apparent reason.
1027 int __init
verify_local_APIC(void)
1029 unsigned int reg0
, reg1
;
1032 * The version register is read-only in a real APIC.
1034 reg0
= apic_read(APIC_LVR
);
1035 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
1036 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
1037 reg1
= apic_read(APIC_LVR
);
1038 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
1041 * The two version reads above should print the same
1042 * numbers. If the second one is different, then we
1043 * poke at a non-APIC.
1049 * Check if the version looks reasonably.
1051 reg1
= GET_APIC_VERSION(reg0
);
1052 if (reg1
== 0x00 || reg1
== 0xff)
1054 reg1
= lapic_get_maxlvt();
1055 if (reg1
< 0x02 || reg1
== 0xff)
1059 * The ID register is read/write in a real APIC.
1061 reg0
= apic_read(APIC_ID
);
1062 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1063 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1064 reg1
= apic_read(APIC_ID
);
1065 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1066 apic_write(APIC_ID
, reg0
);
1067 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1071 * The next two are just to see if we have sane values.
1072 * They're only really relevant if we're in Virtual Wire
1073 * compatibility mode, but most boxes are anymore.
1075 reg0
= apic_read(APIC_LVT0
);
1076 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1077 reg1
= apic_read(APIC_LVT1
);
1078 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1084 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1086 void __init
sync_Arb_IDs(void)
1089 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1092 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1098 apic_wait_icr_idle();
1100 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1101 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1102 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1106 * An initial setup of the virtual wire mode.
1108 void __init
init_bsp_APIC(void)
1113 * Don't do the setup now if we have a SMP BIOS as the
1114 * through-I/O-APIC virtual wire mode might be active.
1116 if (smp_found_config
|| !cpu_has_apic
)
1120 * Do not trust the local APIC being empty at bootup.
1127 value
= apic_read(APIC_SPIV
);
1128 value
&= ~APIC_VECTOR_MASK
;
1129 value
|= APIC_SPIV_APIC_ENABLED
;
1131 #ifdef CONFIG_X86_32
1132 /* This bit is reserved on P4/Xeon and should be cleared */
1133 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1134 (boot_cpu_data
.x86
== 15))
1135 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1138 value
|= APIC_SPIV_FOCUS_DISABLED
;
1139 value
|= SPURIOUS_APIC_VECTOR
;
1140 apic_write(APIC_SPIV
, value
);
1143 * Set up the virtual wire mode.
1145 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1146 value
= APIC_DM_NMI
;
1147 if (!lapic_is_integrated()) /* 82489DX */
1148 value
|= APIC_LVT_LEVEL_TRIGGER
;
1149 apic_write(APIC_LVT1
, value
);
1152 static void __cpuinit
lapic_setup_esr(void)
1154 unsigned int oldvalue
, value
, maxlvt
;
1156 if (!lapic_is_integrated()) {
1157 pr_info("No ESR for 82489DX.\n");
1161 if (apic
->disable_esr
) {
1163 * Something untraceable is creating bad interrupts on
1164 * secondary quads ... for the moment, just leave the
1165 * ESR disabled - we can't do anything useful with the
1166 * errors anyway - mbligh
1168 pr_info("Leaving ESR disabled.\n");
1172 maxlvt
= lapic_get_maxlvt();
1173 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1174 apic_write(APIC_ESR
, 0);
1175 oldvalue
= apic_read(APIC_ESR
);
1177 /* enables sending errors */
1178 value
= ERROR_APIC_VECTOR
;
1179 apic_write(APIC_LVTERR
, value
);
1182 * spec says clear errors after enabling vector.
1185 apic_write(APIC_ESR
, 0);
1186 value
= apic_read(APIC_ESR
);
1187 if (value
!= oldvalue
)
1188 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1189 "vector: 0x%08x after: 0x%08x\n",
1195 * setup_local_APIC - setup the local APIC
1197 void __cpuinit
setup_local_APIC(void)
1199 unsigned int value
, queued
;
1200 int i
, j
, acked
= 0;
1201 unsigned long long tsc
= 0, ntsc
;
1202 long long max_loops
= cpu_khz
;
1208 arch_disable_smp_support();
1212 #ifdef CONFIG_X86_32
1213 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1214 if (lapic_is_integrated() && apic
->disable_esr
) {
1215 apic_write(APIC_ESR
, 0);
1216 apic_write(APIC_ESR
, 0);
1217 apic_write(APIC_ESR
, 0);
1218 apic_write(APIC_ESR
, 0);
1221 perf_events_lapic_init();
1226 * Double-check whether this APIC is really registered.
1227 * This is meaningless in clustered apic mode, so we skip it.
1229 BUG_ON(!apic
->apic_id_registered());
1232 * Intel recommends to set DFR, LDR and TPR before enabling
1233 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1234 * document number 292116). So here it goes...
1236 apic
->init_apic_ldr();
1239 * Set Task Priority to 'accept all'. We never change this
1242 value
= apic_read(APIC_TASKPRI
);
1243 value
&= ~APIC_TPRI_MASK
;
1244 apic_write(APIC_TASKPRI
, value
);
1247 * After a crash, we no longer service the interrupts and a pending
1248 * interrupt from previous kernel might still have ISR bit set.
1250 * Most probably by now CPU has serviced that pending interrupt and
1251 * it might not have done the ack_APIC_irq() because it thought,
1252 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1253 * does not clear the ISR bit and cpu thinks it has already serivced
1254 * the interrupt. Hence a vector might get locked. It was noticed
1255 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1259 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--)
1260 queued
|= apic_read(APIC_IRR
+ i
*0x10);
1262 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1263 value
= apic_read(APIC_ISR
+ i
*0x10);
1264 for (j
= 31; j
>= 0; j
--) {
1265 if (value
& (1<<j
)) {
1272 printk(KERN_ERR
"LAPIC pending interrupts after %d EOI\n",
1278 max_loops
= (cpu_khz
<< 10) - (ntsc
- tsc
);
1281 } while (queued
&& max_loops
> 0);
1282 WARN_ON(max_loops
<= 0);
1285 * Now that we are all set up, enable the APIC
1287 value
= apic_read(APIC_SPIV
);
1288 value
&= ~APIC_VECTOR_MASK
;
1292 value
|= APIC_SPIV_APIC_ENABLED
;
1294 #ifdef CONFIG_X86_32
1296 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1297 * certain networking cards. If high frequency interrupts are
1298 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1299 * entry is masked/unmasked at a high rate as well then sooner or
1300 * later IOAPIC line gets 'stuck', no more interrupts are received
1301 * from the device. If focus CPU is disabled then the hang goes
1304 * [ This bug can be reproduced easily with a level-triggered
1305 * PCI Ne2000 networking cards and PII/PIII processors, dual
1309 * Actually disabling the focus CPU check just makes the hang less
1310 * frequent as it makes the interrupt distributon model be more
1311 * like LRU than MRU (the short-term load is more even across CPUs).
1312 * See also the comment in end_level_ioapic_irq(). --macro
1316 * - enable focus processor (bit==0)
1317 * - 64bit mode always use processor focus
1318 * so no need to set it
1320 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1324 * Set spurious IRQ vector
1326 value
|= SPURIOUS_APIC_VECTOR
;
1327 apic_write(APIC_SPIV
, value
);
1330 * Set up LVT0, LVT1:
1332 * set up through-local-APIC on the BP's LINT0. This is not
1333 * strictly necessary in pure symmetric-IO mode, but sometimes
1334 * we delegate interrupts to the 8259A.
1337 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1339 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1340 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1341 value
= APIC_DM_EXTINT
;
1342 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1343 smp_processor_id());
1345 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1346 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1347 smp_processor_id());
1349 apic_write(APIC_LVT0
, value
);
1352 * only the BP should see the LINT1 NMI signal, obviously.
1354 if (!smp_processor_id())
1355 value
= APIC_DM_NMI
;
1357 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1358 if (!lapic_is_integrated()) /* 82489DX */
1359 value
|= APIC_LVT_LEVEL_TRIGGER
;
1360 apic_write(APIC_LVT1
, value
);
1364 #ifdef CONFIG_X86_MCE_INTEL
1365 /* Recheck CMCI information after local APIC is up on CPU #0 */
1366 if (smp_processor_id() == 0)
1371 void __cpuinit
end_local_APIC_setup(void)
1375 #ifdef CONFIG_X86_32
1378 /* Disable the local apic timer */
1379 value
= apic_read(APIC_LVTT
);
1380 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1381 apic_write(APIC_LVTT
, value
);
1388 * Now that local APIC setup is completed for BP, configure the fault
1389 * handling for interrupt remapping.
1391 if (!smp_processor_id() && intr_remapping_enabled
)
1392 enable_drhd_fault_handling();
1396 #ifdef CONFIG_X86_X2APIC
1397 void check_x2apic(void)
1399 if (x2apic_enabled()) {
1400 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1401 x2apic_preenabled
= x2apic_mode
= 1;
1405 void enable_x2apic(void)
1412 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1413 if (!(msr
& X2APIC_ENABLE
)) {
1414 printk_once(KERN_INFO
"Enabling x2apic\n");
1415 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1418 #endif /* CONFIG_X86_X2APIC */
1420 int __init
enable_IR(void)
1422 #ifdef CONFIG_INTR_REMAP
1423 if (!intr_remapping_supported()) {
1424 pr_debug("intr-remapping not supported\n");
1428 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1429 pr_info("Skipped enabling intr-remap because of skipping "
1434 if (enable_intr_remapping(x2apic_supported()))
1437 pr_info("Enabled Interrupt-remapping\n");
1445 void __init
enable_IR_x2apic(void)
1447 unsigned long flags
;
1448 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
1449 int ret
, x2apic_enabled
= 0;
1450 int dmar_table_init_ret
;
1452 dmar_table_init_ret
= dmar_table_init();
1453 if (dmar_table_init_ret
&& !x2apic_supported())
1456 ioapic_entries
= alloc_ioapic_entries();
1457 if (!ioapic_entries
) {
1458 pr_err("Allocate ioapic_entries failed\n");
1462 ret
= save_IO_APIC_setup(ioapic_entries
);
1464 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1468 local_irq_save(flags
);
1469 legacy_pic
->mask_all();
1470 mask_IO_APIC_setup(ioapic_entries
);
1472 if (dmar_table_init_ret
)
1478 /* IR is required if there is APIC ID > 255 even when running
1481 if (max_physical_apicid
> 255 || !kvm_para_available())
1484 * without IR all CPUs can be addressed by IOAPIC/MSI
1485 * only in physical mode
1487 x2apic_force_phys();
1492 if (x2apic_supported() && !x2apic_mode
) {
1495 pr_info("Enabled x2apic\n");
1499 if (!ret
) /* IR enabling failed */
1500 restore_IO_APIC_setup(ioapic_entries
);
1501 legacy_pic
->restore_mask();
1502 local_irq_restore(flags
);
1506 free_ioapic_entries(ioapic_entries
);
1511 if (x2apic_preenabled
)
1512 panic("x2apic: enabled by BIOS but kernel init failed.");
1513 else if (cpu_has_x2apic
)
1514 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1517 #ifdef CONFIG_X86_64
1519 * Detect and enable local APICs on non-SMP boards.
1520 * Original code written by Keir Fraser.
1521 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1522 * not correctly set up (usually the APIC timer won't work etc.)
1524 static int __init
detect_init_APIC(void)
1526 if (!cpu_has_apic
) {
1527 pr_info("No local APIC present\n");
1531 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1536 * Detect and initialize APIC
1538 static int __init
detect_init_APIC(void)
1542 /* Disabled by kernel option? */
1546 switch (boot_cpu_data
.x86_vendor
) {
1547 case X86_VENDOR_AMD
:
1548 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1549 (boot_cpu_data
.x86
>= 15))
1552 case X86_VENDOR_INTEL
:
1553 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1554 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1561 if (!cpu_has_apic
) {
1563 * Over-ride BIOS and try to enable the local APIC only if
1564 * "lapic" specified.
1566 if (!force_enable_local_apic
) {
1567 pr_info("Local APIC disabled by BIOS -- "
1568 "you can enable it with \"lapic\"\n");
1572 * Some BIOSes disable the local APIC in the APIC_BASE
1573 * MSR. This can only be done in software for Intel P6 or later
1574 * and AMD K7 (Model > 1) or later.
1576 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1577 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1578 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1579 l
&= ~MSR_IA32_APICBASE_BASE
;
1580 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1581 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1582 enabled_via_apicbase
= 1;
1586 * The APIC feature bit should now be enabled
1589 features
= cpuid_edx(1);
1590 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1591 pr_warning("Could not enable APIC!\n");
1594 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1595 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1597 /* The BIOS may have set up the APIC at some other address */
1598 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1599 if (l
& MSR_IA32_APICBASE_ENABLE
)
1600 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1602 pr_info("Found and enabled local APIC!\n");
1609 pr_info("No local APIC present or hardware disabled\n");
1614 #ifdef CONFIG_X86_64
1615 void __init
early_init_lapic_mapping(void)
1618 * If no local APIC can be found then go out
1619 * : it means there is no mpatable and MADT
1621 if (!smp_found_config
)
1624 set_fixmap_nocache(FIX_APIC_BASE
, mp_lapic_addr
);
1625 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1626 APIC_BASE
, mp_lapic_addr
);
1629 * Fetch the APIC ID of the BSP in case we have a
1630 * default configuration (or the MP table is broken).
1632 boot_cpu_physical_apicid
= read_apic_id();
1637 * init_apic_mappings - initialize APIC mappings
1639 void __init
init_apic_mappings(void)
1641 unsigned int new_apicid
;
1644 boot_cpu_physical_apicid
= read_apic_id();
1648 /* If no local APIC can be found return early */
1649 if (!smp_found_config
&& detect_init_APIC()) {
1650 /* lets NOP'ify apic operations */
1651 pr_info("APIC: disable apic facility\n");
1654 apic_phys
= mp_lapic_addr
;
1657 * acpi lapic path already maps that address in
1658 * acpi_register_lapic_address()
1660 if (!acpi_lapic
&& !smp_found_config
)
1661 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1663 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1664 APIC_BASE
, apic_phys
);
1668 * Fetch the APIC ID of the BSP in case we have a
1669 * default configuration (or the MP table is broken).
1671 new_apicid
= read_apic_id();
1672 if (boot_cpu_physical_apicid
!= new_apicid
) {
1673 boot_cpu_physical_apicid
= new_apicid
;
1675 * yeah -- we lie about apic_version
1676 * in case if apic was disabled via boot option
1677 * but it's not a problem for SMP compiled kernel
1678 * since smp_sanity_check is prepared for such a case
1679 * and disable smp mode
1681 apic_version
[new_apicid
] =
1682 GET_APIC_VERSION(apic_read(APIC_LVR
));
1687 * This initializes the IO-APIC and APIC hardware if this is
1690 int apic_version
[MAX_APICS
];
1692 int __init
APIC_init_uniprocessor(void)
1695 pr_info("Apic disabled\n");
1698 #ifdef CONFIG_X86_64
1699 if (!cpu_has_apic
) {
1701 pr_info("Apic disabled by BIOS\n");
1705 if (!smp_found_config
&& !cpu_has_apic
)
1709 * Complain if the BIOS pretends there is one.
1711 if (!cpu_has_apic
&&
1712 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1713 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1714 boot_cpu_physical_apicid
);
1719 default_setup_apic_routing();
1721 verify_local_APIC();
1724 #ifdef CONFIG_X86_64
1725 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1728 * Hack: In case of kdump, after a crash, kernel might be booting
1729 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1730 * might be zero if read from MP tables. Get it from LAPIC.
1732 # ifdef CONFIG_CRASH_DUMP
1733 boot_cpu_physical_apicid
= read_apic_id();
1736 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1739 #ifdef CONFIG_X86_IO_APIC
1741 * Now enable IO-APICs, actually call clear_IO_APIC
1742 * We need clear_IO_APIC before enabling error vector
1744 if (!skip_ioapic_setup
&& nr_ioapics
)
1748 end_local_APIC_setup();
1750 #ifdef CONFIG_X86_IO_APIC
1751 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1758 x86_init
.timers
.setup_percpu_clockev();
1763 * Local APIC interrupts
1767 * This interrupt should _never_ happen with our APIC/SMP architecture
1769 void smp_spurious_interrupt(struct pt_regs
*regs
)
1776 * Check if this really is a spurious interrupt and ACK it
1777 * if it is a vectored one. Just in case...
1778 * Spurious interrupts should not be ACKed.
1780 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1781 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1784 inc_irq_stat(irq_spurious_count
);
1786 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1787 pr_info("spurious APIC interrupt on CPU#%d, "
1788 "should never happen.\n", smp_processor_id());
1793 * This interrupt should never happen with our APIC/SMP architecture
1795 void smp_error_interrupt(struct pt_regs
*regs
)
1801 /* First tickle the hardware, only then report what went on. -- REW */
1802 v
= apic_read(APIC_ESR
);
1803 apic_write(APIC_ESR
, 0);
1804 v1
= apic_read(APIC_ESR
);
1806 atomic_inc(&irq_err_count
);
1809 * Here is what the APIC error bits mean:
1811 * 1: Receive CS error
1812 * 2: Send accept error
1813 * 3: Receive accept error
1815 * 5: Send illegal vector
1816 * 6: Received illegal vector
1817 * 7: Illegal register address
1819 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1820 smp_processor_id(), v
, v1
);
1825 * connect_bsp_APIC - attach the APIC to the interrupt system
1827 void __init
connect_bsp_APIC(void)
1829 #ifdef CONFIG_X86_32
1832 * Do not trust the local APIC being empty at bootup.
1836 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1837 * local APIC to INT and NMI lines.
1839 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1840 "enabling APIC mode.\n");
1844 if (apic
->enable_apic_mode
)
1845 apic
->enable_apic_mode();
1849 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1850 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1852 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1855 void disconnect_bsp_APIC(int virt_wire_setup
)
1859 #ifdef CONFIG_X86_32
1862 * Put the board back into PIC mode (has an effect only on
1863 * certain older boards). Note that APIC interrupts, including
1864 * IPIs, won't work beyond this point! The only exception are
1867 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1868 "entering PIC mode.\n");
1874 /* Go back to Virtual Wire compatibility mode */
1876 /* For the spurious interrupt use vector F, and enable it */
1877 value
= apic_read(APIC_SPIV
);
1878 value
&= ~APIC_VECTOR_MASK
;
1879 value
|= APIC_SPIV_APIC_ENABLED
;
1881 apic_write(APIC_SPIV
, value
);
1883 if (!virt_wire_setup
) {
1885 * For LVT0 make it edge triggered, active high,
1886 * external and enabled
1888 value
= apic_read(APIC_LVT0
);
1889 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1890 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1891 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1892 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1893 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1894 apic_write(APIC_LVT0
, value
);
1897 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1901 * For LVT1 make it edge triggered, active high,
1904 value
= apic_read(APIC_LVT1
);
1905 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1906 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1907 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1908 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1909 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1910 apic_write(APIC_LVT1
, value
);
1913 void __cpuinit
generic_processor_info(int apicid
, int version
)
1920 if (version
== 0x0) {
1921 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1922 "fixing up to 0x10. (tell your hw vendor)\n",
1926 apic_version
[apicid
] = version
;
1928 if (num_processors
>= nr_cpu_ids
) {
1929 int max
= nr_cpu_ids
;
1930 int thiscpu
= max
+ disabled_cpus
;
1933 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1934 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1941 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1943 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1945 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1946 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1948 physid_set(apicid
, phys_cpu_present_map
);
1949 if (apicid
== boot_cpu_physical_apicid
) {
1951 * x86_bios_cpu_apicid is required to have processors listed
1952 * in same order as logical cpu numbers. Hence the first
1953 * entry is BSP, and so on.
1957 if (apicid
> max_physical_apicid
)
1958 max_physical_apicid
= apicid
;
1960 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1961 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1962 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1965 set_cpu_possible(cpu
, true);
1966 set_cpu_present(cpu
, true);
1969 int hard_smp_processor_id(void)
1971 return read_apic_id();
1974 void default_init_apic_ldr(void)
1978 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1979 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1980 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1981 apic_write(APIC_LDR
, val
);
1984 #ifdef CONFIG_X86_32
1985 int default_apicid_to_node(int logical_apicid
)
1988 return apicid_2_node
[hard_smp_processor_id()];
2002 * 'active' is true if the local APIC was enabled by us and
2003 * not the BIOS; this signifies that we are also responsible
2004 * for disabling it before entering apm/acpi suspend
2007 /* r/w apic fields */
2008 unsigned int apic_id
;
2009 unsigned int apic_taskpri
;
2010 unsigned int apic_ldr
;
2011 unsigned int apic_dfr
;
2012 unsigned int apic_spiv
;
2013 unsigned int apic_lvtt
;
2014 unsigned int apic_lvtpc
;
2015 unsigned int apic_lvt0
;
2016 unsigned int apic_lvt1
;
2017 unsigned int apic_lvterr
;
2018 unsigned int apic_tmict
;
2019 unsigned int apic_tdcr
;
2020 unsigned int apic_thmr
;
2023 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2025 unsigned long flags
;
2028 if (!apic_pm_state
.active
)
2031 maxlvt
= lapic_get_maxlvt();
2033 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
2034 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
2035 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
2036 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
2037 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
2038 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
2040 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
2041 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
2042 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
2043 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
2044 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
2045 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
2046 #ifdef CONFIG_X86_THERMAL_VECTOR
2048 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
2051 local_irq_save(flags
);
2052 disable_local_APIC();
2054 if (intr_remapping_enabled
)
2055 disable_intr_remapping();
2057 local_irq_restore(flags
);
2061 static int lapic_resume(struct sys_device
*dev
)
2064 unsigned long flags
;
2067 struct IO_APIC_route_entry
**ioapic_entries
= NULL
;
2069 if (!apic_pm_state
.active
)
2072 local_irq_save(flags
);
2073 if (intr_remapping_enabled
) {
2074 ioapic_entries
= alloc_ioapic_entries();
2075 if (!ioapic_entries
) {
2076 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2081 ret
= save_IO_APIC_setup(ioapic_entries
);
2083 WARN(1, "Saving IO-APIC state failed: %d\n", ret
);
2084 free_ioapic_entries(ioapic_entries
);
2088 mask_IO_APIC_setup(ioapic_entries
);
2089 legacy_pic
->mask_all();
2096 * Make sure the APICBASE points to the right address
2098 * FIXME! This will be wrong if we ever support suspend on
2099 * SMP! We'll need to do this as part of the CPU restore!
2101 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2102 l
&= ~MSR_IA32_APICBASE_BASE
;
2103 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2104 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2107 maxlvt
= lapic_get_maxlvt();
2108 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2109 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2110 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2111 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2112 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2113 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2114 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2115 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2116 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2118 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2121 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2122 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2123 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2124 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2125 apic_write(APIC_ESR
, 0);
2126 apic_read(APIC_ESR
);
2127 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2128 apic_write(APIC_ESR
, 0);
2129 apic_read(APIC_ESR
);
2131 if (intr_remapping_enabled
) {
2132 reenable_intr_remapping(x2apic_mode
);
2133 legacy_pic
->restore_mask();
2134 restore_IO_APIC_setup(ioapic_entries
);
2135 free_ioapic_entries(ioapic_entries
);
2138 local_irq_restore(flags
);
2144 * This device has no shutdown method - fully functioning local APICs
2145 * are needed on every CPU up until machine_halt/restart/poweroff.
2148 static struct sysdev_class lapic_sysclass
= {
2150 .resume
= lapic_resume
,
2151 .suspend
= lapic_suspend
,
2154 static struct sys_device device_lapic
= {
2156 .cls
= &lapic_sysclass
,
2159 static void __cpuinit
apic_pm_activate(void)
2161 apic_pm_state
.active
= 1;
2164 static int __init
init_lapic_sysfs(void)
2170 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2172 error
= sysdev_class_register(&lapic_sysclass
);
2174 error
= sysdev_register(&device_lapic
);
2178 /* local apic needs to resume before other devices access its registers. */
2179 core_initcall(init_lapic_sysfs
);
2181 #else /* CONFIG_PM */
2183 static void apic_pm_activate(void) { }
2185 #endif /* CONFIG_PM */
2187 #ifdef CONFIG_X86_64
2189 static int __cpuinit
apic_cluster_num(void)
2191 int i
, clusters
, zeros
;
2193 u16
*bios_cpu_apicid
;
2194 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2196 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2197 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2199 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2200 /* are we being called early in kernel startup? */
2201 if (bios_cpu_apicid
) {
2202 id
= bios_cpu_apicid
[i
];
2203 } else if (i
< nr_cpu_ids
) {
2205 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2211 if (id
!= BAD_APICID
)
2212 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2215 /* Problem: Partially populated chassis may not have CPUs in some of
2216 * the APIC clusters they have been allocated. Only present CPUs have
2217 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2218 * Since clusters are allocated sequentially, count zeros only if
2219 * they are bounded by ones.
2223 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2224 if (test_bit(i
, clustermap
)) {
2225 clusters
+= 1 + zeros
;
2234 static int __cpuinitdata multi_checked
;
2235 static int __cpuinitdata multi
;
2237 static int __cpuinit
set_multi(const struct dmi_system_id
*d
)
2241 pr_info("APIC: %s detected, Multi Chassis\n", d
->ident
);
2246 static const __cpuinitconst
struct dmi_system_id multi_dmi_table
[] = {
2248 .callback
= set_multi
,
2249 .ident
= "IBM System Summit2",
2251 DMI_MATCH(DMI_SYS_VENDOR
, "IBM"),
2252 DMI_MATCH(DMI_PRODUCT_NAME
, "Summit2"),
2258 static void __cpuinit
dmi_check_multi(void)
2263 dmi_check_system(multi_dmi_table
);
2268 * apic_is_clustered_box() -- Check if we can expect good TSC
2270 * Thus far, the major user of this is IBM's Summit2 series:
2271 * Clustered boxes may have unsynced TSC problems if they are
2273 * Use DMI to check them
2275 __cpuinit
int apic_is_clustered_box(void)
2285 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2286 * not guaranteed to be synced between boards
2288 if (apic_cluster_num() > 1)
2296 * APIC command line parameters
2298 static int __init
setup_disableapic(char *arg
)
2301 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2304 early_param("disableapic", setup_disableapic
);
2306 /* same as disableapic, for compatibility */
2307 static int __init
setup_nolapic(char *arg
)
2309 return setup_disableapic(arg
);
2311 early_param("nolapic", setup_nolapic
);
2313 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2315 local_apic_timer_c2_ok
= 1;
2318 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2320 static int __init
parse_disable_apic_timer(char *arg
)
2322 disable_apic_timer
= 1;
2325 early_param("noapictimer", parse_disable_apic_timer
);
2327 static int __init
parse_nolapic_timer(char *arg
)
2329 disable_apic_timer
= 1;
2332 early_param("nolapic_timer", parse_nolapic_timer
);
2334 static int __init
apic_set_verbosity(char *arg
)
2337 #ifdef CONFIG_X86_64
2338 skip_ioapic_setup
= 0;
2344 if (strcmp("debug", arg
) == 0)
2345 apic_verbosity
= APIC_DEBUG
;
2346 else if (strcmp("verbose", arg
) == 0)
2347 apic_verbosity
= APIC_VERBOSE
;
2349 pr_warning("APIC Verbosity level %s not recognised"
2350 " use apic=verbose or apic=debug\n", arg
);
2356 early_param("apic", apic_set_verbosity
);
2358 static int __init
lapic_insert_resource(void)
2363 /* Put local APIC into the resource map. */
2364 lapic_resource
.start
= apic_phys
;
2365 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2366 insert_resource(&iomem_resource
, &lapic_resource
);
2372 * need call insert after e820_reserve_resources()
2373 * that is using request_resource
2375 late_initcall(lapic_insert_resource
);