2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug
= -1;
75 static DEFINE_SPINLOCK(ioapic_lock
);
76 static DEFINE_SPINLOCK(vector_lock
);
79 * # of IRQ routing registers
81 int nr_ioapic_registers
[MAX_IO_APICS
];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
97 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
99 int skip_ioapic_setup
;
101 void arch_disable_smp_support(void)
105 noioapicreroute
= -1;
107 skip_ioapic_setup
= 1;
110 static int __init
parse_noapic(char *str
)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic
);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list
{
129 struct irq_pin_list
*next
;
132 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
134 struct irq_pin_list
*pin
;
137 node
= cpu_to_node(cpu
);
139 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
145 struct irq_pin_list
*irq_2_pin
;
146 cpumask_var_t domain
;
147 cpumask_var_t old_domain
;
148 unsigned move_cleanup_count
;
150 u8 move_in_progress
: 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending
: 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx
[] = {
160 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
162 [0] = { .vector
= IRQ0_VECTOR
, },
163 [1] = { .vector
= IRQ1_VECTOR
, },
164 [2] = { .vector
= IRQ2_VECTOR
, },
165 [3] = { .vector
= IRQ3_VECTOR
, },
166 [4] = { .vector
= IRQ4_VECTOR
, },
167 [5] = { .vector
= IRQ5_VECTOR
, },
168 [6] = { .vector
= IRQ6_VECTOR
, },
169 [7] = { .vector
= IRQ7_VECTOR
, },
170 [8] = { .vector
= IRQ8_VECTOR
, },
171 [9] = { .vector
= IRQ9_VECTOR
, },
172 [10] = { .vector
= IRQ10_VECTOR
, },
173 [11] = { .vector
= IRQ11_VECTOR
, },
174 [12] = { .vector
= IRQ12_VECTOR
, },
175 [13] = { .vector
= IRQ13_VECTOR
, },
176 [14] = { .vector
= IRQ14_VECTOR
, },
177 [15] = { .vector
= IRQ15_VECTOR
, },
180 int __init
arch_early_irq_init(void)
183 struct irq_desc
*desc
;
188 count
= ARRAY_SIZE(irq_cfgx
);
190 for (i
= 0; i
< count
; i
++) {
191 desc
= irq_to_desc(i
);
192 desc
->chip_data
= &cfg
[i
];
193 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
194 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
195 if (i
< NR_IRQS_LEGACY
)
196 cpumask_setall(cfg
[i
].domain
);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg
*irq_cfg(unsigned int irq
)
205 struct irq_cfg
*cfg
= NULL
;
206 struct irq_desc
*desc
;
208 desc
= irq_to_desc(irq
);
210 cfg
= desc
->chip_data
;
215 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
220 node
= cpu_to_node(cpu
);
222 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
224 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
227 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
229 free_cpumask_var(cfg
->domain
);
233 cpumask_clear(cfg
->domain
);
234 cpumask_clear(cfg
->old_domain
);
241 int arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
245 cfg
= desc
->chip_data
;
247 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
248 if (!desc
->chip_data
) {
249 printk(KERN_ERR
"can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
262 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
264 cfg
->irq_2_pin
= NULL
;
265 old_entry
= old_cfg
->irq_2_pin
;
269 entry
= get_one_free_irq_2_pin(cpu
);
273 entry
->apic
= old_entry
->apic
;
274 entry
->pin
= old_entry
->pin
;
277 old_entry
= old_entry
->next
;
279 entry
= get_one_free_irq_2_pin(cpu
);
287 /* still use the old one */
290 entry
->apic
= old_entry
->apic
;
291 entry
->pin
= old_entry
->pin
;
294 old_entry
= old_entry
->next
;
298 cfg
->irq_2_pin
= head
;
301 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
303 struct irq_pin_list
*entry
, *next
;
305 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
308 entry
= old_cfg
->irq_2_pin
;
315 old_cfg
->irq_2_pin
= NULL
;
318 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
319 struct irq_desc
*desc
, int cpu
)
322 struct irq_cfg
*old_cfg
;
324 cfg
= get_one_free_irq_cfg(cpu
);
329 desc
->chip_data
= cfg
;
331 old_cfg
= old_desc
->chip_data
;
333 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
335 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
338 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
343 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
345 struct irq_cfg
*old_cfg
, *cfg
;
347 old_cfg
= old_desc
->chip_data
;
348 cfg
= desc
->chip_data
;
354 free_irq_2_pin(old_cfg
, cfg
);
355 free_irq_cfg(old_cfg
);
356 old_desc
->chip_data
= NULL
;
361 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
363 struct irq_cfg
*cfg
= desc
->chip_data
;
365 if (!cfg
->move_in_progress
) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc
->affinity
, mask
))
368 cfg
->move_desc_pending
= 1;
374 static struct irq_cfg
*irq_cfg(unsigned int irq
)
376 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
390 unsigned int unused
[3];
392 unsigned int unused2
[11];
396 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
398 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
399 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
402 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
405 writel(vector
, &io_apic
->eoi
);
408 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
410 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
411 writel(reg
, &io_apic
->index
);
412 return readl(&io_apic
->data
);
415 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
417 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
418 writel(reg
, &io_apic
->index
);
419 writel(value
, &io_apic
->data
);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
430 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
433 writel(reg
, &io_apic
->index
);
434 writel(value
, &io_apic
->data
);
437 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
439 struct irq_pin_list
*entry
;
442 spin_lock_irqsave(&ioapic_lock
, flags
);
443 entry
= cfg
->irq_2_pin
;
451 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
452 /* Is the remote IRR bit set? */
453 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
454 spin_unlock_irqrestore(&ioapic_lock
, flags
);
461 spin_unlock_irqrestore(&ioapic_lock
, flags
);
467 struct { u32 w1
, w2
; };
468 struct IO_APIC_route_entry entry
;
471 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
473 union entry_union eu
;
475 spin_lock_irqsave(&ioapic_lock
, flags
);
476 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
477 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
478 spin_unlock_irqrestore(&ioapic_lock
, flags
);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
491 union entry_union eu
;
493 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
494 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
497 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
500 spin_lock_irqsave(&ioapic_lock
, flags
);
501 __ioapic_write_entry(apic
, pin
, e
);
502 spin_unlock_irqrestore(&ioapic_lock
, flags
);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic
, int pin
)
513 union entry_union eu
= { .entry
.mask
= 1 };
515 spin_lock_irqsave(&ioapic_lock
, flags
);
516 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
517 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
518 spin_unlock_irqrestore(&ioapic_lock
, flags
);
522 static void send_cleanup_vector(struct irq_cfg
*cfg
)
524 cpumask_var_t cleanup_mask
;
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
528 cfg
->move_cleanup_count
= 0;
529 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
530 cfg
->move_cleanup_count
++;
531 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
532 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
534 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
535 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
536 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
537 free_cpumask_var(cleanup_mask
);
539 cfg
->move_in_progress
= 0;
542 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
545 struct irq_pin_list
*entry
;
546 u8 vector
= cfg
->vector
;
548 entry
= cfg
->irq_2_pin
;
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
561 if (!irq_remapped(irq
))
562 io_apic_write(apic
, 0x11 + pin
*2, dest
);
563 reg
= io_apic_read(apic
, 0x10 + pin
*2);
564 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
566 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
574 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
582 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
587 if (!cpumask_intersects(mask
, cpu_online_mask
))
591 cfg
= desc
->chip_data
;
592 if (assign_irq_vector(irq
, cfg
, mask
))
595 /* check that before desc->addinity get updated */
596 set_extra_move_desc(desc
, mask
);
598 cpumask_copy(desc
->affinity
, mask
);
600 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
604 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
612 cfg
= desc
->chip_data
;
614 spin_lock_irqsave(&ioapic_lock
, flags
);
615 dest
= set_desc_affinity(desc
, mask
);
616 if (dest
!= BAD_APICID
) {
617 /* Only the high 8 bits are valid. */
618 dest
= SET_APIC_LOGICAL_ID(dest
);
619 __target_IO_APIC_irq(irq
, dest
, cfg
);
621 spin_unlock_irqrestore(&ioapic_lock
, flags
);
625 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
627 struct irq_desc
*desc
;
629 desc
= irq_to_desc(irq
);
631 set_ioapic_affinity_irq_desc(desc
, mask
);
633 #endif /* CONFIG_SMP */
636 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
637 * shared ISA-space IRQs, so we have to support them. We are super
638 * fast in the common case, and fast for shared ISA-space IRQs.
640 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
642 struct irq_pin_list
*entry
;
644 entry
= cfg
->irq_2_pin
;
646 entry
= get_one_free_irq_2_pin(cpu
);
648 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
652 cfg
->irq_2_pin
= entry
;
658 while (entry
->next
) {
659 /* not again, please */
660 if (entry
->apic
== apic
&& entry
->pin
== pin
)
666 entry
->next
= get_one_free_irq_2_pin(cpu
);
673 * Reroute an IRQ to a different pin.
675 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
676 int oldapic
, int oldpin
,
677 int newapic
, int newpin
)
679 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
683 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
684 entry
->apic
= newapic
;
687 /* every one is different, right? */
693 /* why? call replace before add? */
695 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
698 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
699 int mask_and
, int mask_or
,
700 void (*final
)(struct irq_pin_list
*entry
))
703 struct irq_pin_list
*entry
;
705 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
708 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
711 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
717 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
719 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
723 static void io_apic_sync(struct irq_pin_list
*entry
)
726 * Synchronize the IO-APIC and the CPU by doing
727 * a dummy read from the IO-APIC
729 struct io_apic __iomem
*io_apic
;
730 io_apic
= io_apic_base(entry
->apic
);
731 readl(&io_apic
->data
);
734 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
736 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
738 #else /* CONFIG_X86_32 */
739 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
741 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
744 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
746 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
747 IO_APIC_REDIR_MASKED
, NULL
);
750 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
752 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
753 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
755 #endif /* CONFIG_X86_32 */
757 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
759 struct irq_cfg
*cfg
= desc
->chip_data
;
764 spin_lock_irqsave(&ioapic_lock
, flags
);
765 __mask_IO_APIC_irq(cfg
);
766 spin_unlock_irqrestore(&ioapic_lock
, flags
);
769 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
771 struct irq_cfg
*cfg
= desc
->chip_data
;
774 spin_lock_irqsave(&ioapic_lock
, flags
);
775 __unmask_IO_APIC_irq(cfg
);
776 spin_unlock_irqrestore(&ioapic_lock
, flags
);
779 static void mask_IO_APIC_irq(unsigned int irq
)
781 struct irq_desc
*desc
= irq_to_desc(irq
);
783 mask_IO_APIC_irq_desc(desc
);
785 static void unmask_IO_APIC_irq(unsigned int irq
)
787 struct irq_desc
*desc
= irq_to_desc(irq
);
789 unmask_IO_APIC_irq_desc(desc
);
792 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
794 struct IO_APIC_route_entry entry
;
796 /* Check delivery_mode to be sure we're not clearing an SMI pin */
797 entry
= ioapic_read_entry(apic
, pin
);
798 if (entry
.delivery_mode
== dest_SMI
)
801 * Disable it in the IO-APIC irq-routing table:
803 ioapic_mask_entry(apic
, pin
);
806 static void clear_IO_APIC (void)
810 for (apic
= 0; apic
< nr_ioapics
; apic
++)
811 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
812 clear_IO_APIC_pin(apic
, pin
);
817 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
818 * specific CPU-side IRQs.
822 static int pirq_entries
[MAX_PIRQS
] = {
823 [0 ... MAX_PIRQS
- 1] = -1
826 static int __init
ioapic_pirq_setup(char *str
)
829 int ints
[MAX_PIRQS
+1];
831 get_options(str
, ARRAY_SIZE(ints
), ints
);
833 apic_printk(APIC_VERBOSE
, KERN_INFO
834 "PIRQ redirection, working around broken MP-BIOS.\n");
836 if (ints
[0] < MAX_PIRQS
)
839 for (i
= 0; i
< max
; i
++) {
840 apic_printk(APIC_VERBOSE
, KERN_DEBUG
841 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
843 * PIRQs are mapped upside down, usually.
845 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
850 __setup("pirq=", ioapic_pirq_setup
);
851 #endif /* CONFIG_X86_32 */
853 #ifdef CONFIG_INTR_REMAP
854 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
857 struct IO_APIC_route_entry
**ioapic_entries
;
859 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
864 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
865 ioapic_entries
[apic
] =
866 kzalloc(sizeof(struct IO_APIC_route_entry
) *
867 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
868 if (!ioapic_entries
[apic
])
872 return ioapic_entries
;
876 kfree(ioapic_entries
[apic
]);
877 kfree(ioapic_entries
);
883 * Saves all the IO-APIC RTE's
885 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
892 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
893 if (!ioapic_entries
[apic
])
896 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
897 ioapic_entries
[apic
][pin
] =
898 ioapic_read_entry(apic
, pin
);
905 * Mask all IO APIC entries.
907 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
914 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
915 if (!ioapic_entries
[apic
])
918 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
919 struct IO_APIC_route_entry entry
;
921 entry
= ioapic_entries
[apic
][pin
];
924 ioapic_write_entry(apic
, pin
, entry
);
931 * Restore IO APIC entries which was saved in ioapic_entries.
933 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
940 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
941 if (!ioapic_entries
[apic
])
944 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
945 ioapic_write_entry(apic
, pin
,
946 ioapic_entries
[apic
][pin
]);
951 void reinit_intr_remapped_IO_APIC(int intr_remapping
,
952 struct IO_APIC_route_entry
**ioapic_entries
)
956 * for now plain restore of previous settings.
957 * TBD: In the case of OS enabling interrupt-remapping,
958 * IO-APIC RTE's need to be setup to point to interrupt-remapping
959 * table entries. for now, do a plain restore, and wait for
960 * the setup_IO_APIC_irqs() to do proper initialization.
962 restore_IO_APIC_setup(ioapic_entries
);
965 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
969 for (apic
= 0; apic
< nr_ioapics
; apic
++)
970 kfree(ioapic_entries
[apic
]);
972 kfree(ioapic_entries
);
977 * Find the IRQ entry number of a certain pin.
979 static int find_irq_entry(int apic
, int pin
, int type
)
983 for (i
= 0; i
< mp_irq_entries
; i
++)
984 if (mp_irqs
[i
].irqtype
== type
&&
985 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
986 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
987 mp_irqs
[i
].dstirq
== pin
)
994 * Find the pin to which IRQ[irq] (ISA) is connected
996 static int __init
find_isa_irq_pin(int irq
, int type
)
1000 for (i
= 0; i
< mp_irq_entries
; i
++) {
1001 int lbus
= mp_irqs
[i
].srcbus
;
1003 if (test_bit(lbus
, mp_bus_not_pci
) &&
1004 (mp_irqs
[i
].irqtype
== type
) &&
1005 (mp_irqs
[i
].srcbusirq
== irq
))
1007 return mp_irqs
[i
].dstirq
;
1012 static int __init
find_isa_irq_apic(int irq
, int type
)
1016 for (i
= 0; i
< mp_irq_entries
; i
++) {
1017 int lbus
= mp_irqs
[i
].srcbus
;
1019 if (test_bit(lbus
, mp_bus_not_pci
) &&
1020 (mp_irqs
[i
].irqtype
== type
) &&
1021 (mp_irqs
[i
].srcbusirq
== irq
))
1024 if (i
< mp_irq_entries
) {
1026 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1027 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
1036 * Find a specific PCI IRQ entry.
1037 * Not an __init, possibly needed by modules
1039 static int pin_2_irq(int idx
, int apic
, int pin
);
1041 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1043 int apic
, i
, best_guess
= -1;
1045 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1047 if (test_bit(bus
, mp_bus_not_pci
)) {
1048 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1051 for (i
= 0; i
< mp_irq_entries
; i
++) {
1052 int lbus
= mp_irqs
[i
].srcbus
;
1054 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1055 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1056 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1059 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1060 !mp_irqs
[i
].irqtype
&&
1062 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1063 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1065 if (!(apic
|| IO_APIC_IRQ(irq
)))
1068 if (pin
== (mp_irqs
[i
].srcbusirq
& 3))
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1081 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1083 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1085 * EISA Edge/Level control register, ELCR
1087 static int EISA_ELCR(unsigned int irq
)
1089 if (irq
< NR_IRQS_LEGACY
) {
1090 unsigned int port
= 0x4d0 + (irq
>> 3);
1091 return (inb(port
) >> (irq
& 7)) & 1;
1093 apic_printk(APIC_VERBOSE
, KERN_INFO
1094 "Broken MPtable reports ISA irq %d\n", irq
);
1100 /* ISA interrupts are always polarity zero edge triggered,
1101 * when listed as conforming in the MP table. */
1103 #define default_ISA_trigger(idx) (0)
1104 #define default_ISA_polarity(idx) (0)
1106 /* EISA interrupts are always polarity zero and can be edge or level
1107 * trigger depending on the ELCR value. If an interrupt is listed as
1108 * EISA conforming in the MP table, that means its trigger type must
1109 * be read in from the ELCR */
1111 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1112 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1114 /* PCI interrupts are always polarity one level triggered,
1115 * when listed as conforming in the MP table. */
1117 #define default_PCI_trigger(idx) (1)
1118 #define default_PCI_polarity(idx) (1)
1120 /* MCA interrupts are always polarity zero level triggered,
1121 * when listed as conforming in the MP table. */
1123 #define default_MCA_trigger(idx) (1)
1124 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1126 static int MPBIOS_polarity(int idx
)
1128 int bus
= mp_irqs
[idx
].srcbus
;
1132 * Determine IRQ line polarity (high active or low active):
1134 switch (mp_irqs
[idx
].irqflag
& 3)
1136 case 0: /* conforms, ie. bus-type dependent polarity */
1137 if (test_bit(bus
, mp_bus_not_pci
))
1138 polarity
= default_ISA_polarity(idx
);
1140 polarity
= default_PCI_polarity(idx
);
1142 case 1: /* high active */
1147 case 2: /* reserved */
1149 printk(KERN_WARNING
"broken BIOS!!\n");
1153 case 3: /* low active */
1158 default: /* invalid */
1160 printk(KERN_WARNING
"broken BIOS!!\n");
1168 static int MPBIOS_trigger(int idx
)
1170 int bus
= mp_irqs
[idx
].srcbus
;
1174 * Determine IRQ trigger mode (edge or level sensitive):
1176 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
1178 case 0: /* conforms, ie. bus-type dependent */
1179 if (test_bit(bus
, mp_bus_not_pci
))
1180 trigger
= default_ISA_trigger(idx
);
1182 trigger
= default_PCI_trigger(idx
);
1183 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1184 switch (mp_bus_id_to_type
[bus
]) {
1185 case MP_BUS_ISA
: /* ISA pin */
1187 /* set before the switch */
1190 case MP_BUS_EISA
: /* EISA pin */
1192 trigger
= default_EISA_trigger(idx
);
1195 case MP_BUS_PCI
: /* PCI pin */
1197 /* set before the switch */
1200 case MP_BUS_MCA
: /* MCA pin */
1202 trigger
= default_MCA_trigger(idx
);
1207 printk(KERN_WARNING
"broken BIOS!!\n");
1219 case 2: /* reserved */
1221 printk(KERN_WARNING
"broken BIOS!!\n");
1230 default: /* invalid */
1232 printk(KERN_WARNING
"broken BIOS!!\n");
1240 static inline int irq_polarity(int idx
)
1242 return MPBIOS_polarity(idx
);
1245 static inline int irq_trigger(int idx
)
1247 return MPBIOS_trigger(idx
);
1250 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1251 static int pin_2_irq(int idx
, int apic
, int pin
)
1254 int bus
= mp_irqs
[idx
].srcbus
;
1257 * Debugging check, we are in big trouble if this message pops up!
1259 if (mp_irqs
[idx
].dstirq
!= pin
)
1260 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1262 if (test_bit(bus
, mp_bus_not_pci
)) {
1263 irq
= mp_irqs
[idx
].srcbusirq
;
1266 * PCI IRQs are mapped in order
1270 irq
+= nr_ioapic_registers
[i
++];
1273 * For MPS mode, so far only needed by ES7000 platform
1275 if (ioapic_renumber_irq
)
1276 irq
= ioapic_renumber_irq(apic
, irq
);
1279 #ifdef CONFIG_X86_32
1281 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1283 if ((pin
>= 16) && (pin
<= 23)) {
1284 if (pirq_entries
[pin
-16] != -1) {
1285 if (!pirq_entries
[pin
-16]) {
1286 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1287 "disabling PIRQ%d\n", pin
-16);
1289 irq
= pirq_entries
[pin
-16];
1290 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1291 "using PIRQ%d -> IRQ %d\n",
1301 void lock_vector_lock(void)
1303 /* Used to the online set of cpus does not change
1304 * during assign_irq_vector.
1306 spin_lock(&vector_lock
);
1309 void unlock_vector_lock(void)
1311 spin_unlock(&vector_lock
);
1315 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1318 * NOTE! The local APIC isn't very good at handling
1319 * multiple interrupts at the same interrupt level.
1320 * As the interrupt level is determined by taking the
1321 * vector number and shifting that right by 4, we
1322 * want to spread these out a bit so that they don't
1323 * all fall in the same interrupt level.
1325 * Also, we've got to be careful not to trash gate
1326 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1328 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1329 unsigned int old_vector
;
1331 cpumask_var_t tmp_mask
;
1333 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1336 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1339 old_vector
= cfg
->vector
;
1341 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1342 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1343 if (!cpumask_empty(tmp_mask
)) {
1344 free_cpumask_var(tmp_mask
);
1349 /* Only try and allocate irqs on cpus that are present */
1351 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1355 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1357 vector
= current_vector
;
1358 offset
= current_offset
;
1361 if (vector
>= first_system_vector
) {
1362 /* If out of vectors on large boxen, must share them. */
1363 offset
= (offset
+ 1) % 8;
1364 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1366 if (unlikely(current_vector
== vector
))
1369 if (test_bit(vector
, used_vectors
))
1372 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1373 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1376 current_vector
= vector
;
1377 current_offset
= offset
;
1379 cfg
->move_in_progress
= 1;
1380 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1382 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1383 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1384 cfg
->vector
= vector
;
1385 cpumask_copy(cfg
->domain
, tmp_mask
);
1389 free_cpumask_var(tmp_mask
);
1394 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1397 unsigned long flags
;
1399 spin_lock_irqsave(&vector_lock
, flags
);
1400 err
= __assign_irq_vector(irq
, cfg
, mask
);
1401 spin_unlock_irqrestore(&vector_lock
, flags
);
1405 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1409 BUG_ON(!cfg
->vector
);
1411 vector
= cfg
->vector
;
1412 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1413 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1416 cpumask_clear(cfg
->domain
);
1418 if (likely(!cfg
->move_in_progress
))
1420 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1421 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1423 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1425 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1429 cfg
->move_in_progress
= 0;
1432 void __setup_vector_irq(int cpu
)
1434 /* Initialize vector_irq on a new cpu */
1435 /* This function must be called with vector_lock held */
1437 struct irq_cfg
*cfg
;
1438 struct irq_desc
*desc
;
1440 /* Mark the inuse vectors */
1441 for_each_irq_desc(irq
, desc
) {
1442 cfg
= desc
->chip_data
;
1443 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1445 vector
= cfg
->vector
;
1446 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1448 /* Mark the free vectors */
1449 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1450 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1455 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1456 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1460 static struct irq_chip ioapic_chip
;
1461 static struct irq_chip ir_ioapic_chip
;
1463 #define IOAPIC_AUTO -1
1464 #define IOAPIC_EDGE 0
1465 #define IOAPIC_LEVEL 1
1467 #ifdef CONFIG_X86_32
1468 static inline int IO_APIC_irq_trigger(int irq
)
1472 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1473 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1474 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1475 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1476 return irq_trigger(idx
);
1480 * nonexistent IRQs are edge default
1485 static inline int IO_APIC_irq_trigger(int irq
)
1491 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1494 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1495 trigger
== IOAPIC_LEVEL
)
1496 desc
->status
|= IRQ_LEVEL
;
1498 desc
->status
&= ~IRQ_LEVEL
;
1500 if (irq_remapped(irq
)) {
1501 desc
->status
|= IRQ_MOVE_PCNTXT
;
1503 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1507 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1508 handle_edge_irq
, "edge");
1512 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1513 trigger
== IOAPIC_LEVEL
)
1514 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1518 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1519 handle_edge_irq
, "edge");
1522 int setup_ioapic_entry(int apic_id
, int irq
,
1523 struct IO_APIC_route_entry
*entry
,
1524 unsigned int destination
, int trigger
,
1525 int polarity
, int vector
, int pin
)
1528 * add it to the IO-APIC irq-routing table:
1530 memset(entry
,0,sizeof(*entry
));
1532 if (intr_remapping_enabled
) {
1533 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1535 struct IR_IO_APIC_route_entry
*ir_entry
=
1536 (struct IR_IO_APIC_route_entry
*) entry
;
1540 panic("No mapping iommu for ioapic %d\n", apic_id
);
1542 index
= alloc_irte(iommu
, irq
, 1);
1544 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1546 memset(&irte
, 0, sizeof(irte
));
1549 irte
.dst_mode
= apic
->irq_dest_mode
;
1551 * Trigger mode in the IRTE will always be edge, and the
1552 * actual level or edge trigger will be setup in the IO-APIC
1553 * RTE. This will help simplify level triggered irq migration.
1554 * For more details, see the comments above explainig IO-APIC
1555 * irq migration in the presence of interrupt-remapping.
1557 irte
.trigger_mode
= 0;
1558 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1559 irte
.vector
= vector
;
1560 irte
.dest_id
= IRTE_DEST(destination
);
1562 modify_irte(irq
, &irte
);
1564 ir_entry
->index2
= (index
>> 15) & 0x1;
1566 ir_entry
->format
= 1;
1567 ir_entry
->index
= (index
& 0x7fff);
1569 * IO-APIC RTE will be configured with virtual vector.
1570 * irq handler will do the explicit EOI to the io-apic.
1572 ir_entry
->vector
= pin
;
1574 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1575 entry
->dest_mode
= apic
->irq_dest_mode
;
1576 entry
->dest
= destination
;
1577 entry
->vector
= vector
;
1580 entry
->mask
= 0; /* enable IRQ */
1581 entry
->trigger
= trigger
;
1582 entry
->polarity
= polarity
;
1584 /* Mask level triggered irqs.
1585 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1592 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1593 int trigger
, int polarity
)
1595 struct irq_cfg
*cfg
;
1596 struct IO_APIC_route_entry entry
;
1599 if (!IO_APIC_IRQ(irq
))
1602 cfg
= desc
->chip_data
;
1604 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1607 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1609 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1610 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1611 "IRQ %d Mode:%i Active:%i)\n",
1612 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1613 irq
, trigger
, polarity
);
1616 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1617 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1618 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1619 mp_ioapics
[apic_id
].apicid
, pin
);
1620 __clear_irq_vector(irq
, cfg
);
1624 ioapic_register_intr(irq
, desc
, trigger
);
1625 if (irq
< NR_IRQS_LEGACY
)
1626 disable_8259A_irq(irq
);
1628 ioapic_write_entry(apic_id
, pin
, entry
);
1631 static void __init
setup_IO_APIC_irqs(void)
1633 int apic_id
, pin
, idx
, irq
;
1635 struct irq_desc
*desc
;
1636 struct irq_cfg
*cfg
;
1637 int cpu
= boot_cpu_id
;
1639 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1641 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1642 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1644 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1648 apic_printk(APIC_VERBOSE
,
1649 KERN_DEBUG
" %d-%d",
1650 mp_ioapics
[apic_id
].apicid
, pin
);
1652 apic_printk(APIC_VERBOSE
, " %d-%d",
1653 mp_ioapics
[apic_id
].apicid
, pin
);
1657 apic_printk(APIC_VERBOSE
,
1658 " (apicid-pin) not connected\n");
1662 irq
= pin_2_irq(idx
, apic_id
, pin
);
1665 * Skip the timer IRQ if there's a quirk handler
1666 * installed and if it returns 1:
1668 if (apic
->multi_timer_check
&&
1669 apic
->multi_timer_check(apic_id
, irq
))
1672 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1674 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1677 cfg
= desc
->chip_data
;
1678 add_pin_to_irq_cpu(cfg
, cpu
, apic_id
, pin
);
1680 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1681 irq_trigger(idx
), irq_polarity(idx
));
1686 apic_printk(APIC_VERBOSE
,
1687 " (apicid-pin) not connected\n");
1691 * Set up the timer pin, possibly with the 8259A-master behind.
1693 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1696 struct IO_APIC_route_entry entry
;
1698 if (intr_remapping_enabled
)
1701 memset(&entry
, 0, sizeof(entry
));
1704 * We use logical delivery to get the timer IRQ
1707 entry
.dest_mode
= apic
->irq_dest_mode
;
1708 entry
.mask
= 0; /* don't mask IRQ for edge */
1709 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1710 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1713 entry
.vector
= vector
;
1716 * The timer IRQ doesn't have to know that behind the
1717 * scene we may have a 8259A-master in AEOI mode ...
1719 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1722 * Add it to the IO-APIC irq-routing table:
1724 ioapic_write_entry(apic_id
, pin
, entry
);
1728 __apicdebuginit(void) print_IO_APIC(void)
1731 union IO_APIC_reg_00 reg_00
;
1732 union IO_APIC_reg_01 reg_01
;
1733 union IO_APIC_reg_02 reg_02
;
1734 union IO_APIC_reg_03 reg_03
;
1735 unsigned long flags
;
1736 struct irq_cfg
*cfg
;
1737 struct irq_desc
*desc
;
1740 if (apic_verbosity
== APIC_QUIET
)
1743 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1744 for (i
= 0; i
< nr_ioapics
; i
++)
1745 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1746 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1749 * We are a bit conservative about what we expect. We have to
1750 * know about every hardware change ASAP.
1752 printk(KERN_INFO
"testing the IO APIC.......................\n");
1754 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1756 spin_lock_irqsave(&ioapic_lock
, flags
);
1757 reg_00
.raw
= io_apic_read(apic
, 0);
1758 reg_01
.raw
= io_apic_read(apic
, 1);
1759 if (reg_01
.bits
.version
>= 0x10)
1760 reg_02
.raw
= io_apic_read(apic
, 2);
1761 if (reg_01
.bits
.version
>= 0x20)
1762 reg_03
.raw
= io_apic_read(apic
, 3);
1763 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1766 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1767 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1768 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1769 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1770 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1772 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1773 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1775 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1776 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1779 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1780 * but the value of reg_02 is read as the previous read register
1781 * value, so ignore it if reg_02 == reg_01.
1783 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1784 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1785 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1789 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1790 * or reg_03, but the value of reg_0[23] is read as the previous read
1791 * register value, so ignore it if reg_03 == reg_0[12].
1793 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1794 reg_03
.raw
!= reg_01
.raw
) {
1795 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1796 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1799 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1801 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1802 " Stat Dmod Deli Vect: \n");
1804 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1805 struct IO_APIC_route_entry entry
;
1807 entry
= ioapic_read_entry(apic
, i
);
1809 printk(KERN_DEBUG
" %02x %03X ",
1814 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1819 entry
.delivery_status
,
1821 entry
.delivery_mode
,
1826 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1827 for_each_irq_desc(irq
, desc
) {
1828 struct irq_pin_list
*entry
;
1830 cfg
= desc
->chip_data
;
1831 entry
= cfg
->irq_2_pin
;
1834 printk(KERN_DEBUG
"IRQ%d ", irq
);
1836 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1839 entry
= entry
->next
;
1844 printk(KERN_INFO
".................................... done.\n");
1849 __apicdebuginit(void) print_APIC_bitfield(int base
)
1854 if (apic_verbosity
== APIC_QUIET
)
1857 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1858 for (i
= 0; i
< 8; i
++) {
1859 v
= apic_read(base
+ i
*0x10);
1860 for (j
= 0; j
< 32; j
++) {
1870 __apicdebuginit(void) print_local_APIC(void *dummy
)
1872 unsigned int v
, ver
, maxlvt
;
1875 if (apic_verbosity
== APIC_QUIET
)
1878 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1879 smp_processor_id(), hard_smp_processor_id());
1880 v
= apic_read(APIC_ID
);
1881 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1882 v
= apic_read(APIC_LVR
);
1883 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1884 ver
= GET_APIC_VERSION(v
);
1885 maxlvt
= lapic_get_maxlvt();
1887 v
= apic_read(APIC_TASKPRI
);
1888 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1890 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1891 if (!APIC_XAPIC(ver
)) {
1892 v
= apic_read(APIC_ARBPRI
);
1893 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1894 v
& APIC_ARBPRI_MASK
);
1896 v
= apic_read(APIC_PROCPRI
);
1897 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1901 * Remote read supported only in the 82489DX and local APIC for
1902 * Pentium processors.
1904 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1905 v
= apic_read(APIC_RRR
);
1906 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1909 v
= apic_read(APIC_LDR
);
1910 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1911 if (!x2apic_enabled()) {
1912 v
= apic_read(APIC_DFR
);
1913 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1915 v
= apic_read(APIC_SPIV
);
1916 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1918 printk(KERN_DEBUG
"... APIC ISR field:\n");
1919 print_APIC_bitfield(APIC_ISR
);
1920 printk(KERN_DEBUG
"... APIC TMR field:\n");
1921 print_APIC_bitfield(APIC_TMR
);
1922 printk(KERN_DEBUG
"... APIC IRR field:\n");
1923 print_APIC_bitfield(APIC_IRR
);
1925 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1926 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1927 apic_write(APIC_ESR
, 0);
1929 v
= apic_read(APIC_ESR
);
1930 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1933 icr
= apic_icr_read();
1934 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1935 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1937 v
= apic_read(APIC_LVTT
);
1938 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1940 if (maxlvt
> 3) { /* PC is LVT#4. */
1941 v
= apic_read(APIC_LVTPC
);
1942 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1944 v
= apic_read(APIC_LVT0
);
1945 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1946 v
= apic_read(APIC_LVT1
);
1947 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1949 if (maxlvt
> 2) { /* ERR is LVT#3. */
1950 v
= apic_read(APIC_LVTERR
);
1951 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1954 v
= apic_read(APIC_TMICT
);
1955 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1956 v
= apic_read(APIC_TMCCT
);
1957 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1958 v
= apic_read(APIC_TDCR
);
1959 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1963 __apicdebuginit(void) print_all_local_APICs(void)
1968 for_each_online_cpu(cpu
)
1969 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1973 __apicdebuginit(void) print_PIC(void)
1976 unsigned long flags
;
1978 if (apic_verbosity
== APIC_QUIET
)
1981 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1983 spin_lock_irqsave(&i8259A_lock
, flags
);
1985 v
= inb(0xa1) << 8 | inb(0x21);
1986 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1988 v
= inb(0xa0) << 8 | inb(0x20);
1989 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1993 v
= inb(0xa0) << 8 | inb(0x20);
1997 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1999 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
2001 v
= inb(0x4d1) << 8 | inb(0x4d0);
2002 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
2005 __apicdebuginit(int) print_all_ICs(void)
2008 print_all_local_APICs();
2014 fs_initcall(print_all_ICs
);
2017 /* Where if anywhere is the i8259 connect in external int mode */
2018 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
2020 void __init
enable_IO_APIC(void)
2022 union IO_APIC_reg_01 reg_01
;
2023 int i8259_apic
, i8259_pin
;
2025 unsigned long flags
;
2028 * The number of IO-APIC IRQ registers (== #pins):
2030 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2031 spin_lock_irqsave(&ioapic_lock
, flags
);
2032 reg_01
.raw
= io_apic_read(apic
, 1);
2033 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2034 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2036 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2038 /* See if any of the pins is in ExtINT mode */
2039 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2040 struct IO_APIC_route_entry entry
;
2041 entry
= ioapic_read_entry(apic
, pin
);
2043 /* If the interrupt line is enabled and in ExtInt mode
2044 * I have found the pin where the i8259 is connected.
2046 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2047 ioapic_i8259
.apic
= apic
;
2048 ioapic_i8259
.pin
= pin
;
2054 /* Look to see what if the MP table has reported the ExtINT */
2055 /* If we could not find the appropriate pin by looking at the ioapic
2056 * the i8259 probably is not connected the ioapic but give the
2057 * mptable a chance anyway.
2059 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2060 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2061 /* Trust the MP table if nothing is setup in the hardware */
2062 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2063 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2064 ioapic_i8259
.pin
= i8259_pin
;
2065 ioapic_i8259
.apic
= i8259_apic
;
2067 /* Complain if the MP table and the hardware disagree */
2068 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2069 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2071 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2075 * Do not trust the IO-APIC being empty at bootup
2081 * Not an __init, needed by the reboot code
2083 void disable_IO_APIC(void)
2086 * Clear the IO-APIC before rebooting:
2091 * If the i8259 is routed through an IOAPIC
2092 * Put that IOAPIC in virtual wire mode
2093 * so legacy interrupts can be delivered.
2095 * With interrupt-remapping, for now we will use virtual wire A mode,
2096 * as virtual wire B is little complex (need to configure both
2097 * IOAPIC RTE aswell as interrupt-remapping table entry).
2098 * As this gets called during crash dump, keep this simple for now.
2100 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2101 struct IO_APIC_route_entry entry
;
2103 memset(&entry
, 0, sizeof(entry
));
2104 entry
.mask
= 0; /* Enabled */
2105 entry
.trigger
= 0; /* Edge */
2107 entry
.polarity
= 0; /* High */
2108 entry
.delivery_status
= 0;
2109 entry
.dest_mode
= 0; /* Physical */
2110 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2112 entry
.dest
= read_apic_id();
2115 * Add it to the IO-APIC irq-routing table:
2117 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2121 * Use virtual wire A mode when interrupt remapping is enabled.
2123 disconnect_bsp_APIC(!intr_remapping_enabled
&& ioapic_i8259
.pin
!= -1);
2126 #ifdef CONFIG_X86_32
2128 * function to set the IO-APIC physical IDs based on the
2129 * values stored in the MPC table.
2131 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2134 static void __init
setup_ioapic_ids_from_mpc(void)
2136 union IO_APIC_reg_00 reg_00
;
2137 physid_mask_t phys_id_present_map
;
2140 unsigned char old_id
;
2141 unsigned long flags
;
2143 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2147 * Don't check I/O APIC IDs for xAPIC systems. They have
2148 * no meaning without the serial APIC bus.
2150 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2151 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2154 * This is broken; anything with a real cpu count has to
2155 * circumvent this idiocy regardless.
2157 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2160 * Set the IOAPIC ID to the value stored in the MPC table.
2162 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2164 /* Read the register 0 value */
2165 spin_lock_irqsave(&ioapic_lock
, flags
);
2166 reg_00
.raw
= io_apic_read(apic_id
, 0);
2167 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2169 old_id
= mp_ioapics
[apic_id
].apicid
;
2171 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2172 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2173 apic_id
, mp_ioapics
[apic_id
].apicid
);
2174 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2176 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2180 * Sanity check, is the ID really free? Every APIC in a
2181 * system must have a unique ID or we get lots of nice
2182 * 'stuck on smp_invalidate_needed IPI wait' messages.
2184 if (apic
->check_apicid_used(phys_id_present_map
,
2185 mp_ioapics
[apic_id
].apicid
)) {
2186 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2187 apic_id
, mp_ioapics
[apic_id
].apicid
);
2188 for (i
= 0; i
< get_physical_broadcast(); i
++)
2189 if (!physid_isset(i
, phys_id_present_map
))
2191 if (i
>= get_physical_broadcast())
2192 panic("Max APIC ID exceeded!\n");
2193 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2195 physid_set(i
, phys_id_present_map
);
2196 mp_ioapics
[apic_id
].apicid
= i
;
2199 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2200 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2201 "phys_id_present_map\n",
2202 mp_ioapics
[apic_id
].apicid
);
2203 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2208 * We need to adjust the IRQ routing table
2209 * if the ID changed.
2211 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2212 for (i
= 0; i
< mp_irq_entries
; i
++)
2213 if (mp_irqs
[i
].dstapic
== old_id
)
2215 = mp_ioapics
[apic_id
].apicid
;
2218 * Read the right value from the MPC table and
2219 * write it into the ID register.
2221 apic_printk(APIC_VERBOSE
, KERN_INFO
2222 "...changing IO-APIC physical APIC ID to %d ...",
2223 mp_ioapics
[apic_id
].apicid
);
2225 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2226 spin_lock_irqsave(&ioapic_lock
, flags
);
2227 io_apic_write(apic_id
, 0, reg_00
.raw
);
2228 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2233 spin_lock_irqsave(&ioapic_lock
, flags
);
2234 reg_00
.raw
= io_apic_read(apic_id
, 0);
2235 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2236 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2237 printk("could not set ID!\n");
2239 apic_printk(APIC_VERBOSE
, " ok.\n");
2244 int no_timer_check __initdata
;
2246 static int __init
notimercheck(char *s
)
2251 __setup("no_timer_check", notimercheck
);
2254 * There is a nasty bug in some older SMP boards, their mptable lies
2255 * about the timer IRQ. We do the following to work around the situation:
2257 * - timer IRQ defaults to IO-APIC IRQ
2258 * - if this function detects that timer IRQs are defunct, then we fall
2259 * back to ISA timer IRQs
2261 static int __init
timer_irq_works(void)
2263 unsigned long t1
= jiffies
;
2264 unsigned long flags
;
2269 local_save_flags(flags
);
2271 /* Let ten ticks pass... */
2272 mdelay((10 * 1000) / HZ
);
2273 local_irq_restore(flags
);
2276 * Expect a few ticks at least, to be sure some possible
2277 * glue logic does not lock up after one or two first
2278 * ticks in a non-ExtINT mode. Also the local APIC
2279 * might have cached one ExtINT interrupt. Finally, at
2280 * least one tick may be lost due to delays.
2284 if (time_after(jiffies
, t1
+ 4))
2290 * In the SMP+IOAPIC case it might happen that there are an unspecified
2291 * number of pending IRQ events unhandled. These cases are very rare,
2292 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2293 * better to do it this way as thus we do not have to be aware of
2294 * 'pending' interrupts in the IRQ path, except at this point.
2297 * Edge triggered needs to resend any interrupt
2298 * that was delayed but this is now handled in the device
2303 * Starting up a edge-triggered IO-APIC interrupt is
2304 * nasty - we need to make sure that we get the edge.
2305 * If it is already asserted for some reason, we need
2306 * return 1 to indicate that is was pending.
2308 * This is not complete - we should be able to fake
2309 * an edge even if it isn't on the 8259A...
2312 static unsigned int startup_ioapic_irq(unsigned int irq
)
2314 int was_pending
= 0;
2315 unsigned long flags
;
2316 struct irq_cfg
*cfg
;
2318 spin_lock_irqsave(&ioapic_lock
, flags
);
2319 if (irq
< NR_IRQS_LEGACY
) {
2320 disable_8259A_irq(irq
);
2321 if (i8259A_irq_pending(irq
))
2325 __unmask_IO_APIC_irq(cfg
);
2326 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2331 #ifdef CONFIG_X86_64
2332 static int ioapic_retrigger_irq(unsigned int irq
)
2335 struct irq_cfg
*cfg
= irq_cfg(irq
);
2336 unsigned long flags
;
2338 spin_lock_irqsave(&vector_lock
, flags
);
2339 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2340 spin_unlock_irqrestore(&vector_lock
, flags
);
2345 static int ioapic_retrigger_irq(unsigned int irq
)
2347 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2354 * Level and edge triggered IO-APIC interrupts need different handling,
2355 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2356 * handled with the level-triggered descriptor, but that one has slightly
2357 * more overhead. Level-triggered interrupts cannot be handled with the
2358 * edge-triggered handler, without risking IRQ storms and other ugly
2364 #ifdef CONFIG_INTR_REMAP
2367 * Migrate the IO-APIC irq in the presence of intr-remapping.
2369 * For both level and edge triggered, irq migration is a simple atomic
2370 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2372 * For level triggered, we eliminate the io-apic RTE modification (with the
2373 * updated vector information), by using a virtual vector (io-apic pin number).
2374 * Real vector that is used for interrupting cpu will be coming from
2375 * the interrupt-remapping table entry.
2378 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2380 struct irq_cfg
*cfg
;
2385 if (!cpumask_intersects(mask
, cpu_online_mask
))
2389 if (get_irte(irq
, &irte
))
2392 cfg
= desc
->chip_data
;
2393 if (assign_irq_vector(irq
, cfg
, mask
))
2396 set_extra_move_desc(desc
, mask
);
2398 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2400 irte
.vector
= cfg
->vector
;
2401 irte
.dest_id
= IRTE_DEST(dest
);
2404 * Modified the IRTE and flushes the Interrupt entry cache.
2406 modify_irte(irq
, &irte
);
2408 if (cfg
->move_in_progress
)
2409 send_cleanup_vector(cfg
);
2411 cpumask_copy(desc
->affinity
, mask
);
2415 * Migrates the IRQ destination in the process context.
2417 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2418 const struct cpumask
*mask
)
2420 migrate_ioapic_irq_desc(desc
, mask
);
2422 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2423 const struct cpumask
*mask
)
2425 struct irq_desc
*desc
= irq_to_desc(irq
);
2427 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2430 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2431 const struct cpumask
*mask
)
2436 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2438 unsigned vector
, me
;
2444 me
= smp_processor_id();
2445 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2448 struct irq_desc
*desc
;
2449 struct irq_cfg
*cfg
;
2450 irq
= __get_cpu_var(vector_irq
)[vector
];
2455 desc
= irq_to_desc(irq
);
2460 spin_lock(&desc
->lock
);
2461 if (!cfg
->move_cleanup_count
)
2464 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2467 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2469 * Check if the vector that needs to be cleanedup is
2470 * registered at the cpu's IRR. If so, then this is not
2471 * the best time to clean it up. Lets clean it up in the
2472 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2475 if (irr
& (1 << (vector
% 32))) {
2476 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2479 __get_cpu_var(vector_irq
)[vector
] = -1;
2480 cfg
->move_cleanup_count
--;
2482 spin_unlock(&desc
->lock
);
2488 static void irq_complete_move(struct irq_desc
**descp
)
2490 struct irq_desc
*desc
= *descp
;
2491 struct irq_cfg
*cfg
= desc
->chip_data
;
2492 unsigned vector
, me
;
2494 if (likely(!cfg
->move_in_progress
)) {
2495 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2496 if (likely(!cfg
->move_desc_pending
))
2499 /* domain has not changed, but affinity did */
2500 me
= smp_processor_id();
2501 if (cpumask_test_cpu(me
, desc
->affinity
)) {
2502 *descp
= desc
= move_irq_desc(desc
, me
);
2503 /* get the new one */
2504 cfg
= desc
->chip_data
;
2505 cfg
->move_desc_pending
= 0;
2511 vector
= ~get_irq_regs()->orig_ax
;
2512 me
= smp_processor_id();
2514 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
)) {
2515 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2516 *descp
= desc
= move_irq_desc(desc
, me
);
2517 /* get the new one */
2518 cfg
= desc
->chip_data
;
2520 send_cleanup_vector(cfg
);
2524 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2527 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2530 struct irq_pin_list
*entry
;
2532 entry
= cfg
->irq_2_pin
;
2540 io_apic_eoi(apic
, pin
);
2541 entry
= entry
->next
;
2546 eoi_ioapic_irq(struct irq_desc
*desc
)
2548 struct irq_cfg
*cfg
;
2549 unsigned long flags
;
2553 cfg
= desc
->chip_data
;
2555 spin_lock_irqsave(&ioapic_lock
, flags
);
2556 __eoi_ioapic_irq(irq
, cfg
);
2557 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2560 #ifdef CONFIG_X86_X2APIC
2561 static void ack_x2apic_level(unsigned int irq
)
2563 struct irq_desc
*desc
= irq_to_desc(irq
);
2565 eoi_ioapic_irq(desc
);
2568 static void ack_x2apic_edge(unsigned int irq
)
2574 static void ack_apic_edge(unsigned int irq
)
2576 struct irq_desc
*desc
= irq_to_desc(irq
);
2578 irq_complete_move(&desc
);
2579 move_native_irq(irq
);
2583 atomic_t irq_mis_count
;
2585 static void ack_apic_level(unsigned int irq
)
2587 struct irq_desc
*desc
= irq_to_desc(irq
);
2589 #ifdef CONFIG_X86_32
2593 struct irq_cfg
*cfg
;
2594 int do_unmask_irq
= 0;
2596 irq_complete_move(&desc
);
2597 #ifdef CONFIG_GENERIC_PENDING_IRQ
2598 /* If we are moving the irq we need to mask it */
2599 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2601 mask_IO_APIC_irq_desc(desc
);
2605 #ifdef CONFIG_X86_32
2607 * It appears there is an erratum which affects at least version 0x11
2608 * of I/O APIC (that's the 82093AA and cores integrated into various
2609 * chipsets). Under certain conditions a level-triggered interrupt is
2610 * erroneously delivered as edge-triggered one but the respective IRR
2611 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2612 * message but it will never arrive and further interrupts are blocked
2613 * from the source. The exact reason is so far unknown, but the
2614 * phenomenon was observed when two consecutive interrupt requests
2615 * from a given source get delivered to the same CPU and the source is
2616 * temporarily disabled in between.
2618 * A workaround is to simulate an EOI message manually. We achieve it
2619 * by setting the trigger mode to edge and then to level when the edge
2620 * trigger mode gets detected in the TMR of a local APIC for a
2621 * level-triggered interrupt. We mask the source for the time of the
2622 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2623 * The idea is from Manfred Spraul. --macro
2625 cfg
= desc
->chip_data
;
2628 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2632 * We must acknowledge the irq before we move it or the acknowledge will
2633 * not propagate properly.
2637 if (irq_remapped(irq
))
2638 eoi_ioapic_irq(desc
);
2640 /* Now we can move and renable the irq */
2641 if (unlikely(do_unmask_irq
)) {
2642 /* Only migrate the irq if the ack has been received.
2644 * On rare occasions the broadcast level triggered ack gets
2645 * delayed going to ioapics, and if we reprogram the
2646 * vector while Remote IRR is still set the irq will never
2649 * To prevent this scenario we read the Remote IRR bit
2650 * of the ioapic. This has two effects.
2651 * - On any sane system the read of the ioapic will
2652 * flush writes (and acks) going to the ioapic from
2654 * - We get to see if the ACK has actually been delivered.
2656 * Based on failed experiments of reprogramming the
2657 * ioapic entry from outside of irq context starting
2658 * with masking the ioapic entry and then polling until
2659 * Remote IRR was clear before reprogramming the
2660 * ioapic I don't trust the Remote IRR bit to be
2661 * completey accurate.
2663 * However there appears to be no other way to plug
2664 * this race, so if the Remote IRR bit is not
2665 * accurate and is causing problems then it is a hardware bug
2666 * and you can go talk to the chipset vendor about it.
2668 cfg
= desc
->chip_data
;
2669 if (!io_apic_level_ack_pending(cfg
))
2670 move_masked_irq(irq
);
2671 unmask_IO_APIC_irq_desc(desc
);
2674 #ifdef CONFIG_X86_32
2675 if (!(v
& (1 << (i
& 0x1f)))) {
2676 atomic_inc(&irq_mis_count
);
2677 spin_lock(&ioapic_lock
);
2678 __mask_and_edge_IO_APIC_irq(cfg
);
2679 __unmask_and_level_IO_APIC_irq(cfg
);
2680 spin_unlock(&ioapic_lock
);
2685 #ifdef CONFIG_INTR_REMAP
2686 static void ir_ack_apic_edge(unsigned int irq
)
2688 #ifdef CONFIG_X86_X2APIC
2689 if (x2apic_enabled())
2690 return ack_x2apic_edge(irq
);
2692 return ack_apic_edge(irq
);
2695 static void ir_ack_apic_level(unsigned int irq
)
2697 #ifdef CONFIG_X86_X2APIC
2698 if (x2apic_enabled())
2699 return ack_x2apic_level(irq
);
2701 return ack_apic_level(irq
);
2703 #endif /* CONFIG_INTR_REMAP */
2705 static struct irq_chip ioapic_chip __read_mostly
= {
2707 .startup
= startup_ioapic_irq
,
2708 .mask
= mask_IO_APIC_irq
,
2709 .unmask
= unmask_IO_APIC_irq
,
2710 .ack
= ack_apic_edge
,
2711 .eoi
= ack_apic_level
,
2713 .set_affinity
= set_ioapic_affinity_irq
,
2715 .retrigger
= ioapic_retrigger_irq
,
2718 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2719 .name
= "IR-IO-APIC",
2720 .startup
= startup_ioapic_irq
,
2721 .mask
= mask_IO_APIC_irq
,
2722 .unmask
= unmask_IO_APIC_irq
,
2723 #ifdef CONFIG_INTR_REMAP
2724 .ack
= ir_ack_apic_edge
,
2725 .eoi
= ir_ack_apic_level
,
2727 .set_affinity
= set_ir_ioapic_affinity_irq
,
2730 .retrigger
= ioapic_retrigger_irq
,
2733 static inline void init_IO_APIC_traps(void)
2736 struct irq_desc
*desc
;
2737 struct irq_cfg
*cfg
;
2740 * NOTE! The local APIC isn't very good at handling
2741 * multiple interrupts at the same interrupt level.
2742 * As the interrupt level is determined by taking the
2743 * vector number and shifting that right by 4, we
2744 * want to spread these out a bit so that they don't
2745 * all fall in the same interrupt level.
2747 * Also, we've got to be careful not to trash gate
2748 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2750 for_each_irq_desc(irq
, desc
) {
2751 cfg
= desc
->chip_data
;
2752 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2754 * Hmm.. We don't have an entry for this,
2755 * so default to an old-fashioned 8259
2756 * interrupt if we can..
2758 if (irq
< NR_IRQS_LEGACY
)
2759 make_8259A_irq(irq
);
2761 /* Strange. Oh, well.. */
2762 desc
->chip
= &no_irq_chip
;
2768 * The local APIC irq-chip implementation:
2771 static void mask_lapic_irq(unsigned int irq
)
2775 v
= apic_read(APIC_LVT0
);
2776 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2779 static void unmask_lapic_irq(unsigned int irq
)
2783 v
= apic_read(APIC_LVT0
);
2784 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2787 static void ack_lapic_irq(unsigned int irq
)
2792 static struct irq_chip lapic_chip __read_mostly
= {
2793 .name
= "local-APIC",
2794 .mask
= mask_lapic_irq
,
2795 .unmask
= unmask_lapic_irq
,
2796 .ack
= ack_lapic_irq
,
2799 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2801 desc
->status
&= ~IRQ_LEVEL
;
2802 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2806 static void __init
setup_nmi(void)
2809 * Dirty trick to enable the NMI watchdog ...
2810 * We put the 8259A master into AEOI mode and
2811 * unmask on all local APICs LVT0 as NMI.
2813 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2814 * is from Maciej W. Rozycki - so we do not have to EOI from
2815 * the NMI handler or the timer interrupt.
2817 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2819 enable_NMI_through_LVT0();
2821 apic_printk(APIC_VERBOSE
, " done.\n");
2825 * This looks a bit hackish but it's about the only one way of sending
2826 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2827 * not support the ExtINT mode, unfortunately. We need to send these
2828 * cycles as some i82489DX-based boards have glue logic that keeps the
2829 * 8259A interrupt line asserted until INTA. --macro
2831 static inline void __init
unlock_ExtINT_logic(void)
2834 struct IO_APIC_route_entry entry0
, entry1
;
2835 unsigned char save_control
, save_freq_select
;
2837 pin
= find_isa_irq_pin(8, mp_INT
);
2842 apic
= find_isa_irq_apic(8, mp_INT
);
2848 entry0
= ioapic_read_entry(apic
, pin
);
2849 clear_IO_APIC_pin(apic
, pin
);
2851 memset(&entry1
, 0, sizeof(entry1
));
2853 entry1
.dest_mode
= 0; /* physical delivery */
2854 entry1
.mask
= 0; /* unmask IRQ now */
2855 entry1
.dest
= hard_smp_processor_id();
2856 entry1
.delivery_mode
= dest_ExtINT
;
2857 entry1
.polarity
= entry0
.polarity
;
2861 ioapic_write_entry(apic
, pin
, entry1
);
2863 save_control
= CMOS_READ(RTC_CONTROL
);
2864 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2865 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2867 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2872 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2876 CMOS_WRITE(save_control
, RTC_CONTROL
);
2877 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2878 clear_IO_APIC_pin(apic
, pin
);
2880 ioapic_write_entry(apic
, pin
, entry0
);
2883 static int disable_timer_pin_1 __initdata
;
2884 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2885 static int __init
disable_timer_pin_setup(char *arg
)
2887 disable_timer_pin_1
= 1;
2890 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2892 int timer_through_8259 __initdata
;
2895 * This code may look a bit paranoid, but it's supposed to cooperate with
2896 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2897 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2898 * fanatically on his truly buggy board.
2900 * FIXME: really need to revamp this for all platforms.
2902 static inline void __init
check_timer(void)
2904 struct irq_desc
*desc
= irq_to_desc(0);
2905 struct irq_cfg
*cfg
= desc
->chip_data
;
2906 int cpu
= boot_cpu_id
;
2907 int apic1
, pin1
, apic2
, pin2
;
2908 unsigned long flags
;
2911 local_irq_save(flags
);
2914 * get/set the timer IRQ vector:
2916 disable_8259A_irq(0);
2917 assign_irq_vector(0, cfg
, apic
->target_cpus());
2920 * As IRQ0 is to be enabled in the 8259A, the virtual
2921 * wire has to be disabled in the local APIC. Also
2922 * timer interrupts need to be acknowledged manually in
2923 * the 8259A for the i82489DX when using the NMI
2924 * watchdog as that APIC treats NMIs as level-triggered.
2925 * The AEOI mode will finish them in the 8259A
2928 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2930 #ifdef CONFIG_X86_32
2934 ver
= apic_read(APIC_LVR
);
2935 ver
= GET_APIC_VERSION(ver
);
2936 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2940 pin1
= find_isa_irq_pin(0, mp_INT
);
2941 apic1
= find_isa_irq_apic(0, mp_INT
);
2942 pin2
= ioapic_i8259
.pin
;
2943 apic2
= ioapic_i8259
.apic
;
2945 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2946 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2947 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2950 * Some BIOS writers are clueless and report the ExtINTA
2951 * I/O APIC input from the cascaded 8259A as the timer
2952 * interrupt input. So just in case, if only one pin
2953 * was found above, try it both directly and through the
2957 if (intr_remapping_enabled
)
2958 panic("BIOS bug: timer not connected to IO-APIC");
2962 } else if (pin2
== -1) {
2969 * Ok, does IRQ0 through the IOAPIC work?
2972 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2973 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2975 /* for edge trigger, setup_IO_APIC_irq already
2976 * leave it unmasked.
2977 * so only need to unmask if it is level-trigger
2978 * do we really have level trigger timer?
2981 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2982 if (idx
!= -1 && irq_trigger(idx
))
2983 unmask_IO_APIC_irq_desc(desc
);
2985 if (timer_irq_works()) {
2986 if (nmi_watchdog
== NMI_IO_APIC
) {
2988 enable_8259A_irq(0);
2990 if (disable_timer_pin_1
> 0)
2991 clear_IO_APIC_pin(0, pin1
);
2994 if (intr_remapping_enabled
)
2995 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2996 local_irq_disable();
2997 clear_IO_APIC_pin(apic1
, pin1
);
2999 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
3000 "8254 timer not connected to IO-APIC\n");
3002 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
3003 "(IRQ0) through the 8259A ...\n");
3004 apic_printk(APIC_QUIET
, KERN_INFO
3005 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
3007 * legacy devices should be connected to IO APIC #0
3009 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
3010 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
3011 enable_8259A_irq(0);
3012 if (timer_irq_works()) {
3013 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
3014 timer_through_8259
= 1;
3015 if (nmi_watchdog
== NMI_IO_APIC
) {
3016 disable_8259A_irq(0);
3018 enable_8259A_irq(0);
3023 * Cleanup, just in case ...
3025 local_irq_disable();
3026 disable_8259A_irq(0);
3027 clear_IO_APIC_pin(apic2
, pin2
);
3028 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3031 if (nmi_watchdog
== NMI_IO_APIC
) {
3032 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3033 "through the IO-APIC - disabling NMI Watchdog!\n");
3034 nmi_watchdog
= NMI_NONE
;
3036 #ifdef CONFIG_X86_32
3040 apic_printk(APIC_QUIET
, KERN_INFO
3041 "...trying to set up timer as Virtual Wire IRQ...\n");
3043 lapic_register_intr(0, desc
);
3044 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3045 enable_8259A_irq(0);
3047 if (timer_irq_works()) {
3048 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3051 local_irq_disable();
3052 disable_8259A_irq(0);
3053 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3054 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3056 apic_printk(APIC_QUIET
, KERN_INFO
3057 "...trying to set up timer as ExtINT IRQ...\n");
3061 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3063 unlock_ExtINT_logic();
3065 if (timer_irq_works()) {
3066 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3069 local_irq_disable();
3070 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3071 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3072 "report. Then try booting with the 'noapic' option.\n");
3074 local_irq_restore(flags
);
3078 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3079 * to devices. However there may be an I/O APIC pin available for
3080 * this interrupt regardless. The pin may be left unconnected, but
3081 * typically it will be reused as an ExtINT cascade interrupt for
3082 * the master 8259A. In the MPS case such a pin will normally be
3083 * reported as an ExtINT interrupt in the MP table. With ACPI
3084 * there is no provision for ExtINT interrupts, and in the absence
3085 * of an override it would be treated as an ordinary ISA I/O APIC
3086 * interrupt, that is edge-triggered and unmasked by default. We
3087 * used to do this, but it caused problems on some systems because
3088 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3089 * the same ExtINT cascade interrupt to drive the local APIC of the
3090 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3091 * the I/O APIC in all cases now. No actual device should request
3092 * it anyway. --macro
3094 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3096 void __init
setup_IO_APIC(void)
3100 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3103 io_apic_irqs
= ~PIC_IRQS
;
3105 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3107 * Set up IO-APIC IRQ routing.
3109 #ifdef CONFIG_X86_32
3111 setup_ioapic_ids_from_mpc();
3114 setup_IO_APIC_irqs();
3115 init_IO_APIC_traps();
3120 * Called after all the initialization is done. If we didnt find any
3121 * APIC bugs then we can allow the modify fast path
3124 static int __init
io_apic_bug_finalize(void)
3126 if (sis_apic_bug
== -1)
3131 late_initcall(io_apic_bug_finalize
);
3133 struct sysfs_ioapic_data
{
3134 struct sys_device dev
;
3135 struct IO_APIC_route_entry entry
[0];
3137 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3139 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3141 struct IO_APIC_route_entry
*entry
;
3142 struct sysfs_ioapic_data
*data
;
3145 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3146 entry
= data
->entry
;
3147 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3148 *entry
= ioapic_read_entry(dev
->id
, i
);
3153 static int ioapic_resume(struct sys_device
*dev
)
3155 struct IO_APIC_route_entry
*entry
;
3156 struct sysfs_ioapic_data
*data
;
3157 unsigned long flags
;
3158 union IO_APIC_reg_00 reg_00
;
3161 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3162 entry
= data
->entry
;
3164 spin_lock_irqsave(&ioapic_lock
, flags
);
3165 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3166 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3167 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3168 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3170 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3171 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3172 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3177 static struct sysdev_class ioapic_sysdev_class
= {
3179 .suspend
= ioapic_suspend
,
3180 .resume
= ioapic_resume
,
3183 static int __init
ioapic_init_sysfs(void)
3185 struct sys_device
* dev
;
3188 error
= sysdev_class_register(&ioapic_sysdev_class
);
3192 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3193 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3194 * sizeof(struct IO_APIC_route_entry
);
3195 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3196 if (!mp_ioapic_data
[i
]) {
3197 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3200 dev
= &mp_ioapic_data
[i
]->dev
;
3202 dev
->cls
= &ioapic_sysdev_class
;
3203 error
= sysdev_register(dev
);
3205 kfree(mp_ioapic_data
[i
]);
3206 mp_ioapic_data
[i
] = NULL
;
3207 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3215 device_initcall(ioapic_init_sysfs
);
3217 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3219 * Dynamic irq allocate and deallocation
3221 unsigned int create_irq_nr(unsigned int irq_want
)
3223 /* Allocate an unused irq */
3226 unsigned long flags
;
3227 struct irq_cfg
*cfg_new
= NULL
;
3228 int cpu
= boot_cpu_id
;
3229 struct irq_desc
*desc_new
= NULL
;
3232 if (irq_want
< nr_irqs_gsi
)
3233 irq_want
= nr_irqs_gsi
;
3235 spin_lock_irqsave(&vector_lock
, flags
);
3236 for (new = irq_want
; new < nr_irqs
; new++) {
3237 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3239 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3242 cfg_new
= desc_new
->chip_data
;
3244 if (cfg_new
->vector
!= 0)
3246 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3250 spin_unlock_irqrestore(&vector_lock
, flags
);
3253 dynamic_irq_init(irq
);
3254 /* restore it, in case dynamic_irq_init clear it */
3256 desc_new
->chip_data
= cfg_new
;
3261 int create_irq(void)
3263 unsigned int irq_want
;
3266 irq_want
= nr_irqs_gsi
;
3267 irq
= create_irq_nr(irq_want
);
3275 void destroy_irq(unsigned int irq
)
3277 unsigned long flags
;
3278 struct irq_cfg
*cfg
;
3279 struct irq_desc
*desc
;
3281 /* store it, in case dynamic_irq_cleanup clear it */
3282 desc
= irq_to_desc(irq
);
3283 cfg
= desc
->chip_data
;
3284 dynamic_irq_cleanup(irq
);
3285 /* connect back irq_cfg */
3287 desc
->chip_data
= cfg
;
3290 spin_lock_irqsave(&vector_lock
, flags
);
3291 __clear_irq_vector(irq
, cfg
);
3292 spin_unlock_irqrestore(&vector_lock
, flags
);
3296 * MSI message composition
3298 #ifdef CONFIG_PCI_MSI
3299 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3301 struct irq_cfg
*cfg
;
3309 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3313 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3315 if (irq_remapped(irq
)) {
3320 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3321 BUG_ON(ir_index
== -1);
3323 memset (&irte
, 0, sizeof(irte
));
3326 irte
.dst_mode
= apic
->irq_dest_mode
;
3327 irte
.trigger_mode
= 0; /* edge */
3328 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3329 irte
.vector
= cfg
->vector
;
3330 irte
.dest_id
= IRTE_DEST(dest
);
3332 modify_irte(irq
, &irte
);
3334 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3335 msg
->data
= sub_handle
;
3336 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3338 MSI_ADDR_IR_INDEX1(ir_index
) |
3339 MSI_ADDR_IR_INDEX2(ir_index
);
3341 if (x2apic_enabled())
3342 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3343 MSI_ADDR_EXT_DEST_ID(dest
);
3345 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3349 ((apic
->irq_dest_mode
== 0) ?
3350 MSI_ADDR_DEST_MODE_PHYSICAL
:
3351 MSI_ADDR_DEST_MODE_LOGICAL
) |
3352 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3353 MSI_ADDR_REDIRECTION_CPU
:
3354 MSI_ADDR_REDIRECTION_LOWPRI
) |
3355 MSI_ADDR_DEST_ID(dest
);
3358 MSI_DATA_TRIGGER_EDGE
|
3359 MSI_DATA_LEVEL_ASSERT
|
3360 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3361 MSI_DATA_DELIVERY_FIXED
:
3362 MSI_DATA_DELIVERY_LOWPRI
) |
3363 MSI_DATA_VECTOR(cfg
->vector
);
3369 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3371 struct irq_desc
*desc
= irq_to_desc(irq
);
3372 struct irq_cfg
*cfg
;
3376 dest
= set_desc_affinity(desc
, mask
);
3377 if (dest
== BAD_APICID
)
3380 cfg
= desc
->chip_data
;
3382 read_msi_msg_desc(desc
, &msg
);
3384 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3385 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3386 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3387 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3389 write_msi_msg_desc(desc
, &msg
);
3391 #ifdef CONFIG_INTR_REMAP
3393 * Migrate the MSI irq to another cpumask. This migration is
3394 * done in the process context using interrupt-remapping hardware.
3397 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3399 struct irq_desc
*desc
= irq_to_desc(irq
);
3400 struct irq_cfg
*cfg
= desc
->chip_data
;
3404 if (get_irte(irq
, &irte
))
3407 dest
= set_desc_affinity(desc
, mask
);
3408 if (dest
== BAD_APICID
)
3411 irte
.vector
= cfg
->vector
;
3412 irte
.dest_id
= IRTE_DEST(dest
);
3415 * atomically update the IRTE with the new destination and vector.
3417 modify_irte(irq
, &irte
);
3420 * After this point, all the interrupts will start arriving
3421 * at the new destination. So, time to cleanup the previous
3422 * vector allocation.
3424 if (cfg
->move_in_progress
)
3425 send_cleanup_vector(cfg
);
3429 #endif /* CONFIG_SMP */
3432 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3433 * which implement the MSI or MSI-X Capability Structure.
3435 static struct irq_chip msi_chip
= {
3437 .unmask
= unmask_msi_irq
,
3438 .mask
= mask_msi_irq
,
3439 .ack
= ack_apic_edge
,
3441 .set_affinity
= set_msi_irq_affinity
,
3443 .retrigger
= ioapic_retrigger_irq
,
3446 static struct irq_chip msi_ir_chip
= {
3447 .name
= "IR-PCI-MSI",
3448 .unmask
= unmask_msi_irq
,
3449 .mask
= mask_msi_irq
,
3450 #ifdef CONFIG_INTR_REMAP
3451 .ack
= ir_ack_apic_edge
,
3453 .set_affinity
= ir_set_msi_irq_affinity
,
3456 .retrigger
= ioapic_retrigger_irq
,
3460 * Map the PCI dev to the corresponding remapping hardware unit
3461 * and allocate 'nvec' consecutive interrupt-remapping table entries
3464 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3466 struct intel_iommu
*iommu
;
3469 iommu
= map_dev_to_ir(dev
);
3472 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3476 index
= alloc_irte(iommu
, irq
, nvec
);
3479 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3486 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3491 ret
= msi_compose_msg(dev
, irq
, &msg
);
3495 set_irq_msi(irq
, msidesc
);
3496 write_msi_msg(irq
, &msg
);
3498 if (irq_remapped(irq
)) {
3499 struct irq_desc
*desc
= irq_to_desc(irq
);
3501 * irq migration in process context
3503 desc
->status
|= IRQ_MOVE_PCNTXT
;
3504 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3506 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3508 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3513 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3516 int ret
, sub_handle
;
3517 struct msi_desc
*msidesc
;
3518 unsigned int irq_want
;
3519 struct intel_iommu
*iommu
= NULL
;
3522 /* x86 doesn't support multiple MSI yet */
3523 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3526 irq_want
= nr_irqs_gsi
;
3528 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3529 irq
= create_irq_nr(irq_want
);
3533 if (!intr_remapping_enabled
)
3538 * allocate the consecutive block of IRTE's
3541 index
= msi_alloc_irte(dev
, irq
, nvec
);
3547 iommu
= map_dev_to_ir(dev
);
3553 * setup the mapping between the irq and the IRTE
3554 * base index, the sub_handle pointing to the
3555 * appropriate interrupt remap table entry.
3557 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3560 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3572 void arch_teardown_msi_irq(unsigned int irq
)
3577 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3579 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3581 struct irq_desc
*desc
= irq_to_desc(irq
);
3582 struct irq_cfg
*cfg
;
3586 dest
= set_desc_affinity(desc
, mask
);
3587 if (dest
== BAD_APICID
)
3590 cfg
= desc
->chip_data
;
3592 dmar_msi_read(irq
, &msg
);
3594 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3595 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3596 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3597 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3599 dmar_msi_write(irq
, &msg
);
3602 #endif /* CONFIG_SMP */
3604 struct irq_chip dmar_msi_type
= {
3606 .unmask
= dmar_msi_unmask
,
3607 .mask
= dmar_msi_mask
,
3608 .ack
= ack_apic_edge
,
3610 .set_affinity
= dmar_msi_set_affinity
,
3612 .retrigger
= ioapic_retrigger_irq
,
3615 int arch_setup_dmar_msi(unsigned int irq
)
3620 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3623 dmar_msi_write(irq
, &msg
);
3624 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3630 #ifdef CONFIG_HPET_TIMER
3633 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3635 struct irq_desc
*desc
= irq_to_desc(irq
);
3636 struct irq_cfg
*cfg
;
3640 dest
= set_desc_affinity(desc
, mask
);
3641 if (dest
== BAD_APICID
)
3644 cfg
= desc
->chip_data
;
3646 hpet_msi_read(irq
, &msg
);
3648 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3649 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3650 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3651 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3653 hpet_msi_write(irq
, &msg
);
3656 #endif /* CONFIG_SMP */
3658 static struct irq_chip hpet_msi_type
= {
3660 .unmask
= hpet_msi_unmask
,
3661 .mask
= hpet_msi_mask
,
3662 .ack
= ack_apic_edge
,
3664 .set_affinity
= hpet_msi_set_affinity
,
3666 .retrigger
= ioapic_retrigger_irq
,
3669 int arch_setup_hpet_msi(unsigned int irq
)
3674 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3678 hpet_msi_write(irq
, &msg
);
3679 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3686 #endif /* CONFIG_PCI_MSI */
3688 * Hypertransport interrupt support
3690 #ifdef CONFIG_HT_IRQ
3694 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3696 struct ht_irq_msg msg
;
3697 fetch_ht_irq_msg(irq
, &msg
);
3699 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3700 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3702 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3703 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3705 write_ht_irq_msg(irq
, &msg
);
3708 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3710 struct irq_desc
*desc
= irq_to_desc(irq
);
3711 struct irq_cfg
*cfg
;
3714 dest
= set_desc_affinity(desc
, mask
);
3715 if (dest
== BAD_APICID
)
3718 cfg
= desc
->chip_data
;
3720 target_ht_irq(irq
, dest
, cfg
->vector
);
3725 static struct irq_chip ht_irq_chip
= {
3727 .mask
= mask_ht_irq
,
3728 .unmask
= unmask_ht_irq
,
3729 .ack
= ack_apic_edge
,
3731 .set_affinity
= set_ht_irq_affinity
,
3733 .retrigger
= ioapic_retrigger_irq
,
3736 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3738 struct irq_cfg
*cfg
;
3745 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3747 struct ht_irq_msg msg
;
3750 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3751 apic
->target_cpus());
3753 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3757 HT_IRQ_LOW_DEST_ID(dest
) |
3758 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3759 ((apic
->irq_dest_mode
== 0) ?
3760 HT_IRQ_LOW_DM_PHYSICAL
:
3761 HT_IRQ_LOW_DM_LOGICAL
) |
3762 HT_IRQ_LOW_RQEOI_EDGE
|
3763 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3764 HT_IRQ_LOW_MT_FIXED
:
3765 HT_IRQ_LOW_MT_ARBITRATED
) |
3766 HT_IRQ_LOW_IRQ_MASKED
;
3768 write_ht_irq_msg(irq
, &msg
);
3770 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3771 handle_edge_irq
, "edge");
3773 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3777 #endif /* CONFIG_HT_IRQ */
3779 #ifdef CONFIG_X86_UV
3781 * Re-target the irq to the specified CPU and enable the specified MMR located
3782 * on the specified blade to allow the sending of MSIs to the specified CPU.
3784 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3785 unsigned long mmr_offset
)
3787 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3788 struct irq_cfg
*cfg
;
3790 unsigned long mmr_value
;
3791 struct uv_IO_APIC_route_entry
*entry
;
3792 unsigned long flags
;
3797 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3801 spin_lock_irqsave(&vector_lock
, flags
);
3802 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3804 spin_unlock_irqrestore(&vector_lock
, flags
);
3807 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3808 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3810 entry
->vector
= cfg
->vector
;
3811 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3812 entry
->dest_mode
= apic
->irq_dest_mode
;
3813 entry
->polarity
= 0;
3816 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3818 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3819 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3825 * Disable the specified MMR located on the specified blade so that MSIs are
3826 * longer allowed to be sent.
3828 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3830 unsigned long mmr_value
;
3831 struct uv_IO_APIC_route_entry
*entry
;
3835 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3836 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3840 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3841 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3843 #endif /* CONFIG_X86_64 */
3845 int __init
io_apic_get_redir_entries (int ioapic
)
3847 union IO_APIC_reg_01 reg_01
;
3848 unsigned long flags
;
3850 spin_lock_irqsave(&ioapic_lock
, flags
);
3851 reg_01
.raw
= io_apic_read(ioapic
, 1);
3852 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3854 return reg_01
.bits
.entries
;
3857 void __init
probe_nr_irqs_gsi(void)
3861 nr
= acpi_probe_gsi();
3862 if (nr
> nr_irqs_gsi
) {
3865 /* for acpi=off or acpi is not compiled in */
3869 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3870 nr
+= io_apic_get_redir_entries(idx
) + 1;
3872 if (nr
> nr_irqs_gsi
)
3876 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3879 #ifdef CONFIG_SPARSE_IRQ
3880 int __init
arch_probe_nr_irqs(void)
3884 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3885 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3887 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3888 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3890 * for MSI and HT dyn irq
3892 nr
+= nr_irqs_gsi
* 16;
3901 /* --------------------------------------------------------------------------
3902 ACPI-based IOAPIC Configuration
3903 -------------------------------------------------------------------------- */
3907 #ifdef CONFIG_X86_32
3908 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3910 union IO_APIC_reg_00 reg_00
;
3911 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3913 unsigned long flags
;
3917 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3918 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3919 * supports up to 16 on one shared APIC bus.
3921 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3922 * advantage of new APIC bus architecture.
3925 if (physids_empty(apic_id_map
))
3926 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3928 spin_lock_irqsave(&ioapic_lock
, flags
);
3929 reg_00
.raw
= io_apic_read(ioapic
, 0);
3930 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3932 if (apic_id
>= get_physical_broadcast()) {
3933 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3934 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3935 apic_id
= reg_00
.bits
.ID
;
3939 * Every APIC in a system must have a unique ID or we get lots of nice
3940 * 'stuck on smp_invalidate_needed IPI wait' messages.
3942 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3944 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3945 if (!apic
->check_apicid_used(apic_id_map
, i
))
3949 if (i
== get_physical_broadcast())
3950 panic("Max apic_id exceeded!\n");
3952 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3953 "trying %d\n", ioapic
, apic_id
, i
);
3958 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3959 physids_or(apic_id_map
, apic_id_map
, tmp
);
3961 if (reg_00
.bits
.ID
!= apic_id
) {
3962 reg_00
.bits
.ID
= apic_id
;
3964 spin_lock_irqsave(&ioapic_lock
, flags
);
3965 io_apic_write(ioapic
, 0, reg_00
.raw
);
3966 reg_00
.raw
= io_apic_read(ioapic
, 0);
3967 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3970 if (reg_00
.bits
.ID
!= apic_id
) {
3971 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3976 apic_printk(APIC_VERBOSE
, KERN_INFO
3977 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3982 int __init
io_apic_get_version(int ioapic
)
3984 union IO_APIC_reg_01 reg_01
;
3985 unsigned long flags
;
3987 spin_lock_irqsave(&ioapic_lock
, flags
);
3988 reg_01
.raw
= io_apic_read(ioapic
, 1);
3989 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3991 return reg_01
.bits
.version
;
3995 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3997 struct irq_desc
*desc
;
3998 struct irq_cfg
*cfg
;
3999 int cpu
= boot_cpu_id
;
4001 if (!IO_APIC_IRQ(irq
)) {
4002 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
4007 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
4009 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
4014 * IRQs < 16 are already in the irq_2_pin[] map
4016 if (irq
>= NR_IRQS_LEGACY
) {
4017 cfg
= desc
->chip_data
;
4018 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
4021 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
4027 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4031 if (skip_ioapic_setup
)
4034 for (i
= 0; i
< mp_irq_entries
; i
++)
4035 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4036 mp_irqs
[i
].srcbusirq
== bus_irq
)
4038 if (i
>= mp_irq_entries
)
4041 *trigger
= irq_trigger(i
);
4042 *polarity
= irq_polarity(i
);
4046 #endif /* CONFIG_ACPI */
4049 * This function currently is only a helper for the i386 smp boot process where
4050 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4051 * so mask in all cases should simply be apic->target_cpus()
4054 void __init
setup_ioapic_dest(void)
4056 int pin
, ioapic
, irq
, irq_entry
;
4057 struct irq_desc
*desc
;
4058 struct irq_cfg
*cfg
;
4059 const struct cpumask
*mask
;
4061 if (skip_ioapic_setup
== 1)
4064 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4065 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4066 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4067 if (irq_entry
== -1)
4069 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4071 /* setup_IO_APIC_irqs could fail to get vector for some device
4072 * when you have too many devices, because at that time only boot
4075 desc
= irq_to_desc(irq
);
4076 cfg
= desc
->chip_data
;
4078 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4079 irq_trigger(irq_entry
),
4080 irq_polarity(irq_entry
));
4086 * Honour affinities which have been set in early boot
4089 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4090 mask
= desc
->affinity
;
4092 mask
= apic
->target_cpus();
4094 if (intr_remapping_enabled
)
4095 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4097 set_ioapic_affinity_irq_desc(desc
, mask
);
4104 #define IOAPIC_RESOURCE_NAME_SIZE 11
4106 static struct resource
*ioapic_resources
;
4108 static struct resource
* __init
ioapic_setup_resources(void)
4111 struct resource
*res
;
4115 if (nr_ioapics
<= 0)
4118 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4121 mem
= alloc_bootmem(n
);
4125 mem
+= sizeof(struct resource
) * nr_ioapics
;
4127 for (i
= 0; i
< nr_ioapics
; i
++) {
4129 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4130 sprintf(mem
, "IOAPIC %u", i
);
4131 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4135 ioapic_resources
= res
;
4140 void __init
ioapic_init_mappings(void)
4142 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4143 struct resource
*ioapic_res
;
4146 ioapic_res
= ioapic_setup_resources();
4147 for (i
= 0; i
< nr_ioapics
; i
++) {
4148 if (smp_found_config
) {
4149 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4150 #ifdef CONFIG_X86_32
4153 "WARNING: bogus zero IO-APIC "
4154 "address found in MPTABLE, "
4155 "disabling IO/APIC support!\n");
4156 smp_found_config
= 0;
4157 skip_ioapic_setup
= 1;
4158 goto fake_ioapic_page
;
4162 #ifdef CONFIG_X86_32
4165 ioapic_phys
= (unsigned long)
4166 alloc_bootmem_pages(PAGE_SIZE
);
4167 ioapic_phys
= __pa(ioapic_phys
);
4169 set_fixmap_nocache(idx
, ioapic_phys
);
4170 apic_printk(APIC_VERBOSE
,
4171 "mapped IOAPIC to %08lx (%08lx)\n",
4172 __fix_to_virt(idx
), ioapic_phys
);
4175 if (ioapic_res
!= NULL
) {
4176 ioapic_res
->start
= ioapic_phys
;
4177 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4183 static int __init
ioapic_insert_resources(void)
4186 struct resource
*r
= ioapic_resources
;
4189 if (nr_ioapics
> 0) {
4191 "IO APIC resources couldn't be allocated.\n");
4197 for (i
= 0; i
< nr_ioapics
; i
++) {
4198 insert_resource(&iomem_resource
, r
);
4205 /* Insert the IO APIC resources after PCI initialization has occured to handle
4206 * IO APICS that are mapped in on a BAR in PCI space. */
4207 late_initcall(ioapic_insert_resources
);