2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug
= -1;
75 static DEFINE_SPINLOCK(ioapic_lock
);
76 static DEFINE_SPINLOCK(vector_lock
);
79 * # of IRQ routing registers
81 int nr_ioapic_registers
[MAX_IO_APICS
];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
97 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
99 int skip_ioapic_setup
;
101 void arch_disable_smp_support(void)
105 noioapicreroute
= -1;
107 skip_ioapic_setup
= 1;
110 static int __init
parse_noapic(char *str
)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic
);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list
{
129 struct irq_pin_list
*next
;
132 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
134 struct irq_pin_list
*pin
;
137 node
= cpu_to_node(cpu
);
139 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
145 struct irq_pin_list
*irq_2_pin
;
146 cpumask_var_t domain
;
147 cpumask_var_t old_domain
;
148 unsigned move_cleanup_count
;
150 u8 move_in_progress
: 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152 u8 move_desc_pending
: 1;
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx
[] = {
160 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
162 [0] = { .vector
= IRQ0_VECTOR
, },
163 [1] = { .vector
= IRQ1_VECTOR
, },
164 [2] = { .vector
= IRQ2_VECTOR
, },
165 [3] = { .vector
= IRQ3_VECTOR
, },
166 [4] = { .vector
= IRQ4_VECTOR
, },
167 [5] = { .vector
= IRQ5_VECTOR
, },
168 [6] = { .vector
= IRQ6_VECTOR
, },
169 [7] = { .vector
= IRQ7_VECTOR
, },
170 [8] = { .vector
= IRQ8_VECTOR
, },
171 [9] = { .vector
= IRQ9_VECTOR
, },
172 [10] = { .vector
= IRQ10_VECTOR
, },
173 [11] = { .vector
= IRQ11_VECTOR
, },
174 [12] = { .vector
= IRQ12_VECTOR
, },
175 [13] = { .vector
= IRQ13_VECTOR
, },
176 [14] = { .vector
= IRQ14_VECTOR
, },
177 [15] = { .vector
= IRQ15_VECTOR
, },
180 int __init
arch_early_irq_init(void)
183 struct irq_desc
*desc
;
188 count
= ARRAY_SIZE(irq_cfgx
);
190 for (i
= 0; i
< count
; i
++) {
191 desc
= irq_to_desc(i
);
192 desc
->chip_data
= &cfg
[i
];
193 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
194 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
195 if (i
< NR_IRQS_LEGACY
)
196 cpumask_setall(cfg
[i
].domain
);
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg
*irq_cfg(unsigned int irq
)
205 struct irq_cfg
*cfg
= NULL
;
206 struct irq_desc
*desc
;
208 desc
= irq_to_desc(irq
);
210 cfg
= desc
->chip_data
;
215 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
220 node
= cpu_to_node(cpu
);
222 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
224 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
227 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
229 free_cpumask_var(cfg
->domain
);
233 cpumask_clear(cfg
->domain
);
234 cpumask_clear(cfg
->old_domain
);
241 int arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
245 cfg
= desc
->chip_data
;
247 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
248 if (!desc
->chip_data
) {
249 printk(KERN_ERR
"can not alloc irq_cfg\n");
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
260 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
262 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
264 cfg
->irq_2_pin
= NULL
;
265 old_entry
= old_cfg
->irq_2_pin
;
269 entry
= get_one_free_irq_2_pin(cpu
);
273 entry
->apic
= old_entry
->apic
;
274 entry
->pin
= old_entry
->pin
;
277 old_entry
= old_entry
->next
;
279 entry
= get_one_free_irq_2_pin(cpu
);
287 /* still use the old one */
290 entry
->apic
= old_entry
->apic
;
291 entry
->pin
= old_entry
->pin
;
294 old_entry
= old_entry
->next
;
298 cfg
->irq_2_pin
= head
;
301 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
303 struct irq_pin_list
*entry
, *next
;
305 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
308 entry
= old_cfg
->irq_2_pin
;
315 old_cfg
->irq_2_pin
= NULL
;
318 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
319 struct irq_desc
*desc
, int cpu
)
322 struct irq_cfg
*old_cfg
;
324 cfg
= get_one_free_irq_cfg(cpu
);
329 desc
->chip_data
= cfg
;
331 old_cfg
= old_desc
->chip_data
;
333 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
335 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
338 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
343 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
345 struct irq_cfg
*old_cfg
, *cfg
;
347 old_cfg
= old_desc
->chip_data
;
348 cfg
= desc
->chip_data
;
354 free_irq_2_pin(old_cfg
, cfg
);
355 free_irq_cfg(old_cfg
);
356 old_desc
->chip_data
= NULL
;
361 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
363 struct irq_cfg
*cfg
= desc
->chip_data
;
365 if (!cfg
->move_in_progress
) {
366 /* it means that domain is not changed */
367 if (!cpumask_intersects(desc
->affinity
, mask
))
368 cfg
->move_desc_pending
= 1;
374 static struct irq_cfg
*irq_cfg(unsigned int irq
)
376 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
383 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
390 unsigned int unused
[3];
392 unsigned int unused2
[11];
396 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
398 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
399 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
402 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
405 writel(vector
, &io_apic
->eoi
);
408 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
410 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
411 writel(reg
, &io_apic
->index
);
412 return readl(&io_apic
->data
);
415 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
417 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
418 writel(reg
, &io_apic
->index
);
419 writel(value
, &io_apic
->data
);
423 * Re-write a value: to be used for read-modify-write
424 * cycles where the read already set up the index register.
426 * Older SiS APIC requires we rewrite the index register
428 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
430 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
433 writel(reg
, &io_apic
->index
);
434 writel(value
, &io_apic
->data
);
437 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
439 struct irq_pin_list
*entry
;
442 spin_lock_irqsave(&ioapic_lock
, flags
);
443 entry
= cfg
->irq_2_pin
;
451 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
452 /* Is the remote IRR bit set? */
453 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
454 spin_unlock_irqrestore(&ioapic_lock
, flags
);
461 spin_unlock_irqrestore(&ioapic_lock
, flags
);
467 struct { u32 w1
, w2
; };
468 struct IO_APIC_route_entry entry
;
471 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
473 union entry_union eu
;
475 spin_lock_irqsave(&ioapic_lock
, flags
);
476 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
477 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
478 spin_unlock_irqrestore(&ioapic_lock
, flags
);
483 * When we write a new IO APIC routing entry, we need to write the high
484 * word first! If the mask bit in the low word is clear, we will enable
485 * the interrupt, and we need to make sure the entry is fully populated
486 * before that happens.
489 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
491 union entry_union eu
;
493 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
494 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
497 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
500 spin_lock_irqsave(&ioapic_lock
, flags
);
501 __ioapic_write_entry(apic
, pin
, e
);
502 spin_unlock_irqrestore(&ioapic_lock
, flags
);
506 * When we mask an IO APIC routing entry, we need to write the low
507 * word first, in order to set the mask bit before we change the
510 static void ioapic_mask_entry(int apic
, int pin
)
513 union entry_union eu
= { .entry
.mask
= 1 };
515 spin_lock_irqsave(&ioapic_lock
, flags
);
516 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
517 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
518 spin_unlock_irqrestore(&ioapic_lock
, flags
);
522 static void send_cleanup_vector(struct irq_cfg
*cfg
)
524 cpumask_var_t cleanup_mask
;
526 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
528 cfg
->move_cleanup_count
= 0;
529 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
530 cfg
->move_cleanup_count
++;
531 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
532 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
534 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
535 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
536 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
537 free_cpumask_var(cleanup_mask
);
539 cfg
->move_in_progress
= 0;
542 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
545 struct irq_pin_list
*entry
;
546 u8 vector
= cfg
->vector
;
548 entry
= cfg
->irq_2_pin
;
558 * With interrupt-remapping, destination information comes
559 * from interrupt-remapping table entry.
561 if (!irq_remapped(irq
))
562 io_apic_write(apic
, 0x11 + pin
*2, dest
);
563 reg
= io_apic_read(apic
, 0x10 + pin
*2);
564 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
566 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
574 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
577 * Either sets desc->affinity to a valid value, and returns
578 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
579 * leaves desc->affinity untouched.
582 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
587 if (!cpumask_intersects(mask
, cpu_online_mask
))
591 cfg
= desc
->chip_data
;
592 if (assign_irq_vector(irq
, cfg
, mask
))
595 /* check that before desc->addinity get updated */
596 set_extra_move_desc(desc
, mask
);
598 cpumask_copy(desc
->affinity
, mask
);
600 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
604 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
612 cfg
= desc
->chip_data
;
614 spin_lock_irqsave(&ioapic_lock
, flags
);
615 dest
= set_desc_affinity(desc
, mask
);
616 if (dest
!= BAD_APICID
) {
617 /* Only the high 8 bits are valid. */
618 dest
= SET_APIC_LOGICAL_ID(dest
);
619 __target_IO_APIC_irq(irq
, dest
, cfg
);
621 spin_unlock_irqrestore(&ioapic_lock
, flags
);
625 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
627 struct irq_desc
*desc
;
629 desc
= irq_to_desc(irq
);
631 set_ioapic_affinity_irq_desc(desc
, mask
);
633 #endif /* CONFIG_SMP */
636 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
637 * shared ISA-space IRQs, so we have to support them. We are super
638 * fast in the common case, and fast for shared ISA-space IRQs.
640 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
642 struct irq_pin_list
*entry
;
644 entry
= cfg
->irq_2_pin
;
646 entry
= get_one_free_irq_2_pin(cpu
);
648 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
652 cfg
->irq_2_pin
= entry
;
658 while (entry
->next
) {
659 /* not again, please */
660 if (entry
->apic
== apic
&& entry
->pin
== pin
)
666 entry
->next
= get_one_free_irq_2_pin(cpu
);
673 * Reroute an IRQ to a different pin.
675 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
676 int oldapic
, int oldpin
,
677 int newapic
, int newpin
)
679 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
683 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
684 entry
->apic
= newapic
;
687 /* every one is different, right? */
693 /* why? call replace before add? */
695 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
698 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
699 int mask_and
, int mask_or
,
700 void (*final
)(struct irq_pin_list
*entry
))
703 struct irq_pin_list
*entry
;
705 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
708 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
711 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
717 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
719 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
723 static void io_apic_sync(struct irq_pin_list
*entry
)
726 * Synchronize the IO-APIC and the CPU by doing
727 * a dummy read from the IO-APIC
729 struct io_apic __iomem
*io_apic
;
730 io_apic
= io_apic_base(entry
->apic
);
731 readl(&io_apic
->data
);
734 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
736 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
738 #else /* CONFIG_X86_32 */
739 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
741 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
744 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
746 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
747 IO_APIC_REDIR_MASKED
, NULL
);
750 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
752 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
753 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
755 #endif /* CONFIG_X86_32 */
757 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
759 struct irq_cfg
*cfg
= desc
->chip_data
;
764 spin_lock_irqsave(&ioapic_lock
, flags
);
765 __mask_IO_APIC_irq(cfg
);
766 spin_unlock_irqrestore(&ioapic_lock
, flags
);
769 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
771 struct irq_cfg
*cfg
= desc
->chip_data
;
774 spin_lock_irqsave(&ioapic_lock
, flags
);
775 __unmask_IO_APIC_irq(cfg
);
776 spin_unlock_irqrestore(&ioapic_lock
, flags
);
779 static void mask_IO_APIC_irq(unsigned int irq
)
781 struct irq_desc
*desc
= irq_to_desc(irq
);
783 mask_IO_APIC_irq_desc(desc
);
785 static void unmask_IO_APIC_irq(unsigned int irq
)
787 struct irq_desc
*desc
= irq_to_desc(irq
);
789 unmask_IO_APIC_irq_desc(desc
);
792 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
794 struct IO_APIC_route_entry entry
;
796 /* Check delivery_mode to be sure we're not clearing an SMI pin */
797 entry
= ioapic_read_entry(apic
, pin
);
798 if (entry
.delivery_mode
== dest_SMI
)
801 * Disable it in the IO-APIC irq-routing table:
803 ioapic_mask_entry(apic
, pin
);
806 static void clear_IO_APIC (void)
810 for (apic
= 0; apic
< nr_ioapics
; apic
++)
811 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
812 clear_IO_APIC_pin(apic
, pin
);
817 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
818 * specific CPU-side IRQs.
822 static int pirq_entries
[MAX_PIRQS
] = {
823 [0 ... MAX_PIRQS
- 1] = -1
826 static int __init
ioapic_pirq_setup(char *str
)
829 int ints
[MAX_PIRQS
+1];
831 get_options(str
, ARRAY_SIZE(ints
), ints
);
833 apic_printk(APIC_VERBOSE
, KERN_INFO
834 "PIRQ redirection, working around broken MP-BIOS.\n");
836 if (ints
[0] < MAX_PIRQS
)
839 for (i
= 0; i
< max
; i
++) {
840 apic_printk(APIC_VERBOSE
, KERN_DEBUG
841 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
843 * PIRQs are mapped upside down, usually.
845 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
850 __setup("pirq=", ioapic_pirq_setup
);
851 #endif /* CONFIG_X86_32 */
853 #ifdef CONFIG_INTR_REMAP
854 /* I/O APIC RTE contents at the OS boot up */
855 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
858 * Saves all the IO-APIC RTE's
860 int save_IO_APIC_setup(void)
862 union IO_APIC_reg_01 reg_01
;
867 * The number of IO-APIC IRQ registers (== #pins):
869 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
870 spin_lock_irqsave(&ioapic_lock
, flags
);
871 reg_01
.raw
= io_apic_read(apic
, 1);
872 spin_unlock_irqrestore(&ioapic_lock
, flags
);
873 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
876 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
877 early_ioapic_entries
[apic
] =
878 kzalloc(sizeof(struct IO_APIC_route_entry
) *
879 nr_ioapic_registers
[apic
], GFP_KERNEL
);
880 if (!early_ioapic_entries
[apic
])
884 for (apic
= 0; apic
< nr_ioapics
; apic
++)
885 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
886 early_ioapic_entries
[apic
][pin
] =
887 ioapic_read_entry(apic
, pin
);
893 kfree(early_ioapic_entries
[apic
--]);
894 memset(early_ioapic_entries
, 0,
895 ARRAY_SIZE(early_ioapic_entries
));
900 void mask_IO_APIC_setup(void)
904 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
905 if (!early_ioapic_entries
[apic
])
907 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
908 struct IO_APIC_route_entry entry
;
910 entry
= early_ioapic_entries
[apic
][pin
];
913 ioapic_write_entry(apic
, pin
, entry
);
919 void restore_IO_APIC_setup(void)
923 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
924 if (!early_ioapic_entries
[apic
])
926 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
927 ioapic_write_entry(apic
, pin
,
928 early_ioapic_entries
[apic
][pin
]);
929 kfree(early_ioapic_entries
[apic
]);
930 early_ioapic_entries
[apic
] = NULL
;
934 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
937 * for now plain restore of previous settings.
938 * TBD: In the case of OS enabling interrupt-remapping,
939 * IO-APIC RTE's need to be setup to point to interrupt-remapping
940 * table entries. for now, do a plain restore, and wait for
941 * the setup_IO_APIC_irqs() to do proper initialization.
943 restore_IO_APIC_setup();
948 * Find the IRQ entry number of a certain pin.
950 static int find_irq_entry(int apic
, int pin
, int type
)
954 for (i
= 0; i
< mp_irq_entries
; i
++)
955 if (mp_irqs
[i
].irqtype
== type
&&
956 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
957 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
958 mp_irqs
[i
].dstirq
== pin
)
965 * Find the pin to which IRQ[irq] (ISA) is connected
967 static int __init
find_isa_irq_pin(int irq
, int type
)
971 for (i
= 0; i
< mp_irq_entries
; i
++) {
972 int lbus
= mp_irqs
[i
].srcbus
;
974 if (test_bit(lbus
, mp_bus_not_pci
) &&
975 (mp_irqs
[i
].irqtype
== type
) &&
976 (mp_irqs
[i
].srcbusirq
== irq
))
978 return mp_irqs
[i
].dstirq
;
983 static int __init
find_isa_irq_apic(int irq
, int type
)
987 for (i
= 0; i
< mp_irq_entries
; i
++) {
988 int lbus
= mp_irqs
[i
].srcbus
;
990 if (test_bit(lbus
, mp_bus_not_pci
) &&
991 (mp_irqs
[i
].irqtype
== type
) &&
992 (mp_irqs
[i
].srcbusirq
== irq
))
995 if (i
< mp_irq_entries
) {
997 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
998 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
1007 * Find a specific PCI IRQ entry.
1008 * Not an __init, possibly needed by modules
1010 static int pin_2_irq(int idx
, int apic
, int pin
);
1012 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1014 int apic
, i
, best_guess
= -1;
1016 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1018 if (test_bit(bus
, mp_bus_not_pci
)) {
1019 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1022 for (i
= 0; i
< mp_irq_entries
; i
++) {
1023 int lbus
= mp_irqs
[i
].srcbus
;
1025 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1026 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1027 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1030 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1031 !mp_irqs
[i
].irqtype
&&
1033 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1034 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1036 if (!(apic
|| IO_APIC_IRQ(irq
)))
1039 if (pin
== (mp_irqs
[i
].srcbusirq
& 3))
1042 * Use the first all-but-pin matching entry as a
1043 * best-guess fuzzy result for broken mptables.
1052 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1054 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1056 * EISA Edge/Level control register, ELCR
1058 static int EISA_ELCR(unsigned int irq
)
1060 if (irq
< NR_IRQS_LEGACY
) {
1061 unsigned int port
= 0x4d0 + (irq
>> 3);
1062 return (inb(port
) >> (irq
& 7)) & 1;
1064 apic_printk(APIC_VERBOSE
, KERN_INFO
1065 "Broken MPtable reports ISA irq %d\n", irq
);
1071 /* ISA interrupts are always polarity zero edge triggered,
1072 * when listed as conforming in the MP table. */
1074 #define default_ISA_trigger(idx) (0)
1075 #define default_ISA_polarity(idx) (0)
1077 /* EISA interrupts are always polarity zero and can be edge or level
1078 * trigger depending on the ELCR value. If an interrupt is listed as
1079 * EISA conforming in the MP table, that means its trigger type must
1080 * be read in from the ELCR */
1082 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1083 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1085 /* PCI interrupts are always polarity one level triggered,
1086 * when listed as conforming in the MP table. */
1088 #define default_PCI_trigger(idx) (1)
1089 #define default_PCI_polarity(idx) (1)
1091 /* MCA interrupts are always polarity zero level triggered,
1092 * when listed as conforming in the MP table. */
1094 #define default_MCA_trigger(idx) (1)
1095 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1097 static int MPBIOS_polarity(int idx
)
1099 int bus
= mp_irqs
[idx
].srcbus
;
1103 * Determine IRQ line polarity (high active or low active):
1105 switch (mp_irqs
[idx
].irqflag
& 3)
1107 case 0: /* conforms, ie. bus-type dependent polarity */
1108 if (test_bit(bus
, mp_bus_not_pci
))
1109 polarity
= default_ISA_polarity(idx
);
1111 polarity
= default_PCI_polarity(idx
);
1113 case 1: /* high active */
1118 case 2: /* reserved */
1120 printk(KERN_WARNING
"broken BIOS!!\n");
1124 case 3: /* low active */
1129 default: /* invalid */
1131 printk(KERN_WARNING
"broken BIOS!!\n");
1139 static int MPBIOS_trigger(int idx
)
1141 int bus
= mp_irqs
[idx
].srcbus
;
1145 * Determine IRQ trigger mode (edge or level sensitive):
1147 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
1149 case 0: /* conforms, ie. bus-type dependent */
1150 if (test_bit(bus
, mp_bus_not_pci
))
1151 trigger
= default_ISA_trigger(idx
);
1153 trigger
= default_PCI_trigger(idx
);
1154 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1155 switch (mp_bus_id_to_type
[bus
]) {
1156 case MP_BUS_ISA
: /* ISA pin */
1158 /* set before the switch */
1161 case MP_BUS_EISA
: /* EISA pin */
1163 trigger
= default_EISA_trigger(idx
);
1166 case MP_BUS_PCI
: /* PCI pin */
1168 /* set before the switch */
1171 case MP_BUS_MCA
: /* MCA pin */
1173 trigger
= default_MCA_trigger(idx
);
1178 printk(KERN_WARNING
"broken BIOS!!\n");
1190 case 2: /* reserved */
1192 printk(KERN_WARNING
"broken BIOS!!\n");
1201 default: /* invalid */
1203 printk(KERN_WARNING
"broken BIOS!!\n");
1211 static inline int irq_polarity(int idx
)
1213 return MPBIOS_polarity(idx
);
1216 static inline int irq_trigger(int idx
)
1218 return MPBIOS_trigger(idx
);
1221 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1222 static int pin_2_irq(int idx
, int apic
, int pin
)
1225 int bus
= mp_irqs
[idx
].srcbus
;
1228 * Debugging check, we are in big trouble if this message pops up!
1230 if (mp_irqs
[idx
].dstirq
!= pin
)
1231 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1233 if (test_bit(bus
, mp_bus_not_pci
)) {
1234 irq
= mp_irqs
[idx
].srcbusirq
;
1237 * PCI IRQs are mapped in order
1241 irq
+= nr_ioapic_registers
[i
++];
1244 * For MPS mode, so far only needed by ES7000 platform
1246 if (ioapic_renumber_irq
)
1247 irq
= ioapic_renumber_irq(apic
, irq
);
1250 #ifdef CONFIG_X86_32
1252 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1254 if ((pin
>= 16) && (pin
<= 23)) {
1255 if (pirq_entries
[pin
-16] != -1) {
1256 if (!pirq_entries
[pin
-16]) {
1257 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1258 "disabling PIRQ%d\n", pin
-16);
1260 irq
= pirq_entries
[pin
-16];
1261 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1262 "using PIRQ%d -> IRQ %d\n",
1272 void lock_vector_lock(void)
1274 /* Used to the online set of cpus does not change
1275 * during assign_irq_vector.
1277 spin_lock(&vector_lock
);
1280 void unlock_vector_lock(void)
1282 spin_unlock(&vector_lock
);
1286 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1289 * NOTE! The local APIC isn't very good at handling
1290 * multiple interrupts at the same interrupt level.
1291 * As the interrupt level is determined by taking the
1292 * vector number and shifting that right by 4, we
1293 * want to spread these out a bit so that they don't
1294 * all fall in the same interrupt level.
1296 * Also, we've got to be careful not to trash gate
1297 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1299 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1300 unsigned int old_vector
;
1302 cpumask_var_t tmp_mask
;
1304 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1307 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1310 old_vector
= cfg
->vector
;
1312 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1313 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1314 if (!cpumask_empty(tmp_mask
)) {
1315 free_cpumask_var(tmp_mask
);
1320 /* Only try and allocate irqs on cpus that are present */
1322 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1326 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1328 vector
= current_vector
;
1329 offset
= current_offset
;
1332 if (vector
>= first_system_vector
) {
1333 /* If out of vectors on large boxen, must share them. */
1334 offset
= (offset
+ 1) % 8;
1335 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1337 if (unlikely(current_vector
== vector
))
1340 if (test_bit(vector
, used_vectors
))
1343 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1344 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1347 current_vector
= vector
;
1348 current_offset
= offset
;
1350 cfg
->move_in_progress
= 1;
1351 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1353 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1354 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1355 cfg
->vector
= vector
;
1356 cpumask_copy(cfg
->domain
, tmp_mask
);
1360 free_cpumask_var(tmp_mask
);
1365 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1368 unsigned long flags
;
1370 spin_lock_irqsave(&vector_lock
, flags
);
1371 err
= __assign_irq_vector(irq
, cfg
, mask
);
1372 spin_unlock_irqrestore(&vector_lock
, flags
);
1376 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1380 BUG_ON(!cfg
->vector
);
1382 vector
= cfg
->vector
;
1383 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1384 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1387 cpumask_clear(cfg
->domain
);
1389 if (likely(!cfg
->move_in_progress
))
1391 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1392 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1394 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1396 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1400 cfg
->move_in_progress
= 0;
1403 void __setup_vector_irq(int cpu
)
1405 /* Initialize vector_irq on a new cpu */
1406 /* This function must be called with vector_lock held */
1408 struct irq_cfg
*cfg
;
1409 struct irq_desc
*desc
;
1411 /* Mark the inuse vectors */
1412 for_each_irq_desc(irq
, desc
) {
1413 cfg
= desc
->chip_data
;
1414 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1416 vector
= cfg
->vector
;
1417 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1419 /* Mark the free vectors */
1420 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1421 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1426 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1427 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1431 static struct irq_chip ioapic_chip
;
1432 static struct irq_chip ir_ioapic_chip
;
1434 #define IOAPIC_AUTO -1
1435 #define IOAPIC_EDGE 0
1436 #define IOAPIC_LEVEL 1
1438 #ifdef CONFIG_X86_32
1439 static inline int IO_APIC_irq_trigger(int irq
)
1443 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1444 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1445 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1446 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1447 return irq_trigger(idx
);
1451 * nonexistent IRQs are edge default
1456 static inline int IO_APIC_irq_trigger(int irq
)
1462 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1465 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1466 trigger
== IOAPIC_LEVEL
)
1467 desc
->status
|= IRQ_LEVEL
;
1469 desc
->status
&= ~IRQ_LEVEL
;
1471 if (irq_remapped(irq
)) {
1472 desc
->status
|= IRQ_MOVE_PCNTXT
;
1474 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1478 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1479 handle_edge_irq
, "edge");
1483 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1484 trigger
== IOAPIC_LEVEL
)
1485 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1489 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1490 handle_edge_irq
, "edge");
1493 int setup_ioapic_entry(int apic_id
, int irq
,
1494 struct IO_APIC_route_entry
*entry
,
1495 unsigned int destination
, int trigger
,
1496 int polarity
, int vector
, int pin
)
1499 * add it to the IO-APIC irq-routing table:
1501 memset(entry
,0,sizeof(*entry
));
1503 if (intr_remapping_enabled
) {
1504 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1506 struct IR_IO_APIC_route_entry
*ir_entry
=
1507 (struct IR_IO_APIC_route_entry
*) entry
;
1511 panic("No mapping iommu for ioapic %d\n", apic_id
);
1513 index
= alloc_irte(iommu
, irq
, 1);
1515 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1517 memset(&irte
, 0, sizeof(irte
));
1520 irte
.dst_mode
= apic
->irq_dest_mode
;
1522 * Trigger mode in the IRTE will always be edge, and the
1523 * actual level or edge trigger will be setup in the IO-APIC
1524 * RTE. This will help simplify level triggered irq migration.
1525 * For more details, see the comments above explainig IO-APIC
1526 * irq migration in the presence of interrupt-remapping.
1528 irte
.trigger_mode
= 0;
1529 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1530 irte
.vector
= vector
;
1531 irte
.dest_id
= IRTE_DEST(destination
);
1533 modify_irte(irq
, &irte
);
1535 ir_entry
->index2
= (index
>> 15) & 0x1;
1537 ir_entry
->format
= 1;
1538 ir_entry
->index
= (index
& 0x7fff);
1540 * IO-APIC RTE will be configured with virtual vector.
1541 * irq handler will do the explicit EOI to the io-apic.
1543 ir_entry
->vector
= pin
;
1545 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1546 entry
->dest_mode
= apic
->irq_dest_mode
;
1547 entry
->dest
= destination
;
1548 entry
->vector
= vector
;
1551 entry
->mask
= 0; /* enable IRQ */
1552 entry
->trigger
= trigger
;
1553 entry
->polarity
= polarity
;
1555 /* Mask level triggered irqs.
1556 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1563 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1564 int trigger
, int polarity
)
1566 struct irq_cfg
*cfg
;
1567 struct IO_APIC_route_entry entry
;
1570 if (!IO_APIC_IRQ(irq
))
1573 cfg
= desc
->chip_data
;
1575 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1578 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1580 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1581 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1582 "IRQ %d Mode:%i Active:%i)\n",
1583 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1584 irq
, trigger
, polarity
);
1587 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1588 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1589 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1590 mp_ioapics
[apic_id
].apicid
, pin
);
1591 __clear_irq_vector(irq
, cfg
);
1595 ioapic_register_intr(irq
, desc
, trigger
);
1596 if (irq
< NR_IRQS_LEGACY
)
1597 disable_8259A_irq(irq
);
1599 ioapic_write_entry(apic_id
, pin
, entry
);
1602 static void __init
setup_IO_APIC_irqs(void)
1604 int apic_id
, pin
, idx
, irq
;
1606 struct irq_desc
*desc
;
1607 struct irq_cfg
*cfg
;
1608 int cpu
= boot_cpu_id
;
1610 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1612 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
1613 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1615 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1619 apic_printk(APIC_VERBOSE
,
1620 KERN_DEBUG
" %d-%d",
1621 mp_ioapics
[apic_id
].apicid
, pin
);
1623 apic_printk(APIC_VERBOSE
, " %d-%d",
1624 mp_ioapics
[apic_id
].apicid
, pin
);
1628 apic_printk(APIC_VERBOSE
,
1629 " (apicid-pin) not connected\n");
1633 irq
= pin_2_irq(idx
, apic_id
, pin
);
1636 * Skip the timer IRQ if there's a quirk handler
1637 * installed and if it returns 1:
1639 if (apic
->multi_timer_check
&&
1640 apic
->multi_timer_check(apic_id
, irq
))
1643 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1645 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1648 cfg
= desc
->chip_data
;
1649 add_pin_to_irq_cpu(cfg
, cpu
, apic_id
, pin
);
1651 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1652 irq_trigger(idx
), irq_polarity(idx
));
1657 apic_printk(APIC_VERBOSE
,
1658 " (apicid-pin) not connected\n");
1662 * Set up the timer pin, possibly with the 8259A-master behind.
1664 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1667 struct IO_APIC_route_entry entry
;
1669 if (intr_remapping_enabled
)
1672 memset(&entry
, 0, sizeof(entry
));
1675 * We use logical delivery to get the timer IRQ
1678 entry
.dest_mode
= apic
->irq_dest_mode
;
1679 entry
.mask
= 0; /* don't mask IRQ for edge */
1680 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1681 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1684 entry
.vector
= vector
;
1687 * The timer IRQ doesn't have to know that behind the
1688 * scene we may have a 8259A-master in AEOI mode ...
1690 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1693 * Add it to the IO-APIC irq-routing table:
1695 ioapic_write_entry(apic_id
, pin
, entry
);
1699 __apicdebuginit(void) print_IO_APIC(void)
1702 union IO_APIC_reg_00 reg_00
;
1703 union IO_APIC_reg_01 reg_01
;
1704 union IO_APIC_reg_02 reg_02
;
1705 union IO_APIC_reg_03 reg_03
;
1706 unsigned long flags
;
1707 struct irq_cfg
*cfg
;
1708 struct irq_desc
*desc
;
1711 if (apic_verbosity
== APIC_QUIET
)
1714 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1715 for (i
= 0; i
< nr_ioapics
; i
++)
1716 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1717 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1720 * We are a bit conservative about what we expect. We have to
1721 * know about every hardware change ASAP.
1723 printk(KERN_INFO
"testing the IO APIC.......................\n");
1725 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1727 spin_lock_irqsave(&ioapic_lock
, flags
);
1728 reg_00
.raw
= io_apic_read(apic
, 0);
1729 reg_01
.raw
= io_apic_read(apic
, 1);
1730 if (reg_01
.bits
.version
>= 0x10)
1731 reg_02
.raw
= io_apic_read(apic
, 2);
1732 if (reg_01
.bits
.version
>= 0x20)
1733 reg_03
.raw
= io_apic_read(apic
, 3);
1734 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1737 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1738 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1739 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1740 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1741 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1743 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1744 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1746 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1747 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1750 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1751 * but the value of reg_02 is read as the previous read register
1752 * value, so ignore it if reg_02 == reg_01.
1754 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1755 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1756 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1760 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1761 * or reg_03, but the value of reg_0[23] is read as the previous read
1762 * register value, so ignore it if reg_03 == reg_0[12].
1764 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1765 reg_03
.raw
!= reg_01
.raw
) {
1766 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1767 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1770 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1772 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1773 " Stat Dmod Deli Vect: \n");
1775 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1776 struct IO_APIC_route_entry entry
;
1778 entry
= ioapic_read_entry(apic
, i
);
1780 printk(KERN_DEBUG
" %02x %03X ",
1785 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1790 entry
.delivery_status
,
1792 entry
.delivery_mode
,
1797 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1798 for_each_irq_desc(irq
, desc
) {
1799 struct irq_pin_list
*entry
;
1801 cfg
= desc
->chip_data
;
1802 entry
= cfg
->irq_2_pin
;
1805 printk(KERN_DEBUG
"IRQ%d ", irq
);
1807 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1810 entry
= entry
->next
;
1815 printk(KERN_INFO
".................................... done.\n");
1820 __apicdebuginit(void) print_APIC_bitfield(int base
)
1825 if (apic_verbosity
== APIC_QUIET
)
1828 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1829 for (i
= 0; i
< 8; i
++) {
1830 v
= apic_read(base
+ i
*0x10);
1831 for (j
= 0; j
< 32; j
++) {
1841 __apicdebuginit(void) print_local_APIC(void *dummy
)
1843 unsigned int v
, ver
, maxlvt
;
1846 if (apic_verbosity
== APIC_QUIET
)
1849 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1850 smp_processor_id(), hard_smp_processor_id());
1851 v
= apic_read(APIC_ID
);
1852 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1853 v
= apic_read(APIC_LVR
);
1854 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1855 ver
= GET_APIC_VERSION(v
);
1856 maxlvt
= lapic_get_maxlvt();
1858 v
= apic_read(APIC_TASKPRI
);
1859 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1861 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1862 if (!APIC_XAPIC(ver
)) {
1863 v
= apic_read(APIC_ARBPRI
);
1864 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1865 v
& APIC_ARBPRI_MASK
);
1867 v
= apic_read(APIC_PROCPRI
);
1868 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1872 * Remote read supported only in the 82489DX and local APIC for
1873 * Pentium processors.
1875 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1876 v
= apic_read(APIC_RRR
);
1877 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1880 v
= apic_read(APIC_LDR
);
1881 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1882 if (!x2apic_enabled()) {
1883 v
= apic_read(APIC_DFR
);
1884 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1886 v
= apic_read(APIC_SPIV
);
1887 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1889 printk(KERN_DEBUG
"... APIC ISR field:\n");
1890 print_APIC_bitfield(APIC_ISR
);
1891 printk(KERN_DEBUG
"... APIC TMR field:\n");
1892 print_APIC_bitfield(APIC_TMR
);
1893 printk(KERN_DEBUG
"... APIC IRR field:\n");
1894 print_APIC_bitfield(APIC_IRR
);
1896 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1897 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1898 apic_write(APIC_ESR
, 0);
1900 v
= apic_read(APIC_ESR
);
1901 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1904 icr
= apic_icr_read();
1905 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1906 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1908 v
= apic_read(APIC_LVTT
);
1909 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1911 if (maxlvt
> 3) { /* PC is LVT#4. */
1912 v
= apic_read(APIC_LVTPC
);
1913 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1915 v
= apic_read(APIC_LVT0
);
1916 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1917 v
= apic_read(APIC_LVT1
);
1918 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1920 if (maxlvt
> 2) { /* ERR is LVT#3. */
1921 v
= apic_read(APIC_LVTERR
);
1922 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1925 v
= apic_read(APIC_TMICT
);
1926 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1927 v
= apic_read(APIC_TMCCT
);
1928 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1929 v
= apic_read(APIC_TDCR
);
1930 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1934 __apicdebuginit(void) print_all_local_APICs(void)
1939 for_each_online_cpu(cpu
)
1940 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1944 __apicdebuginit(void) print_PIC(void)
1947 unsigned long flags
;
1949 if (apic_verbosity
== APIC_QUIET
)
1952 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1954 spin_lock_irqsave(&i8259A_lock
, flags
);
1956 v
= inb(0xa1) << 8 | inb(0x21);
1957 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1959 v
= inb(0xa0) << 8 | inb(0x20);
1960 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1964 v
= inb(0xa0) << 8 | inb(0x20);
1968 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1970 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1972 v
= inb(0x4d1) << 8 | inb(0x4d0);
1973 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1976 __apicdebuginit(int) print_all_ICs(void)
1979 print_all_local_APICs();
1985 fs_initcall(print_all_ICs
);
1988 /* Where if anywhere is the i8259 connect in external int mode */
1989 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1991 void __init
enable_IO_APIC(void)
1993 union IO_APIC_reg_01 reg_01
;
1994 int i8259_apic
, i8259_pin
;
1996 unsigned long flags
;
1999 * The number of IO-APIC IRQ registers (== #pins):
2001 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2002 spin_lock_irqsave(&ioapic_lock
, flags
);
2003 reg_01
.raw
= io_apic_read(apic
, 1);
2004 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2005 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2007 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2009 /* See if any of the pins is in ExtINT mode */
2010 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2011 struct IO_APIC_route_entry entry
;
2012 entry
= ioapic_read_entry(apic
, pin
);
2014 /* If the interrupt line is enabled and in ExtInt mode
2015 * I have found the pin where the i8259 is connected.
2017 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2018 ioapic_i8259
.apic
= apic
;
2019 ioapic_i8259
.pin
= pin
;
2025 /* Look to see what if the MP table has reported the ExtINT */
2026 /* If we could not find the appropriate pin by looking at the ioapic
2027 * the i8259 probably is not connected the ioapic but give the
2028 * mptable a chance anyway.
2030 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2031 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2032 /* Trust the MP table if nothing is setup in the hardware */
2033 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2034 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2035 ioapic_i8259
.pin
= i8259_pin
;
2036 ioapic_i8259
.apic
= i8259_apic
;
2038 /* Complain if the MP table and the hardware disagree */
2039 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2040 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2042 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2046 * Do not trust the IO-APIC being empty at bootup
2052 * Not an __init, needed by the reboot code
2054 void disable_IO_APIC(void)
2057 * Clear the IO-APIC before rebooting:
2062 * If the i8259 is routed through an IOAPIC
2063 * Put that IOAPIC in virtual wire mode
2064 * so legacy interrupts can be delivered.
2066 * With interrupt-remapping, for now we will use virtual wire A mode,
2067 * as virtual wire B is little complex (need to configure both
2068 * IOAPIC RTE aswell as interrupt-remapping table entry).
2069 * As this gets called during crash dump, keep this simple for now.
2071 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2072 struct IO_APIC_route_entry entry
;
2074 memset(&entry
, 0, sizeof(entry
));
2075 entry
.mask
= 0; /* Enabled */
2076 entry
.trigger
= 0; /* Edge */
2078 entry
.polarity
= 0; /* High */
2079 entry
.delivery_status
= 0;
2080 entry
.dest_mode
= 0; /* Physical */
2081 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2083 entry
.dest
= read_apic_id();
2086 * Add it to the IO-APIC irq-routing table:
2088 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2092 * Use virtual wire A mode when interrupt remapping is enabled.
2094 disconnect_bsp_APIC(!intr_remapping_enabled
&& ioapic_i8259
.pin
!= -1);
2097 #ifdef CONFIG_X86_32
2099 * function to set the IO-APIC physical IDs based on the
2100 * values stored in the MPC table.
2102 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2105 static void __init
setup_ioapic_ids_from_mpc(void)
2107 union IO_APIC_reg_00 reg_00
;
2108 physid_mask_t phys_id_present_map
;
2111 unsigned char old_id
;
2112 unsigned long flags
;
2114 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2118 * Don't check I/O APIC IDs for xAPIC systems. They have
2119 * no meaning without the serial APIC bus.
2121 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2122 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2125 * This is broken; anything with a real cpu count has to
2126 * circumvent this idiocy regardless.
2128 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2131 * Set the IOAPIC ID to the value stored in the MPC table.
2133 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2135 /* Read the register 0 value */
2136 spin_lock_irqsave(&ioapic_lock
, flags
);
2137 reg_00
.raw
= io_apic_read(apic_id
, 0);
2138 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2140 old_id
= mp_ioapics
[apic_id
].apicid
;
2142 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2143 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2144 apic_id
, mp_ioapics
[apic_id
].apicid
);
2145 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2147 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2151 * Sanity check, is the ID really free? Every APIC in a
2152 * system must have a unique ID or we get lots of nice
2153 * 'stuck on smp_invalidate_needed IPI wait' messages.
2155 if (apic
->check_apicid_used(phys_id_present_map
,
2156 mp_ioapics
[apic_id
].apicid
)) {
2157 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2158 apic_id
, mp_ioapics
[apic_id
].apicid
);
2159 for (i
= 0; i
< get_physical_broadcast(); i
++)
2160 if (!physid_isset(i
, phys_id_present_map
))
2162 if (i
>= get_physical_broadcast())
2163 panic("Max APIC ID exceeded!\n");
2164 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2166 physid_set(i
, phys_id_present_map
);
2167 mp_ioapics
[apic_id
].apicid
= i
;
2170 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2171 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2172 "phys_id_present_map\n",
2173 mp_ioapics
[apic_id
].apicid
);
2174 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2179 * We need to adjust the IRQ routing table
2180 * if the ID changed.
2182 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2183 for (i
= 0; i
< mp_irq_entries
; i
++)
2184 if (mp_irqs
[i
].dstapic
== old_id
)
2186 = mp_ioapics
[apic_id
].apicid
;
2189 * Read the right value from the MPC table and
2190 * write it into the ID register.
2192 apic_printk(APIC_VERBOSE
, KERN_INFO
2193 "...changing IO-APIC physical APIC ID to %d ...",
2194 mp_ioapics
[apic_id
].apicid
);
2196 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2197 spin_lock_irqsave(&ioapic_lock
, flags
);
2198 io_apic_write(apic_id
, 0, reg_00
.raw
);
2199 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2204 spin_lock_irqsave(&ioapic_lock
, flags
);
2205 reg_00
.raw
= io_apic_read(apic_id
, 0);
2206 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2207 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2208 printk("could not set ID!\n");
2210 apic_printk(APIC_VERBOSE
, " ok.\n");
2215 int no_timer_check __initdata
;
2217 static int __init
notimercheck(char *s
)
2222 __setup("no_timer_check", notimercheck
);
2225 * There is a nasty bug in some older SMP boards, their mptable lies
2226 * about the timer IRQ. We do the following to work around the situation:
2228 * - timer IRQ defaults to IO-APIC IRQ
2229 * - if this function detects that timer IRQs are defunct, then we fall
2230 * back to ISA timer IRQs
2232 static int __init
timer_irq_works(void)
2234 unsigned long t1
= jiffies
;
2235 unsigned long flags
;
2240 local_save_flags(flags
);
2242 /* Let ten ticks pass... */
2243 mdelay((10 * 1000) / HZ
);
2244 local_irq_restore(flags
);
2247 * Expect a few ticks at least, to be sure some possible
2248 * glue logic does not lock up after one or two first
2249 * ticks in a non-ExtINT mode. Also the local APIC
2250 * might have cached one ExtINT interrupt. Finally, at
2251 * least one tick may be lost due to delays.
2255 if (time_after(jiffies
, t1
+ 4))
2261 * In the SMP+IOAPIC case it might happen that there are an unspecified
2262 * number of pending IRQ events unhandled. These cases are very rare,
2263 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2264 * better to do it this way as thus we do not have to be aware of
2265 * 'pending' interrupts in the IRQ path, except at this point.
2268 * Edge triggered needs to resend any interrupt
2269 * that was delayed but this is now handled in the device
2274 * Starting up a edge-triggered IO-APIC interrupt is
2275 * nasty - we need to make sure that we get the edge.
2276 * If it is already asserted for some reason, we need
2277 * return 1 to indicate that is was pending.
2279 * This is not complete - we should be able to fake
2280 * an edge even if it isn't on the 8259A...
2283 static unsigned int startup_ioapic_irq(unsigned int irq
)
2285 int was_pending
= 0;
2286 unsigned long flags
;
2287 struct irq_cfg
*cfg
;
2289 spin_lock_irqsave(&ioapic_lock
, flags
);
2290 if (irq
< NR_IRQS_LEGACY
) {
2291 disable_8259A_irq(irq
);
2292 if (i8259A_irq_pending(irq
))
2296 __unmask_IO_APIC_irq(cfg
);
2297 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2302 #ifdef CONFIG_X86_64
2303 static int ioapic_retrigger_irq(unsigned int irq
)
2306 struct irq_cfg
*cfg
= irq_cfg(irq
);
2307 unsigned long flags
;
2309 spin_lock_irqsave(&vector_lock
, flags
);
2310 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2311 spin_unlock_irqrestore(&vector_lock
, flags
);
2316 static int ioapic_retrigger_irq(unsigned int irq
)
2318 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2325 * Level and edge triggered IO-APIC interrupts need different handling,
2326 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2327 * handled with the level-triggered descriptor, but that one has slightly
2328 * more overhead. Level-triggered interrupts cannot be handled with the
2329 * edge-triggered handler, without risking IRQ storms and other ugly
2335 #ifdef CONFIG_INTR_REMAP
2338 * Migrate the IO-APIC irq in the presence of intr-remapping.
2340 * For both level and edge triggered, irq migration is a simple atomic
2341 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2343 * For level triggered, we eliminate the io-apic RTE modification (with the
2344 * updated vector information), by using a virtual vector (io-apic pin number).
2345 * Real vector that is used for interrupting cpu will be coming from
2346 * the interrupt-remapping table entry.
2349 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2351 struct irq_cfg
*cfg
;
2356 if (!cpumask_intersects(mask
, cpu_online_mask
))
2360 if (get_irte(irq
, &irte
))
2363 cfg
= desc
->chip_data
;
2364 if (assign_irq_vector(irq
, cfg
, mask
))
2367 set_extra_move_desc(desc
, mask
);
2369 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2371 irte
.vector
= cfg
->vector
;
2372 irte
.dest_id
= IRTE_DEST(dest
);
2375 * Modified the IRTE and flushes the Interrupt entry cache.
2377 modify_irte(irq
, &irte
);
2379 if (cfg
->move_in_progress
)
2380 send_cleanup_vector(cfg
);
2382 cpumask_copy(desc
->affinity
, mask
);
2386 * Migrates the IRQ destination in the process context.
2388 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2389 const struct cpumask
*mask
)
2391 migrate_ioapic_irq_desc(desc
, mask
);
2393 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2394 const struct cpumask
*mask
)
2396 struct irq_desc
*desc
= irq_to_desc(irq
);
2398 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2401 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2402 const struct cpumask
*mask
)
2407 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2409 unsigned vector
, me
;
2415 me
= smp_processor_id();
2416 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2419 struct irq_desc
*desc
;
2420 struct irq_cfg
*cfg
;
2421 irq
= __get_cpu_var(vector_irq
)[vector
];
2426 desc
= irq_to_desc(irq
);
2431 spin_lock(&desc
->lock
);
2432 if (!cfg
->move_cleanup_count
)
2435 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2438 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2440 * Check if the vector that needs to be cleanedup is
2441 * registered at the cpu's IRR. If so, then this is not
2442 * the best time to clean it up. Lets clean it up in the
2443 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2446 if (irr
& (1 << (vector
% 32))) {
2447 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2450 __get_cpu_var(vector_irq
)[vector
] = -1;
2451 cfg
->move_cleanup_count
--;
2453 spin_unlock(&desc
->lock
);
2459 static void irq_complete_move(struct irq_desc
**descp
)
2461 struct irq_desc
*desc
= *descp
;
2462 struct irq_cfg
*cfg
= desc
->chip_data
;
2463 unsigned vector
, me
;
2465 if (likely(!cfg
->move_in_progress
)) {
2466 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2467 if (likely(!cfg
->move_desc_pending
))
2470 /* domain has not changed, but affinity did */
2471 me
= smp_processor_id();
2472 if (cpumask_test_cpu(me
, desc
->affinity
)) {
2473 *descp
= desc
= move_irq_desc(desc
, me
);
2474 /* get the new one */
2475 cfg
= desc
->chip_data
;
2476 cfg
->move_desc_pending
= 0;
2482 vector
= ~get_irq_regs()->orig_ax
;
2483 me
= smp_processor_id();
2485 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
)) {
2486 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2487 *descp
= desc
= move_irq_desc(desc
, me
);
2488 /* get the new one */
2489 cfg
= desc
->chip_data
;
2491 send_cleanup_vector(cfg
);
2495 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2498 #ifdef CONFIG_INTR_REMAP
2499 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2502 struct irq_pin_list
*entry
;
2504 entry
= cfg
->irq_2_pin
;
2512 io_apic_eoi(apic
, pin
);
2513 entry
= entry
->next
;
2518 eoi_ioapic_irq(struct irq_desc
*desc
)
2520 struct irq_cfg
*cfg
;
2521 unsigned long flags
;
2525 cfg
= desc
->chip_data
;
2527 spin_lock_irqsave(&ioapic_lock
, flags
);
2528 __eoi_ioapic_irq(irq
, cfg
);
2529 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2532 static void ack_x2apic_level(unsigned int irq
)
2534 struct irq_desc
*desc
= irq_to_desc(irq
);
2536 eoi_ioapic_irq(desc
);
2539 static void ack_x2apic_edge(unsigned int irq
)
2546 static void ack_apic_edge(unsigned int irq
)
2548 struct irq_desc
*desc
= irq_to_desc(irq
);
2550 irq_complete_move(&desc
);
2551 move_native_irq(irq
);
2555 atomic_t irq_mis_count
;
2557 static void ack_apic_level(unsigned int irq
)
2559 struct irq_desc
*desc
= irq_to_desc(irq
);
2561 #ifdef CONFIG_X86_32
2565 struct irq_cfg
*cfg
;
2566 int do_unmask_irq
= 0;
2568 irq_complete_move(&desc
);
2569 #ifdef CONFIG_GENERIC_PENDING_IRQ
2570 /* If we are moving the irq we need to mask it */
2571 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2573 mask_IO_APIC_irq_desc(desc
);
2577 #ifdef CONFIG_X86_32
2579 * It appears there is an erratum which affects at least version 0x11
2580 * of I/O APIC (that's the 82093AA and cores integrated into various
2581 * chipsets). Under certain conditions a level-triggered interrupt is
2582 * erroneously delivered as edge-triggered one but the respective IRR
2583 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2584 * message but it will never arrive and further interrupts are blocked
2585 * from the source. The exact reason is so far unknown, but the
2586 * phenomenon was observed when two consecutive interrupt requests
2587 * from a given source get delivered to the same CPU and the source is
2588 * temporarily disabled in between.
2590 * A workaround is to simulate an EOI message manually. We achieve it
2591 * by setting the trigger mode to edge and then to level when the edge
2592 * trigger mode gets detected in the TMR of a local APIC for a
2593 * level-triggered interrupt. We mask the source for the time of the
2594 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2595 * The idea is from Manfred Spraul. --macro
2597 cfg
= desc
->chip_data
;
2600 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2604 * We must acknowledge the irq before we move it or the acknowledge will
2605 * not propagate properly.
2609 /* Now we can move and renable the irq */
2610 if (unlikely(do_unmask_irq
)) {
2611 /* Only migrate the irq if the ack has been received.
2613 * On rare occasions the broadcast level triggered ack gets
2614 * delayed going to ioapics, and if we reprogram the
2615 * vector while Remote IRR is still set the irq will never
2618 * To prevent this scenario we read the Remote IRR bit
2619 * of the ioapic. This has two effects.
2620 * - On any sane system the read of the ioapic will
2621 * flush writes (and acks) going to the ioapic from
2623 * - We get to see if the ACK has actually been delivered.
2625 * Based on failed experiments of reprogramming the
2626 * ioapic entry from outside of irq context starting
2627 * with masking the ioapic entry and then polling until
2628 * Remote IRR was clear before reprogramming the
2629 * ioapic I don't trust the Remote IRR bit to be
2630 * completey accurate.
2632 * However there appears to be no other way to plug
2633 * this race, so if the Remote IRR bit is not
2634 * accurate and is causing problems then it is a hardware bug
2635 * and you can go talk to the chipset vendor about it.
2637 cfg
= desc
->chip_data
;
2638 if (!io_apic_level_ack_pending(cfg
))
2639 move_masked_irq(irq
);
2640 unmask_IO_APIC_irq_desc(desc
);
2643 #ifdef CONFIG_X86_32
2644 if (!(v
& (1 << (i
& 0x1f)))) {
2645 atomic_inc(&irq_mis_count
);
2646 spin_lock(&ioapic_lock
);
2647 __mask_and_edge_IO_APIC_irq(cfg
);
2648 __unmask_and_level_IO_APIC_irq(cfg
);
2649 spin_unlock(&ioapic_lock
);
2654 static struct irq_chip ioapic_chip __read_mostly
= {
2656 .startup
= startup_ioapic_irq
,
2657 .mask
= mask_IO_APIC_irq
,
2658 .unmask
= unmask_IO_APIC_irq
,
2659 .ack
= ack_apic_edge
,
2660 .eoi
= ack_apic_level
,
2662 .set_affinity
= set_ioapic_affinity_irq
,
2664 .retrigger
= ioapic_retrigger_irq
,
2667 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2668 .name
= "IR-IO-APIC",
2669 .startup
= startup_ioapic_irq
,
2670 .mask
= mask_IO_APIC_irq
,
2671 .unmask
= unmask_IO_APIC_irq
,
2672 #ifdef CONFIG_INTR_REMAP
2673 .ack
= ack_x2apic_edge
,
2674 .eoi
= ack_x2apic_level
,
2676 .set_affinity
= set_ir_ioapic_affinity_irq
,
2679 .retrigger
= ioapic_retrigger_irq
,
2682 static inline void init_IO_APIC_traps(void)
2685 struct irq_desc
*desc
;
2686 struct irq_cfg
*cfg
;
2689 * NOTE! The local APIC isn't very good at handling
2690 * multiple interrupts at the same interrupt level.
2691 * As the interrupt level is determined by taking the
2692 * vector number and shifting that right by 4, we
2693 * want to spread these out a bit so that they don't
2694 * all fall in the same interrupt level.
2696 * Also, we've got to be careful not to trash gate
2697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2699 for_each_irq_desc(irq
, desc
) {
2700 cfg
= desc
->chip_data
;
2701 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2703 * Hmm.. We don't have an entry for this,
2704 * so default to an old-fashioned 8259
2705 * interrupt if we can..
2707 if (irq
< NR_IRQS_LEGACY
)
2708 make_8259A_irq(irq
);
2710 /* Strange. Oh, well.. */
2711 desc
->chip
= &no_irq_chip
;
2717 * The local APIC irq-chip implementation:
2720 static void mask_lapic_irq(unsigned int irq
)
2724 v
= apic_read(APIC_LVT0
);
2725 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2728 static void unmask_lapic_irq(unsigned int irq
)
2732 v
= apic_read(APIC_LVT0
);
2733 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2736 static void ack_lapic_irq(unsigned int irq
)
2741 static struct irq_chip lapic_chip __read_mostly
= {
2742 .name
= "local-APIC",
2743 .mask
= mask_lapic_irq
,
2744 .unmask
= unmask_lapic_irq
,
2745 .ack
= ack_lapic_irq
,
2748 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2750 desc
->status
&= ~IRQ_LEVEL
;
2751 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2755 static void __init
setup_nmi(void)
2758 * Dirty trick to enable the NMI watchdog ...
2759 * We put the 8259A master into AEOI mode and
2760 * unmask on all local APICs LVT0 as NMI.
2762 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2763 * is from Maciej W. Rozycki - so we do not have to EOI from
2764 * the NMI handler or the timer interrupt.
2766 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2768 enable_NMI_through_LVT0();
2770 apic_printk(APIC_VERBOSE
, " done.\n");
2774 * This looks a bit hackish but it's about the only one way of sending
2775 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2776 * not support the ExtINT mode, unfortunately. We need to send these
2777 * cycles as some i82489DX-based boards have glue logic that keeps the
2778 * 8259A interrupt line asserted until INTA. --macro
2780 static inline void __init
unlock_ExtINT_logic(void)
2783 struct IO_APIC_route_entry entry0
, entry1
;
2784 unsigned char save_control
, save_freq_select
;
2786 pin
= find_isa_irq_pin(8, mp_INT
);
2791 apic
= find_isa_irq_apic(8, mp_INT
);
2797 entry0
= ioapic_read_entry(apic
, pin
);
2798 clear_IO_APIC_pin(apic
, pin
);
2800 memset(&entry1
, 0, sizeof(entry1
));
2802 entry1
.dest_mode
= 0; /* physical delivery */
2803 entry1
.mask
= 0; /* unmask IRQ now */
2804 entry1
.dest
= hard_smp_processor_id();
2805 entry1
.delivery_mode
= dest_ExtINT
;
2806 entry1
.polarity
= entry0
.polarity
;
2810 ioapic_write_entry(apic
, pin
, entry1
);
2812 save_control
= CMOS_READ(RTC_CONTROL
);
2813 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2814 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2816 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2821 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2825 CMOS_WRITE(save_control
, RTC_CONTROL
);
2826 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2827 clear_IO_APIC_pin(apic
, pin
);
2829 ioapic_write_entry(apic
, pin
, entry0
);
2832 static int disable_timer_pin_1 __initdata
;
2833 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2834 static int __init
disable_timer_pin_setup(char *arg
)
2836 disable_timer_pin_1
= 1;
2839 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2841 int timer_through_8259 __initdata
;
2844 * This code may look a bit paranoid, but it's supposed to cooperate with
2845 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2846 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2847 * fanatically on his truly buggy board.
2849 * FIXME: really need to revamp this for all platforms.
2851 static inline void __init
check_timer(void)
2853 struct irq_desc
*desc
= irq_to_desc(0);
2854 struct irq_cfg
*cfg
= desc
->chip_data
;
2855 int cpu
= boot_cpu_id
;
2856 int apic1
, pin1
, apic2
, pin2
;
2857 unsigned long flags
;
2860 local_irq_save(flags
);
2863 * get/set the timer IRQ vector:
2865 disable_8259A_irq(0);
2866 assign_irq_vector(0, cfg
, apic
->target_cpus());
2869 * As IRQ0 is to be enabled in the 8259A, the virtual
2870 * wire has to be disabled in the local APIC. Also
2871 * timer interrupts need to be acknowledged manually in
2872 * the 8259A for the i82489DX when using the NMI
2873 * watchdog as that APIC treats NMIs as level-triggered.
2874 * The AEOI mode will finish them in the 8259A
2877 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2879 #ifdef CONFIG_X86_32
2883 ver
= apic_read(APIC_LVR
);
2884 ver
= GET_APIC_VERSION(ver
);
2885 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2889 pin1
= find_isa_irq_pin(0, mp_INT
);
2890 apic1
= find_isa_irq_apic(0, mp_INT
);
2891 pin2
= ioapic_i8259
.pin
;
2892 apic2
= ioapic_i8259
.apic
;
2894 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2895 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2896 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2899 * Some BIOS writers are clueless and report the ExtINTA
2900 * I/O APIC input from the cascaded 8259A as the timer
2901 * interrupt input. So just in case, if only one pin
2902 * was found above, try it both directly and through the
2906 if (intr_remapping_enabled
)
2907 panic("BIOS bug: timer not connected to IO-APIC");
2911 } else if (pin2
== -1) {
2918 * Ok, does IRQ0 through the IOAPIC work?
2921 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2922 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2924 /* for edge trigger, setup_IO_APIC_irq already
2925 * leave it unmasked.
2926 * so only need to unmask if it is level-trigger
2927 * do we really have level trigger timer?
2930 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2931 if (idx
!= -1 && irq_trigger(idx
))
2932 unmask_IO_APIC_irq_desc(desc
);
2934 if (timer_irq_works()) {
2935 if (nmi_watchdog
== NMI_IO_APIC
) {
2937 enable_8259A_irq(0);
2939 if (disable_timer_pin_1
> 0)
2940 clear_IO_APIC_pin(0, pin1
);
2943 if (intr_remapping_enabled
)
2944 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2945 local_irq_disable();
2946 clear_IO_APIC_pin(apic1
, pin1
);
2948 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2949 "8254 timer not connected to IO-APIC\n");
2951 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2952 "(IRQ0) through the 8259A ...\n");
2953 apic_printk(APIC_QUIET
, KERN_INFO
2954 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2956 * legacy devices should be connected to IO APIC #0
2958 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2959 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2960 enable_8259A_irq(0);
2961 if (timer_irq_works()) {
2962 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2963 timer_through_8259
= 1;
2964 if (nmi_watchdog
== NMI_IO_APIC
) {
2965 disable_8259A_irq(0);
2967 enable_8259A_irq(0);
2972 * Cleanup, just in case ...
2974 local_irq_disable();
2975 disable_8259A_irq(0);
2976 clear_IO_APIC_pin(apic2
, pin2
);
2977 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2980 if (nmi_watchdog
== NMI_IO_APIC
) {
2981 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2982 "through the IO-APIC - disabling NMI Watchdog!\n");
2983 nmi_watchdog
= NMI_NONE
;
2985 #ifdef CONFIG_X86_32
2989 apic_printk(APIC_QUIET
, KERN_INFO
2990 "...trying to set up timer as Virtual Wire IRQ...\n");
2992 lapic_register_intr(0, desc
);
2993 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2994 enable_8259A_irq(0);
2996 if (timer_irq_works()) {
2997 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3000 local_irq_disable();
3001 disable_8259A_irq(0);
3002 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3003 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3005 apic_printk(APIC_QUIET
, KERN_INFO
3006 "...trying to set up timer as ExtINT IRQ...\n");
3010 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3012 unlock_ExtINT_logic();
3014 if (timer_irq_works()) {
3015 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3018 local_irq_disable();
3019 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3020 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3021 "report. Then try booting with the 'noapic' option.\n");
3023 local_irq_restore(flags
);
3027 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3028 * to devices. However there may be an I/O APIC pin available for
3029 * this interrupt regardless. The pin may be left unconnected, but
3030 * typically it will be reused as an ExtINT cascade interrupt for
3031 * the master 8259A. In the MPS case such a pin will normally be
3032 * reported as an ExtINT interrupt in the MP table. With ACPI
3033 * there is no provision for ExtINT interrupts, and in the absence
3034 * of an override it would be treated as an ordinary ISA I/O APIC
3035 * interrupt, that is edge-triggered and unmasked by default. We
3036 * used to do this, but it caused problems on some systems because
3037 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3038 * the same ExtINT cascade interrupt to drive the local APIC of the
3039 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3040 * the I/O APIC in all cases now. No actual device should request
3041 * it anyway. --macro
3043 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3045 void __init
setup_IO_APIC(void)
3049 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3052 io_apic_irqs
= ~PIC_IRQS
;
3054 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3056 * Set up IO-APIC IRQ routing.
3058 #ifdef CONFIG_X86_32
3060 setup_ioapic_ids_from_mpc();
3063 setup_IO_APIC_irqs();
3064 init_IO_APIC_traps();
3069 * Called after all the initialization is done. If we didnt find any
3070 * APIC bugs then we can allow the modify fast path
3073 static int __init
io_apic_bug_finalize(void)
3075 if (sis_apic_bug
== -1)
3080 late_initcall(io_apic_bug_finalize
);
3082 struct sysfs_ioapic_data
{
3083 struct sys_device dev
;
3084 struct IO_APIC_route_entry entry
[0];
3086 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3088 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3090 struct IO_APIC_route_entry
*entry
;
3091 struct sysfs_ioapic_data
*data
;
3094 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3095 entry
= data
->entry
;
3096 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3097 *entry
= ioapic_read_entry(dev
->id
, i
);
3102 static int ioapic_resume(struct sys_device
*dev
)
3104 struct IO_APIC_route_entry
*entry
;
3105 struct sysfs_ioapic_data
*data
;
3106 unsigned long flags
;
3107 union IO_APIC_reg_00 reg_00
;
3110 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3111 entry
= data
->entry
;
3113 spin_lock_irqsave(&ioapic_lock
, flags
);
3114 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3115 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3116 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3117 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3119 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3120 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3121 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3126 static struct sysdev_class ioapic_sysdev_class
= {
3128 .suspend
= ioapic_suspend
,
3129 .resume
= ioapic_resume
,
3132 static int __init
ioapic_init_sysfs(void)
3134 struct sys_device
* dev
;
3137 error
= sysdev_class_register(&ioapic_sysdev_class
);
3141 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3142 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3143 * sizeof(struct IO_APIC_route_entry
);
3144 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3145 if (!mp_ioapic_data
[i
]) {
3146 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3149 dev
= &mp_ioapic_data
[i
]->dev
;
3151 dev
->cls
= &ioapic_sysdev_class
;
3152 error
= sysdev_register(dev
);
3154 kfree(mp_ioapic_data
[i
]);
3155 mp_ioapic_data
[i
] = NULL
;
3156 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3164 device_initcall(ioapic_init_sysfs
);
3166 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3168 * Dynamic irq allocate and deallocation
3170 unsigned int create_irq_nr(unsigned int irq_want
)
3172 /* Allocate an unused irq */
3175 unsigned long flags
;
3176 struct irq_cfg
*cfg_new
= NULL
;
3177 int cpu
= boot_cpu_id
;
3178 struct irq_desc
*desc_new
= NULL
;
3181 if (irq_want
< nr_irqs_gsi
)
3182 irq_want
= nr_irqs_gsi
;
3184 spin_lock_irqsave(&vector_lock
, flags
);
3185 for (new = irq_want
; new < nr_irqs
; new++) {
3186 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3188 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3191 cfg_new
= desc_new
->chip_data
;
3193 if (cfg_new
->vector
!= 0)
3195 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3199 spin_unlock_irqrestore(&vector_lock
, flags
);
3202 dynamic_irq_init(irq
);
3203 /* restore it, in case dynamic_irq_init clear it */
3205 desc_new
->chip_data
= cfg_new
;
3210 int create_irq(void)
3212 unsigned int irq_want
;
3215 irq_want
= nr_irqs_gsi
;
3216 irq
= create_irq_nr(irq_want
);
3224 void destroy_irq(unsigned int irq
)
3226 unsigned long flags
;
3227 struct irq_cfg
*cfg
;
3228 struct irq_desc
*desc
;
3230 /* store it, in case dynamic_irq_cleanup clear it */
3231 desc
= irq_to_desc(irq
);
3232 cfg
= desc
->chip_data
;
3233 dynamic_irq_cleanup(irq
);
3234 /* connect back irq_cfg */
3236 desc
->chip_data
= cfg
;
3239 spin_lock_irqsave(&vector_lock
, flags
);
3240 __clear_irq_vector(irq
, cfg
);
3241 spin_unlock_irqrestore(&vector_lock
, flags
);
3245 * MSI message composition
3247 #ifdef CONFIG_PCI_MSI
3248 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3250 struct irq_cfg
*cfg
;
3258 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3262 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3264 if (irq_remapped(irq
)) {
3269 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3270 BUG_ON(ir_index
== -1);
3272 memset (&irte
, 0, sizeof(irte
));
3275 irte
.dst_mode
= apic
->irq_dest_mode
;
3276 irte
.trigger_mode
= 0; /* edge */
3277 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3278 irte
.vector
= cfg
->vector
;
3279 irte
.dest_id
= IRTE_DEST(dest
);
3281 modify_irte(irq
, &irte
);
3283 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3284 msg
->data
= sub_handle
;
3285 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3287 MSI_ADDR_IR_INDEX1(ir_index
) |
3288 MSI_ADDR_IR_INDEX2(ir_index
);
3290 if (x2apic_enabled())
3291 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3292 MSI_ADDR_EXT_DEST_ID(dest
);
3294 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3298 ((apic
->irq_dest_mode
== 0) ?
3299 MSI_ADDR_DEST_MODE_PHYSICAL
:
3300 MSI_ADDR_DEST_MODE_LOGICAL
) |
3301 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3302 MSI_ADDR_REDIRECTION_CPU
:
3303 MSI_ADDR_REDIRECTION_LOWPRI
) |
3304 MSI_ADDR_DEST_ID(dest
);
3307 MSI_DATA_TRIGGER_EDGE
|
3308 MSI_DATA_LEVEL_ASSERT
|
3309 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3310 MSI_DATA_DELIVERY_FIXED
:
3311 MSI_DATA_DELIVERY_LOWPRI
) |
3312 MSI_DATA_VECTOR(cfg
->vector
);
3318 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3320 struct irq_desc
*desc
= irq_to_desc(irq
);
3321 struct irq_cfg
*cfg
;
3325 dest
= set_desc_affinity(desc
, mask
);
3326 if (dest
== BAD_APICID
)
3329 cfg
= desc
->chip_data
;
3331 read_msi_msg_desc(desc
, &msg
);
3333 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3334 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3335 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3336 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3338 write_msi_msg_desc(desc
, &msg
);
3340 #ifdef CONFIG_INTR_REMAP
3342 * Migrate the MSI irq to another cpumask. This migration is
3343 * done in the process context using interrupt-remapping hardware.
3346 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3348 struct irq_desc
*desc
= irq_to_desc(irq
);
3349 struct irq_cfg
*cfg
= desc
->chip_data
;
3353 if (get_irte(irq
, &irte
))
3356 dest
= set_desc_affinity(desc
, mask
);
3357 if (dest
== BAD_APICID
)
3360 irte
.vector
= cfg
->vector
;
3361 irte
.dest_id
= IRTE_DEST(dest
);
3364 * atomically update the IRTE with the new destination and vector.
3366 modify_irte(irq
, &irte
);
3369 * After this point, all the interrupts will start arriving
3370 * at the new destination. So, time to cleanup the previous
3371 * vector allocation.
3373 if (cfg
->move_in_progress
)
3374 send_cleanup_vector(cfg
);
3378 #endif /* CONFIG_SMP */
3381 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3382 * which implement the MSI or MSI-X Capability Structure.
3384 static struct irq_chip msi_chip
= {
3386 .unmask
= unmask_msi_irq
,
3387 .mask
= mask_msi_irq
,
3388 .ack
= ack_apic_edge
,
3390 .set_affinity
= set_msi_irq_affinity
,
3392 .retrigger
= ioapic_retrigger_irq
,
3395 static struct irq_chip msi_ir_chip
= {
3396 .name
= "IR-PCI-MSI",
3397 .unmask
= unmask_msi_irq
,
3398 .mask
= mask_msi_irq
,
3399 #ifdef CONFIG_INTR_REMAP
3400 .ack
= ack_x2apic_edge
,
3402 .set_affinity
= ir_set_msi_irq_affinity
,
3405 .retrigger
= ioapic_retrigger_irq
,
3409 * Map the PCI dev to the corresponding remapping hardware unit
3410 * and allocate 'nvec' consecutive interrupt-remapping table entries
3413 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3415 struct intel_iommu
*iommu
;
3418 iommu
= map_dev_to_ir(dev
);
3421 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3425 index
= alloc_irte(iommu
, irq
, nvec
);
3428 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3435 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3440 ret
= msi_compose_msg(dev
, irq
, &msg
);
3444 set_irq_msi(irq
, msidesc
);
3445 write_msi_msg(irq
, &msg
);
3447 if (irq_remapped(irq
)) {
3448 struct irq_desc
*desc
= irq_to_desc(irq
);
3450 * irq migration in process context
3452 desc
->status
|= IRQ_MOVE_PCNTXT
;
3453 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3455 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3457 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3462 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3465 int ret
, sub_handle
;
3466 struct msi_desc
*msidesc
;
3467 unsigned int irq_want
;
3468 struct intel_iommu
*iommu
= NULL
;
3471 /* x86 doesn't support multiple MSI yet */
3472 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3475 irq_want
= nr_irqs_gsi
;
3477 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3478 irq
= create_irq_nr(irq_want
);
3482 if (!intr_remapping_enabled
)
3487 * allocate the consecutive block of IRTE's
3490 index
= msi_alloc_irte(dev
, irq
, nvec
);
3496 iommu
= map_dev_to_ir(dev
);
3502 * setup the mapping between the irq and the IRTE
3503 * base index, the sub_handle pointing to the
3504 * appropriate interrupt remap table entry.
3506 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3509 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3521 void arch_teardown_msi_irq(unsigned int irq
)
3526 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3528 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3530 struct irq_desc
*desc
= irq_to_desc(irq
);
3531 struct irq_cfg
*cfg
;
3535 dest
= set_desc_affinity(desc
, mask
);
3536 if (dest
== BAD_APICID
)
3539 cfg
= desc
->chip_data
;
3541 dmar_msi_read(irq
, &msg
);
3543 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3544 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3545 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3546 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3548 dmar_msi_write(irq
, &msg
);
3551 #endif /* CONFIG_SMP */
3553 struct irq_chip dmar_msi_type
= {
3555 .unmask
= dmar_msi_unmask
,
3556 .mask
= dmar_msi_mask
,
3557 .ack
= ack_apic_edge
,
3559 .set_affinity
= dmar_msi_set_affinity
,
3561 .retrigger
= ioapic_retrigger_irq
,
3564 int arch_setup_dmar_msi(unsigned int irq
)
3569 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3572 dmar_msi_write(irq
, &msg
);
3573 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3579 #ifdef CONFIG_HPET_TIMER
3582 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3584 struct irq_desc
*desc
= irq_to_desc(irq
);
3585 struct irq_cfg
*cfg
;
3589 dest
= set_desc_affinity(desc
, mask
);
3590 if (dest
== BAD_APICID
)
3593 cfg
= desc
->chip_data
;
3595 hpet_msi_read(irq
, &msg
);
3597 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3598 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3599 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3600 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3602 hpet_msi_write(irq
, &msg
);
3605 #endif /* CONFIG_SMP */
3607 static struct irq_chip hpet_msi_type
= {
3609 .unmask
= hpet_msi_unmask
,
3610 .mask
= hpet_msi_mask
,
3611 .ack
= ack_apic_edge
,
3613 .set_affinity
= hpet_msi_set_affinity
,
3615 .retrigger
= ioapic_retrigger_irq
,
3618 int arch_setup_hpet_msi(unsigned int irq
)
3623 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3627 hpet_msi_write(irq
, &msg
);
3628 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3635 #endif /* CONFIG_PCI_MSI */
3637 * Hypertransport interrupt support
3639 #ifdef CONFIG_HT_IRQ
3643 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3645 struct ht_irq_msg msg
;
3646 fetch_ht_irq_msg(irq
, &msg
);
3648 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3649 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3651 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3652 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3654 write_ht_irq_msg(irq
, &msg
);
3657 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3659 struct irq_desc
*desc
= irq_to_desc(irq
);
3660 struct irq_cfg
*cfg
;
3663 dest
= set_desc_affinity(desc
, mask
);
3664 if (dest
== BAD_APICID
)
3667 cfg
= desc
->chip_data
;
3669 target_ht_irq(irq
, dest
, cfg
->vector
);
3674 static struct irq_chip ht_irq_chip
= {
3676 .mask
= mask_ht_irq
,
3677 .unmask
= unmask_ht_irq
,
3678 .ack
= ack_apic_edge
,
3680 .set_affinity
= set_ht_irq_affinity
,
3682 .retrigger
= ioapic_retrigger_irq
,
3685 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3687 struct irq_cfg
*cfg
;
3694 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3696 struct ht_irq_msg msg
;
3699 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3700 apic
->target_cpus());
3702 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3706 HT_IRQ_LOW_DEST_ID(dest
) |
3707 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3708 ((apic
->irq_dest_mode
== 0) ?
3709 HT_IRQ_LOW_DM_PHYSICAL
:
3710 HT_IRQ_LOW_DM_LOGICAL
) |
3711 HT_IRQ_LOW_RQEOI_EDGE
|
3712 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3713 HT_IRQ_LOW_MT_FIXED
:
3714 HT_IRQ_LOW_MT_ARBITRATED
) |
3715 HT_IRQ_LOW_IRQ_MASKED
;
3717 write_ht_irq_msg(irq
, &msg
);
3719 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3720 handle_edge_irq
, "edge");
3722 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3726 #endif /* CONFIG_HT_IRQ */
3728 #ifdef CONFIG_X86_UV
3730 * Re-target the irq to the specified CPU and enable the specified MMR located
3731 * on the specified blade to allow the sending of MSIs to the specified CPU.
3733 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3734 unsigned long mmr_offset
)
3736 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3737 struct irq_cfg
*cfg
;
3739 unsigned long mmr_value
;
3740 struct uv_IO_APIC_route_entry
*entry
;
3741 unsigned long flags
;
3746 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3750 spin_lock_irqsave(&vector_lock
, flags
);
3751 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3753 spin_unlock_irqrestore(&vector_lock
, flags
);
3756 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3757 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3759 entry
->vector
= cfg
->vector
;
3760 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3761 entry
->dest_mode
= apic
->irq_dest_mode
;
3762 entry
->polarity
= 0;
3765 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3767 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3768 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3774 * Disable the specified MMR located on the specified blade so that MSIs are
3775 * longer allowed to be sent.
3777 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3779 unsigned long mmr_value
;
3780 struct uv_IO_APIC_route_entry
*entry
;
3784 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3785 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3789 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3790 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3792 #endif /* CONFIG_X86_64 */
3794 int __init
io_apic_get_redir_entries (int ioapic
)
3796 union IO_APIC_reg_01 reg_01
;
3797 unsigned long flags
;
3799 spin_lock_irqsave(&ioapic_lock
, flags
);
3800 reg_01
.raw
= io_apic_read(ioapic
, 1);
3801 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3803 return reg_01
.bits
.entries
;
3806 void __init
probe_nr_irqs_gsi(void)
3810 nr
= acpi_probe_gsi();
3811 if (nr
> nr_irqs_gsi
) {
3814 /* for acpi=off or acpi is not compiled in */
3818 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3819 nr
+= io_apic_get_redir_entries(idx
) + 1;
3821 if (nr
> nr_irqs_gsi
)
3825 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3828 #ifdef CONFIG_SPARSE_IRQ
3829 int __init
arch_probe_nr_irqs(void)
3833 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3834 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3836 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3837 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3839 * for MSI and HT dyn irq
3841 nr
+= nr_irqs_gsi
* 16;
3850 /* --------------------------------------------------------------------------
3851 ACPI-based IOAPIC Configuration
3852 -------------------------------------------------------------------------- */
3856 #ifdef CONFIG_X86_32
3857 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3859 union IO_APIC_reg_00 reg_00
;
3860 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3862 unsigned long flags
;
3866 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3867 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3868 * supports up to 16 on one shared APIC bus.
3870 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3871 * advantage of new APIC bus architecture.
3874 if (physids_empty(apic_id_map
))
3875 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3877 spin_lock_irqsave(&ioapic_lock
, flags
);
3878 reg_00
.raw
= io_apic_read(ioapic
, 0);
3879 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3881 if (apic_id
>= get_physical_broadcast()) {
3882 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3883 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3884 apic_id
= reg_00
.bits
.ID
;
3888 * Every APIC in a system must have a unique ID or we get lots of nice
3889 * 'stuck on smp_invalidate_needed IPI wait' messages.
3891 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3893 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3894 if (!apic
->check_apicid_used(apic_id_map
, i
))
3898 if (i
== get_physical_broadcast())
3899 panic("Max apic_id exceeded!\n");
3901 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3902 "trying %d\n", ioapic
, apic_id
, i
);
3907 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3908 physids_or(apic_id_map
, apic_id_map
, tmp
);
3910 if (reg_00
.bits
.ID
!= apic_id
) {
3911 reg_00
.bits
.ID
= apic_id
;
3913 spin_lock_irqsave(&ioapic_lock
, flags
);
3914 io_apic_write(ioapic
, 0, reg_00
.raw
);
3915 reg_00
.raw
= io_apic_read(ioapic
, 0);
3916 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3919 if (reg_00
.bits
.ID
!= apic_id
) {
3920 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3925 apic_printk(APIC_VERBOSE
, KERN_INFO
3926 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3931 int __init
io_apic_get_version(int ioapic
)
3933 union IO_APIC_reg_01 reg_01
;
3934 unsigned long flags
;
3936 spin_lock_irqsave(&ioapic_lock
, flags
);
3937 reg_01
.raw
= io_apic_read(ioapic
, 1);
3938 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3940 return reg_01
.bits
.version
;
3944 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3946 struct irq_desc
*desc
;
3947 struct irq_cfg
*cfg
;
3948 int cpu
= boot_cpu_id
;
3950 if (!IO_APIC_IRQ(irq
)) {
3951 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3956 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3958 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3963 * IRQs < 16 are already in the irq_2_pin[] map
3965 if (irq
>= NR_IRQS_LEGACY
) {
3966 cfg
= desc
->chip_data
;
3967 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3970 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3976 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3980 if (skip_ioapic_setup
)
3983 for (i
= 0; i
< mp_irq_entries
; i
++)
3984 if (mp_irqs
[i
].irqtype
== mp_INT
&&
3985 mp_irqs
[i
].srcbusirq
== bus_irq
)
3987 if (i
>= mp_irq_entries
)
3990 *trigger
= irq_trigger(i
);
3991 *polarity
= irq_polarity(i
);
3995 #endif /* CONFIG_ACPI */
3998 * This function currently is only a helper for the i386 smp boot process where
3999 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4000 * so mask in all cases should simply be apic->target_cpus()
4003 void __init
setup_ioapic_dest(void)
4005 int pin
, ioapic
, irq
, irq_entry
;
4006 struct irq_desc
*desc
;
4007 struct irq_cfg
*cfg
;
4008 const struct cpumask
*mask
;
4010 if (skip_ioapic_setup
== 1)
4013 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4014 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4015 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4016 if (irq_entry
== -1)
4018 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4020 /* setup_IO_APIC_irqs could fail to get vector for some device
4021 * when you have too many devices, because at that time only boot
4024 desc
= irq_to_desc(irq
);
4025 cfg
= desc
->chip_data
;
4027 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4028 irq_trigger(irq_entry
),
4029 irq_polarity(irq_entry
));
4035 * Honour affinities which have been set in early boot
4038 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4039 mask
= desc
->affinity
;
4041 mask
= apic
->target_cpus();
4043 if (intr_remapping_enabled
)
4044 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4046 set_ioapic_affinity_irq_desc(desc
, mask
);
4053 #define IOAPIC_RESOURCE_NAME_SIZE 11
4055 static struct resource
*ioapic_resources
;
4057 static struct resource
* __init
ioapic_setup_resources(void)
4060 struct resource
*res
;
4064 if (nr_ioapics
<= 0)
4067 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4070 mem
= alloc_bootmem(n
);
4074 mem
+= sizeof(struct resource
) * nr_ioapics
;
4076 for (i
= 0; i
< nr_ioapics
; i
++) {
4078 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4079 sprintf(mem
, "IOAPIC %u", i
);
4080 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4084 ioapic_resources
= res
;
4089 void __init
ioapic_init_mappings(void)
4091 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4092 struct resource
*ioapic_res
;
4095 ioapic_res
= ioapic_setup_resources();
4096 for (i
= 0; i
< nr_ioapics
; i
++) {
4097 if (smp_found_config
) {
4098 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4099 #ifdef CONFIG_X86_32
4102 "WARNING: bogus zero IO-APIC "
4103 "address found in MPTABLE, "
4104 "disabling IO/APIC support!\n");
4105 smp_found_config
= 0;
4106 skip_ioapic_setup
= 1;
4107 goto fake_ioapic_page
;
4111 #ifdef CONFIG_X86_32
4114 ioapic_phys
= (unsigned long)
4115 alloc_bootmem_pages(PAGE_SIZE
);
4116 ioapic_phys
= __pa(ioapic_phys
);
4118 set_fixmap_nocache(idx
, ioapic_phys
);
4119 apic_printk(APIC_VERBOSE
,
4120 "mapped IOAPIC to %08lx (%08lx)\n",
4121 __fix_to_virt(idx
), ioapic_phys
);
4124 if (ioapic_res
!= NULL
) {
4125 ioapic_res
->start
= ioapic_phys
;
4126 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4132 static int __init
ioapic_insert_resources(void)
4135 struct resource
*r
= ioapic_resources
;
4138 if (nr_ioapics
> 0) {
4140 "IO APIC resources couldn't be allocated.\n");
4146 for (i
= 0; i
< nr_ioapics
; i
++) {
4147 insert_resource(&iomem_resource
, r
);
4154 /* Insert the IO APIC resources after PCI initialization has occured to handle
4155 * IO APICS that are mapped in on a BAR in PCI space. */
4156 late_initcall(ioapic_insert_resources
);