2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
40 #include <linux/bootmem.h>
41 #include <linux/dmar.h>
42 #include <linux/hpet.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
54 #include <asm/msidef.h>
55 #include <asm/hypertransport.h>
56 #include <asm/setup.h>
57 #include <asm/irq_remapping.h>
59 #include <asm/hw_irq.h>
63 #define __apicdebuginit(type) static type __init
65 #define for_each_ioapic(idx) \
66 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
67 #define for_each_ioapic_reverse(idx) \
68 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
69 #define for_each_pin(idx, pin) \
70 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
71 #define for_each_ioapic_pin(idx, pin) \
72 for_each_ioapic((idx)) \
73 for_each_pin((idx), (pin))
75 #define for_each_irq_pin(entry, head) \
76 for (entry = head; entry; entry = entry->next)
79 * Is the SiS APIC rmw bug present ?
80 * -1 = don't know, 0 = no, 1 = yes
82 int sis_apic_bug
= -1;
84 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
85 static DEFINE_RAW_SPINLOCK(vector_lock
);
87 static struct ioapic
{
89 * # of IRQ routing registers
93 * Saved state during suspend/resume, or while enabling intr-remap.
95 struct IO_APIC_route_entry
*saved_registers
;
97 struct mpc_ioapic mp_config
;
98 /* IO APIC gsi routing info */
99 struct mp_ioapic_gsi gsi_config
;
100 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
101 } ioapics
[MAX_IO_APICS
];
103 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
105 int mpc_ioapic_id(int ioapic_idx
)
107 return ioapics
[ioapic_idx
].mp_config
.apicid
;
110 unsigned int mpc_ioapic_addr(int ioapic_idx
)
112 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
115 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
117 return &ioapics
[ioapic_idx
].gsi_config
;
120 static inline int mp_ioapic_pin_count(int ioapic
)
122 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
124 return gsi_cfg
->gsi_end
- gsi_cfg
->gsi_base
+ 1;
127 u32
mp_pin_to_gsi(int ioapic
, int pin
)
129 return mp_ioapic_gsi_routing(ioapic
)->gsi_base
+ pin
;
133 * Initialize all legacy IRQs and all pins on the first IOAPIC
134 * if we have legacy interrupt controller. Kernel boot option "pirq="
135 * may rely on non-legacy pins on the first IOAPIC.
137 static inline int mp_init_irq_at_boot(int ioapic
, int irq
)
139 if (!nr_legacy_irqs())
142 return ioapic
== 0 || (irq
>= 0 && irq
< nr_legacy_irqs());
147 /* The one past the highest gsi number used */
150 /* MP IRQ source entries */
151 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
153 /* # of MP IRQ source entries */
157 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
160 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
162 int skip_ioapic_setup
;
165 * disable_ioapic_support() - disables ioapic support at runtime
167 void disable_ioapic_support(void)
171 noioapicreroute
= -1;
173 skip_ioapic_setup
= 1;
176 static int __init
parse_noapic(char *str
)
178 /* disable IO-APIC */
179 disable_ioapic_support();
182 early_param("noapic", parse_noapic
);
184 static int io_apic_setup_irq_pin(unsigned int irq
, int node
,
185 struct io_apic_irq_attr
*attr
);
187 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
188 void mp_save_irq(struct mpc_intsrc
*m
)
192 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
193 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
194 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
195 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
197 for (i
= 0; i
< mp_irq_entries
; i
++) {
198 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
202 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
203 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
204 panic("Max # of irq sources exceeded!!\n");
207 struct irq_pin_list
{
209 struct irq_pin_list
*next
;
212 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
214 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
218 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
219 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
221 int __init
arch_early_irq_init(void)
226 if (!nr_legacy_irqs())
230 ioapics
[i
].saved_registers
=
231 kzalloc(sizeof(struct IO_APIC_route_entry
) *
232 ioapics
[i
].nr_registers
, GFP_KERNEL
);
233 if (!ioapics
[i
].saved_registers
)
234 pr_err("IOAPIC %d: suspend/resume impossible!\n", i
);
238 count
= ARRAY_SIZE(irq_cfgx
);
239 node
= cpu_to_node(0);
241 for (i
= 0; i
< count
; i
++) {
242 irq_set_chip_data(i
, &cfg
[i
]);
243 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
244 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
246 * For legacy IRQ's, start with assigning irq0 to irq15 to
247 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
249 if (i
< nr_legacy_irqs()) {
250 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
251 cpumask_setall(cfg
[i
].domain
);
258 static inline struct irq_cfg
*irq_cfg(unsigned int irq
)
260 return irq_get_chip_data(irq
);
263 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
267 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
270 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
272 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
276 free_cpumask_var(cfg
->domain
);
282 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
286 irq_set_chip_data(at
, NULL
);
287 free_cpumask_var(cfg
->domain
);
288 free_cpumask_var(cfg
->old_domain
);
292 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
294 int res
= irq_alloc_desc_at(at
, node
);
305 cfg
= alloc_irq_cfg(at
, node
);
307 irq_set_chip_data(at
, cfg
);
315 unsigned int unused
[3];
317 unsigned int unused2
[11];
321 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
323 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
324 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
327 void io_apic_eoi(unsigned int apic
, unsigned int vector
)
329 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
330 writel(vector
, &io_apic
->eoi
);
333 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
335 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
336 writel(reg
, &io_apic
->index
);
337 return readl(&io_apic
->data
);
340 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
342 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
344 writel(reg
, &io_apic
->index
);
345 writel(value
, &io_apic
->data
);
349 * Re-write a value: to be used for read-modify-write
350 * cycles where the read already set up the index register.
352 * Older SiS APIC requires we rewrite the index register
354 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
356 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
359 writel(reg
, &io_apic
->index
);
360 writel(value
, &io_apic
->data
);
364 struct { u32 w1
, w2
; };
365 struct IO_APIC_route_entry entry
;
368 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
370 union entry_union eu
;
372 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
373 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
378 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
380 union entry_union eu
;
383 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
384 eu
.entry
= __ioapic_read_entry(apic
, pin
);
385 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
391 * When we write a new IO APIC routing entry, we need to write the high
392 * word first! If the mask bit in the low word is clear, we will enable
393 * the interrupt, and we need to make sure the entry is fully populated
394 * before that happens.
396 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
398 union entry_union eu
= {{0, 0}};
401 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
402 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
405 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
409 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
410 __ioapic_write_entry(apic
, pin
, e
);
411 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
415 * When we mask an IO APIC routing entry, we need to write the low
416 * word first, in order to set the mask bit before we change the
419 static void ioapic_mask_entry(int apic
, int pin
)
422 union entry_union eu
= { .entry
.mask
= 1 };
424 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
425 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
426 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
427 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
431 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
432 * shared ISA-space IRQs, so we have to support them. We are super
433 * fast in the common case, and fast for shared ISA-space IRQs.
435 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
437 struct irq_pin_list
**last
, *entry
;
439 /* don't allow duplicates */
440 last
= &cfg
->irq_2_pin
;
441 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
442 if (entry
->apic
== apic
&& entry
->pin
== pin
)
447 entry
= alloc_irq_pin_list(node
);
449 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
460 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
462 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
463 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
467 * Reroute an IRQ to a different pin.
469 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
470 int oldapic
, int oldpin
,
471 int newapic
, int newpin
)
473 struct irq_pin_list
*entry
;
475 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
476 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
477 entry
->apic
= newapic
;
479 /* every one is different, right? */
484 /* old apic/pin didn't exist, so just add new ones */
485 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
488 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
489 int mask_and
, int mask_or
,
490 void (*final
)(struct irq_pin_list
*entry
))
492 unsigned int reg
, pin
;
495 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
498 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
503 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
504 int mask_and
, int mask_or
,
505 void (*final
)(struct irq_pin_list
*entry
))
507 struct irq_pin_list
*entry
;
509 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
510 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
513 static void io_apic_sync(struct irq_pin_list
*entry
)
516 * Synchronize the IO-APIC and the CPU by doing
517 * a dummy read from the IO-APIC
519 struct io_apic __iomem
*io_apic
;
521 io_apic
= io_apic_base(entry
->apic
);
522 readl(&io_apic
->data
);
525 static void mask_ioapic(struct irq_cfg
*cfg
)
529 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
530 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
531 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
534 static void mask_ioapic_irq(struct irq_data
*data
)
536 mask_ioapic(data
->chip_data
);
539 static void __unmask_ioapic(struct irq_cfg
*cfg
)
541 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
544 static void unmask_ioapic(struct irq_cfg
*cfg
)
548 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
549 __unmask_ioapic(cfg
);
550 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
553 static void unmask_ioapic_irq(struct irq_data
*data
)
555 unmask_ioapic(data
->chip_data
);
559 * IO-APIC versions below 0x20 don't support EOI register.
560 * For the record, here is the information about various versions:
562 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
563 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
566 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
567 * version as 0x2. This is an error with documentation and these ICH chips
568 * use io-apic's of version 0x20.
570 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
571 * Otherwise, we simulate the EOI message manually by changing the trigger
572 * mode to edge and then back to level, with RTE being masked during this.
574 void native_eoi_ioapic_pin(int apic
, int pin
, int vector
)
576 if (mpc_ioapic_ver(apic
) >= 0x20) {
577 io_apic_eoi(apic
, vector
);
579 struct IO_APIC_route_entry entry
, entry1
;
581 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
584 * Mask the entry and change the trigger mode to edge.
587 entry1
.trigger
= IOAPIC_EDGE
;
589 __ioapic_write_entry(apic
, pin
, entry1
);
592 * Restore the previous level triggered entry.
594 __ioapic_write_entry(apic
, pin
, entry
);
598 void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
600 struct irq_pin_list
*entry
;
603 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
604 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
605 x86_io_apic_ops
.eoi_ioapic_pin(entry
->apic
, entry
->pin
,
607 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
610 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
612 struct IO_APIC_route_entry entry
;
614 /* Check delivery_mode to be sure we're not clearing an SMI pin */
615 entry
= ioapic_read_entry(apic
, pin
);
616 if (entry
.delivery_mode
== dest_SMI
)
620 * Make sure the entry is masked and re-read the contents to check
621 * if it is a level triggered pin and if the remote-IRR is set.
625 ioapic_write_entry(apic
, pin
, entry
);
626 entry
= ioapic_read_entry(apic
, pin
);
633 * Make sure the trigger mode is set to level. Explicit EOI
634 * doesn't clear the remote-IRR if the trigger mode is not
637 if (!entry
.trigger
) {
638 entry
.trigger
= IOAPIC_LEVEL
;
639 ioapic_write_entry(apic
, pin
, entry
);
642 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
643 x86_io_apic_ops
.eoi_ioapic_pin(apic
, pin
, entry
.vector
);
644 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
648 * Clear the rest of the bits in the IO-APIC RTE except for the mask
651 ioapic_mask_entry(apic
, pin
);
652 entry
= ioapic_read_entry(apic
, pin
);
654 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
655 mpc_ioapic_id(apic
), pin
);
658 static void clear_IO_APIC (void)
662 for_each_ioapic_pin(apic
, pin
)
663 clear_IO_APIC_pin(apic
, pin
);
668 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
669 * specific CPU-side IRQs.
673 static int pirq_entries
[MAX_PIRQS
] = {
674 [0 ... MAX_PIRQS
- 1] = -1
677 static int __init
ioapic_pirq_setup(char *str
)
680 int ints
[MAX_PIRQS
+1];
682 get_options(str
, ARRAY_SIZE(ints
), ints
);
684 apic_printk(APIC_VERBOSE
, KERN_INFO
685 "PIRQ redirection, working around broken MP-BIOS.\n");
687 if (ints
[0] < MAX_PIRQS
)
690 for (i
= 0; i
< max
; i
++) {
691 apic_printk(APIC_VERBOSE
, KERN_DEBUG
692 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
694 * PIRQs are mapped upside down, usually.
696 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
701 __setup("pirq=", ioapic_pirq_setup
);
702 #endif /* CONFIG_X86_32 */
705 * Saves all the IO-APIC RTE's
707 int save_ioapic_entries(void)
712 for_each_ioapic(apic
) {
713 if (!ioapics
[apic
].saved_registers
) {
718 for_each_pin(apic
, pin
)
719 ioapics
[apic
].saved_registers
[pin
] =
720 ioapic_read_entry(apic
, pin
);
727 * Mask all IO APIC entries.
729 void mask_ioapic_entries(void)
733 for_each_ioapic(apic
) {
734 if (!ioapics
[apic
].saved_registers
)
737 for_each_pin(apic
, pin
) {
738 struct IO_APIC_route_entry entry
;
740 entry
= ioapics
[apic
].saved_registers
[pin
];
743 ioapic_write_entry(apic
, pin
, entry
);
750 * Restore IO APIC entries which was saved in the ioapic structure.
752 int restore_ioapic_entries(void)
756 for_each_ioapic(apic
) {
757 if (!ioapics
[apic
].saved_registers
)
760 for_each_pin(apic
, pin
)
761 ioapic_write_entry(apic
, pin
,
762 ioapics
[apic
].saved_registers
[pin
]);
768 * Find the IRQ entry number of a certain pin.
770 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
774 for (i
= 0; i
< mp_irq_entries
; i
++)
775 if (mp_irqs
[i
].irqtype
== type
&&
776 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
777 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
778 mp_irqs
[i
].dstirq
== pin
)
785 * Find the pin to which IRQ[irq] (ISA) is connected
787 static int __init
find_isa_irq_pin(int irq
, int type
)
791 for (i
= 0; i
< mp_irq_entries
; i
++) {
792 int lbus
= mp_irqs
[i
].srcbus
;
794 if (test_bit(lbus
, mp_bus_not_pci
) &&
795 (mp_irqs
[i
].irqtype
== type
) &&
796 (mp_irqs
[i
].srcbusirq
== irq
))
798 return mp_irqs
[i
].dstirq
;
803 static int __init
find_isa_irq_apic(int irq
, int type
)
807 for (i
= 0; i
< mp_irq_entries
; i
++) {
808 int lbus
= mp_irqs
[i
].srcbus
;
810 if (test_bit(lbus
, mp_bus_not_pci
) &&
811 (mp_irqs
[i
].irqtype
== type
) &&
812 (mp_irqs
[i
].srcbusirq
== irq
))
816 if (i
< mp_irq_entries
) {
819 for_each_ioapic(ioapic_idx
)
820 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
829 * EISA Edge/Level control register, ELCR
831 static int EISA_ELCR(unsigned int irq
)
833 if (irq
< nr_legacy_irqs()) {
834 unsigned int port
= 0x4d0 + (irq
>> 3);
835 return (inb(port
) >> (irq
& 7)) & 1;
837 apic_printk(APIC_VERBOSE
, KERN_INFO
838 "Broken MPtable reports ISA irq %d\n", irq
);
844 /* ISA interrupts are always polarity zero edge triggered,
845 * when listed as conforming in the MP table. */
847 #define default_ISA_trigger(idx) (0)
848 #define default_ISA_polarity(idx) (0)
850 /* EISA interrupts are always polarity zero and can be edge or level
851 * trigger depending on the ELCR value. If an interrupt is listed as
852 * EISA conforming in the MP table, that means its trigger type must
853 * be read in from the ELCR */
855 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
856 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
858 /* PCI interrupts are always polarity one level triggered,
859 * when listed as conforming in the MP table. */
861 #define default_PCI_trigger(idx) (1)
862 #define default_PCI_polarity(idx) (1)
864 static int irq_polarity(int idx
)
866 int bus
= mp_irqs
[idx
].srcbus
;
870 * Determine IRQ line polarity (high active or low active):
872 switch (mp_irqs
[idx
].irqflag
& 3)
874 case 0: /* conforms, ie. bus-type dependent polarity */
875 if (test_bit(bus
, mp_bus_not_pci
))
876 polarity
= default_ISA_polarity(idx
);
878 polarity
= default_PCI_polarity(idx
);
880 case 1: /* high active */
885 case 2: /* reserved */
887 pr_warn("broken BIOS!!\n");
891 case 3: /* low active */
896 default: /* invalid */
898 pr_warn("broken BIOS!!\n");
906 static int irq_trigger(int idx
)
908 int bus
= mp_irqs
[idx
].srcbus
;
912 * Determine IRQ trigger mode (edge or level sensitive):
914 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
916 case 0: /* conforms, ie. bus-type dependent */
917 if (test_bit(bus
, mp_bus_not_pci
))
918 trigger
= default_ISA_trigger(idx
);
920 trigger
= default_PCI_trigger(idx
);
922 switch (mp_bus_id_to_type
[bus
]) {
923 case MP_BUS_ISA
: /* ISA pin */
925 /* set before the switch */
928 case MP_BUS_EISA
: /* EISA pin */
930 trigger
= default_EISA_trigger(idx
);
933 case MP_BUS_PCI
: /* PCI pin */
935 /* set before the switch */
940 pr_warn("broken BIOS!!\n");
952 case 2: /* reserved */
954 pr_warn("broken BIOS!!\n");
963 default: /* invalid */
965 pr_warn("broken BIOS!!\n");
973 static int pin_2_irq(int idx
, int apic
, int pin
)
976 int bus
= mp_irqs
[idx
].srcbus
;
977 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(apic
);
980 * Debugging check, we are in big trouble if this message pops up!
982 if (mp_irqs
[idx
].dstirq
!= pin
)
983 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
985 if (test_bit(bus
, mp_bus_not_pci
)) {
986 irq
= mp_irqs
[idx
].srcbusirq
;
988 u32 gsi
= gsi_cfg
->gsi_base
+ pin
;
990 if (gsi
>= nr_legacy_irqs())
998 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1000 if ((pin
>= 16) && (pin
<= 23)) {
1001 if (pirq_entries
[pin
-16] != -1) {
1002 if (!pirq_entries
[pin
-16]) {
1003 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1004 "disabling PIRQ%d\n", pin
-16);
1006 irq
= pirq_entries
[pin
-16];
1007 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1008 "using PIRQ%d -> IRQ %d\n",
1019 * Find a specific PCI IRQ entry.
1020 * Not an __init, possibly needed by modules
1022 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1023 struct io_apic_irq_attr
*irq_attr
)
1025 int irq
, i
, best_guess
= -1;
1027 apic_printk(APIC_DEBUG
,
1028 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1030 if (test_bit(bus
, mp_bus_not_pci
)) {
1031 apic_printk(APIC_VERBOSE
,
1032 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1036 for (i
= 0; i
< mp_irq_entries
; i
++) {
1037 int lbus
= mp_irqs
[i
].srcbus
;
1038 int ioapic_idx
, found
= 0;
1040 if (bus
!= lbus
|| mp_irqs
[i
].irqtype
!= mp_INT
||
1041 slot
!= ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))
1044 for_each_ioapic(ioapic_idx
)
1045 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1046 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) {
1054 irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
);
1055 if (ioapic_idx
== 0 && !IO_APIC_IRQ(irq
))
1058 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1059 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1066 * Use the first all-but-pin matching entry as a
1067 * best-guess fuzzy result for broken mptables.
1069 if (best_guess
< 0) {
1070 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1079 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1081 void lock_vector_lock(void)
1083 /* Used to the online set of cpus does not change
1084 * during assign_irq_vector.
1086 raw_spin_lock(&vector_lock
);
1089 void unlock_vector_lock(void)
1091 raw_spin_unlock(&vector_lock
);
1095 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1098 * NOTE! The local APIC isn't very good at handling
1099 * multiple interrupts at the same interrupt level.
1100 * As the interrupt level is determined by taking the
1101 * vector number and shifting that right by 4, we
1102 * want to spread these out a bit so that they don't
1103 * all fall in the same interrupt level.
1105 * Also, we've got to be careful not to trash gate
1106 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1108 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1109 static int current_offset
= VECTOR_OFFSET_START
% 16;
1111 cpumask_var_t tmp_mask
;
1113 if (cfg
->move_in_progress
)
1116 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1119 /* Only try and allocate irqs on cpus that are present */
1121 cpumask_clear(cfg
->old_domain
);
1122 cpu
= cpumask_first_and(mask
, cpu_online_mask
);
1123 while (cpu
< nr_cpu_ids
) {
1124 int new_cpu
, vector
, offset
;
1126 apic
->vector_allocation_domain(cpu
, tmp_mask
, mask
);
1128 if (cpumask_subset(tmp_mask
, cfg
->domain
)) {
1130 if (cpumask_equal(tmp_mask
, cfg
->domain
))
1133 * New cpumask using the vector is a proper subset of
1134 * the current in use mask. So cleanup the vector
1135 * allocation for the members that are not used anymore.
1137 cpumask_andnot(cfg
->old_domain
, cfg
->domain
, tmp_mask
);
1138 cfg
->move_in_progress
=
1139 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1140 cpumask_and(cfg
->domain
, cfg
->domain
, tmp_mask
);
1144 vector
= current_vector
;
1145 offset
= current_offset
;
1148 if (vector
>= first_system_vector
) {
1149 offset
= (offset
+ 1) % 16;
1150 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1153 if (unlikely(current_vector
== vector
)) {
1154 cpumask_or(cfg
->old_domain
, cfg
->old_domain
, tmp_mask
);
1155 cpumask_andnot(tmp_mask
, mask
, cfg
->old_domain
);
1156 cpu
= cpumask_first_and(tmp_mask
, cpu_online_mask
);
1160 if (test_bit(vector
, used_vectors
))
1163 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
) {
1164 if (per_cpu(vector_irq
, new_cpu
)[vector
] > VECTOR_UNDEFINED
)
1168 current_vector
= vector
;
1169 current_offset
= offset
;
1171 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1172 cfg
->move_in_progress
=
1173 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1175 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1176 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1177 cfg
->vector
= vector
;
1178 cpumask_copy(cfg
->domain
, tmp_mask
);
1182 free_cpumask_var(tmp_mask
);
1186 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1189 unsigned long flags
;
1191 raw_spin_lock_irqsave(&vector_lock
, flags
);
1192 err
= __assign_irq_vector(irq
, cfg
, mask
);
1193 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1197 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1201 BUG_ON(!cfg
->vector
);
1203 vector
= cfg
->vector
;
1204 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1205 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1208 cpumask_clear(cfg
->domain
);
1210 if (likely(!cfg
->move_in_progress
))
1212 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1213 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1214 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1216 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1220 cfg
->move_in_progress
= 0;
1223 void __setup_vector_irq(int cpu
)
1225 /* Initialize vector_irq on a new cpu */
1227 struct irq_cfg
*cfg
;
1230 * vector_lock will make sure that we don't run into irq vector
1231 * assignments that might be happening on another cpu in parallel,
1232 * while we setup our initial vector to irq mappings.
1234 raw_spin_lock(&vector_lock
);
1235 /* Mark the inuse vectors */
1236 for_each_active_irq(irq
) {
1241 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1243 vector
= cfg
->vector
;
1244 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1246 /* Mark the free vectors */
1247 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1248 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1249 if (irq
<= VECTOR_UNDEFINED
)
1253 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1254 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1256 raw_spin_unlock(&vector_lock
);
1259 static struct irq_chip ioapic_chip
;
1261 #ifdef CONFIG_X86_32
1262 static inline int IO_APIC_irq_trigger(int irq
)
1266 for_each_ioapic_pin(apic
, pin
) {
1267 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1268 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1269 return irq_trigger(idx
);
1272 * nonexistent IRQs are edge default
1277 static inline int IO_APIC_irq_trigger(int irq
)
1283 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1284 unsigned long trigger
)
1286 struct irq_chip
*chip
= &ioapic_chip
;
1287 irq_flow_handler_t hdl
;
1290 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1291 trigger
== IOAPIC_LEVEL
) {
1292 irq_set_status_flags(irq
, IRQ_LEVEL
);
1295 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1299 if (setup_remapped_irq(irq
, cfg
, chip
))
1300 fasteoi
= trigger
!= 0;
1302 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1303 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1304 fasteoi
? "fasteoi" : "edge");
1307 int native_setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1308 unsigned int destination
, int vector
,
1309 struct io_apic_irq_attr
*attr
)
1311 memset(entry
, 0, sizeof(*entry
));
1313 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1314 entry
->dest_mode
= apic
->irq_dest_mode
;
1315 entry
->dest
= destination
;
1316 entry
->vector
= vector
;
1317 entry
->mask
= 0; /* enable IRQ */
1318 entry
->trigger
= attr
->trigger
;
1319 entry
->polarity
= attr
->polarity
;
1322 * Mask level triggered irqs.
1323 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1331 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1332 struct io_apic_irq_attr
*attr
)
1334 struct IO_APIC_route_entry entry
;
1337 if (!IO_APIC_IRQ(irq
))
1340 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1343 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1345 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1346 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1347 __clear_irq_vector(irq
, cfg
);
1352 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1353 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1354 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1355 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1356 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1358 if (x86_io_apic_ops
.setup_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1359 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1360 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1361 __clear_irq_vector(irq
, cfg
);
1366 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1367 if (irq
< nr_legacy_irqs())
1368 legacy_pic
->mask(irq
);
1370 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1373 static bool __init
io_apic_pin_not_connected(int idx
, int ioapic_idx
, int pin
)
1378 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" apic %d pin %d not connected\n",
1379 mpc_ioapic_id(ioapic_idx
), pin
);
1383 static void __init
__io_apic_setup_irqs(unsigned int ioapic_idx
)
1385 int idx
, node
= cpu_to_node(0);
1386 struct io_apic_irq_attr attr
;
1387 unsigned int pin
, irq
;
1389 for_each_pin(ioapic_idx
, pin
) {
1390 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1391 if (io_apic_pin_not_connected(idx
, ioapic_idx
, pin
))
1394 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1395 if (!mp_init_irq_at_boot(ioapic_idx
, irq
))
1399 * Skip the timer IRQ if there's a quirk handler
1400 * installed and if it returns 1:
1402 if (apic
->multi_timer_check
&&
1403 apic
->multi_timer_check(ioapic_idx
, irq
))
1406 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1409 io_apic_setup_irq_pin(irq
, node
, &attr
);
1413 static void __init
setup_IO_APIC_irqs(void)
1415 unsigned int ioapic_idx
;
1417 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1419 for_each_ioapic(ioapic_idx
)
1420 __io_apic_setup_irqs(ioapic_idx
);
1424 * for the gsi that is not in first ioapic
1425 * but could not use acpi_register_gsi()
1426 * like some special sci in IBM x3330
1428 void setup_IO_APIC_irq_extra(u32 gsi
)
1430 int ioapic_idx
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1431 struct io_apic_irq_attr attr
;
1434 * Convert 'gsi' to 'ioapic.pin'.
1436 ioapic_idx
= mp_find_ioapic(gsi
);
1440 pin
= mp_find_ioapic_pin(ioapic_idx
, gsi
);
1441 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1445 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1446 if (mp_init_irq_at_boot(ioapic_idx
, irq
))
1449 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1452 io_apic_setup_irq_pin_once(irq
, node
, &attr
);
1456 * Set up the timer pin, possibly with the 8259A-master behind.
1458 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1459 unsigned int pin
, int vector
)
1461 struct IO_APIC_route_entry entry
;
1464 memset(&entry
, 0, sizeof(entry
));
1467 * We use logical delivery to get the timer IRQ
1470 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1471 apic
->target_cpus(), &dest
)))
1474 entry
.dest_mode
= apic
->irq_dest_mode
;
1475 entry
.mask
= 0; /* don't mask IRQ for edge */
1477 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1480 entry
.vector
= vector
;
1483 * The timer IRQ doesn't have to know that behind the
1484 * scene we may have a 8259A-master in AEOI mode ...
1486 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1490 * Add it to the IO-APIC irq-routing table:
1492 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1495 void native_io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1499 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1501 for (i
= 0; i
<= nr_entries
; i
++) {
1502 struct IO_APIC_route_entry entry
;
1504 entry
= ioapic_read_entry(apic
, i
);
1506 pr_debug(" %02x %02X ", i
, entry
.dest
);
1507 pr_cont("%1d %1d %1d %1d %1d "
1513 entry
.delivery_status
,
1515 entry
.delivery_mode
,
1520 void intel_ir_io_apic_print_entries(unsigned int apic
,
1521 unsigned int nr_entries
)
1525 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1527 for (i
= 0; i
<= nr_entries
; i
++) {
1528 struct IR_IO_APIC_route_entry
*ir_entry
;
1529 struct IO_APIC_route_entry entry
;
1531 entry
= ioapic_read_entry(apic
, i
);
1533 ir_entry
= (struct IR_IO_APIC_route_entry
*)&entry
;
1535 pr_debug(" %02x %04X ", i
, ir_entry
->index
);
1536 pr_cont("%1d %1d %1d %1d %1d "
1537 "%1d %1d %X %02X\n",
1543 ir_entry
->delivery_status
,
1550 void ioapic_zap_locks(void)
1552 raw_spin_lock_init(&ioapic_lock
);
1555 __apicdebuginit(void) print_IO_APIC(int ioapic_idx
)
1557 union IO_APIC_reg_00 reg_00
;
1558 union IO_APIC_reg_01 reg_01
;
1559 union IO_APIC_reg_02 reg_02
;
1560 union IO_APIC_reg_03 reg_03
;
1561 unsigned long flags
;
1563 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1564 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1565 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1566 if (reg_01
.bits
.version
>= 0x10)
1567 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1568 if (reg_01
.bits
.version
>= 0x20)
1569 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1570 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1572 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1573 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1574 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1575 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1576 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1578 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1579 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1580 reg_01
.bits
.entries
);
1582 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1583 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1584 reg_01
.bits
.version
);
1587 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1588 * but the value of reg_02 is read as the previous read register
1589 * value, so ignore it if reg_02 == reg_01.
1591 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1592 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1593 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1597 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1598 * or reg_03, but the value of reg_0[23] is read as the previous read
1599 * register value, so ignore it if reg_03 == reg_0[12].
1601 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1602 reg_03
.raw
!= reg_01
.raw
) {
1603 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1604 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1607 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1609 x86_io_apic_ops
.print_entries(ioapic_idx
, reg_01
.bits
.entries
);
1612 __apicdebuginit(void) print_IO_APICs(void)
1615 struct irq_cfg
*cfg
;
1617 struct irq_chip
*chip
;
1619 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1620 for_each_ioapic(ioapic_idx
)
1621 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1622 mpc_ioapic_id(ioapic_idx
),
1623 ioapics
[ioapic_idx
].nr_registers
);
1626 * We are a bit conservative about what we expect. We have to
1627 * know about every hardware change ASAP.
1629 printk(KERN_INFO
"testing the IO APIC.......................\n");
1631 for_each_ioapic(ioapic_idx
)
1632 print_IO_APIC(ioapic_idx
);
1634 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1635 for_each_active_irq(irq
) {
1636 struct irq_pin_list
*entry
;
1638 chip
= irq_get_chip(irq
);
1639 if (chip
!= &ioapic_chip
)
1645 entry
= cfg
->irq_2_pin
;
1648 printk(KERN_DEBUG
"IRQ%d ", irq
);
1649 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1650 pr_cont("-> %d:%d", entry
->apic
, entry
->pin
);
1654 printk(KERN_INFO
".................................... done.\n");
1657 __apicdebuginit(void) print_APIC_field(int base
)
1663 for (i
= 0; i
< 8; i
++)
1664 pr_cont("%08x", apic_read(base
+ i
*0x10));
1669 __apicdebuginit(void) print_local_APIC(void *dummy
)
1671 unsigned int i
, v
, ver
, maxlvt
;
1674 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1675 smp_processor_id(), hard_smp_processor_id());
1676 v
= apic_read(APIC_ID
);
1677 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1678 v
= apic_read(APIC_LVR
);
1679 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1680 ver
= GET_APIC_VERSION(v
);
1681 maxlvt
= lapic_get_maxlvt();
1683 v
= apic_read(APIC_TASKPRI
);
1684 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1686 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1687 if (!APIC_XAPIC(ver
)) {
1688 v
= apic_read(APIC_ARBPRI
);
1689 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1690 v
& APIC_ARBPRI_MASK
);
1692 v
= apic_read(APIC_PROCPRI
);
1693 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1697 * Remote read supported only in the 82489DX and local APIC for
1698 * Pentium processors.
1700 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1701 v
= apic_read(APIC_RRR
);
1702 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1705 v
= apic_read(APIC_LDR
);
1706 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1707 if (!x2apic_enabled()) {
1708 v
= apic_read(APIC_DFR
);
1709 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1711 v
= apic_read(APIC_SPIV
);
1712 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1714 printk(KERN_DEBUG
"... APIC ISR field:\n");
1715 print_APIC_field(APIC_ISR
);
1716 printk(KERN_DEBUG
"... APIC TMR field:\n");
1717 print_APIC_field(APIC_TMR
);
1718 printk(KERN_DEBUG
"... APIC IRR field:\n");
1719 print_APIC_field(APIC_IRR
);
1721 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1722 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1723 apic_write(APIC_ESR
, 0);
1725 v
= apic_read(APIC_ESR
);
1726 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1729 icr
= apic_icr_read();
1730 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1731 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1733 v
= apic_read(APIC_LVTT
);
1734 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1736 if (maxlvt
> 3) { /* PC is LVT#4. */
1737 v
= apic_read(APIC_LVTPC
);
1738 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1740 v
= apic_read(APIC_LVT0
);
1741 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1742 v
= apic_read(APIC_LVT1
);
1743 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1745 if (maxlvt
> 2) { /* ERR is LVT#3. */
1746 v
= apic_read(APIC_LVTERR
);
1747 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1750 v
= apic_read(APIC_TMICT
);
1751 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1752 v
= apic_read(APIC_TMCCT
);
1753 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1754 v
= apic_read(APIC_TDCR
);
1755 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1757 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1758 v
= apic_read(APIC_EFEAT
);
1759 maxlvt
= (v
>> 16) & 0xff;
1760 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1761 v
= apic_read(APIC_ECTRL
);
1762 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1763 for (i
= 0; i
< maxlvt
; i
++) {
1764 v
= apic_read(APIC_EILVTn(i
));
1765 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1771 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1779 for_each_online_cpu(cpu
) {
1782 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1787 __apicdebuginit(void) print_PIC(void)
1790 unsigned long flags
;
1792 if (!nr_legacy_irqs())
1795 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1797 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1799 v
= inb(0xa1) << 8 | inb(0x21);
1800 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1802 v
= inb(0xa0) << 8 | inb(0x20);
1803 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1807 v
= inb(0xa0) << 8 | inb(0x20);
1811 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1813 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1815 v
= inb(0x4d1) << 8 | inb(0x4d0);
1816 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1819 static int __initdata show_lapic
= 1;
1820 static __init
int setup_show_lapic(char *arg
)
1824 if (strcmp(arg
, "all") == 0) {
1825 show_lapic
= CONFIG_NR_CPUS
;
1827 get_option(&arg
, &num
);
1834 __setup("show_lapic=", setup_show_lapic
);
1836 __apicdebuginit(int) print_ICs(void)
1838 if (apic_verbosity
== APIC_QUIET
)
1843 /* don't print out if apic is not there */
1844 if (!cpu_has_apic
&& !apic_from_smp_config())
1847 print_local_APICs(show_lapic
);
1853 late_initcall(print_ICs
);
1856 /* Where if anywhere is the i8259 connect in external int mode */
1857 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1859 void __init
enable_IO_APIC(void)
1861 int i8259_apic
, i8259_pin
;
1864 if (!nr_legacy_irqs())
1867 for_each_ioapic_pin(apic
, pin
) {
1868 /* See if any of the pins is in ExtINT mode */
1869 struct IO_APIC_route_entry entry
= ioapic_read_entry(apic
, pin
);
1871 /* If the interrupt line is enabled and in ExtInt mode
1872 * I have found the pin where the i8259 is connected.
1874 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1875 ioapic_i8259
.apic
= apic
;
1876 ioapic_i8259
.pin
= pin
;
1881 /* Look to see what if the MP table has reported the ExtINT */
1882 /* If we could not find the appropriate pin by looking at the ioapic
1883 * the i8259 probably is not connected the ioapic but give the
1884 * mptable a chance anyway.
1886 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1887 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1888 /* Trust the MP table if nothing is setup in the hardware */
1889 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1890 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1891 ioapic_i8259
.pin
= i8259_pin
;
1892 ioapic_i8259
.apic
= i8259_apic
;
1894 /* Complain if the MP table and the hardware disagree */
1895 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1896 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1898 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1902 * Do not trust the IO-APIC being empty at bootup
1907 void native_disable_io_apic(void)
1910 * If the i8259 is routed through an IOAPIC
1911 * Put that IOAPIC in virtual wire mode
1912 * so legacy interrupts can be delivered.
1914 if (ioapic_i8259
.pin
!= -1) {
1915 struct IO_APIC_route_entry entry
;
1917 memset(&entry
, 0, sizeof(entry
));
1918 entry
.mask
= 0; /* Enabled */
1919 entry
.trigger
= 0; /* Edge */
1921 entry
.polarity
= 0; /* High */
1922 entry
.delivery_status
= 0;
1923 entry
.dest_mode
= 0; /* Physical */
1924 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1926 entry
.dest
= read_apic_id();
1929 * Add it to the IO-APIC irq-routing table:
1931 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1934 if (cpu_has_apic
|| apic_from_smp_config())
1935 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1940 * Not an __init, needed by the reboot code
1942 void disable_IO_APIC(void)
1945 * Clear the IO-APIC before rebooting:
1949 if (!nr_legacy_irqs())
1952 x86_io_apic_ops
.disable();
1955 #ifdef CONFIG_X86_32
1957 * function to set the IO-APIC physical IDs based on the
1958 * values stored in the MPC table.
1960 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1962 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1964 union IO_APIC_reg_00 reg_00
;
1965 physid_mask_t phys_id_present_map
;
1968 unsigned char old_id
;
1969 unsigned long flags
;
1972 * This is broken; anything with a real cpu count has to
1973 * circumvent this idiocy regardless.
1975 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1978 * Set the IOAPIC ID to the value stored in the MPC table.
1980 for_each_ioapic(ioapic_idx
) {
1981 /* Read the register 0 value */
1982 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1983 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1984 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1986 old_id
= mpc_ioapic_id(ioapic_idx
);
1988 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
1989 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1990 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1991 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1993 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
1997 * Sanity check, is the ID really free? Every APIC in a
1998 * system must have a unique ID or we get lots of nice
1999 * 'stuck on smp_invalidate_needed IPI wait' messages.
2001 if (apic
->check_apicid_used(&phys_id_present_map
,
2002 mpc_ioapic_id(ioapic_idx
))) {
2003 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2004 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
2005 for (i
= 0; i
< get_physical_broadcast(); i
++)
2006 if (!physid_isset(i
, phys_id_present_map
))
2008 if (i
>= get_physical_broadcast())
2009 panic("Max APIC ID exceeded!\n");
2010 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2012 physid_set(i
, phys_id_present_map
);
2013 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
2016 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
2018 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2019 "phys_id_present_map\n",
2020 mpc_ioapic_id(ioapic_idx
));
2021 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2025 * We need to adjust the IRQ routing table
2026 * if the ID changed.
2028 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
2029 for (i
= 0; i
< mp_irq_entries
; i
++)
2030 if (mp_irqs
[i
].dstapic
== old_id
)
2032 = mpc_ioapic_id(ioapic_idx
);
2035 * Update the ID register according to the right value
2036 * from the MPC table if they are different.
2038 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
2041 apic_printk(APIC_VERBOSE
, KERN_INFO
2042 "...changing IO-APIC physical APIC ID to %d ...",
2043 mpc_ioapic_id(ioapic_idx
));
2045 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2046 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2047 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2048 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2053 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2054 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2055 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2056 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
2057 pr_cont("could not set ID!\n");
2059 apic_printk(APIC_VERBOSE
, " ok.\n");
2063 void __init
setup_ioapic_ids_from_mpc(void)
2069 * Don't check I/O APIC IDs for xAPIC systems. They have
2070 * no meaning without the serial APIC bus.
2072 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2073 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2075 setup_ioapic_ids_from_mpc_nocheck();
2079 int no_timer_check __initdata
;
2081 static int __init
notimercheck(char *s
)
2086 __setup("no_timer_check", notimercheck
);
2089 * There is a nasty bug in some older SMP boards, their mptable lies
2090 * about the timer IRQ. We do the following to work around the situation:
2092 * - timer IRQ defaults to IO-APIC IRQ
2093 * - if this function detects that timer IRQs are defunct, then we fall
2094 * back to ISA timer IRQs
2096 static int __init
timer_irq_works(void)
2098 unsigned long t1
= jiffies
;
2099 unsigned long flags
;
2104 local_save_flags(flags
);
2106 /* Let ten ticks pass... */
2107 mdelay((10 * 1000) / HZ
);
2108 local_irq_restore(flags
);
2111 * Expect a few ticks at least, to be sure some possible
2112 * glue logic does not lock up after one or two first
2113 * ticks in a non-ExtINT mode. Also the local APIC
2114 * might have cached one ExtINT interrupt. Finally, at
2115 * least one tick may be lost due to delays.
2119 if (time_after(jiffies
, t1
+ 4))
2125 * In the SMP+IOAPIC case it might happen that there are an unspecified
2126 * number of pending IRQ events unhandled. These cases are very rare,
2127 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2128 * better to do it this way as thus we do not have to be aware of
2129 * 'pending' interrupts in the IRQ path, except at this point.
2132 * Edge triggered needs to resend any interrupt
2133 * that was delayed but this is now handled in the device
2138 * Starting up a edge-triggered IO-APIC interrupt is
2139 * nasty - we need to make sure that we get the edge.
2140 * If it is already asserted for some reason, we need
2141 * return 1 to indicate that is was pending.
2143 * This is not complete - we should be able to fake
2144 * an edge even if it isn't on the 8259A...
2147 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2149 int was_pending
= 0, irq
= data
->irq
;
2150 unsigned long flags
;
2152 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2153 if (irq
< nr_legacy_irqs()) {
2154 legacy_pic
->mask(irq
);
2155 if (legacy_pic
->irq_pending(irq
))
2158 __unmask_ioapic(data
->chip_data
);
2159 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2164 static int ioapic_retrigger_irq(struct irq_data
*data
)
2166 struct irq_cfg
*cfg
= data
->chip_data
;
2167 unsigned long flags
;
2170 raw_spin_lock_irqsave(&vector_lock
, flags
);
2171 cpu
= cpumask_first_and(cfg
->domain
, cpu_online_mask
);
2172 apic
->send_IPI_mask(cpumask_of(cpu
), cfg
->vector
);
2173 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2179 * Level and edge triggered IO-APIC interrupts need different handling,
2180 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2181 * handled with the level-triggered descriptor, but that one has slightly
2182 * more overhead. Level-triggered interrupts cannot be handled with the
2183 * edge-triggered handler, without risking IRQ storms and other ugly
2188 void send_cleanup_vector(struct irq_cfg
*cfg
)
2190 cpumask_var_t cleanup_mask
;
2192 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2194 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2195 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2197 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2198 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2199 free_cpumask_var(cleanup_mask
);
2201 cfg
->move_in_progress
= 0;
2204 asmlinkage __visible
void smp_irq_move_cleanup_interrupt(void)
2206 unsigned vector
, me
;
2212 me
= smp_processor_id();
2213 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2216 struct irq_desc
*desc
;
2217 struct irq_cfg
*cfg
;
2218 irq
= __this_cpu_read(vector_irq
[vector
]);
2220 if (irq
<= VECTOR_UNDEFINED
)
2223 desc
= irq_to_desc(irq
);
2231 raw_spin_lock(&desc
->lock
);
2234 * Check if the irq migration is in progress. If so, we
2235 * haven't received the cleanup request yet for this irq.
2237 if (cfg
->move_in_progress
)
2240 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2243 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2245 * Check if the vector that needs to be cleanedup is
2246 * registered at the cpu's IRR. If so, then this is not
2247 * the best time to clean it up. Lets clean it up in the
2248 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2251 if (irr
& (1 << (vector
% 32))) {
2252 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2255 __this_cpu_write(vector_irq
[vector
], VECTOR_UNDEFINED
);
2257 raw_spin_unlock(&desc
->lock
);
2263 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2267 if (likely(!cfg
->move_in_progress
))
2270 me
= smp_processor_id();
2272 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2273 send_cleanup_vector(cfg
);
2276 static void irq_complete_move(struct irq_cfg
*cfg
)
2278 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2281 void irq_force_complete_move(int irq
)
2283 struct irq_cfg
*cfg
= irq_cfg(irq
);
2288 __irq_complete_move(cfg
, cfg
->vector
);
2291 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2294 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2297 struct irq_pin_list
*entry
;
2298 u8 vector
= cfg
->vector
;
2300 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2306 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2307 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2308 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2310 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2315 * Either sets data->affinity to a valid value, and returns
2316 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2317 * leaves data->affinity untouched.
2319 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2320 unsigned int *dest_id
)
2322 struct irq_cfg
*cfg
= data
->chip_data
;
2323 unsigned int irq
= data
->irq
;
2326 if (!config_enabled(CONFIG_SMP
))
2329 if (!cpumask_intersects(mask
, cpu_online_mask
))
2332 err
= assign_irq_vector(irq
, cfg
, mask
);
2336 err
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
, dest_id
);
2338 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
2339 pr_err("Failed to recover vector for irq %d\n", irq
);
2343 cpumask_copy(data
->affinity
, mask
);
2349 int native_ioapic_set_affinity(struct irq_data
*data
,
2350 const struct cpumask
*mask
,
2353 unsigned int dest
, irq
= data
->irq
;
2354 unsigned long flags
;
2357 if (!config_enabled(CONFIG_SMP
))
2360 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2361 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2363 /* Only the high 8 bits are valid. */
2364 dest
= SET_APIC_LOGICAL_ID(dest
);
2365 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2366 ret
= IRQ_SET_MASK_OK_NOCOPY
;
2368 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2372 static void ack_apic_edge(struct irq_data
*data
)
2374 irq_complete_move(data
->chip_data
);
2379 atomic_t irq_mis_count
;
2381 #ifdef CONFIG_GENERIC_PENDING_IRQ
2382 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
2384 struct irq_pin_list
*entry
;
2385 unsigned long flags
;
2387 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2388 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2393 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
2394 /* Is the remote IRR bit set? */
2395 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
2396 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2400 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2405 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2407 /* If we are moving the irq we need to mask it */
2408 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2415 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2416 struct irq_cfg
*cfg
, bool masked
)
2418 if (unlikely(masked
)) {
2419 /* Only migrate the irq if the ack has been received.
2421 * On rare occasions the broadcast level triggered ack gets
2422 * delayed going to ioapics, and if we reprogram the
2423 * vector while Remote IRR is still set the irq will never
2426 * To prevent this scenario we read the Remote IRR bit
2427 * of the ioapic. This has two effects.
2428 * - On any sane system the read of the ioapic will
2429 * flush writes (and acks) going to the ioapic from
2431 * - We get to see if the ACK has actually been delivered.
2433 * Based on failed experiments of reprogramming the
2434 * ioapic entry from outside of irq context starting
2435 * with masking the ioapic entry and then polling until
2436 * Remote IRR was clear before reprogramming the
2437 * ioapic I don't trust the Remote IRR bit to be
2438 * completey accurate.
2440 * However there appears to be no other way to plug
2441 * this race, so if the Remote IRR bit is not
2442 * accurate and is causing problems then it is a hardware bug
2443 * and you can go talk to the chipset vendor about it.
2445 if (!io_apic_level_ack_pending(cfg
))
2446 irq_move_masked_irq(data
);
2451 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2455 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2456 struct irq_cfg
*cfg
, bool masked
)
2461 static void ack_apic_level(struct irq_data
*data
)
2463 struct irq_cfg
*cfg
= data
->chip_data
;
2464 int i
, irq
= data
->irq
;
2468 irq_complete_move(cfg
);
2469 masked
= ioapic_irqd_mask(data
, cfg
);
2472 * It appears there is an erratum which affects at least version 0x11
2473 * of I/O APIC (that's the 82093AA and cores integrated into various
2474 * chipsets). Under certain conditions a level-triggered interrupt is
2475 * erroneously delivered as edge-triggered one but the respective IRR
2476 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2477 * message but it will never arrive and further interrupts are blocked
2478 * from the source. The exact reason is so far unknown, but the
2479 * phenomenon was observed when two consecutive interrupt requests
2480 * from a given source get delivered to the same CPU and the source is
2481 * temporarily disabled in between.
2483 * A workaround is to simulate an EOI message manually. We achieve it
2484 * by setting the trigger mode to edge and then to level when the edge
2485 * trigger mode gets detected in the TMR of a local APIC for a
2486 * level-triggered interrupt. We mask the source for the time of the
2487 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2488 * The idea is from Manfred Spraul. --macro
2490 * Also in the case when cpu goes offline, fixup_irqs() will forward
2491 * any unhandled interrupt on the offlined cpu to the new cpu
2492 * destination that is handling the corresponding interrupt. This
2493 * interrupt forwarding is done via IPI's. Hence, in this case also
2494 * level-triggered io-apic interrupt will be seen as an edge
2495 * interrupt in the IRR. And we can't rely on the cpu's EOI
2496 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2497 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2498 * supporting EOI register, we do an explicit EOI to clear the
2499 * remote IRR and on IO-APIC's which don't have an EOI register,
2500 * we use the above logic (mask+edge followed by unmask+level) from
2501 * Manfred Spraul to clear the remote IRR.
2504 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2507 * We must acknowledge the irq before we move it or the acknowledge will
2508 * not propagate properly.
2513 * Tail end of clearing remote IRR bit (either by delivering the EOI
2514 * message via io-apic EOI register write or simulating it using
2515 * mask+edge followed by unnask+level logic) manually when the
2516 * level triggered interrupt is seen as the edge triggered interrupt
2519 if (!(v
& (1 << (i
& 0x1f)))) {
2520 atomic_inc(&irq_mis_count
);
2522 eoi_ioapic_irq(irq
, cfg
);
2525 ioapic_irqd_unmask(data
, cfg
, masked
);
2528 static struct irq_chip ioapic_chip __read_mostly
= {
2530 .irq_startup
= startup_ioapic_irq
,
2531 .irq_mask
= mask_ioapic_irq
,
2532 .irq_unmask
= unmask_ioapic_irq
,
2533 .irq_ack
= ack_apic_edge
,
2534 .irq_eoi
= ack_apic_level
,
2535 .irq_set_affinity
= native_ioapic_set_affinity
,
2536 .irq_retrigger
= ioapic_retrigger_irq
,
2539 static inline void init_IO_APIC_traps(void)
2541 struct irq_cfg
*cfg
;
2544 for_each_active_irq(irq
) {
2546 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2548 * Hmm.. We don't have an entry for this,
2549 * so default to an old-fashioned 8259
2550 * interrupt if we can..
2552 if (irq
< nr_legacy_irqs())
2553 legacy_pic
->make_irq(irq
);
2555 /* Strange. Oh, well.. */
2556 irq_set_chip(irq
, &no_irq_chip
);
2562 * The local APIC irq-chip implementation:
2565 static void mask_lapic_irq(struct irq_data
*data
)
2569 v
= apic_read(APIC_LVT0
);
2570 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2573 static void unmask_lapic_irq(struct irq_data
*data
)
2577 v
= apic_read(APIC_LVT0
);
2578 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2581 static void ack_lapic_irq(struct irq_data
*data
)
2586 static struct irq_chip lapic_chip __read_mostly
= {
2587 .name
= "local-APIC",
2588 .irq_mask
= mask_lapic_irq
,
2589 .irq_unmask
= unmask_lapic_irq
,
2590 .irq_ack
= ack_lapic_irq
,
2593 static void lapic_register_intr(int irq
)
2595 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2596 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2601 * This looks a bit hackish but it's about the only one way of sending
2602 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2603 * not support the ExtINT mode, unfortunately. We need to send these
2604 * cycles as some i82489DX-based boards have glue logic that keeps the
2605 * 8259A interrupt line asserted until INTA. --macro
2607 static inline void __init
unlock_ExtINT_logic(void)
2610 struct IO_APIC_route_entry entry0
, entry1
;
2611 unsigned char save_control
, save_freq_select
;
2613 pin
= find_isa_irq_pin(8, mp_INT
);
2618 apic
= find_isa_irq_apic(8, mp_INT
);
2624 entry0
= ioapic_read_entry(apic
, pin
);
2625 clear_IO_APIC_pin(apic
, pin
);
2627 memset(&entry1
, 0, sizeof(entry1
));
2629 entry1
.dest_mode
= 0; /* physical delivery */
2630 entry1
.mask
= 0; /* unmask IRQ now */
2631 entry1
.dest
= hard_smp_processor_id();
2632 entry1
.delivery_mode
= dest_ExtINT
;
2633 entry1
.polarity
= entry0
.polarity
;
2637 ioapic_write_entry(apic
, pin
, entry1
);
2639 save_control
= CMOS_READ(RTC_CONTROL
);
2640 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2641 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2643 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2648 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2652 CMOS_WRITE(save_control
, RTC_CONTROL
);
2653 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2654 clear_IO_APIC_pin(apic
, pin
);
2656 ioapic_write_entry(apic
, pin
, entry0
);
2659 static int disable_timer_pin_1 __initdata
;
2660 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2661 static int __init
disable_timer_pin_setup(char *arg
)
2663 disable_timer_pin_1
= 1;
2666 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2669 * This code may look a bit paranoid, but it's supposed to cooperate with
2670 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2671 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2672 * fanatically on his truly buggy board.
2674 * FIXME: really need to revamp this for all platforms.
2676 static inline void __init
check_timer(void)
2678 struct irq_cfg
*cfg
= irq_cfg(0);
2679 int node
= cpu_to_node(0);
2680 int apic1
, pin1
, apic2
, pin2
;
2681 unsigned long flags
;
2684 local_irq_save(flags
);
2687 * get/set the timer IRQ vector:
2689 legacy_pic
->mask(0);
2690 assign_irq_vector(0, cfg
, apic
->target_cpus());
2693 * As IRQ0 is to be enabled in the 8259A, the virtual
2694 * wire has to be disabled in the local APIC. Also
2695 * timer interrupts need to be acknowledged manually in
2696 * the 8259A for the i82489DX when using the NMI
2697 * watchdog as that APIC treats NMIs as level-triggered.
2698 * The AEOI mode will finish them in the 8259A
2701 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2702 legacy_pic
->init(1);
2704 pin1
= find_isa_irq_pin(0, mp_INT
);
2705 apic1
= find_isa_irq_apic(0, mp_INT
);
2706 pin2
= ioapic_i8259
.pin
;
2707 apic2
= ioapic_i8259
.apic
;
2709 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2710 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2711 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2714 * Some BIOS writers are clueless and report the ExtINTA
2715 * I/O APIC input from the cascaded 8259A as the timer
2716 * interrupt input. So just in case, if only one pin
2717 * was found above, try it both directly and through the
2721 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2725 } else if (pin2
== -1) {
2732 * Ok, does IRQ0 through the IOAPIC work?
2735 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2736 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2738 /* for edge trigger, setup_ioapic_irq already
2739 * leave it unmasked.
2740 * so only need to unmask if it is level-trigger
2741 * do we really have level trigger timer?
2744 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2745 if (idx
!= -1 && irq_trigger(idx
))
2748 if (timer_irq_works()) {
2749 if (disable_timer_pin_1
> 0)
2750 clear_IO_APIC_pin(0, pin1
);
2753 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2754 local_irq_disable();
2755 clear_IO_APIC_pin(apic1
, pin1
);
2757 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2758 "8254 timer not connected to IO-APIC\n");
2760 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2761 "(IRQ0) through the 8259A ...\n");
2762 apic_printk(APIC_QUIET
, KERN_INFO
2763 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2765 * legacy devices should be connected to IO APIC #0
2767 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2768 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2769 legacy_pic
->unmask(0);
2770 if (timer_irq_works()) {
2771 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2775 * Cleanup, just in case ...
2777 local_irq_disable();
2778 legacy_pic
->mask(0);
2779 clear_IO_APIC_pin(apic2
, pin2
);
2780 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2783 apic_printk(APIC_QUIET
, KERN_INFO
2784 "...trying to set up timer as Virtual Wire IRQ...\n");
2786 lapic_register_intr(0);
2787 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2788 legacy_pic
->unmask(0);
2790 if (timer_irq_works()) {
2791 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2794 local_irq_disable();
2795 legacy_pic
->mask(0);
2796 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2797 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2799 apic_printk(APIC_QUIET
, KERN_INFO
2800 "...trying to set up timer as ExtINT IRQ...\n");
2802 legacy_pic
->init(0);
2803 legacy_pic
->make_irq(0);
2804 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2806 unlock_ExtINT_logic();
2808 if (timer_irq_works()) {
2809 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2812 local_irq_disable();
2813 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2814 if (x2apic_preenabled
)
2815 apic_printk(APIC_QUIET
, KERN_INFO
2816 "Perhaps problem with the pre-enabled x2apic mode\n"
2817 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2818 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2819 "report. Then try booting with the 'noapic' option.\n");
2821 local_irq_restore(flags
);
2825 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2826 * to devices. However there may be an I/O APIC pin available for
2827 * this interrupt regardless. The pin may be left unconnected, but
2828 * typically it will be reused as an ExtINT cascade interrupt for
2829 * the master 8259A. In the MPS case such a pin will normally be
2830 * reported as an ExtINT interrupt in the MP table. With ACPI
2831 * there is no provision for ExtINT interrupts, and in the absence
2832 * of an override it would be treated as an ordinary ISA I/O APIC
2833 * interrupt, that is edge-triggered and unmasked by default. We
2834 * used to do this, but it caused problems on some systems because
2835 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2836 * the same ExtINT cascade interrupt to drive the local APIC of the
2837 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2838 * the I/O APIC in all cases now. No actual device should request
2839 * it anyway. --macro
2841 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2843 void __init
setup_IO_APIC(void)
2847 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2849 io_apic_irqs
= nr_legacy_irqs() ? ~PIC_IRQS
: ~0UL;
2851 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2853 * Set up IO-APIC IRQ routing.
2855 x86_init
.mpparse
.setup_ioapic_ids();
2858 setup_IO_APIC_irqs();
2859 init_IO_APIC_traps();
2860 if (nr_legacy_irqs())
2865 * Called after all the initialization is done. If we didn't find any
2866 * APIC bugs then we can allow the modify fast path
2869 static int __init
io_apic_bug_finalize(void)
2871 if (sis_apic_bug
== -1)
2876 late_initcall(io_apic_bug_finalize
);
2878 static void resume_ioapic_id(int ioapic_idx
)
2880 unsigned long flags
;
2881 union IO_APIC_reg_00 reg_00
;
2883 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2884 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2885 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
2886 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2887 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2889 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2892 static void ioapic_resume(void)
2896 for_each_ioapic_reverse(ioapic_idx
)
2897 resume_ioapic_id(ioapic_idx
);
2899 restore_ioapic_entries();
2902 static struct syscore_ops ioapic_syscore_ops
= {
2903 .suspend
= save_ioapic_entries
,
2904 .resume
= ioapic_resume
,
2907 static int __init
ioapic_init_ops(void)
2909 register_syscore_ops(&ioapic_syscore_ops
);
2914 device_initcall(ioapic_init_ops
);
2917 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
2919 int arch_setup_hwirq(unsigned int irq
, int node
)
2921 struct irq_cfg
*cfg
;
2922 unsigned long flags
;
2925 cfg
= alloc_irq_cfg(irq
, node
);
2929 raw_spin_lock_irqsave(&vector_lock
, flags
);
2930 ret
= __assign_irq_vector(irq
, cfg
, apic
->target_cpus());
2931 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2934 irq_set_chip_data(irq
, cfg
);
2936 free_irq_cfg(irq
, cfg
);
2940 void arch_teardown_hwirq(unsigned int irq
)
2942 struct irq_cfg
*cfg
= irq_cfg(irq
);
2943 unsigned long flags
;
2945 free_remapped_irq(irq
);
2946 raw_spin_lock_irqsave(&vector_lock
, flags
);
2947 __clear_irq_vector(irq
, cfg
);
2948 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2949 free_irq_cfg(irq
, cfg
);
2953 * MSI message composition
2955 void native_compose_msi_msg(struct pci_dev
*pdev
,
2956 unsigned int irq
, unsigned int dest
,
2957 struct msi_msg
*msg
, u8 hpet_id
)
2959 struct irq_cfg
*cfg
= irq_cfg(irq
);
2961 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2963 if (x2apic_enabled())
2964 msg
->address_hi
|= MSI_ADDR_EXT_DEST_ID(dest
);
2968 ((apic
->irq_dest_mode
== 0) ?
2969 MSI_ADDR_DEST_MODE_PHYSICAL
:
2970 MSI_ADDR_DEST_MODE_LOGICAL
) |
2971 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
2972 MSI_ADDR_REDIRECTION_CPU
:
2973 MSI_ADDR_REDIRECTION_LOWPRI
) |
2974 MSI_ADDR_DEST_ID(dest
);
2977 MSI_DATA_TRIGGER_EDGE
|
2978 MSI_DATA_LEVEL_ASSERT
|
2979 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
2980 MSI_DATA_DELIVERY_FIXED
:
2981 MSI_DATA_DELIVERY_LOWPRI
) |
2982 MSI_DATA_VECTOR(cfg
->vector
);
2985 #ifdef CONFIG_PCI_MSI
2986 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
2987 struct msi_msg
*msg
, u8 hpet_id
)
2989 struct irq_cfg
*cfg
;
2997 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3001 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3002 apic
->target_cpus(), &dest
);
3006 x86_msi
.compose_msi_msg(pdev
, irq
, dest
, msg
, hpet_id
);
3012 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3014 struct irq_cfg
*cfg
= data
->chip_data
;
3019 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3023 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3025 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3026 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3027 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3028 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3030 __write_msi_msg(data
->msi_desc
, &msg
);
3032 return IRQ_SET_MASK_OK_NOCOPY
;
3036 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3037 * which implement the MSI or MSI-X Capability Structure.
3039 static struct irq_chip msi_chip
= {
3041 .irq_unmask
= unmask_msi_irq
,
3042 .irq_mask
= mask_msi_irq
,
3043 .irq_ack
= ack_apic_edge
,
3044 .irq_set_affinity
= msi_set_affinity
,
3045 .irq_retrigger
= ioapic_retrigger_irq
,
3048 int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
,
3049 unsigned int irq_base
, unsigned int irq_offset
)
3051 struct irq_chip
*chip
= &msi_chip
;
3053 unsigned int irq
= irq_base
+ irq_offset
;
3056 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3060 irq_set_msi_desc_off(irq_base
, irq_offset
, msidesc
);
3063 * MSI-X message is written per-IRQ, the offset is always 0.
3064 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3067 write_msi_msg(irq
, &msg
);
3069 setup_remapped_irq(irq
, irq_cfg(irq
), chip
);
3071 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3073 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3078 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3080 struct msi_desc
*msidesc
;
3084 /* Multiple MSI vectors only supported with interrupt remapping */
3085 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3088 node
= dev_to_node(&dev
->dev
);
3090 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3091 irq
= irq_alloc_hwirq(node
);
3095 ret
= setup_msi_irq(dev
, msidesc
, irq
, 0);
3097 irq_free_hwirq(irq
);
3105 void native_teardown_msi_irq(unsigned int irq
)
3107 irq_free_hwirq(irq
);
3110 #ifdef CONFIG_DMAR_TABLE
3112 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3115 struct irq_cfg
*cfg
= data
->chip_data
;
3116 unsigned int dest
, irq
= data
->irq
;
3120 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3124 dmar_msi_read(irq
, &msg
);
3126 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3127 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3128 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3129 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3130 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3132 dmar_msi_write(irq
, &msg
);
3134 return IRQ_SET_MASK_OK_NOCOPY
;
3137 static struct irq_chip dmar_msi_type
= {
3139 .irq_unmask
= dmar_msi_unmask
,
3140 .irq_mask
= dmar_msi_mask
,
3141 .irq_ack
= ack_apic_edge
,
3142 .irq_set_affinity
= dmar_msi_set_affinity
,
3143 .irq_retrigger
= ioapic_retrigger_irq
,
3146 int arch_setup_dmar_msi(unsigned int irq
)
3151 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3154 dmar_msi_write(irq
, &msg
);
3155 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3161 #ifdef CONFIG_HPET_TIMER
3163 static int hpet_msi_set_affinity(struct irq_data
*data
,
3164 const struct cpumask
*mask
, bool force
)
3166 struct irq_cfg
*cfg
= data
->chip_data
;
3171 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3175 hpet_msi_read(data
->handler_data
, &msg
);
3177 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3178 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3179 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3180 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3182 hpet_msi_write(data
->handler_data
, &msg
);
3184 return IRQ_SET_MASK_OK_NOCOPY
;
3187 static struct irq_chip hpet_msi_type
= {
3189 .irq_unmask
= hpet_msi_unmask
,
3190 .irq_mask
= hpet_msi_mask
,
3191 .irq_ack
= ack_apic_edge
,
3192 .irq_set_affinity
= hpet_msi_set_affinity
,
3193 .irq_retrigger
= ioapic_retrigger_irq
,
3196 int default_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3198 struct irq_chip
*chip
= &hpet_msi_type
;
3202 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3206 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3207 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3208 setup_remapped_irq(irq
, irq_cfg(irq
), chip
);
3210 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3215 #endif /* CONFIG_PCI_MSI */
3217 * Hypertransport interrupt support
3219 #ifdef CONFIG_HT_IRQ
3221 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3223 struct ht_irq_msg msg
;
3224 fetch_ht_irq_msg(irq
, &msg
);
3226 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3227 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3229 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3230 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3232 write_ht_irq_msg(irq
, &msg
);
3236 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3238 struct irq_cfg
*cfg
= data
->chip_data
;
3242 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
3246 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3247 return IRQ_SET_MASK_OK_NOCOPY
;
3250 static struct irq_chip ht_irq_chip
= {
3252 .irq_mask
= mask_ht_irq
,
3253 .irq_unmask
= unmask_ht_irq
,
3254 .irq_ack
= ack_apic_edge
,
3255 .irq_set_affinity
= ht_set_affinity
,
3256 .irq_retrigger
= ioapic_retrigger_irq
,
3259 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3261 struct irq_cfg
*cfg
;
3262 struct ht_irq_msg msg
;
3270 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3274 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3275 apic
->target_cpus(), &dest
);
3279 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3283 HT_IRQ_LOW_DEST_ID(dest
) |
3284 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3285 ((apic
->irq_dest_mode
== 0) ?
3286 HT_IRQ_LOW_DM_PHYSICAL
:
3287 HT_IRQ_LOW_DM_LOGICAL
) |
3288 HT_IRQ_LOW_RQEOI_EDGE
|
3289 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3290 HT_IRQ_LOW_MT_FIXED
:
3291 HT_IRQ_LOW_MT_ARBITRATED
) |
3292 HT_IRQ_LOW_IRQ_MASKED
;
3294 write_ht_irq_msg(irq
, &msg
);
3296 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3297 handle_edge_irq
, "edge");
3299 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3303 #endif /* CONFIG_HT_IRQ */
3306 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3308 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3313 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3315 setup_ioapic_irq(irq
, cfg
, attr
);
3319 int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
3320 struct io_apic_irq_attr
*attr
)
3322 unsigned int ioapic_idx
= attr
->ioapic
, pin
= attr
->ioapic_pin
;
3324 struct IO_APIC_route_entry orig_entry
;
3326 /* Avoid redundant programming */
3327 if (test_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
)) {
3328 pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx
), pin
);
3329 orig_entry
= ioapic_read_entry(attr
->ioapic
, pin
);
3330 if (attr
->trigger
== orig_entry
.trigger
&& attr
->polarity
== orig_entry
.polarity
)
3334 ret
= io_apic_setup_irq_pin(irq
, node
, attr
);
3336 set_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
);
3340 static int __init
io_apic_get_redir_entries(int ioapic
)
3342 union IO_APIC_reg_01 reg_01
;
3343 unsigned long flags
;
3345 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3346 reg_01
.raw
= io_apic_read(ioapic
, 1);
3347 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3349 /* The register returns the maximum index redir index
3350 * supported, which is one less than the total number of redir
3353 return reg_01
.bits
.entries
+ 1;
3356 unsigned int arch_dynirq_lower_bound(unsigned int from
)
3358 unsigned int min
= gsi_top
+ nr_legacy_irqs();
3360 return from
< min
? min
: from
;
3363 int __init
arch_probe_nr_irqs(void)
3367 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3368 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3370 nr
= (gsi_top
+ nr_legacy_irqs()) + 8 * nr_cpu_ids
;
3371 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3373 * for MSI and HT dyn irq
3380 return nr_legacy_irqs();
3383 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3384 struct io_apic_irq_attr
*irq_attr
)
3388 if (!IO_APIC_IRQ(irq
)) {
3389 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3394 node
= dev
? dev_to_node(dev
) : cpu_to_node(0);
3396 return io_apic_setup_irq_pin_once(irq
, node
, irq_attr
);
3399 #ifdef CONFIG_X86_32
3400 static int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3402 union IO_APIC_reg_00 reg_00
;
3403 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3405 unsigned long flags
;
3409 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3410 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3411 * supports up to 16 on one shared APIC bus.
3413 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3414 * advantage of new APIC bus architecture.
3417 if (physids_empty(apic_id_map
))
3418 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3420 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3421 reg_00
.raw
= io_apic_read(ioapic
, 0);
3422 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3424 if (apic_id
>= get_physical_broadcast()) {
3425 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3426 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3427 apic_id
= reg_00
.bits
.ID
;
3431 * Every APIC in a system must have a unique ID or we get lots of nice
3432 * 'stuck on smp_invalidate_needed IPI wait' messages.
3434 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3436 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3437 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3441 if (i
== get_physical_broadcast())
3442 panic("Max apic_id exceeded!\n");
3444 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3445 "trying %d\n", ioapic
, apic_id
, i
);
3450 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3451 physids_or(apic_id_map
, apic_id_map
, tmp
);
3453 if (reg_00
.bits
.ID
!= apic_id
) {
3454 reg_00
.bits
.ID
= apic_id
;
3456 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3457 io_apic_write(ioapic
, 0, reg_00
.raw
);
3458 reg_00
.raw
= io_apic_read(ioapic
, 0);
3459 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3462 if (reg_00
.bits
.ID
!= apic_id
) {
3463 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3469 apic_printk(APIC_VERBOSE
, KERN_INFO
3470 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3475 static u8 __init
io_apic_unique_id(u8 id
)
3477 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3478 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3479 return io_apic_get_unique_id(nr_ioapics
, id
);
3484 static u8 __init
io_apic_unique_id(u8 id
)
3487 DECLARE_BITMAP(used
, 256);
3489 bitmap_zero(used
, 256);
3491 __set_bit(mpc_ioapic_id(i
), used
);
3492 if (!test_bit(id
, used
))
3494 return find_first_zero_bit(used
, 256);
3498 static int __init
io_apic_get_version(int ioapic
)
3500 union IO_APIC_reg_01 reg_01
;
3501 unsigned long flags
;
3503 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3504 reg_01
.raw
= io_apic_read(ioapic
, 1);
3505 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3507 return reg_01
.bits
.version
;
3510 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3512 int ioapic
, pin
, idx
;
3514 if (skip_ioapic_setup
)
3517 ioapic
= mp_find_ioapic(gsi
);
3521 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3525 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3529 *trigger
= irq_trigger(idx
);
3530 *polarity
= irq_polarity(idx
);
3535 * This function currently is only a helper for the i386 smp boot process where
3536 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3537 * so mask in all cases should simply be apic->target_cpus()
3540 void __init
setup_ioapic_dest(void)
3542 int pin
, ioapic
, irq
, irq_entry
;
3543 const struct cpumask
*mask
;
3544 struct irq_data
*idata
;
3546 if (skip_ioapic_setup
== 1)
3549 for_each_ioapic_pin(ioapic
, pin
) {
3550 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3551 if (irq_entry
== -1)
3554 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3555 if (!mp_init_irq_at_boot(ioapic
, irq
))
3558 idata
= irq_get_irq_data(irq
);
3561 * Honour affinities which have been set in early boot
3563 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3564 mask
= idata
->affinity
;
3566 mask
= apic
->target_cpus();
3568 x86_io_apic_ops
.set_affinity(idata
, mask
, false);
3574 #define IOAPIC_RESOURCE_NAME_SIZE 11
3576 static struct resource
*ioapic_resources
;
3578 static struct resource
* __init
ioapic_setup_resources(void)
3581 struct resource
*res
;
3590 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3593 mem
= alloc_bootmem(n
);
3596 mem
+= sizeof(struct resource
) * num
;
3599 for_each_ioapic(i
) {
3600 res
[num
].name
= mem
;
3601 res
[num
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3602 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3603 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3607 ioapic_resources
= res
;
3612 void __init
native_io_apic_init_mappings(void)
3614 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3615 struct resource
*ioapic_res
;
3618 ioapic_res
= ioapic_setup_resources();
3619 for_each_ioapic(i
) {
3620 if (smp_found_config
) {
3621 ioapic_phys
= mpc_ioapic_addr(i
);
3622 #ifdef CONFIG_X86_32
3625 "WARNING: bogus zero IO-APIC "
3626 "address found in MPTABLE, "
3627 "disabling IO/APIC support!\n");
3628 smp_found_config
= 0;
3629 skip_ioapic_setup
= 1;
3630 goto fake_ioapic_page
;
3634 #ifdef CONFIG_X86_32
3637 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3638 ioapic_phys
= __pa(ioapic_phys
);
3640 set_fixmap_nocache(idx
, ioapic_phys
);
3641 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3642 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3646 ioapic_res
->start
= ioapic_phys
;
3647 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3652 void __init
ioapic_insert_resources(void)
3655 struct resource
*r
= ioapic_resources
;
3660 "IO APIC resources couldn't be allocated.\n");
3664 for_each_ioapic(i
) {
3665 insert_resource(&iomem_resource
, r
);
3670 int mp_find_ioapic(u32 gsi
)
3674 if (nr_ioapics
== 0)
3677 /* Find the IOAPIC that manages this GSI. */
3678 for_each_ioapic(i
) {
3679 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
3680 if (gsi
>= gsi_cfg
->gsi_base
&& gsi
<= gsi_cfg
->gsi_end
)
3684 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3688 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3690 struct mp_ioapic_gsi
*gsi_cfg
;
3692 if (WARN_ON(ioapic
< 0))
3695 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3696 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
3699 return gsi
- gsi_cfg
->gsi_base
;
3702 static __init
int bad_ioapic(unsigned long address
)
3704 if (nr_ioapics
>= MAX_IO_APICS
) {
3705 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3706 MAX_IO_APICS
, nr_ioapics
);
3710 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3716 static __init
int bad_ioapic_register(int idx
)
3718 union IO_APIC_reg_00 reg_00
;
3719 union IO_APIC_reg_01 reg_01
;
3720 union IO_APIC_reg_02 reg_02
;
3722 reg_00
.raw
= io_apic_read(idx
, 0);
3723 reg_01
.raw
= io_apic_read(idx
, 1);
3724 reg_02
.raw
= io_apic_read(idx
, 2);
3726 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
3727 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3728 mpc_ioapic_addr(idx
));
3735 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
3739 struct mp_ioapic_gsi
*gsi_cfg
;
3741 if (bad_ioapic(address
))
3746 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
3747 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
3748 ioapics
[idx
].mp_config
.apicaddr
= address
;
3750 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
3752 if (bad_ioapic_register(idx
)) {
3753 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3757 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(id
);
3758 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
3761 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3762 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3764 entries
= io_apic_get_redir_entries(idx
);
3765 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
3766 gsi_cfg
->gsi_base
= gsi_base
;
3767 gsi_cfg
->gsi_end
= gsi_base
+ entries
- 1;
3770 * The number of IO-APIC IRQ registers (== #pins):
3772 ioapics
[idx
].nr_registers
= entries
;
3774 if (gsi_cfg
->gsi_end
>= gsi_top
)
3775 gsi_top
= gsi_cfg
->gsi_end
+ 1;
3777 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3778 idx
, mpc_ioapic_id(idx
),
3779 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
3780 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3785 /* Enable IOAPIC early just for system timer */
3786 void __init
pre_init_apic_IRQ0(void)
3788 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
3790 printk(KERN_INFO
"Early APIC setup for system timer0\n");
3792 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
3793 &phys_cpu_present_map
);
3797 io_apic_setup_irq_pin(0, 0, &attr
);
3798 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,