2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/irqdomain.h>
35 #include <linux/freezer.h>
36 #include <linux/kthread.h>
37 #include <linux/jiffies.h> /* time_after() */
38 #include <linux/slab.h>
39 #include <linux/bootmem.h>
46 #include <asm/proto.h>
49 #include <asm/timer.h>
50 #include <asm/i8259.h>
51 #include <asm/setup.h>
52 #include <asm/irq_remapping.h>
53 #include <asm/hw_irq.h>
57 #define for_each_ioapic(idx) \
58 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
59 #define for_each_ioapic_reverse(idx) \
60 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
61 #define for_each_pin(idx, pin) \
62 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
63 #define for_each_ioapic_pin(idx, pin) \
64 for_each_ioapic((idx)) \
65 for_each_pin((idx), (pin))
67 #define for_each_irq_pin(entry, head) \
68 list_for_each_entry(entry, &head, list)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_MUTEX(ioapic_mutex
);
78 static unsigned int ioapic_dynirq_base
;
79 static int ioapic_initialized
;
82 struct IO_APIC_route_entry entry
;
96 static struct ioapic
{
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry
*saved_registers
;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config
;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config
;
109 struct ioapic_domain_cfg irqdomain_cfg
;
110 struct irq_domain
*irqdomain
;
111 struct mp_pin_info
*pin_info
;
112 struct resource
*iomem_res
;
113 } ioapics
[MAX_IO_APICS
];
115 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
117 int mpc_ioapic_id(int ioapic_idx
)
119 return ioapics
[ioapic_idx
].mp_config
.apicid
;
122 unsigned int mpc_ioapic_addr(int ioapic_idx
)
124 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
127 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
129 return &ioapics
[ioapic_idx
].gsi_config
;
132 static inline int mp_ioapic_pin_count(int ioapic
)
134 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
136 return gsi_cfg
->gsi_end
- gsi_cfg
->gsi_base
+ 1;
139 u32
mp_pin_to_gsi(int ioapic
, int pin
)
141 return mp_ioapic_gsi_routing(ioapic
)->gsi_base
+ pin
;
145 * Initialize all legacy IRQs and all pins on the first IOAPIC
146 * if we have legacy interrupt controller. Kernel boot option "pirq="
147 * may rely on non-legacy pins on the first IOAPIC.
149 static inline int mp_init_irq_at_boot(int ioapic
, int irq
)
151 if (!nr_legacy_irqs())
154 return ioapic
== 0 || (irq
>= 0 && irq
< nr_legacy_irqs());
157 static inline struct mp_pin_info
*mp_pin_info(int ioapic_idx
, int pin
)
159 return ioapics
[ioapic_idx
].pin_info
+ pin
;
162 static inline struct irq_domain
*mp_ioapic_irqdomain(int ioapic
)
164 return ioapics
[ioapic
].irqdomain
;
169 /* The one past the highest gsi number used */
172 /* MP IRQ source entries */
173 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
175 /* # of MP IRQ source entries */
179 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
182 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
184 int skip_ioapic_setup
;
187 * disable_ioapic_support() - disables ioapic support at runtime
189 void disable_ioapic_support(void)
193 noioapicreroute
= -1;
195 skip_ioapic_setup
= 1;
198 static int __init
parse_noapic(char *str
)
200 /* disable IO-APIC */
201 disable_ioapic_support();
204 early_param("noapic", parse_noapic
);
206 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
207 void mp_save_irq(struct mpc_intsrc
*m
)
211 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
212 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
213 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
214 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
216 for (i
= 0; i
< mp_irq_entries
; i
++) {
217 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
221 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
222 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
223 panic("Max # of irq sources exceeded!!\n");
226 struct irq_pin_list
{
227 struct list_head list
;
231 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
233 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
236 static void alloc_ioapic_saved_registers(int idx
)
240 if (ioapics
[idx
].saved_registers
)
243 size
= sizeof(struct IO_APIC_route_entry
) * ioapics
[idx
].nr_registers
;
244 ioapics
[idx
].saved_registers
= kzalloc(size
, GFP_KERNEL
);
245 if (!ioapics
[idx
].saved_registers
)
246 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx
);
249 static void free_ioapic_saved_registers(int idx
)
251 kfree(ioapics
[idx
].saved_registers
);
252 ioapics
[idx
].saved_registers
= NULL
;
255 int __init
arch_early_ioapic_init(void)
259 if (!nr_legacy_irqs())
263 alloc_ioapic_saved_registers(i
);
270 unsigned int unused
[3];
272 unsigned int unused2
[11];
276 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
278 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
279 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
282 void io_apic_eoi(unsigned int apic
, unsigned int vector
)
284 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
285 writel(vector
, &io_apic
->eoi
);
288 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
290 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
291 writel(reg
, &io_apic
->index
);
292 return readl(&io_apic
->data
);
295 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
297 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
299 writel(reg
, &io_apic
->index
);
300 writel(value
, &io_apic
->data
);
304 * Re-write a value: to be used for read-modify-write
305 * cycles where the read already set up the index register.
307 * Older SiS APIC requires we rewrite the index register
309 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
311 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
314 writel(reg
, &io_apic
->index
);
315 writel(value
, &io_apic
->data
);
319 struct { u32 w1
, w2
; };
320 struct IO_APIC_route_entry entry
;
323 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
325 union entry_union eu
;
327 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
328 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
333 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
335 union entry_union eu
;
338 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
339 eu
.entry
= __ioapic_read_entry(apic
, pin
);
340 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
346 * When we write a new IO APIC routing entry, we need to write the high
347 * word first! If the mask bit in the low word is clear, we will enable
348 * the interrupt, and we need to make sure the entry is fully populated
349 * before that happens.
351 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
353 union entry_union eu
= {{0, 0}};
356 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
357 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
360 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
364 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
365 __ioapic_write_entry(apic
, pin
, e
);
366 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
370 * When we mask an IO APIC routing entry, we need to write the low
371 * word first, in order to set the mask bit before we change the
374 static void ioapic_mask_entry(int apic
, int pin
)
377 union entry_union eu
= { .entry
.mask
= 1 };
379 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
380 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
381 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
382 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
386 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
387 * shared ISA-space IRQs, so we have to support them. We are super
388 * fast in the common case, and fast for shared ISA-space IRQs.
390 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
392 struct irq_pin_list
*entry
;
394 /* don't allow duplicates */
395 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
396 if (entry
->apic
== apic
&& entry
->pin
== pin
)
399 entry
= alloc_irq_pin_list(node
);
401 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
408 list_add_tail(&entry
->list
, &cfg
->irq_2_pin
);
412 static void __remove_pin_from_irq(struct irq_cfg
*cfg
, int apic
, int pin
)
414 struct irq_pin_list
*tmp
, *entry
;
416 list_for_each_entry_safe(entry
, tmp
, &cfg
->irq_2_pin
, list
)
417 if (entry
->apic
== apic
&& entry
->pin
== pin
) {
418 list_del(&entry
->list
);
424 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
426 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
427 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
431 * Reroute an IRQ to a different pin.
433 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
434 int oldapic
, int oldpin
,
435 int newapic
, int newpin
)
437 struct irq_pin_list
*entry
;
439 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
440 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
441 entry
->apic
= newapic
;
443 /* every one is different, right? */
448 /* old apic/pin didn't exist, so just add new ones */
449 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
452 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
453 int mask_and
, int mask_or
,
454 void (*final
)(struct irq_pin_list
*entry
))
456 unsigned int reg
, pin
;
459 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
462 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
467 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
468 int mask_and
, int mask_or
,
469 void (*final
)(struct irq_pin_list
*entry
))
471 struct irq_pin_list
*entry
;
473 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
474 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
477 static void io_apic_sync(struct irq_pin_list
*entry
)
480 * Synchronize the IO-APIC and the CPU by doing
481 * a dummy read from the IO-APIC
483 struct io_apic __iomem
*io_apic
;
485 io_apic
= io_apic_base(entry
->apic
);
486 readl(&io_apic
->data
);
489 static void mask_ioapic(struct irq_cfg
*cfg
)
493 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
494 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
495 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
498 static void mask_ioapic_irq(struct irq_data
*data
)
500 mask_ioapic(irqd_cfg(data
));
503 static void __unmask_ioapic(struct irq_cfg
*cfg
)
505 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
508 static void unmask_ioapic(struct irq_cfg
*cfg
)
512 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
513 __unmask_ioapic(cfg
);
514 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
517 static void unmask_ioapic_irq(struct irq_data
*data
)
519 unmask_ioapic(irqd_cfg(data
));
523 * IO-APIC versions below 0x20 don't support EOI register.
524 * For the record, here is the information about various versions:
526 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
527 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
530 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
531 * version as 0x2. This is an error with documentation and these ICH chips
532 * use io-apic's of version 0x20.
534 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
535 * Otherwise, we simulate the EOI message manually by changing the trigger
536 * mode to edge and then back to level, with RTE being masked during this.
538 void native_eoi_ioapic_pin(int apic
, int pin
, int vector
)
540 if (mpc_ioapic_ver(apic
) >= 0x20) {
541 io_apic_eoi(apic
, vector
);
543 struct IO_APIC_route_entry entry
, entry1
;
545 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
548 * Mask the entry and change the trigger mode to edge.
551 entry1
.trigger
= IOAPIC_EDGE
;
553 __ioapic_write_entry(apic
, pin
, entry1
);
556 * Restore the previous level triggered entry.
558 __ioapic_write_entry(apic
, pin
, entry
);
562 void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
564 struct irq_pin_list
*entry
;
567 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
568 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
569 x86_io_apic_ops
.eoi_ioapic_pin(entry
->apic
, entry
->pin
,
571 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
574 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
576 struct IO_APIC_route_entry entry
;
578 /* Check delivery_mode to be sure we're not clearing an SMI pin */
579 entry
= ioapic_read_entry(apic
, pin
);
580 if (entry
.delivery_mode
== dest_SMI
)
584 * Make sure the entry is masked and re-read the contents to check
585 * if it is a level triggered pin and if the remote-IRR is set.
589 ioapic_write_entry(apic
, pin
, entry
);
590 entry
= ioapic_read_entry(apic
, pin
);
597 * Make sure the trigger mode is set to level. Explicit EOI
598 * doesn't clear the remote-IRR if the trigger mode is not
601 if (!entry
.trigger
) {
602 entry
.trigger
= IOAPIC_LEVEL
;
603 ioapic_write_entry(apic
, pin
, entry
);
606 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
607 x86_io_apic_ops
.eoi_ioapic_pin(apic
, pin
, entry
.vector
);
608 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
612 * Clear the rest of the bits in the IO-APIC RTE except for the mask
615 ioapic_mask_entry(apic
, pin
);
616 entry
= ioapic_read_entry(apic
, pin
);
618 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
619 mpc_ioapic_id(apic
), pin
);
622 static void clear_IO_APIC (void)
626 for_each_ioapic_pin(apic
, pin
)
627 clear_IO_APIC_pin(apic
, pin
);
632 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
633 * specific CPU-side IRQs.
637 static int pirq_entries
[MAX_PIRQS
] = {
638 [0 ... MAX_PIRQS
- 1] = -1
641 static int __init
ioapic_pirq_setup(char *str
)
644 int ints
[MAX_PIRQS
+1];
646 get_options(str
, ARRAY_SIZE(ints
), ints
);
648 apic_printk(APIC_VERBOSE
, KERN_INFO
649 "PIRQ redirection, working around broken MP-BIOS.\n");
651 if (ints
[0] < MAX_PIRQS
)
654 for (i
= 0; i
< max
; i
++) {
655 apic_printk(APIC_VERBOSE
, KERN_DEBUG
656 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
658 * PIRQs are mapped upside down, usually.
660 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
665 __setup("pirq=", ioapic_pirq_setup
);
666 #endif /* CONFIG_X86_32 */
669 * Saves all the IO-APIC RTE's
671 int save_ioapic_entries(void)
676 for_each_ioapic(apic
) {
677 if (!ioapics
[apic
].saved_registers
) {
682 for_each_pin(apic
, pin
)
683 ioapics
[apic
].saved_registers
[pin
] =
684 ioapic_read_entry(apic
, pin
);
691 * Mask all IO APIC entries.
693 void mask_ioapic_entries(void)
697 for_each_ioapic(apic
) {
698 if (!ioapics
[apic
].saved_registers
)
701 for_each_pin(apic
, pin
) {
702 struct IO_APIC_route_entry entry
;
704 entry
= ioapics
[apic
].saved_registers
[pin
];
707 ioapic_write_entry(apic
, pin
, entry
);
714 * Restore IO APIC entries which was saved in the ioapic structure.
716 int restore_ioapic_entries(void)
720 for_each_ioapic(apic
) {
721 if (!ioapics
[apic
].saved_registers
)
724 for_each_pin(apic
, pin
)
725 ioapic_write_entry(apic
, pin
,
726 ioapics
[apic
].saved_registers
[pin
]);
732 * Find the IRQ entry number of a certain pin.
734 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
738 for (i
= 0; i
< mp_irq_entries
; i
++)
739 if (mp_irqs
[i
].irqtype
== type
&&
740 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
741 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
742 mp_irqs
[i
].dstirq
== pin
)
749 * Find the pin to which IRQ[irq] (ISA) is connected
751 static int __init
find_isa_irq_pin(int irq
, int type
)
755 for (i
= 0; i
< mp_irq_entries
; i
++) {
756 int lbus
= mp_irqs
[i
].srcbus
;
758 if (test_bit(lbus
, mp_bus_not_pci
) &&
759 (mp_irqs
[i
].irqtype
== type
) &&
760 (mp_irqs
[i
].srcbusirq
== irq
))
762 return mp_irqs
[i
].dstirq
;
767 static int __init
find_isa_irq_apic(int irq
, int type
)
771 for (i
= 0; i
< mp_irq_entries
; i
++) {
772 int lbus
= mp_irqs
[i
].srcbus
;
774 if (test_bit(lbus
, mp_bus_not_pci
) &&
775 (mp_irqs
[i
].irqtype
== type
) &&
776 (mp_irqs
[i
].srcbusirq
== irq
))
780 if (i
< mp_irq_entries
) {
783 for_each_ioapic(ioapic_idx
)
784 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
793 * EISA Edge/Level control register, ELCR
795 static int EISA_ELCR(unsigned int irq
)
797 if (irq
< nr_legacy_irqs()) {
798 unsigned int port
= 0x4d0 + (irq
>> 3);
799 return (inb(port
) >> (irq
& 7)) & 1;
801 apic_printk(APIC_VERBOSE
, KERN_INFO
802 "Broken MPtable reports ISA irq %d\n", irq
);
808 /* ISA interrupts are always polarity zero edge triggered,
809 * when listed as conforming in the MP table. */
811 #define default_ISA_trigger(idx) (0)
812 #define default_ISA_polarity(idx) (0)
814 /* EISA interrupts are always polarity zero and can be edge or level
815 * trigger depending on the ELCR value. If an interrupt is listed as
816 * EISA conforming in the MP table, that means its trigger type must
817 * be read in from the ELCR */
819 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
820 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
822 /* PCI interrupts are always polarity one level triggered,
823 * when listed as conforming in the MP table. */
825 #define default_PCI_trigger(idx) (1)
826 #define default_PCI_polarity(idx) (1)
828 static int irq_polarity(int idx
)
830 int bus
= mp_irqs
[idx
].srcbus
;
834 * Determine IRQ line polarity (high active or low active):
836 switch (mp_irqs
[idx
].irqflag
& 3)
838 case 0: /* conforms, ie. bus-type dependent polarity */
839 if (test_bit(bus
, mp_bus_not_pci
))
840 polarity
= default_ISA_polarity(idx
);
842 polarity
= default_PCI_polarity(idx
);
844 case 1: /* high active */
849 case 2: /* reserved */
851 pr_warn("broken BIOS!!\n");
855 case 3: /* low active */
860 default: /* invalid */
862 pr_warn("broken BIOS!!\n");
870 static int irq_trigger(int idx
)
872 int bus
= mp_irqs
[idx
].srcbus
;
876 * Determine IRQ trigger mode (edge or level sensitive):
878 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
880 case 0: /* conforms, ie. bus-type dependent */
881 if (test_bit(bus
, mp_bus_not_pci
))
882 trigger
= default_ISA_trigger(idx
);
884 trigger
= default_PCI_trigger(idx
);
886 switch (mp_bus_id_to_type
[bus
]) {
887 case MP_BUS_ISA
: /* ISA pin */
889 /* set before the switch */
892 case MP_BUS_EISA
: /* EISA pin */
894 trigger
= default_EISA_trigger(idx
);
897 case MP_BUS_PCI
: /* PCI pin */
899 /* set before the switch */
904 pr_warn("broken BIOS!!\n");
916 case 2: /* reserved */
918 pr_warn("broken BIOS!!\n");
927 default: /* invalid */
929 pr_warn("broken BIOS!!\n");
937 void ioapic_set_alloc_attr(struct irq_alloc_info
*info
, int node
,
938 int trigger
, int polarity
)
940 init_irq_alloc_info(info
, NULL
);
941 info
->type
= X86_IRQ_ALLOC_TYPE_IOAPIC
;
942 info
->ioapic_node
= node
;
943 info
->ioapic_trigger
= trigger
;
944 info
->ioapic_polarity
= polarity
;
945 info
->ioapic_valid
= 1;
948 static void mp_register_handler(unsigned int irq
, unsigned long trigger
)
950 irq_flow_handler_t hdl
;
954 irq_set_status_flags(irq
, IRQ_LEVEL
);
957 irq_clear_status_flags(irq
, IRQ_LEVEL
);
961 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
962 __irq_set_handler(irq
, hdl
, 0, fasteoi
? "fasteoi" : "edge");
965 static int alloc_irq_from_domain(struct irq_domain
*domain
, u32 gsi
, int pin
,
966 struct irq_alloc_info
*info
)
969 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
970 int type
= ioapics
[ioapic
].irqdomain_cfg
.type
;
973 case IOAPIC_DOMAIN_LEGACY
:
975 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
976 * GSIs on some weird platforms.
978 if (gsi
< nr_legacy_irqs())
979 irq
= irq_create_mapping(domain
, pin
);
980 else if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
983 case IOAPIC_DOMAIN_STRICT
:
984 if (irq_create_strict_mappings(domain
, gsi
, pin
, 1) == 0)
987 case IOAPIC_DOMAIN_DYNAMIC
:
988 irq
= irq_create_mapping(domain
, pin
);
991 WARN(1, "ioapic: unknown irqdomain type %d\n", type
);
995 return irq
> 0 ? irq
: -1;
998 static int mp_map_pin_to_irq(u32 gsi
, int idx
, int ioapic
, int pin
,
999 unsigned int flags
, struct irq_alloc_info
*info
)
1002 struct irq_domain
*domain
= mp_ioapic_irqdomain(ioapic
);
1003 struct mp_pin_info
*pinfo
= mp_pin_info(ioapic
, pin
);
1008 mutex_lock(&ioapic_mutex
);
1011 * Don't use irqdomain to manage ISA IRQs because there may be
1012 * multiple IOAPIC pins sharing the same ISA IRQ number and
1013 * irqdomain only supports 1:1 mapping between IOAPIC pin and
1014 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
1015 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1016 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
1017 * available, and some BIOSes may use MP Interrupt Source records
1018 * to override IRQ numbers for PIRQs instead of reprogramming
1019 * the interrupt routing logic. Thus there may be multiple pins
1020 * sharing the same legacy IRQ number when ACPI is disabled.
1022 if (idx
>= 0 && test_bit(mp_irqs
[idx
].srcbus
, mp_bus_not_pci
)) {
1023 irq
= mp_irqs
[idx
].srcbusirq
;
1024 if (flags
& IOAPIC_MAP_ALLOC
) {
1025 if (pinfo
->count
== 0 &&
1026 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1029 /* special handling for timer IRQ0 */
1034 irq
= irq_find_mapping(domain
, pin
);
1035 if (irq
<= 0 && (flags
& IOAPIC_MAP_ALLOC
))
1036 irq
= alloc_irq_from_domain(domain
, gsi
, pin
, info
);
1039 if (flags
& IOAPIC_MAP_ALLOC
) {
1040 /* special handling for legacy IRQs */
1041 if (irq
< nr_legacy_irqs() && pinfo
->count
== 1 &&
1042 mp_irqdomain_map(domain
, irq
, pin
) != 0)
1047 else if (pinfo
->count
== 0)
1051 mutex_unlock(&ioapic_mutex
);
1053 return irq
> 0 ? irq
: -1;
1056 static int pin_2_irq(int idx
, int ioapic
, int pin
, unsigned int flags
)
1058 u32 gsi
= mp_pin_to_gsi(ioapic
, pin
);
1061 * Debugging check, we are in big trouble if this message pops up!
1063 if (mp_irqs
[idx
].dstirq
!= pin
)
1064 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1066 #ifdef CONFIG_X86_32
1068 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1070 if ((pin
>= 16) && (pin
<= 23)) {
1071 if (pirq_entries
[pin
-16] != -1) {
1072 if (!pirq_entries
[pin
-16]) {
1073 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1074 "disabling PIRQ%d\n", pin
-16);
1076 int irq
= pirq_entries
[pin
-16];
1077 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1078 "using PIRQ%d -> IRQ %d\n",
1086 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
, NULL
);
1089 int mp_map_gsi_to_irq(u32 gsi
, unsigned int flags
,
1090 struct irq_alloc_info
*info
)
1092 int ioapic
, pin
, idx
;
1094 ioapic
= mp_find_ioapic(gsi
);
1098 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
1099 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1100 if ((flags
& IOAPIC_MAP_CHECK
) && idx
< 0)
1103 return mp_map_pin_to_irq(gsi
, idx
, ioapic
, pin
, flags
, info
);
1106 void mp_unmap_irq(int irq
)
1108 struct irq_data
*data
= irq_get_irq_data(irq
);
1109 struct mp_pin_info
*info
;
1112 if (!data
|| !data
->domain
)
1115 ioapic
= (int)(long)data
->domain
->host_data
;
1116 pin
= (int)data
->hwirq
;
1117 info
= mp_pin_info(ioapic
, pin
);
1119 mutex_lock(&ioapic_mutex
);
1120 if (--info
->count
== 0) {
1122 if (irq
< nr_legacy_irqs() &&
1123 ioapics
[ioapic
].irqdomain_cfg
.type
== IOAPIC_DOMAIN_LEGACY
)
1124 mp_irqdomain_unmap(data
->domain
, irq
);
1126 irq_dispose_mapping(irq
);
1128 mutex_unlock(&ioapic_mutex
);
1132 * Find a specific PCI IRQ entry.
1133 * Not an __init, possibly needed by modules
1135 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1137 int irq
, i
, best_ioapic
= -1, best_idx
= -1;
1139 apic_printk(APIC_DEBUG
,
1140 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1142 if (test_bit(bus
, mp_bus_not_pci
)) {
1143 apic_printk(APIC_VERBOSE
,
1144 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1148 for (i
= 0; i
< mp_irq_entries
; i
++) {
1149 int lbus
= mp_irqs
[i
].srcbus
;
1150 int ioapic_idx
, found
= 0;
1152 if (bus
!= lbus
|| mp_irqs
[i
].irqtype
!= mp_INT
||
1153 slot
!= ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))
1156 for_each_ioapic(ioapic_idx
)
1157 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1158 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) {
1166 irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
, 0);
1167 if (irq
> 0 && !IO_APIC_IRQ(irq
))
1170 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1172 best_ioapic
= ioapic_idx
;
1177 * Use the first all-but-pin matching entry as a
1178 * best-guess fuzzy result for broken mptables.
1182 best_ioapic
= ioapic_idx
;
1189 return pin_2_irq(best_idx
, best_ioapic
, mp_irqs
[best_idx
].dstirq
,
1192 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1194 static struct irq_chip ioapic_chip
;
1196 #ifdef CONFIG_X86_32
1197 static inline int IO_APIC_irq_trigger(int irq
)
1201 for_each_ioapic_pin(apic
, pin
) {
1202 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1203 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
, 0)))
1204 return irq_trigger(idx
);
1207 * nonexistent IRQs are edge default
1212 static inline int IO_APIC_irq_trigger(int irq
)
1218 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1219 unsigned long trigger
)
1221 struct irq_chip
*chip
= &ioapic_chip
;
1222 irq_flow_handler_t hdl
;
1225 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1226 trigger
== IOAPIC_LEVEL
) {
1227 irq_set_status_flags(irq
, IRQ_LEVEL
);
1230 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1234 if (setup_remapped_irq(irq
, cfg
, chip
))
1235 fasteoi
= trigger
!= 0;
1237 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1238 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1239 fasteoi
? "fasteoi" : "edge");
1242 int native_setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1243 unsigned int destination
, int vector
,
1244 struct io_apic_irq_attr
*attr
)
1246 memset(entry
, 0, sizeof(*entry
));
1248 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1249 entry
->dest_mode
= apic
->irq_dest_mode
;
1250 entry
->dest
= destination
;
1251 entry
->vector
= vector
;
1252 entry
->mask
= 0; /* enable IRQ */
1253 entry
->trigger
= attr
->trigger
;
1254 entry
->polarity
= attr
->polarity
;
1257 * Mask level triggered irqs.
1258 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1266 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1267 struct io_apic_irq_attr
*attr
)
1269 struct IO_APIC_route_entry entry
;
1272 if (!IO_APIC_IRQ(irq
))
1275 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1278 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1280 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1281 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1282 clear_irq_vector(irq
, cfg
);
1287 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1288 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1289 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1290 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1291 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1293 if (x86_io_apic_ops
.setup_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1294 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1295 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1296 clear_irq_vector(irq
, cfg
);
1301 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1302 if (irq
< nr_legacy_irqs())
1303 legacy_pic
->mask(irq
);
1305 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1308 static void __init
setup_IO_APIC_irqs(void)
1310 unsigned int ioapic
, pin
;
1313 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1315 for_each_ioapic_pin(ioapic
, pin
) {
1316 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
1318 apic_printk(APIC_VERBOSE
,
1319 KERN_DEBUG
" apic %d pin %d not connected\n",
1320 mpc_ioapic_id(ioapic
), pin
);
1322 pin_2_irq(idx
, ioapic
, pin
,
1323 ioapic
? 0 : IOAPIC_MAP_ALLOC
);
1328 * Set up the timer pin, possibly with the 8259A-master behind.
1330 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1331 unsigned int pin
, int vector
)
1333 struct IO_APIC_route_entry entry
;
1336 memset(&entry
, 0, sizeof(entry
));
1339 * We use logical delivery to get the timer IRQ
1342 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1343 apic
->target_cpus(), &dest
)))
1346 entry
.dest_mode
= apic
->irq_dest_mode
;
1347 entry
.mask
= 0; /* don't mask IRQ for edge */
1349 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1352 entry
.vector
= vector
;
1355 * The timer IRQ doesn't have to know that behind the
1356 * scene we may have a 8259A-master in AEOI mode ...
1358 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1362 * Add it to the IO-APIC irq-routing table:
1364 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1367 void native_io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1371 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1373 for (i
= 0; i
<= nr_entries
; i
++) {
1374 struct IO_APIC_route_entry entry
;
1376 entry
= ioapic_read_entry(apic
, i
);
1378 pr_debug(" %02x %02X ", i
, entry
.dest
);
1379 pr_cont("%1d %1d %1d %1d %1d "
1385 entry
.delivery_status
,
1387 entry
.delivery_mode
,
1392 void intel_ir_io_apic_print_entries(unsigned int apic
,
1393 unsigned int nr_entries
)
1397 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1399 for (i
= 0; i
<= nr_entries
; i
++) {
1400 struct IR_IO_APIC_route_entry
*ir_entry
;
1401 struct IO_APIC_route_entry entry
;
1403 entry
= ioapic_read_entry(apic
, i
);
1405 ir_entry
= (struct IR_IO_APIC_route_entry
*)&entry
;
1407 pr_debug(" %02x %04X ", i
, ir_entry
->index
);
1408 pr_cont("%1d %1d %1d %1d %1d "
1409 "%1d %1d %X %02X\n",
1415 ir_entry
->delivery_status
,
1422 void ioapic_zap_locks(void)
1424 raw_spin_lock_init(&ioapic_lock
);
1427 static void io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1431 struct IO_APIC_route_entry entry
;
1432 struct IR_IO_APIC_route_entry
*ir_entry
= (void *)&entry
;
1434 printk(KERN_DEBUG
"IOAPIC %d:\n", apic
);
1435 for (i
= 0; i
<= nr_entries
; i
++) {
1436 entry
= ioapic_read_entry(apic
, i
);
1437 snprintf(buf
, sizeof(buf
),
1438 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1439 i
, entry
.mask
? "disabled" : "enabled ",
1440 entry
.trigger
? "level" : "edge ",
1441 entry
.polarity
? "low " : "high",
1442 entry
.vector
, entry
.irr
, entry
.delivery_status
);
1443 if (ir_entry
->format
)
1444 printk(KERN_DEBUG
"%s, remapped, I(%04X), Z(%X)\n",
1445 buf
, (ir_entry
->index
<< 15) | ir_entry
->index
,
1448 printk(KERN_DEBUG
"%s, %s, D(%02X), M(%1d)\n",
1449 buf
, entry
.dest_mode
? "logical " : "physical",
1450 entry
.dest
, entry
.delivery_mode
);
1454 static void __init
print_IO_APIC(int ioapic_idx
)
1456 union IO_APIC_reg_00 reg_00
;
1457 union IO_APIC_reg_01 reg_01
;
1458 union IO_APIC_reg_02 reg_02
;
1459 union IO_APIC_reg_03 reg_03
;
1460 unsigned long flags
;
1462 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1463 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1464 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1465 if (reg_01
.bits
.version
>= 0x10)
1466 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1467 if (reg_01
.bits
.version
>= 0x20)
1468 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1469 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1471 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1472 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1473 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1474 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1475 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1477 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1478 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1479 reg_01
.bits
.entries
);
1481 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1482 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1483 reg_01
.bits
.version
);
1486 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1487 * but the value of reg_02 is read as the previous read register
1488 * value, so ignore it if reg_02 == reg_01.
1490 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1491 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1492 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1496 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1497 * or reg_03, but the value of reg_0[23] is read as the previous read
1498 * register value, so ignore it if reg_03 == reg_0[12].
1500 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1501 reg_03
.raw
!= reg_01
.raw
) {
1502 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1503 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1506 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1507 io_apic_print_entries(ioapic_idx
, reg_01
.bits
.entries
);
1510 void __init
print_IO_APICs(void)
1513 struct irq_cfg
*cfg
;
1515 struct irq_chip
*chip
;
1517 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1518 for_each_ioapic(ioapic_idx
)
1519 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1520 mpc_ioapic_id(ioapic_idx
),
1521 ioapics
[ioapic_idx
].nr_registers
);
1524 * We are a bit conservative about what we expect. We have to
1525 * know about every hardware change ASAP.
1527 printk(KERN_INFO
"testing the IO APIC.......................\n");
1529 for_each_ioapic(ioapic_idx
)
1530 print_IO_APIC(ioapic_idx
);
1532 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1533 for_each_active_irq(irq
) {
1534 struct irq_pin_list
*entry
;
1536 chip
= irq_get_chip(irq
);
1537 if (chip
!= &ioapic_chip
)
1543 if (list_empty(&cfg
->irq_2_pin
))
1545 printk(KERN_DEBUG
"IRQ%d ", irq
);
1546 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1547 pr_cont("-> %d:%d", entry
->apic
, entry
->pin
);
1551 printk(KERN_INFO
".................................... done.\n");
1554 /* Where if anywhere is the i8259 connect in external int mode */
1555 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1557 void __init
enable_IO_APIC(void)
1559 int i8259_apic
, i8259_pin
;
1562 if (skip_ioapic_setup
)
1565 if (!nr_legacy_irqs() || !nr_ioapics
)
1568 for_each_ioapic_pin(apic
, pin
) {
1569 /* See if any of the pins is in ExtINT mode */
1570 struct IO_APIC_route_entry entry
= ioapic_read_entry(apic
, pin
);
1572 /* If the interrupt line is enabled and in ExtInt mode
1573 * I have found the pin where the i8259 is connected.
1575 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1576 ioapic_i8259
.apic
= apic
;
1577 ioapic_i8259
.pin
= pin
;
1582 /* Look to see what if the MP table has reported the ExtINT */
1583 /* If we could not find the appropriate pin by looking at the ioapic
1584 * the i8259 probably is not connected the ioapic but give the
1585 * mptable a chance anyway.
1587 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1588 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1589 /* Trust the MP table if nothing is setup in the hardware */
1590 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1591 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1592 ioapic_i8259
.pin
= i8259_pin
;
1593 ioapic_i8259
.apic
= i8259_apic
;
1595 /* Complain if the MP table and the hardware disagree */
1596 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1597 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1599 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1603 * Do not trust the IO-APIC being empty at bootup
1608 void native_disable_io_apic(void)
1611 * If the i8259 is routed through an IOAPIC
1612 * Put that IOAPIC in virtual wire mode
1613 * so legacy interrupts can be delivered.
1615 if (ioapic_i8259
.pin
!= -1) {
1616 struct IO_APIC_route_entry entry
;
1618 memset(&entry
, 0, sizeof(entry
));
1619 entry
.mask
= 0; /* Enabled */
1620 entry
.trigger
= 0; /* Edge */
1622 entry
.polarity
= 0; /* High */
1623 entry
.delivery_status
= 0;
1624 entry
.dest_mode
= 0; /* Physical */
1625 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1627 entry
.dest
= read_apic_id();
1630 * Add it to the IO-APIC irq-routing table:
1632 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1635 if (cpu_has_apic
|| apic_from_smp_config())
1636 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1641 * Not an __init, needed by the reboot code
1643 void disable_IO_APIC(void)
1646 * Clear the IO-APIC before rebooting:
1650 if (!nr_legacy_irqs())
1653 x86_io_apic_ops
.disable();
1656 #ifdef CONFIG_X86_32
1658 * function to set the IO-APIC physical IDs based on the
1659 * values stored in the MPC table.
1661 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1663 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1665 union IO_APIC_reg_00 reg_00
;
1666 physid_mask_t phys_id_present_map
;
1669 unsigned char old_id
;
1670 unsigned long flags
;
1673 * This is broken; anything with a real cpu count has to
1674 * circumvent this idiocy regardless.
1676 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1679 * Set the IOAPIC ID to the value stored in the MPC table.
1681 for_each_ioapic(ioapic_idx
) {
1682 /* Read the register 0 value */
1683 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1684 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1685 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1687 old_id
= mpc_ioapic_id(ioapic_idx
);
1689 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
1690 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1691 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1692 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1694 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
1698 * Sanity check, is the ID really free? Every APIC in a
1699 * system must have a unique ID or we get lots of nice
1700 * 'stuck on smp_invalidate_needed IPI wait' messages.
1702 if (apic
->check_apicid_used(&phys_id_present_map
,
1703 mpc_ioapic_id(ioapic_idx
))) {
1704 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1705 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1706 for (i
= 0; i
< get_physical_broadcast(); i
++)
1707 if (!physid_isset(i
, phys_id_present_map
))
1709 if (i
>= get_physical_broadcast())
1710 panic("Max APIC ID exceeded!\n");
1711 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1713 physid_set(i
, phys_id_present_map
);
1714 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
1717 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
1719 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1720 "phys_id_present_map\n",
1721 mpc_ioapic_id(ioapic_idx
));
1722 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1726 * We need to adjust the IRQ routing table
1727 * if the ID changed.
1729 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
1730 for (i
= 0; i
< mp_irq_entries
; i
++)
1731 if (mp_irqs
[i
].dstapic
== old_id
)
1733 = mpc_ioapic_id(ioapic_idx
);
1736 * Update the ID register according to the right value
1737 * from the MPC table if they are different.
1739 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
1742 apic_printk(APIC_VERBOSE
, KERN_INFO
1743 "...changing IO-APIC physical APIC ID to %d ...",
1744 mpc_ioapic_id(ioapic_idx
));
1746 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
1747 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1748 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
1749 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1754 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1755 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1756 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1757 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
1758 pr_cont("could not set ID!\n");
1760 apic_printk(APIC_VERBOSE
, " ok.\n");
1764 void __init
setup_ioapic_ids_from_mpc(void)
1770 * Don't check I/O APIC IDs for xAPIC systems. They have
1771 * no meaning without the serial APIC bus.
1773 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1774 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1776 setup_ioapic_ids_from_mpc_nocheck();
1780 int no_timer_check __initdata
;
1782 static int __init
notimercheck(char *s
)
1787 __setup("no_timer_check", notimercheck
);
1790 * There is a nasty bug in some older SMP boards, their mptable lies
1791 * about the timer IRQ. We do the following to work around the situation:
1793 * - timer IRQ defaults to IO-APIC IRQ
1794 * - if this function detects that timer IRQs are defunct, then we fall
1795 * back to ISA timer IRQs
1797 static int __init
timer_irq_works(void)
1799 unsigned long t1
= jiffies
;
1800 unsigned long flags
;
1805 local_save_flags(flags
);
1807 /* Let ten ticks pass... */
1808 mdelay((10 * 1000) / HZ
);
1809 local_irq_restore(flags
);
1812 * Expect a few ticks at least, to be sure some possible
1813 * glue logic does not lock up after one or two first
1814 * ticks in a non-ExtINT mode. Also the local APIC
1815 * might have cached one ExtINT interrupt. Finally, at
1816 * least one tick may be lost due to delays.
1820 if (time_after(jiffies
, t1
+ 4))
1826 * In the SMP+IOAPIC case it might happen that there are an unspecified
1827 * number of pending IRQ events unhandled. These cases are very rare,
1828 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1829 * better to do it this way as thus we do not have to be aware of
1830 * 'pending' interrupts in the IRQ path, except at this point.
1833 * Edge triggered needs to resend any interrupt
1834 * that was delayed but this is now handled in the device
1839 * Starting up a edge-triggered IO-APIC interrupt is
1840 * nasty - we need to make sure that we get the edge.
1841 * If it is already asserted for some reason, we need
1842 * return 1 to indicate that is was pending.
1844 * This is not complete - we should be able to fake
1845 * an edge even if it isn't on the 8259A...
1848 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
1850 int was_pending
= 0, irq
= data
->irq
;
1851 unsigned long flags
;
1853 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1854 if (irq
< nr_legacy_irqs()) {
1855 legacy_pic
->mask(irq
);
1856 if (legacy_pic
->irq_pending(irq
))
1859 __unmask_ioapic(irqd_cfg(data
));
1860 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1866 * Level and edge triggered IO-APIC interrupts need different handling,
1867 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1868 * handled with the level-triggered descriptor, but that one has slightly
1869 * more overhead. Level-triggered interrupts cannot be handled with the
1870 * edge-triggered handler, without risking IRQ storms and other ugly
1874 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
1877 struct irq_pin_list
*entry
;
1878 u8 vector
= cfg
->vector
;
1880 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
1886 io_apic_write(apic
, 0x11 + pin
*2, dest
);
1887 reg
= io_apic_read(apic
, 0x10 + pin
*2);
1888 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
1890 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
1894 int native_ioapic_set_affinity(struct irq_data
*data
,
1895 const struct cpumask
*mask
,
1898 unsigned int dest
, irq
= data
->irq
;
1899 unsigned long flags
;
1902 if (!config_enabled(CONFIG_SMP
))
1905 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1906 ret
= apic_set_affinity(data
, mask
, &dest
);
1908 /* Only the high 8 bits are valid. */
1909 dest
= SET_APIC_LOGICAL_ID(dest
);
1910 __target_IO_APIC_irq(irq
, dest
, irqd_cfg(data
));
1911 ret
= IRQ_SET_MASK_OK_NOCOPY
;
1913 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1917 atomic_t irq_mis_count
;
1919 #ifdef CONFIG_GENERIC_PENDING_IRQ
1920 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
1922 struct irq_pin_list
*entry
;
1923 unsigned long flags
;
1925 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1926 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
1931 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
1932 /* Is the remote IRR bit set? */
1933 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
1934 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1938 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1943 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
1945 /* If we are moving the irq we need to mask it */
1946 if (unlikely(irqd_is_setaffinity_pending(data
))) {
1953 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
1954 struct irq_cfg
*cfg
, bool masked
)
1956 if (unlikely(masked
)) {
1957 /* Only migrate the irq if the ack has been received.
1959 * On rare occasions the broadcast level triggered ack gets
1960 * delayed going to ioapics, and if we reprogram the
1961 * vector while Remote IRR is still set the irq will never
1964 * To prevent this scenario we read the Remote IRR bit
1965 * of the ioapic. This has two effects.
1966 * - On any sane system the read of the ioapic will
1967 * flush writes (and acks) going to the ioapic from
1969 * - We get to see if the ACK has actually been delivered.
1971 * Based on failed experiments of reprogramming the
1972 * ioapic entry from outside of irq context starting
1973 * with masking the ioapic entry and then polling until
1974 * Remote IRR was clear before reprogramming the
1975 * ioapic I don't trust the Remote IRR bit to be
1976 * completey accurate.
1978 * However there appears to be no other way to plug
1979 * this race, so if the Remote IRR bit is not
1980 * accurate and is causing problems then it is a hardware bug
1981 * and you can go talk to the chipset vendor about it.
1983 if (!io_apic_level_ack_pending(cfg
))
1984 irq_move_masked_irq(data
);
1989 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
1993 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
1994 struct irq_cfg
*cfg
, bool masked
)
1999 static void ack_ioapic_level(struct irq_data
*data
)
2001 struct irq_cfg
*cfg
= irqd_cfg(data
);
2002 int i
, irq
= data
->irq
;
2006 irq_complete_move(cfg
);
2007 masked
= ioapic_irqd_mask(data
, cfg
);
2010 * It appears there is an erratum which affects at least version 0x11
2011 * of I/O APIC (that's the 82093AA and cores integrated into various
2012 * chipsets). Under certain conditions a level-triggered interrupt is
2013 * erroneously delivered as edge-triggered one but the respective IRR
2014 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2015 * message but it will never arrive and further interrupts are blocked
2016 * from the source. The exact reason is so far unknown, but the
2017 * phenomenon was observed when two consecutive interrupt requests
2018 * from a given source get delivered to the same CPU and the source is
2019 * temporarily disabled in between.
2021 * A workaround is to simulate an EOI message manually. We achieve it
2022 * by setting the trigger mode to edge and then to level when the edge
2023 * trigger mode gets detected in the TMR of a local APIC for a
2024 * level-triggered interrupt. We mask the source for the time of the
2025 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2026 * The idea is from Manfred Spraul. --macro
2028 * Also in the case when cpu goes offline, fixup_irqs() will forward
2029 * any unhandled interrupt on the offlined cpu to the new cpu
2030 * destination that is handling the corresponding interrupt. This
2031 * interrupt forwarding is done via IPI's. Hence, in this case also
2032 * level-triggered io-apic interrupt will be seen as an edge
2033 * interrupt in the IRR. And we can't rely on the cpu's EOI
2034 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2035 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2036 * supporting EOI register, we do an explicit EOI to clear the
2037 * remote IRR and on IO-APIC's which don't have an EOI register,
2038 * we use the above logic (mask+edge followed by unmask+level) from
2039 * Manfred Spraul to clear the remote IRR.
2042 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2045 * We must acknowledge the irq before we move it or the acknowledge will
2046 * not propagate properly.
2051 * Tail end of clearing remote IRR bit (either by delivering the EOI
2052 * message via io-apic EOI register write or simulating it using
2053 * mask+edge followed by unnask+level logic) manually when the
2054 * level triggered interrupt is seen as the edge triggered interrupt
2057 if (!(v
& (1 << (i
& 0x1f)))) {
2058 atomic_inc(&irq_mis_count
);
2060 eoi_ioapic_irq(irq
, cfg
);
2063 ioapic_irqd_unmask(data
, cfg
, masked
);
2066 static struct irq_chip ioapic_chip __read_mostly
= {
2068 .irq_startup
= startup_ioapic_irq
,
2069 .irq_mask
= mask_ioapic_irq
,
2070 .irq_unmask
= unmask_ioapic_irq
,
2071 .irq_ack
= apic_ack_edge
,
2072 .irq_eoi
= ack_ioapic_level
,
2073 .irq_set_affinity
= native_ioapic_set_affinity
,
2074 .irq_retrigger
= apic_retrigger_irq
,
2075 .flags
= IRQCHIP_SKIP_SET_WAKE
,
2078 static inline void init_IO_APIC_traps(void)
2080 struct irq_cfg
*cfg
;
2083 for_each_active_irq(irq
) {
2085 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2087 * Hmm.. We don't have an entry for this,
2088 * so default to an old-fashioned 8259
2089 * interrupt if we can..
2091 if (irq
< nr_legacy_irqs())
2092 legacy_pic
->make_irq(irq
);
2094 /* Strange. Oh, well.. */
2095 irq_set_chip(irq
, &no_irq_chip
);
2101 * The local APIC irq-chip implementation:
2104 static void mask_lapic_irq(struct irq_data
*data
)
2108 v
= apic_read(APIC_LVT0
);
2109 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2112 static void unmask_lapic_irq(struct irq_data
*data
)
2116 v
= apic_read(APIC_LVT0
);
2117 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2120 static void ack_lapic_irq(struct irq_data
*data
)
2125 static struct irq_chip lapic_chip __read_mostly
= {
2126 .name
= "local-APIC",
2127 .irq_mask
= mask_lapic_irq
,
2128 .irq_unmask
= unmask_lapic_irq
,
2129 .irq_ack
= ack_lapic_irq
,
2132 static void lapic_register_intr(int irq
)
2134 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2135 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2140 * This looks a bit hackish but it's about the only one way of sending
2141 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2142 * not support the ExtINT mode, unfortunately. We need to send these
2143 * cycles as some i82489DX-based boards have glue logic that keeps the
2144 * 8259A interrupt line asserted until INTA. --macro
2146 static inline void __init
unlock_ExtINT_logic(void)
2149 struct IO_APIC_route_entry entry0
, entry1
;
2150 unsigned char save_control
, save_freq_select
;
2152 pin
= find_isa_irq_pin(8, mp_INT
);
2157 apic
= find_isa_irq_apic(8, mp_INT
);
2163 entry0
= ioapic_read_entry(apic
, pin
);
2164 clear_IO_APIC_pin(apic
, pin
);
2166 memset(&entry1
, 0, sizeof(entry1
));
2168 entry1
.dest_mode
= 0; /* physical delivery */
2169 entry1
.mask
= 0; /* unmask IRQ now */
2170 entry1
.dest
= hard_smp_processor_id();
2171 entry1
.delivery_mode
= dest_ExtINT
;
2172 entry1
.polarity
= entry0
.polarity
;
2176 ioapic_write_entry(apic
, pin
, entry1
);
2178 save_control
= CMOS_READ(RTC_CONTROL
);
2179 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2180 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2182 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2187 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2191 CMOS_WRITE(save_control
, RTC_CONTROL
);
2192 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2193 clear_IO_APIC_pin(apic
, pin
);
2195 ioapic_write_entry(apic
, pin
, entry0
);
2198 static int disable_timer_pin_1 __initdata
;
2199 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2200 static int __init
disable_timer_pin_setup(char *arg
)
2202 disable_timer_pin_1
= 1;
2205 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2208 * This code may look a bit paranoid, but it's supposed to cooperate with
2209 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2210 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2211 * fanatically on his truly buggy board.
2213 * FIXME: really need to revamp this for all platforms.
2215 static inline void __init
check_timer(void)
2217 struct irq_cfg
*cfg
= irq_cfg(0);
2218 int node
= cpu_to_node(0);
2219 int apic1
, pin1
, apic2
, pin2
;
2220 unsigned long flags
;
2223 local_irq_save(flags
);
2226 * get/set the timer IRQ vector:
2228 legacy_pic
->mask(0);
2229 assign_irq_vector(0, cfg
, apic
->target_cpus());
2232 * As IRQ0 is to be enabled in the 8259A, the virtual
2233 * wire has to be disabled in the local APIC. Also
2234 * timer interrupts need to be acknowledged manually in
2235 * the 8259A for the i82489DX when using the NMI
2236 * watchdog as that APIC treats NMIs as level-triggered.
2237 * The AEOI mode will finish them in the 8259A
2240 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2241 legacy_pic
->init(1);
2243 pin1
= find_isa_irq_pin(0, mp_INT
);
2244 apic1
= find_isa_irq_apic(0, mp_INT
);
2245 pin2
= ioapic_i8259
.pin
;
2246 apic2
= ioapic_i8259
.apic
;
2248 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2249 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2250 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2253 * Some BIOS writers are clueless and report the ExtINTA
2254 * I/O APIC input from the cascaded 8259A as the timer
2255 * interrupt input. So just in case, if only one pin
2256 * was found above, try it both directly and through the
2260 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2264 } else if (pin2
== -1) {
2271 * Ok, does IRQ0 through the IOAPIC work?
2274 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2275 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2277 /* for edge trigger, setup_ioapic_irq already
2278 * leave it unmasked.
2279 * so only need to unmask if it is level-trigger
2280 * do we really have level trigger timer?
2283 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2284 if (idx
!= -1 && irq_trigger(idx
))
2287 if (timer_irq_works()) {
2288 if (disable_timer_pin_1
> 0)
2289 clear_IO_APIC_pin(0, pin1
);
2292 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2293 local_irq_disable();
2294 clear_IO_APIC_pin(apic1
, pin1
);
2296 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2297 "8254 timer not connected to IO-APIC\n");
2299 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2300 "(IRQ0) through the 8259A ...\n");
2301 apic_printk(APIC_QUIET
, KERN_INFO
2302 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2304 * legacy devices should be connected to IO APIC #0
2306 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2307 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2308 legacy_pic
->unmask(0);
2309 if (timer_irq_works()) {
2310 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2314 * Cleanup, just in case ...
2316 local_irq_disable();
2317 legacy_pic
->mask(0);
2318 clear_IO_APIC_pin(apic2
, pin2
);
2319 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2322 apic_printk(APIC_QUIET
, KERN_INFO
2323 "...trying to set up timer as Virtual Wire IRQ...\n");
2325 lapic_register_intr(0);
2326 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2327 legacy_pic
->unmask(0);
2329 if (timer_irq_works()) {
2330 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2333 local_irq_disable();
2334 legacy_pic
->mask(0);
2335 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2336 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2338 apic_printk(APIC_QUIET
, KERN_INFO
2339 "...trying to set up timer as ExtINT IRQ...\n");
2341 legacy_pic
->init(0);
2342 legacy_pic
->make_irq(0);
2343 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2345 unlock_ExtINT_logic();
2347 if (timer_irq_works()) {
2348 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2351 local_irq_disable();
2352 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2353 if (apic_is_x2apic_enabled())
2354 apic_printk(APIC_QUIET
, KERN_INFO
2355 "Perhaps problem with the pre-enabled x2apic mode\n"
2356 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2357 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2358 "report. Then try booting with the 'noapic' option.\n");
2360 local_irq_restore(flags
);
2364 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2365 * to devices. However there may be an I/O APIC pin available for
2366 * this interrupt regardless. The pin may be left unconnected, but
2367 * typically it will be reused as an ExtINT cascade interrupt for
2368 * the master 8259A. In the MPS case such a pin will normally be
2369 * reported as an ExtINT interrupt in the MP table. With ACPI
2370 * there is no provision for ExtINT interrupts, and in the absence
2371 * of an override it would be treated as an ordinary ISA I/O APIC
2372 * interrupt, that is edge-triggered and unmasked by default. We
2373 * used to do this, but it caused problems on some systems because
2374 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2375 * the same ExtINT cascade interrupt to drive the local APIC of the
2376 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2377 * the I/O APIC in all cases now. No actual device should request
2378 * it anyway. --macro
2380 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2382 static int mp_irqdomain_create(int ioapic
)
2385 int hwirqs
= mp_ioapic_pin_count(ioapic
);
2386 struct ioapic
*ip
= &ioapics
[ioapic
];
2387 struct ioapic_domain_cfg
*cfg
= &ip
->irqdomain_cfg
;
2388 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2390 size
= sizeof(struct mp_pin_info
) * mp_ioapic_pin_count(ioapic
);
2391 ip
->pin_info
= kzalloc(size
, GFP_KERNEL
);
2395 if (cfg
->type
== IOAPIC_DOMAIN_INVALID
)
2398 ip
->irqdomain
= irq_domain_add_linear(cfg
->dev
, hwirqs
, cfg
->ops
,
2399 (void *)(long)ioapic
);
2400 if(!ip
->irqdomain
) {
2401 kfree(ip
->pin_info
);
2402 ip
->pin_info
= NULL
;
2406 if (cfg
->type
== IOAPIC_DOMAIN_LEGACY
||
2407 cfg
->type
== IOAPIC_DOMAIN_STRICT
)
2408 ioapic_dynirq_base
= max(ioapic_dynirq_base
,
2409 gsi_cfg
->gsi_end
+ 1);
2414 static void ioapic_destroy_irqdomain(int idx
)
2416 if (ioapics
[idx
].irqdomain
) {
2417 irq_domain_remove(ioapics
[idx
].irqdomain
);
2418 ioapics
[idx
].irqdomain
= NULL
;
2420 kfree(ioapics
[idx
].pin_info
);
2421 ioapics
[idx
].pin_info
= NULL
;
2424 void __init
setup_IO_APIC(void)
2428 if (skip_ioapic_setup
|| !nr_ioapics
)
2431 io_apic_irqs
= nr_legacy_irqs() ? ~PIC_IRQS
: ~0UL;
2433 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2434 for_each_ioapic(ioapic
)
2435 BUG_ON(mp_irqdomain_create(ioapic
));
2438 * Set up IO-APIC IRQ routing.
2440 x86_init
.mpparse
.setup_ioapic_ids();
2443 setup_IO_APIC_irqs();
2444 init_IO_APIC_traps();
2445 if (nr_legacy_irqs())
2448 ioapic_initialized
= 1;
2452 * Called after all the initialization is done. If we didn't find any
2453 * APIC bugs then we can allow the modify fast path
2456 static int __init
io_apic_bug_finalize(void)
2458 if (sis_apic_bug
== -1)
2463 late_initcall(io_apic_bug_finalize
);
2465 static void resume_ioapic_id(int ioapic_idx
)
2467 unsigned long flags
;
2468 union IO_APIC_reg_00 reg_00
;
2470 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2471 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2472 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
2473 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2474 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2476 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2479 static void ioapic_resume(void)
2483 for_each_ioapic_reverse(ioapic_idx
)
2484 resume_ioapic_id(ioapic_idx
);
2486 restore_ioapic_entries();
2489 static struct syscore_ops ioapic_syscore_ops
= {
2490 .suspend
= save_ioapic_entries
,
2491 .resume
= ioapic_resume
,
2494 static int __init
ioapic_init_ops(void)
2496 register_syscore_ops(&ioapic_syscore_ops
);
2501 device_initcall(ioapic_init_ops
);
2504 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
2506 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
2511 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
2513 setup_ioapic_irq(irq
, cfg
, attr
);
2517 static int io_apic_get_redir_entries(int ioapic
)
2519 union IO_APIC_reg_01 reg_01
;
2520 unsigned long flags
;
2522 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2523 reg_01
.raw
= io_apic_read(ioapic
, 1);
2524 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2526 /* The register returns the maximum index redir index
2527 * supported, which is one less than the total number of redir
2530 return reg_01
.bits
.entries
+ 1;
2533 unsigned int arch_dynirq_lower_bound(unsigned int from
)
2536 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2537 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2539 return ioapic_initialized
? ioapic_dynirq_base
: gsi_top
;
2542 #ifdef CONFIG_X86_32
2543 static int io_apic_get_unique_id(int ioapic
, int apic_id
)
2545 union IO_APIC_reg_00 reg_00
;
2546 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2548 unsigned long flags
;
2552 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2553 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2554 * supports up to 16 on one shared APIC bus.
2556 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2557 * advantage of new APIC bus architecture.
2560 if (physids_empty(apic_id_map
))
2561 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
2563 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2564 reg_00
.raw
= io_apic_read(ioapic
, 0);
2565 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2567 if (apic_id
>= get_physical_broadcast()) {
2568 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2569 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2570 apic_id
= reg_00
.bits
.ID
;
2574 * Every APIC in a system must have a unique ID or we get lots of nice
2575 * 'stuck on smp_invalidate_needed IPI wait' messages.
2577 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
2579 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2580 if (!apic
->check_apicid_used(&apic_id_map
, i
))
2584 if (i
== get_physical_broadcast())
2585 panic("Max apic_id exceeded!\n");
2587 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2588 "trying %d\n", ioapic
, apic_id
, i
);
2593 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
2594 physids_or(apic_id_map
, apic_id_map
, tmp
);
2596 if (reg_00
.bits
.ID
!= apic_id
) {
2597 reg_00
.bits
.ID
= apic_id
;
2599 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2600 io_apic_write(ioapic
, 0, reg_00
.raw
);
2601 reg_00
.raw
= io_apic_read(ioapic
, 0);
2602 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2605 if (reg_00
.bits
.ID
!= apic_id
) {
2606 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2612 apic_printk(APIC_VERBOSE
, KERN_INFO
2613 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2618 static u8
io_apic_unique_id(int idx
, u8 id
)
2620 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
2621 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2622 return io_apic_get_unique_id(idx
, id
);
2627 static u8
io_apic_unique_id(int idx
, u8 id
)
2629 union IO_APIC_reg_00 reg_00
;
2630 DECLARE_BITMAP(used
, 256);
2631 unsigned long flags
;
2635 bitmap_zero(used
, 256);
2637 __set_bit(mpc_ioapic_id(i
), used
);
2639 /* Hand out the requested id if available */
2640 if (!test_bit(id
, used
))
2644 * Read the current id from the ioapic and keep it if
2647 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2648 reg_00
.raw
= io_apic_read(idx
, 0);
2649 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2650 new_id
= reg_00
.bits
.ID
;
2651 if (!test_bit(new_id
, used
)) {
2652 apic_printk(APIC_VERBOSE
, KERN_INFO
2653 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2659 * Get the next free id and write it to the ioapic.
2661 new_id
= find_first_zero_bit(used
, 256);
2662 reg_00
.bits
.ID
= new_id
;
2663 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2664 io_apic_write(idx
, 0, reg_00
.raw
);
2665 reg_00
.raw
= io_apic_read(idx
, 0);
2666 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2668 BUG_ON(reg_00
.bits
.ID
!= new_id
);
2674 static int io_apic_get_version(int ioapic
)
2676 union IO_APIC_reg_01 reg_01
;
2677 unsigned long flags
;
2679 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2680 reg_01
.raw
= io_apic_read(ioapic
, 1);
2681 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2683 return reg_01
.bits
.version
;
2686 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
2688 int ioapic
, pin
, idx
;
2690 if (skip_ioapic_setup
)
2693 ioapic
= mp_find_ioapic(gsi
);
2697 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
2701 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
2705 *trigger
= irq_trigger(idx
);
2706 *polarity
= irq_polarity(idx
);
2711 * This function currently is only a helper for the i386 smp boot process where
2712 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2713 * so mask in all cases should simply be apic->target_cpus()
2716 void __init
setup_ioapic_dest(void)
2718 int pin
, ioapic
, irq
, irq_entry
;
2719 const struct cpumask
*mask
;
2720 struct irq_data
*idata
;
2722 if (skip_ioapic_setup
== 1)
2725 for_each_ioapic_pin(ioapic
, pin
) {
2726 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2727 if (irq_entry
== -1)
2730 irq
= pin_2_irq(irq_entry
, ioapic
, pin
, 0);
2731 if (irq
< 0 || !mp_init_irq_at_boot(ioapic
, irq
))
2734 idata
= irq_get_irq_data(irq
);
2737 * Honour affinities which have been set in early boot
2739 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
2740 mask
= idata
->affinity
;
2742 mask
= apic
->target_cpus();
2744 x86_io_apic_ops
.set_affinity(idata
, mask
, false);
2750 #define IOAPIC_RESOURCE_NAME_SIZE 11
2752 static struct resource
*ioapic_resources
;
2754 static struct resource
* __init
ioapic_setup_resources(void)
2757 struct resource
*res
;
2766 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
2769 mem
= alloc_bootmem(n
);
2772 mem
+= sizeof(struct resource
) * num
;
2775 for_each_ioapic(i
) {
2776 res
[num
].name
= mem
;
2777 res
[num
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
2778 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
2779 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
2781 ioapics
[i
].iomem_res
= res
;
2784 ioapic_resources
= res
;
2789 void __init
native_io_apic_init_mappings(void)
2791 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2792 struct resource
*ioapic_res
;
2795 ioapic_res
= ioapic_setup_resources();
2796 for_each_ioapic(i
) {
2797 if (smp_found_config
) {
2798 ioapic_phys
= mpc_ioapic_addr(i
);
2799 #ifdef CONFIG_X86_32
2802 "WARNING: bogus zero IO-APIC "
2803 "address found in MPTABLE, "
2804 "disabling IO/APIC support!\n");
2805 smp_found_config
= 0;
2806 skip_ioapic_setup
= 1;
2807 goto fake_ioapic_page
;
2811 #ifdef CONFIG_X86_32
2814 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
2815 ioapic_phys
= __pa(ioapic_phys
);
2817 set_fixmap_nocache(idx
, ioapic_phys
);
2818 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
2819 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
2823 ioapic_res
->start
= ioapic_phys
;
2824 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
2829 void __init
ioapic_insert_resources(void)
2832 struct resource
*r
= ioapic_resources
;
2837 "IO APIC resources couldn't be allocated.\n");
2841 for_each_ioapic(i
) {
2842 insert_resource(&iomem_resource
, r
);
2847 int mp_find_ioapic(u32 gsi
)
2851 if (nr_ioapics
== 0)
2854 /* Find the IOAPIC that manages this GSI. */
2855 for_each_ioapic(i
) {
2856 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
2857 if (gsi
>= gsi_cfg
->gsi_base
&& gsi
<= gsi_cfg
->gsi_end
)
2861 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
2865 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
2867 struct mp_ioapic_gsi
*gsi_cfg
;
2869 if (WARN_ON(ioapic
< 0))
2872 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2873 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
2876 return gsi
- gsi_cfg
->gsi_base
;
2879 static int bad_ioapic_register(int idx
)
2881 union IO_APIC_reg_00 reg_00
;
2882 union IO_APIC_reg_01 reg_01
;
2883 union IO_APIC_reg_02 reg_02
;
2885 reg_00
.raw
= io_apic_read(idx
, 0);
2886 reg_01
.raw
= io_apic_read(idx
, 1);
2887 reg_02
.raw
= io_apic_read(idx
, 2);
2889 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
2890 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2891 mpc_ioapic_addr(idx
));
2898 static int find_free_ioapic_entry(void)
2902 for (idx
= 0; idx
< MAX_IO_APICS
; idx
++)
2903 if (ioapics
[idx
].nr_registers
== 0)
2906 return MAX_IO_APICS
;
2910 * mp_register_ioapic - Register an IOAPIC device
2911 * @id: hardware IOAPIC ID
2912 * @address: physical address of IOAPIC register area
2913 * @gsi_base: base of GSI associated with the IOAPIC
2914 * @cfg: configuration information for the IOAPIC
2916 int mp_register_ioapic(int id
, u32 address
, u32 gsi_base
,
2917 struct ioapic_domain_cfg
*cfg
)
2919 bool hotplug
= !!ioapic_initialized
;
2920 struct mp_ioapic_gsi
*gsi_cfg
;
2921 int idx
, ioapic
, entries
;
2925 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2928 for_each_ioapic(ioapic
)
2929 if (ioapics
[ioapic
].mp_config
.apicaddr
== address
) {
2930 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2935 idx
= find_free_ioapic_entry();
2936 if (idx
>= MAX_IO_APICS
) {
2937 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2942 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
2943 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
2944 ioapics
[idx
].mp_config
.apicaddr
= address
;
2946 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
2947 if (bad_ioapic_register(idx
)) {
2948 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2952 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(idx
, id
);
2953 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
2956 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2957 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2959 entries
= io_apic_get_redir_entries(idx
);
2960 gsi_end
= gsi_base
+ entries
- 1;
2961 for_each_ioapic(ioapic
) {
2962 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
2963 if ((gsi_base
>= gsi_cfg
->gsi_base
&&
2964 gsi_base
<= gsi_cfg
->gsi_end
) ||
2965 (gsi_end
>= gsi_cfg
->gsi_base
&&
2966 gsi_end
<= gsi_cfg
->gsi_end
)) {
2967 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2969 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
2970 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2974 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
2975 gsi_cfg
->gsi_base
= gsi_base
;
2976 gsi_cfg
->gsi_end
= gsi_end
;
2978 ioapics
[idx
].irqdomain
= NULL
;
2979 ioapics
[idx
].irqdomain_cfg
= *cfg
;
2982 * If mp_register_ioapic() is called during early boot stage when
2983 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2984 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2987 if (mp_irqdomain_create(idx
)) {
2988 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
2991 alloc_ioapic_saved_registers(idx
);
2994 if (gsi_cfg
->gsi_end
>= gsi_top
)
2995 gsi_top
= gsi_cfg
->gsi_end
+ 1;
2996 if (nr_ioapics
<= idx
)
2997 nr_ioapics
= idx
+ 1;
2999 /* Set nr_registers to mark entry present */
3000 ioapics
[idx
].nr_registers
= entries
;
3002 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3003 idx
, mpc_ioapic_id(idx
),
3004 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
3005 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3010 int mp_unregister_ioapic(u32 gsi_base
)
3014 struct mp_pin_info
*pin_info
;
3016 for_each_ioapic(ioapic
)
3017 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
) {
3022 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base
);
3026 for_each_pin(ioapic
, pin
) {
3027 pin_info
= mp_pin_info(ioapic
, pin
);
3028 if (pin_info
->count
) {
3029 pr_warn("pin%d on IOAPIC%d is still in use.\n",
3035 /* Mark entry not present */
3036 ioapics
[ioapic
].nr_registers
= 0;
3037 ioapic_destroy_irqdomain(ioapic
);
3038 free_ioapic_saved_registers(ioapic
);
3039 if (ioapics
[ioapic
].iomem_res
)
3040 release_resource(ioapics
[ioapic
].iomem_res
);
3041 clear_fixmap(FIX_IO_APIC_BASE_0
+ ioapic
);
3042 memset(&ioapics
[ioapic
], 0, sizeof(ioapics
[ioapic
]));
3047 int mp_ioapic_registered(u32 gsi_base
)
3051 for_each_ioapic(ioapic
)
3052 if (ioapics
[ioapic
].gsi_config
.gsi_base
== gsi_base
)
3058 static inline void set_io_apic_irq_attr(struct io_apic_irq_attr
*irq_attr
,
3059 int ioapic
, int ioapic_pin
,
3060 int trigger
, int polarity
)
3062 irq_attr
->ioapic
= ioapic
;
3063 irq_attr
->ioapic_pin
= ioapic_pin
;
3064 irq_attr
->trigger
= trigger
;
3065 irq_attr
->polarity
= polarity
;
3068 int mp_irqdomain_map(struct irq_domain
*domain
, unsigned int virq
,
3069 irq_hw_number_t hwirq
)
3071 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
3072 struct mp_pin_info
*info
= mp_pin_info(ioapic
, hwirq
);
3073 struct io_apic_irq_attr attr
;
3075 /* Get default attribute if not set by caller yet */
3077 u32 gsi
= mp_pin_to_gsi(ioapic
, hwirq
);
3079 if (acpi_get_override_irq(gsi
, &info
->trigger
,
3080 &info
->polarity
) < 0) {
3082 * PCI interrupts are always polarity one level
3088 info
->node
= NUMA_NO_NODE
;
3091 * setup_IO_APIC_irqs() programs all legacy IRQs with default
3092 * trigger and polarity attributes. Don't set the flag for that
3093 * case so the first legacy IRQ user could reprogram the pin
3094 * with real trigger and polarity attributes.
3096 if (virq
>= nr_legacy_irqs() || info
->count
)
3099 set_io_apic_irq_attr(&attr
, ioapic
, hwirq
, info
->trigger
,
3102 return io_apic_setup_irq_pin(virq
, info
->node
, &attr
);
3105 void mp_irqdomain_unmap(struct irq_domain
*domain
, unsigned int virq
)
3107 struct irq_data
*data
= irq_get_irq_data(virq
);
3108 struct irq_cfg
*cfg
= irq_cfg(virq
);
3109 int ioapic
= mp_irqdomain_ioapic_idx(domain
);
3110 int pin
= (int)data
->hwirq
;
3112 ioapic_mask_entry(ioapic
, pin
);
3113 __remove_pin_from_irq(cfg
, ioapic
, pin
);
3114 WARN_ON(!list_empty(&cfg
->irq_2_pin
));
3115 arch_teardown_hwirq(virq
);
3118 static void mp_irqdomain_get_attr(u32 gsi
, struct mp_chip_data
*data
,
3119 struct irq_alloc_info
*info
)
3121 if (info
&& info
->ioapic_valid
) {
3122 data
->trigger
= info
->ioapic_trigger
;
3123 data
->polarity
= info
->ioapic_polarity
;
3124 } else if (acpi_get_override_irq(gsi
, &data
->trigger
,
3125 &data
->polarity
) < 0) {
3126 /* PCI interrupts are always polarity one level triggered. */
3132 static void mp_setup_entry(struct irq_cfg
*cfg
, struct mp_chip_data
*data
,
3133 struct IO_APIC_route_entry
*entry
)
3135 memset(entry
, 0, sizeof(*entry
));
3136 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3137 entry
->dest_mode
= apic
->irq_dest_mode
;
3138 entry
->dest
= cfg
->dest_apicid
;
3139 entry
->vector
= cfg
->vector
;
3140 entry
->mask
= 0; /* enable IRQ */
3141 entry
->trigger
= data
->trigger
;
3142 entry
->polarity
= data
->polarity
;
3144 * Mask level triggered irqs.
3145 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
3151 int mp_irqdomain_alloc(struct irq_domain
*domain
, unsigned int virq
,
3152 unsigned int nr_irqs
, void *arg
)
3154 int ret
, ioapic
, pin
;
3155 struct irq_cfg
*cfg
;
3156 struct irq_data
*irq_data
;
3157 struct mp_chip_data
*data
;
3158 struct irq_alloc_info
*info
= arg
;
3160 if (!info
|| nr_irqs
> 1)
3162 irq_data
= irq_domain_get_irq_data(domain
, virq
);
3166 ioapic
= mp_irqdomain_ioapic_idx(domain
);
3167 pin
= info
->ioapic_pin
;
3168 if (irq_find_mapping(domain
, (irq_hw_number_t
)pin
) > 0)
3171 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
3175 info
->ioapic_entry
= &data
->entry
;
3176 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, info
);
3182 irq_data
->hwirq
= info
->ioapic_pin
;
3183 irq_data
->chip
= &ioapic_chip
;
3184 irq_data
->chip_data
= data
;
3185 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic
, pin
), data
, info
);
3187 cfg
= irqd_cfg(irq_data
);
3188 add_pin_to_irq_node(cfg
, info
->ioapic_node
, ioapic
, pin
);
3189 if (info
->ioapic_entry
)
3190 mp_setup_entry(cfg
, data
, info
->ioapic_entry
);
3191 mp_register_handler(virq
, data
->trigger
);
3192 if (virq
< nr_legacy_irqs())
3193 legacy_pic
->mask(virq
);
3195 apic_printk(APIC_VERBOSE
, KERN_DEBUG
3196 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3197 ioapic
, mpc_ioapic_id(ioapic
), pin
, cfg
->vector
,
3198 virq
, data
->trigger
, data
->polarity
, cfg
->dest_apicid
);
3203 void mp_irqdomain_free(struct irq_domain
*domain
, unsigned int virq
,
3204 unsigned int nr_irqs
)
3206 struct irq_cfg
*cfg
= irq_cfg(virq
);
3207 struct irq_data
*irq_data
;
3209 BUG_ON(nr_irqs
!= 1);
3210 irq_data
= irq_domain_get_irq_data(domain
, virq
);
3211 if (irq_data
&& irq_data
->chip_data
) {
3212 __remove_pin_from_irq(cfg
, mp_irqdomain_ioapic_idx(domain
),
3213 (int)irq_data
->hwirq
);
3214 WARN_ON(!list_empty(&cfg
->irq_2_pin
));
3215 kfree(irq_data
->chip_data
);
3217 irq_domain_free_irqs_top(domain
, virq
, nr_irqs
);
3220 void mp_irqdomain_activate(struct irq_domain
*domain
,
3221 struct irq_data
*irq_data
)
3223 unsigned long flags
;
3224 struct irq_pin_list
*entry
;
3225 struct mp_chip_data
*data
= irq_data
->chip_data
;
3226 struct irq_cfg
*cfg
= irqd_cfg(irq_data
);
3228 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3229 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
3230 __ioapic_write_entry(entry
->apic
, entry
->pin
, data
->entry
);
3231 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3234 void mp_irqdomain_deactivate(struct irq_domain
*domain
,
3235 struct irq_data
*irq_data
)
3237 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3238 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain
),
3239 (int)irq_data
->hwirq
);
3242 int mp_set_gsi_attr(u32 gsi
, int trigger
, int polarity
, int node
)
3246 struct mp_pin_info
*info
;
3248 ioapic
= mp_find_ioapic(gsi
);
3252 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3253 info
= mp_pin_info(ioapic
, pin
);
3254 trigger
= trigger
? 1 : 0;
3255 polarity
= polarity
? 1 : 0;
3257 mutex_lock(&ioapic_mutex
);
3259 info
->trigger
= trigger
;
3260 info
->polarity
= polarity
;
3263 } else if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
3266 mutex_unlock(&ioapic_mutex
);
3271 int mp_irqdomain_ioapic_idx(struct irq_domain
*domain
)
3273 return (int)(long)domain
->host_data
;