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Merge branch 'fix/ctxfi' into for-linus
[deliverable/linux.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
65
66 #include <asm/apic.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80 * # of IRQ routing registers
81 */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 void arch_disable_smp_support(void)
103 {
104 #ifdef CONFIG_PCI
105 noioapicquirk = 1;
106 noioapicreroute = -1;
107 #endif
108 skip_ioapic_setup = 1;
109 }
110
111 static int __init parse_noapic(char *str)
112 {
113 /* disable IO-APIC */
114 arch_disable_smp_support();
115 return 0;
116 }
117 early_param("noapic", parse_noapic);
118
119 struct irq_pin_list;
120
121 /*
122 * This is performance-critical, we want to do it O(1)
123 *
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
126 */
127
128 struct irq_pin_list {
129 int apic, pin;
130 struct irq_pin_list *next;
131 };
132
133 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 {
135 struct irq_pin_list *pin;
136
137 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
138
139 return pin;
140 }
141
142 struct irq_cfg {
143 struct irq_pin_list *irq_2_pin;
144 cpumask_var_t domain;
145 cpumask_var_t old_domain;
146 unsigned move_cleanup_count;
147 u8 vector;
148 u8 move_in_progress : 1;
149 };
150
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx[] = {
154 #else
155 static struct irq_cfg irq_cfgx[NR_IRQS] = {
156 #endif
157 [0] = { .vector = IRQ0_VECTOR, },
158 [1] = { .vector = IRQ1_VECTOR, },
159 [2] = { .vector = IRQ2_VECTOR, },
160 [3] = { .vector = IRQ3_VECTOR, },
161 [4] = { .vector = IRQ4_VECTOR, },
162 [5] = { .vector = IRQ5_VECTOR, },
163 [6] = { .vector = IRQ6_VECTOR, },
164 [7] = { .vector = IRQ7_VECTOR, },
165 [8] = { .vector = IRQ8_VECTOR, },
166 [9] = { .vector = IRQ9_VECTOR, },
167 [10] = { .vector = IRQ10_VECTOR, },
168 [11] = { .vector = IRQ11_VECTOR, },
169 [12] = { .vector = IRQ12_VECTOR, },
170 [13] = { .vector = IRQ13_VECTOR, },
171 [14] = { .vector = IRQ14_VECTOR, },
172 [15] = { .vector = IRQ15_VECTOR, },
173 };
174
175 int __init arch_early_irq_init(void)
176 {
177 struct irq_cfg *cfg;
178 struct irq_desc *desc;
179 int count;
180 int node;
181 int i;
182
183 cfg = irq_cfgx;
184 count = ARRAY_SIZE(irq_cfgx);
185 node= cpu_to_node(boot_cpu_id);
186
187 for (i = 0; i < count; i++) {
188 desc = irq_to_desc(i);
189 desc->chip_data = &cfg[i];
190 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
191 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
192 if (i < NR_IRQS_LEGACY)
193 cpumask_setall(cfg[i].domain);
194 }
195
196 return 0;
197 }
198
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg *irq_cfg(unsigned int irq)
201 {
202 struct irq_cfg *cfg = NULL;
203 struct irq_desc *desc;
204
205 desc = irq_to_desc(irq);
206 if (desc)
207 cfg = desc->chip_data;
208
209 return cfg;
210 }
211
212 static struct irq_cfg *get_one_free_irq_cfg(int node)
213 {
214 struct irq_cfg *cfg;
215
216 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
217 if (cfg) {
218 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
219 kfree(cfg);
220 cfg = NULL;
221 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
222 GFP_ATOMIC, node)) {
223 free_cpumask_var(cfg->domain);
224 kfree(cfg);
225 cfg = NULL;
226 } else {
227 cpumask_clear(cfg->domain);
228 cpumask_clear(cfg->old_domain);
229 }
230 }
231
232 return cfg;
233 }
234
235 int arch_init_chip_data(struct irq_desc *desc, int node)
236 {
237 struct irq_cfg *cfg;
238
239 cfg = desc->chip_data;
240 if (!cfg) {
241 desc->chip_data = get_one_free_irq_cfg(node);
242 if (!desc->chip_data) {
243 printk(KERN_ERR "can not alloc irq_cfg\n");
244 BUG_ON(1);
245 }
246 }
247
248 return 0;
249 }
250
251 /* for move_irq_desc */
252 static void
253 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
254 {
255 struct irq_pin_list *old_entry, *head, *tail, *entry;
256
257 cfg->irq_2_pin = NULL;
258 old_entry = old_cfg->irq_2_pin;
259 if (!old_entry)
260 return;
261
262 entry = get_one_free_irq_2_pin(node);
263 if (!entry)
264 return;
265
266 entry->apic = old_entry->apic;
267 entry->pin = old_entry->pin;
268 head = entry;
269 tail = entry;
270 old_entry = old_entry->next;
271 while (old_entry) {
272 entry = get_one_free_irq_2_pin(node);
273 if (!entry) {
274 entry = head;
275 while (entry) {
276 head = entry->next;
277 kfree(entry);
278 entry = head;
279 }
280 /* still use the old one */
281 return;
282 }
283 entry->apic = old_entry->apic;
284 entry->pin = old_entry->pin;
285 tail->next = entry;
286 tail = entry;
287 old_entry = old_entry->next;
288 }
289
290 tail->next = NULL;
291 cfg->irq_2_pin = head;
292 }
293
294 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
295 {
296 struct irq_pin_list *entry, *next;
297
298 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 return;
300
301 entry = old_cfg->irq_2_pin;
302
303 while (entry) {
304 next = entry->next;
305 kfree(entry);
306 entry = next;
307 }
308 old_cfg->irq_2_pin = NULL;
309 }
310
311 void arch_init_copy_chip_data(struct irq_desc *old_desc,
312 struct irq_desc *desc, int node)
313 {
314 struct irq_cfg *cfg;
315 struct irq_cfg *old_cfg;
316
317 cfg = get_one_free_irq_cfg(node);
318
319 if (!cfg)
320 return;
321
322 desc->chip_data = cfg;
323
324 old_cfg = old_desc->chip_data;
325
326 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
327
328 init_copy_irq_2_pin(old_cfg, cfg, node);
329 }
330
331 static void free_irq_cfg(struct irq_cfg *old_cfg)
332 {
333 kfree(old_cfg);
334 }
335
336 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
337 {
338 struct irq_cfg *old_cfg, *cfg;
339
340 old_cfg = old_desc->chip_data;
341 cfg = desc->chip_data;
342
343 if (old_cfg == cfg)
344 return;
345
346 if (old_cfg) {
347 free_irq_2_pin(old_cfg, cfg);
348 free_irq_cfg(old_cfg);
349 old_desc->chip_data = NULL;
350 }
351 }
352 /* end for move_irq_desc */
353
354 #else
355 static struct irq_cfg *irq_cfg(unsigned int irq)
356 {
357 return irq < nr_irqs ? irq_cfgx + irq : NULL;
358 }
359
360 #endif
361
362 struct io_apic {
363 unsigned int index;
364 unsigned int unused[3];
365 unsigned int data;
366 unsigned int unused2[11];
367 unsigned int eoi;
368 };
369
370 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
371 {
372 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
373 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
374 }
375
376 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
377 {
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(vector, &io_apic->eoi);
380 }
381
382 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
383 {
384 struct io_apic __iomem *io_apic = io_apic_base(apic);
385 writel(reg, &io_apic->index);
386 return readl(&io_apic->data);
387 }
388
389 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
390 {
391 struct io_apic __iomem *io_apic = io_apic_base(apic);
392 writel(reg, &io_apic->index);
393 writel(value, &io_apic->data);
394 }
395
396 /*
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
399 *
400 * Older SiS APIC requires we rewrite the index register
401 */
402 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
403 {
404 struct io_apic __iomem *io_apic = io_apic_base(apic);
405
406 if (sis_apic_bug)
407 writel(reg, &io_apic->index);
408 writel(value, &io_apic->data);
409 }
410
411 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
412 {
413 struct irq_pin_list *entry;
414 unsigned long flags;
415
416 spin_lock_irqsave(&ioapic_lock, flags);
417 entry = cfg->irq_2_pin;
418 for (;;) {
419 unsigned int reg;
420 int pin;
421
422 if (!entry)
423 break;
424 pin = entry->pin;
425 reg = io_apic_read(entry->apic, 0x10 + pin*2);
426 /* Is the remote IRR bit set? */
427 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
428 spin_unlock_irqrestore(&ioapic_lock, flags);
429 return true;
430 }
431 if (!entry->next)
432 break;
433 entry = entry->next;
434 }
435 spin_unlock_irqrestore(&ioapic_lock, flags);
436
437 return false;
438 }
439
440 union entry_union {
441 struct { u32 w1, w2; };
442 struct IO_APIC_route_entry entry;
443 };
444
445 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
446 {
447 union entry_union eu;
448 unsigned long flags;
449 spin_lock_irqsave(&ioapic_lock, flags);
450 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
451 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
452 spin_unlock_irqrestore(&ioapic_lock, flags);
453 return eu.entry;
454 }
455
456 /*
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
461 */
462 static void
463 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
464 {
465 union entry_union eu = {{0, 0}};
466
467 eu.entry = e;
468 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
469 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
470 }
471
472 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
473 {
474 unsigned long flags;
475 spin_lock_irqsave(&ioapic_lock, flags);
476 __ioapic_write_entry(apic, pin, e);
477 spin_unlock_irqrestore(&ioapic_lock, flags);
478 }
479
480 /*
481 * When we mask an IO APIC routing entry, we need to write the low
482 * word first, in order to set the mask bit before we change the
483 * high bits!
484 */
485 static void ioapic_mask_entry(int apic, int pin)
486 {
487 unsigned long flags;
488 union entry_union eu = { .entry.mask = 1 };
489
490 spin_lock_irqsave(&ioapic_lock, flags);
491 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
492 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
493 spin_unlock_irqrestore(&ioapic_lock, flags);
494 }
495
496 /*
497 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
498 * shared ISA-space IRQs, so we have to support them. We are super
499 * fast in the common case, and fast for shared ISA-space IRQs.
500 */
501 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
502 {
503 struct irq_pin_list *entry;
504
505 entry = cfg->irq_2_pin;
506 if (!entry) {
507 entry = get_one_free_irq_2_pin(node);
508 if (!entry) {
509 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
510 apic, pin);
511 return;
512 }
513 cfg->irq_2_pin = entry;
514 entry->apic = apic;
515 entry->pin = pin;
516 return;
517 }
518
519 while (entry->next) {
520 /* not again, please */
521 if (entry->apic == apic && entry->pin == pin)
522 return;
523
524 entry = entry->next;
525 }
526
527 entry->next = get_one_free_irq_2_pin(node);
528 entry = entry->next;
529 entry->apic = apic;
530 entry->pin = pin;
531 }
532
533 /*
534 * Reroute an IRQ to a different pin.
535 */
536 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
537 int oldapic, int oldpin,
538 int newapic, int newpin)
539 {
540 struct irq_pin_list *entry = cfg->irq_2_pin;
541 int replaced = 0;
542
543 while (entry) {
544 if (entry->apic == oldapic && entry->pin == oldpin) {
545 entry->apic = newapic;
546 entry->pin = newpin;
547 replaced = 1;
548 /* every one is different, right? */
549 break;
550 }
551 entry = entry->next;
552 }
553
554 /* why? call replace before add? */
555 if (!replaced)
556 add_pin_to_irq_node(cfg, node, newapic, newpin);
557 }
558
559 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
560 int mask_and, int mask_or,
561 void (*final)(struct irq_pin_list *entry))
562 {
563 int pin;
564 struct irq_pin_list *entry;
565
566 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
567 unsigned int reg;
568 pin = entry->pin;
569 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
570 reg &= mask_and;
571 reg |= mask_or;
572 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
573 if (final)
574 final(entry);
575 }
576 }
577
578 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
579 {
580 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
581 }
582
583 #ifdef CONFIG_X86_64
584 static void io_apic_sync(struct irq_pin_list *entry)
585 {
586 /*
587 * Synchronize the IO-APIC and the CPU by doing
588 * a dummy read from the IO-APIC
589 */
590 struct io_apic __iomem *io_apic;
591 io_apic = io_apic_base(entry->apic);
592 readl(&io_apic->data);
593 }
594
595 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
596 {
597 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
598 }
599 #else /* CONFIG_X86_32 */
600 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
601 {
602 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
603 }
604
605 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
606 {
607 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
608 IO_APIC_REDIR_MASKED, NULL);
609 }
610
611 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
612 {
613 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
614 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
615 }
616 #endif /* CONFIG_X86_32 */
617
618 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
619 {
620 struct irq_cfg *cfg = desc->chip_data;
621 unsigned long flags;
622
623 BUG_ON(!cfg);
624
625 spin_lock_irqsave(&ioapic_lock, flags);
626 __mask_IO_APIC_irq(cfg);
627 spin_unlock_irqrestore(&ioapic_lock, flags);
628 }
629
630 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
631 {
632 struct irq_cfg *cfg = desc->chip_data;
633 unsigned long flags;
634
635 spin_lock_irqsave(&ioapic_lock, flags);
636 __unmask_IO_APIC_irq(cfg);
637 spin_unlock_irqrestore(&ioapic_lock, flags);
638 }
639
640 static void mask_IO_APIC_irq(unsigned int irq)
641 {
642 struct irq_desc *desc = irq_to_desc(irq);
643
644 mask_IO_APIC_irq_desc(desc);
645 }
646 static void unmask_IO_APIC_irq(unsigned int irq)
647 {
648 struct irq_desc *desc = irq_to_desc(irq);
649
650 unmask_IO_APIC_irq_desc(desc);
651 }
652
653 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
654 {
655 struct IO_APIC_route_entry entry;
656
657 /* Check delivery_mode to be sure we're not clearing an SMI pin */
658 entry = ioapic_read_entry(apic, pin);
659 if (entry.delivery_mode == dest_SMI)
660 return;
661 /*
662 * Disable it in the IO-APIC irq-routing table:
663 */
664 ioapic_mask_entry(apic, pin);
665 }
666
667 static void clear_IO_APIC (void)
668 {
669 int apic, pin;
670
671 for (apic = 0; apic < nr_ioapics; apic++)
672 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
673 clear_IO_APIC_pin(apic, pin);
674 }
675
676 #ifdef CONFIG_X86_32
677 /*
678 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
679 * specific CPU-side IRQs.
680 */
681
682 #define MAX_PIRQS 8
683 static int pirq_entries[MAX_PIRQS] = {
684 [0 ... MAX_PIRQS - 1] = -1
685 };
686
687 static int __init ioapic_pirq_setup(char *str)
688 {
689 int i, max;
690 int ints[MAX_PIRQS+1];
691
692 get_options(str, ARRAY_SIZE(ints), ints);
693
694 apic_printk(APIC_VERBOSE, KERN_INFO
695 "PIRQ redirection, working around broken MP-BIOS.\n");
696 max = MAX_PIRQS;
697 if (ints[0] < MAX_PIRQS)
698 max = ints[0];
699
700 for (i = 0; i < max; i++) {
701 apic_printk(APIC_VERBOSE, KERN_DEBUG
702 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
703 /*
704 * PIRQs are mapped upside down, usually.
705 */
706 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
707 }
708 return 1;
709 }
710
711 __setup("pirq=", ioapic_pirq_setup);
712 #endif /* CONFIG_X86_32 */
713
714 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
715 {
716 int apic;
717 struct IO_APIC_route_entry **ioapic_entries;
718
719 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
720 GFP_ATOMIC);
721 if (!ioapic_entries)
722 return 0;
723
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 ioapic_entries[apic] =
726 kzalloc(sizeof(struct IO_APIC_route_entry) *
727 nr_ioapic_registers[apic], GFP_ATOMIC);
728 if (!ioapic_entries[apic])
729 goto nomem;
730 }
731
732 return ioapic_entries;
733
734 nomem:
735 while (--apic >= 0)
736 kfree(ioapic_entries[apic]);
737 kfree(ioapic_entries);
738
739 return 0;
740 }
741
742 /*
743 * Saves all the IO-APIC RTE's
744 */
745 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
746 {
747 int apic, pin;
748
749 if (!ioapic_entries)
750 return -ENOMEM;
751
752 for (apic = 0; apic < nr_ioapics; apic++) {
753 if (!ioapic_entries[apic])
754 return -ENOMEM;
755
756 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
757 ioapic_entries[apic][pin] =
758 ioapic_read_entry(apic, pin);
759 }
760
761 return 0;
762 }
763
764 /*
765 * Mask all IO APIC entries.
766 */
767 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
768 {
769 int apic, pin;
770
771 if (!ioapic_entries)
772 return;
773
774 for (apic = 0; apic < nr_ioapics; apic++) {
775 if (!ioapic_entries[apic])
776 break;
777
778 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
779 struct IO_APIC_route_entry entry;
780
781 entry = ioapic_entries[apic][pin];
782 if (!entry.mask) {
783 entry.mask = 1;
784 ioapic_write_entry(apic, pin, entry);
785 }
786 }
787 }
788 }
789
790 /*
791 * Restore IO APIC entries which was saved in ioapic_entries.
792 */
793 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
794 {
795 int apic, pin;
796
797 if (!ioapic_entries)
798 return -ENOMEM;
799
800 for (apic = 0; apic < nr_ioapics; apic++) {
801 if (!ioapic_entries[apic])
802 return -ENOMEM;
803
804 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
805 ioapic_write_entry(apic, pin,
806 ioapic_entries[apic][pin]);
807 }
808 return 0;
809 }
810
811 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
812 {
813 int apic;
814
815 for (apic = 0; apic < nr_ioapics; apic++)
816 kfree(ioapic_entries[apic]);
817
818 kfree(ioapic_entries);
819 }
820
821 /*
822 * Find the IRQ entry number of a certain pin.
823 */
824 static int find_irq_entry(int apic, int pin, int type)
825 {
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++)
829 if (mp_irqs[i].irqtype == type &&
830 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
831 mp_irqs[i].dstapic == MP_APIC_ALL) &&
832 mp_irqs[i].dstirq == pin)
833 return i;
834
835 return -1;
836 }
837
838 /*
839 * Find the pin to which IRQ[irq] (ISA) is connected
840 */
841 static int __init find_isa_irq_pin(int irq, int type)
842 {
843 int i;
844
845 for (i = 0; i < mp_irq_entries; i++) {
846 int lbus = mp_irqs[i].srcbus;
847
848 if (test_bit(lbus, mp_bus_not_pci) &&
849 (mp_irqs[i].irqtype == type) &&
850 (mp_irqs[i].srcbusirq == irq))
851
852 return mp_irqs[i].dstirq;
853 }
854 return -1;
855 }
856
857 static int __init find_isa_irq_apic(int irq, int type)
858 {
859 int i;
860
861 for (i = 0; i < mp_irq_entries; i++) {
862 int lbus = mp_irqs[i].srcbus;
863
864 if (test_bit(lbus, mp_bus_not_pci) &&
865 (mp_irqs[i].irqtype == type) &&
866 (mp_irqs[i].srcbusirq == irq))
867 break;
868 }
869 if (i < mp_irq_entries) {
870 int apic;
871 for(apic = 0; apic < nr_ioapics; apic++) {
872 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
873 return apic;
874 }
875 }
876
877 return -1;
878 }
879
880 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
881 /*
882 * EISA Edge/Level control register, ELCR
883 */
884 static int EISA_ELCR(unsigned int irq)
885 {
886 if (irq < NR_IRQS_LEGACY) {
887 unsigned int port = 0x4d0 + (irq >> 3);
888 return (inb(port) >> (irq & 7)) & 1;
889 }
890 apic_printk(APIC_VERBOSE, KERN_INFO
891 "Broken MPtable reports ISA irq %d\n", irq);
892 return 0;
893 }
894
895 #endif
896
897 /* ISA interrupts are always polarity zero edge triggered,
898 * when listed as conforming in the MP table. */
899
900 #define default_ISA_trigger(idx) (0)
901 #define default_ISA_polarity(idx) (0)
902
903 /* EISA interrupts are always polarity zero and can be edge or level
904 * trigger depending on the ELCR value. If an interrupt is listed as
905 * EISA conforming in the MP table, that means its trigger type must
906 * be read in from the ELCR */
907
908 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
909 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
910
911 /* PCI interrupts are always polarity one level triggered,
912 * when listed as conforming in the MP table. */
913
914 #define default_PCI_trigger(idx) (1)
915 #define default_PCI_polarity(idx) (1)
916
917 /* MCA interrupts are always polarity zero level triggered,
918 * when listed as conforming in the MP table. */
919
920 #define default_MCA_trigger(idx) (1)
921 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
922
923 static int MPBIOS_polarity(int idx)
924 {
925 int bus = mp_irqs[idx].srcbus;
926 int polarity;
927
928 /*
929 * Determine IRQ line polarity (high active or low active):
930 */
931 switch (mp_irqs[idx].irqflag & 3)
932 {
933 case 0: /* conforms, ie. bus-type dependent polarity */
934 if (test_bit(bus, mp_bus_not_pci))
935 polarity = default_ISA_polarity(idx);
936 else
937 polarity = default_PCI_polarity(idx);
938 break;
939 case 1: /* high active */
940 {
941 polarity = 0;
942 break;
943 }
944 case 2: /* reserved */
945 {
946 printk(KERN_WARNING "broken BIOS!!\n");
947 polarity = 1;
948 break;
949 }
950 case 3: /* low active */
951 {
952 polarity = 1;
953 break;
954 }
955 default: /* invalid */
956 {
957 printk(KERN_WARNING "broken BIOS!!\n");
958 polarity = 1;
959 break;
960 }
961 }
962 return polarity;
963 }
964
965 static int MPBIOS_trigger(int idx)
966 {
967 int bus = mp_irqs[idx].srcbus;
968 int trigger;
969
970 /*
971 * Determine IRQ trigger mode (edge or level sensitive):
972 */
973 switch ((mp_irqs[idx].irqflag>>2) & 3)
974 {
975 case 0: /* conforms, ie. bus-type dependent */
976 if (test_bit(bus, mp_bus_not_pci))
977 trigger = default_ISA_trigger(idx);
978 else
979 trigger = default_PCI_trigger(idx);
980 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
981 switch (mp_bus_id_to_type[bus]) {
982 case MP_BUS_ISA: /* ISA pin */
983 {
984 /* set before the switch */
985 break;
986 }
987 case MP_BUS_EISA: /* EISA pin */
988 {
989 trigger = default_EISA_trigger(idx);
990 break;
991 }
992 case MP_BUS_PCI: /* PCI pin */
993 {
994 /* set before the switch */
995 break;
996 }
997 case MP_BUS_MCA: /* MCA pin */
998 {
999 trigger = default_MCA_trigger(idx);
1000 break;
1001 }
1002 default:
1003 {
1004 printk(KERN_WARNING "broken BIOS!!\n");
1005 trigger = 1;
1006 break;
1007 }
1008 }
1009 #endif
1010 break;
1011 case 1: /* edge */
1012 {
1013 trigger = 0;
1014 break;
1015 }
1016 case 2: /* reserved */
1017 {
1018 printk(KERN_WARNING "broken BIOS!!\n");
1019 trigger = 1;
1020 break;
1021 }
1022 case 3: /* level */
1023 {
1024 trigger = 1;
1025 break;
1026 }
1027 default: /* invalid */
1028 {
1029 printk(KERN_WARNING "broken BIOS!!\n");
1030 trigger = 0;
1031 break;
1032 }
1033 }
1034 return trigger;
1035 }
1036
1037 static inline int irq_polarity(int idx)
1038 {
1039 return MPBIOS_polarity(idx);
1040 }
1041
1042 static inline int irq_trigger(int idx)
1043 {
1044 return MPBIOS_trigger(idx);
1045 }
1046
1047 int (*ioapic_renumber_irq)(int ioapic, int irq);
1048 static int pin_2_irq(int idx, int apic, int pin)
1049 {
1050 int irq, i;
1051 int bus = mp_irqs[idx].srcbus;
1052
1053 /*
1054 * Debugging check, we are in big trouble if this message pops up!
1055 */
1056 if (mp_irqs[idx].dstirq != pin)
1057 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1058
1059 if (test_bit(bus, mp_bus_not_pci)) {
1060 irq = mp_irqs[idx].srcbusirq;
1061 } else {
1062 /*
1063 * PCI IRQs are mapped in order
1064 */
1065 i = irq = 0;
1066 while (i < apic)
1067 irq += nr_ioapic_registers[i++];
1068 irq += pin;
1069 /*
1070 * For MPS mode, so far only needed by ES7000 platform
1071 */
1072 if (ioapic_renumber_irq)
1073 irq = ioapic_renumber_irq(apic, irq);
1074 }
1075
1076 #ifdef CONFIG_X86_32
1077 /*
1078 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1079 */
1080 if ((pin >= 16) && (pin <= 23)) {
1081 if (pirq_entries[pin-16] != -1) {
1082 if (!pirq_entries[pin-16]) {
1083 apic_printk(APIC_VERBOSE, KERN_DEBUG
1084 "disabling PIRQ%d\n", pin-16);
1085 } else {
1086 irq = pirq_entries[pin-16];
1087 apic_printk(APIC_VERBOSE, KERN_DEBUG
1088 "using PIRQ%d -> IRQ %d\n",
1089 pin-16, irq);
1090 }
1091 }
1092 }
1093 #endif
1094
1095 return irq;
1096 }
1097
1098 /*
1099 * Find a specific PCI IRQ entry.
1100 * Not an __init, possibly needed by modules
1101 */
1102 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1103 struct io_apic_irq_attr *irq_attr)
1104 {
1105 int apic, i, best_guess = -1;
1106
1107 apic_printk(APIC_DEBUG,
1108 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1109 bus, slot, pin);
1110 if (test_bit(bus, mp_bus_not_pci)) {
1111 apic_printk(APIC_VERBOSE,
1112 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1113 return -1;
1114 }
1115 for (i = 0; i < mp_irq_entries; i++) {
1116 int lbus = mp_irqs[i].srcbus;
1117
1118 for (apic = 0; apic < nr_ioapics; apic++)
1119 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1120 mp_irqs[i].dstapic == MP_APIC_ALL)
1121 break;
1122
1123 if (!test_bit(lbus, mp_bus_not_pci) &&
1124 !mp_irqs[i].irqtype &&
1125 (bus == lbus) &&
1126 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1127 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1128
1129 if (!(apic || IO_APIC_IRQ(irq)))
1130 continue;
1131
1132 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1133 set_io_apic_irq_attr(irq_attr, apic,
1134 mp_irqs[i].dstirq,
1135 irq_trigger(i),
1136 irq_polarity(i));
1137 return irq;
1138 }
1139 /*
1140 * Use the first all-but-pin matching entry as a
1141 * best-guess fuzzy result for broken mptables.
1142 */
1143 if (best_guess < 0) {
1144 set_io_apic_irq_attr(irq_attr, apic,
1145 mp_irqs[i].dstirq,
1146 irq_trigger(i),
1147 irq_polarity(i));
1148 best_guess = irq;
1149 }
1150 }
1151 }
1152 return best_guess;
1153 }
1154 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1155
1156 void lock_vector_lock(void)
1157 {
1158 /* Used to the online set of cpus does not change
1159 * during assign_irq_vector.
1160 */
1161 spin_lock(&vector_lock);
1162 }
1163
1164 void unlock_vector_lock(void)
1165 {
1166 spin_unlock(&vector_lock);
1167 }
1168
1169 static int
1170 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1171 {
1172 /*
1173 * NOTE! The local APIC isn't very good at handling
1174 * multiple interrupts at the same interrupt level.
1175 * As the interrupt level is determined by taking the
1176 * vector number and shifting that right by 4, we
1177 * want to spread these out a bit so that they don't
1178 * all fall in the same interrupt level.
1179 *
1180 * Also, we've got to be careful not to trash gate
1181 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1182 */
1183 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1184 unsigned int old_vector;
1185 int cpu, err;
1186 cpumask_var_t tmp_mask;
1187
1188 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1189 return -EBUSY;
1190
1191 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1192 return -ENOMEM;
1193
1194 old_vector = cfg->vector;
1195 if (old_vector) {
1196 cpumask_and(tmp_mask, mask, cpu_online_mask);
1197 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1198 if (!cpumask_empty(tmp_mask)) {
1199 free_cpumask_var(tmp_mask);
1200 return 0;
1201 }
1202 }
1203
1204 /* Only try and allocate irqs on cpus that are present */
1205 err = -ENOSPC;
1206 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1207 int new_cpu;
1208 int vector, offset;
1209
1210 apic->vector_allocation_domain(cpu, tmp_mask);
1211
1212 vector = current_vector;
1213 offset = current_offset;
1214 next:
1215 vector += 8;
1216 if (vector >= first_system_vector) {
1217 /* If out of vectors on large boxen, must share them. */
1218 offset = (offset + 1) % 8;
1219 vector = FIRST_DEVICE_VECTOR + offset;
1220 }
1221 if (unlikely(current_vector == vector))
1222 continue;
1223
1224 if (test_bit(vector, used_vectors))
1225 goto next;
1226
1227 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1228 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1229 goto next;
1230 /* Found one! */
1231 current_vector = vector;
1232 current_offset = offset;
1233 if (old_vector) {
1234 cfg->move_in_progress = 1;
1235 cpumask_copy(cfg->old_domain, cfg->domain);
1236 }
1237 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1238 per_cpu(vector_irq, new_cpu)[vector] = irq;
1239 cfg->vector = vector;
1240 cpumask_copy(cfg->domain, tmp_mask);
1241 err = 0;
1242 break;
1243 }
1244 free_cpumask_var(tmp_mask);
1245 return err;
1246 }
1247
1248 static int
1249 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1250 {
1251 int err;
1252 unsigned long flags;
1253
1254 spin_lock_irqsave(&vector_lock, flags);
1255 err = __assign_irq_vector(irq, cfg, mask);
1256 spin_unlock_irqrestore(&vector_lock, flags);
1257 return err;
1258 }
1259
1260 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1261 {
1262 int cpu, vector;
1263
1264 BUG_ON(!cfg->vector);
1265
1266 vector = cfg->vector;
1267 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1268 per_cpu(vector_irq, cpu)[vector] = -1;
1269
1270 cfg->vector = 0;
1271 cpumask_clear(cfg->domain);
1272
1273 if (likely(!cfg->move_in_progress))
1274 return;
1275 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1276 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1277 vector++) {
1278 if (per_cpu(vector_irq, cpu)[vector] != irq)
1279 continue;
1280 per_cpu(vector_irq, cpu)[vector] = -1;
1281 break;
1282 }
1283 }
1284 cfg->move_in_progress = 0;
1285 }
1286
1287 void __setup_vector_irq(int cpu)
1288 {
1289 /* Initialize vector_irq on a new cpu */
1290 /* This function must be called with vector_lock held */
1291 int irq, vector;
1292 struct irq_cfg *cfg;
1293 struct irq_desc *desc;
1294
1295 /* Mark the inuse vectors */
1296 for_each_irq_desc(irq, desc) {
1297 cfg = desc->chip_data;
1298 if (!cpumask_test_cpu(cpu, cfg->domain))
1299 continue;
1300 vector = cfg->vector;
1301 per_cpu(vector_irq, cpu)[vector] = irq;
1302 }
1303 /* Mark the free vectors */
1304 for (vector = 0; vector < NR_VECTORS; ++vector) {
1305 irq = per_cpu(vector_irq, cpu)[vector];
1306 if (irq < 0)
1307 continue;
1308
1309 cfg = irq_cfg(irq);
1310 if (!cpumask_test_cpu(cpu, cfg->domain))
1311 per_cpu(vector_irq, cpu)[vector] = -1;
1312 }
1313 }
1314
1315 static struct irq_chip ioapic_chip;
1316 static struct irq_chip ir_ioapic_chip;
1317
1318 #define IOAPIC_AUTO -1
1319 #define IOAPIC_EDGE 0
1320 #define IOAPIC_LEVEL 1
1321
1322 #ifdef CONFIG_X86_32
1323 static inline int IO_APIC_irq_trigger(int irq)
1324 {
1325 int apic, idx, pin;
1326
1327 for (apic = 0; apic < nr_ioapics; apic++) {
1328 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1329 idx = find_irq_entry(apic, pin, mp_INT);
1330 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1331 return irq_trigger(idx);
1332 }
1333 }
1334 /*
1335 * nonexistent IRQs are edge default
1336 */
1337 return 0;
1338 }
1339 #else
1340 static inline int IO_APIC_irq_trigger(int irq)
1341 {
1342 return 1;
1343 }
1344 #endif
1345
1346 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1347 {
1348
1349 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1350 trigger == IOAPIC_LEVEL)
1351 desc->status |= IRQ_LEVEL;
1352 else
1353 desc->status &= ~IRQ_LEVEL;
1354
1355 if (irq_remapped(irq)) {
1356 desc->status |= IRQ_MOVE_PCNTXT;
1357 if (trigger)
1358 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1359 handle_fasteoi_irq,
1360 "fasteoi");
1361 else
1362 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1363 handle_edge_irq, "edge");
1364 return;
1365 }
1366
1367 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1368 trigger == IOAPIC_LEVEL)
1369 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1370 handle_fasteoi_irq,
1371 "fasteoi");
1372 else
1373 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1374 handle_edge_irq, "edge");
1375 }
1376
1377 int setup_ioapic_entry(int apic_id, int irq,
1378 struct IO_APIC_route_entry *entry,
1379 unsigned int destination, int trigger,
1380 int polarity, int vector, int pin)
1381 {
1382 /*
1383 * add it to the IO-APIC irq-routing table:
1384 */
1385 memset(entry,0,sizeof(*entry));
1386
1387 if (intr_remapping_enabled) {
1388 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1389 struct irte irte;
1390 struct IR_IO_APIC_route_entry *ir_entry =
1391 (struct IR_IO_APIC_route_entry *) entry;
1392 int index;
1393
1394 if (!iommu)
1395 panic("No mapping iommu for ioapic %d\n", apic_id);
1396
1397 index = alloc_irte(iommu, irq, 1);
1398 if (index < 0)
1399 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1400
1401 memset(&irte, 0, sizeof(irte));
1402
1403 irte.present = 1;
1404 irte.dst_mode = apic->irq_dest_mode;
1405 /*
1406 * Trigger mode in the IRTE will always be edge, and the
1407 * actual level or edge trigger will be setup in the IO-APIC
1408 * RTE. This will help simplify level triggered irq migration.
1409 * For more details, see the comments above explainig IO-APIC
1410 * irq migration in the presence of interrupt-remapping.
1411 */
1412 irte.trigger_mode = 0;
1413 irte.dlvry_mode = apic->irq_delivery_mode;
1414 irte.vector = vector;
1415 irte.dest_id = IRTE_DEST(destination);
1416
1417 /* Set source-id of interrupt request */
1418 set_ioapic_sid(&irte, apic_id);
1419
1420 modify_irte(irq, &irte);
1421
1422 ir_entry->index2 = (index >> 15) & 0x1;
1423 ir_entry->zero = 0;
1424 ir_entry->format = 1;
1425 ir_entry->index = (index & 0x7fff);
1426 /*
1427 * IO-APIC RTE will be configured with virtual vector.
1428 * irq handler will do the explicit EOI to the io-apic.
1429 */
1430 ir_entry->vector = pin;
1431 } else {
1432 entry->delivery_mode = apic->irq_delivery_mode;
1433 entry->dest_mode = apic->irq_dest_mode;
1434 entry->dest = destination;
1435 entry->vector = vector;
1436 }
1437
1438 entry->mask = 0; /* enable IRQ */
1439 entry->trigger = trigger;
1440 entry->polarity = polarity;
1441
1442 /* Mask level triggered irqs.
1443 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1444 */
1445 if (trigger)
1446 entry->mask = 1;
1447 return 0;
1448 }
1449
1450 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1451 int trigger, int polarity)
1452 {
1453 struct irq_cfg *cfg;
1454 struct IO_APIC_route_entry entry;
1455 unsigned int dest;
1456
1457 if (!IO_APIC_IRQ(irq))
1458 return;
1459
1460 cfg = desc->chip_data;
1461
1462 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1463 return;
1464
1465 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1466
1467 apic_printk(APIC_VERBOSE,KERN_DEBUG
1468 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1469 "IRQ %d Mode:%i Active:%i)\n",
1470 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1471 irq, trigger, polarity);
1472
1473
1474 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1475 dest, trigger, polarity, cfg->vector, pin)) {
1476 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1477 mp_ioapics[apic_id].apicid, pin);
1478 __clear_irq_vector(irq, cfg);
1479 return;
1480 }
1481
1482 ioapic_register_intr(irq, desc, trigger);
1483 if (irq < NR_IRQS_LEGACY)
1484 disable_8259A_irq(irq);
1485
1486 ioapic_write_entry(apic_id, pin, entry);
1487 }
1488
1489 static struct {
1490 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1491 } mp_ioapic_routing[MAX_IO_APICS];
1492
1493 static void __init setup_IO_APIC_irqs(void)
1494 {
1495 int apic_id = 0, pin, idx, irq;
1496 int notcon = 0;
1497 struct irq_desc *desc;
1498 struct irq_cfg *cfg;
1499 int node = cpu_to_node(boot_cpu_id);
1500
1501 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1502
1503 #ifdef CONFIG_ACPI
1504 if (!acpi_disabled && acpi_ioapic) {
1505 apic_id = mp_find_ioapic(0);
1506 if (apic_id < 0)
1507 apic_id = 0;
1508 }
1509 #endif
1510
1511 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1512 idx = find_irq_entry(apic_id, pin, mp_INT);
1513 if (idx == -1) {
1514 if (!notcon) {
1515 notcon = 1;
1516 apic_printk(APIC_VERBOSE,
1517 KERN_DEBUG " %d-%d",
1518 mp_ioapics[apic_id].apicid, pin);
1519 } else
1520 apic_printk(APIC_VERBOSE, " %d-%d",
1521 mp_ioapics[apic_id].apicid, pin);
1522 continue;
1523 }
1524 if (notcon) {
1525 apic_printk(APIC_VERBOSE,
1526 " (apicid-pin) not connected\n");
1527 notcon = 0;
1528 }
1529
1530 irq = pin_2_irq(idx, apic_id, pin);
1531
1532 /*
1533 * Skip the timer IRQ if there's a quirk handler
1534 * installed and if it returns 1:
1535 */
1536 if (apic->multi_timer_check &&
1537 apic->multi_timer_check(apic_id, irq))
1538 continue;
1539
1540 desc = irq_to_desc_alloc_node(irq, node);
1541 if (!desc) {
1542 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1543 continue;
1544 }
1545 cfg = desc->chip_data;
1546 add_pin_to_irq_node(cfg, node, apic_id, pin);
1547 /*
1548 * don't mark it in pin_programmed, so later acpi could
1549 * set it correctly when irq < 16
1550 */
1551 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1552 irq_trigger(idx), irq_polarity(idx));
1553 }
1554
1555 if (notcon)
1556 apic_printk(APIC_VERBOSE,
1557 " (apicid-pin) not connected\n");
1558 }
1559
1560 /*
1561 * Set up the timer pin, possibly with the 8259A-master behind.
1562 */
1563 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1564 int vector)
1565 {
1566 struct IO_APIC_route_entry entry;
1567
1568 if (intr_remapping_enabled)
1569 return;
1570
1571 memset(&entry, 0, sizeof(entry));
1572
1573 /*
1574 * We use logical delivery to get the timer IRQ
1575 * to the first CPU.
1576 */
1577 entry.dest_mode = apic->irq_dest_mode;
1578 entry.mask = 0; /* don't mask IRQ for edge */
1579 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1580 entry.delivery_mode = apic->irq_delivery_mode;
1581 entry.polarity = 0;
1582 entry.trigger = 0;
1583 entry.vector = vector;
1584
1585 /*
1586 * The timer IRQ doesn't have to know that behind the
1587 * scene we may have a 8259A-master in AEOI mode ...
1588 */
1589 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1590
1591 /*
1592 * Add it to the IO-APIC irq-routing table:
1593 */
1594 ioapic_write_entry(apic_id, pin, entry);
1595 }
1596
1597
1598 __apicdebuginit(void) print_IO_APIC(void)
1599 {
1600 int apic, i;
1601 union IO_APIC_reg_00 reg_00;
1602 union IO_APIC_reg_01 reg_01;
1603 union IO_APIC_reg_02 reg_02;
1604 union IO_APIC_reg_03 reg_03;
1605 unsigned long flags;
1606 struct irq_cfg *cfg;
1607 struct irq_desc *desc;
1608 unsigned int irq;
1609
1610 if (apic_verbosity == APIC_QUIET)
1611 return;
1612
1613 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1614 for (i = 0; i < nr_ioapics; i++)
1615 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1616 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1617
1618 /*
1619 * We are a bit conservative about what we expect. We have to
1620 * know about every hardware change ASAP.
1621 */
1622 printk(KERN_INFO "testing the IO APIC.......................\n");
1623
1624 for (apic = 0; apic < nr_ioapics; apic++) {
1625
1626 spin_lock_irqsave(&ioapic_lock, flags);
1627 reg_00.raw = io_apic_read(apic, 0);
1628 reg_01.raw = io_apic_read(apic, 1);
1629 if (reg_01.bits.version >= 0x10)
1630 reg_02.raw = io_apic_read(apic, 2);
1631 if (reg_01.bits.version >= 0x20)
1632 reg_03.raw = io_apic_read(apic, 3);
1633 spin_unlock_irqrestore(&ioapic_lock, flags);
1634
1635 printk("\n");
1636 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1637 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1638 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1639 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1640 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1641
1642 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1643 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1644
1645 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1646 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1647
1648 /*
1649 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1650 * but the value of reg_02 is read as the previous read register
1651 * value, so ignore it if reg_02 == reg_01.
1652 */
1653 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1654 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1655 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1656 }
1657
1658 /*
1659 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1660 * or reg_03, but the value of reg_0[23] is read as the previous read
1661 * register value, so ignore it if reg_03 == reg_0[12].
1662 */
1663 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1664 reg_03.raw != reg_01.raw) {
1665 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1666 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1667 }
1668
1669 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1670
1671 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1672 " Stat Dmod Deli Vect: \n");
1673
1674 for (i = 0; i <= reg_01.bits.entries; i++) {
1675 struct IO_APIC_route_entry entry;
1676
1677 entry = ioapic_read_entry(apic, i);
1678
1679 printk(KERN_DEBUG " %02x %03X ",
1680 i,
1681 entry.dest
1682 );
1683
1684 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1685 entry.mask,
1686 entry.trigger,
1687 entry.irr,
1688 entry.polarity,
1689 entry.delivery_status,
1690 entry.dest_mode,
1691 entry.delivery_mode,
1692 entry.vector
1693 );
1694 }
1695 }
1696 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1697 for_each_irq_desc(irq, desc) {
1698 struct irq_pin_list *entry;
1699
1700 cfg = desc->chip_data;
1701 entry = cfg->irq_2_pin;
1702 if (!entry)
1703 continue;
1704 printk(KERN_DEBUG "IRQ%d ", irq);
1705 for (;;) {
1706 printk("-> %d:%d", entry->apic, entry->pin);
1707 if (!entry->next)
1708 break;
1709 entry = entry->next;
1710 }
1711 printk("\n");
1712 }
1713
1714 printk(KERN_INFO ".................................... done.\n");
1715
1716 return;
1717 }
1718
1719 __apicdebuginit(void) print_APIC_field(int base)
1720 {
1721 int i;
1722
1723 if (apic_verbosity == APIC_QUIET)
1724 return;
1725
1726 printk(KERN_DEBUG);
1727
1728 for (i = 0; i < 8; i++)
1729 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1730
1731 printk(KERN_CONT "\n");
1732 }
1733
1734 __apicdebuginit(void) print_local_APIC(void *dummy)
1735 {
1736 unsigned int i, v, ver, maxlvt;
1737 u64 icr;
1738
1739 if (apic_verbosity == APIC_QUIET)
1740 return;
1741
1742 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1743 smp_processor_id(), hard_smp_processor_id());
1744 v = apic_read(APIC_ID);
1745 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1746 v = apic_read(APIC_LVR);
1747 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1748 ver = GET_APIC_VERSION(v);
1749 maxlvt = lapic_get_maxlvt();
1750
1751 v = apic_read(APIC_TASKPRI);
1752 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1753
1754 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1755 if (!APIC_XAPIC(ver)) {
1756 v = apic_read(APIC_ARBPRI);
1757 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1758 v & APIC_ARBPRI_MASK);
1759 }
1760 v = apic_read(APIC_PROCPRI);
1761 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1762 }
1763
1764 /*
1765 * Remote read supported only in the 82489DX and local APIC for
1766 * Pentium processors.
1767 */
1768 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1769 v = apic_read(APIC_RRR);
1770 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1771 }
1772
1773 v = apic_read(APIC_LDR);
1774 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1775 if (!x2apic_enabled()) {
1776 v = apic_read(APIC_DFR);
1777 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1778 }
1779 v = apic_read(APIC_SPIV);
1780 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1781
1782 printk(KERN_DEBUG "... APIC ISR field:\n");
1783 print_APIC_field(APIC_ISR);
1784 printk(KERN_DEBUG "... APIC TMR field:\n");
1785 print_APIC_field(APIC_TMR);
1786 printk(KERN_DEBUG "... APIC IRR field:\n");
1787 print_APIC_field(APIC_IRR);
1788
1789 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1790 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1791 apic_write(APIC_ESR, 0);
1792
1793 v = apic_read(APIC_ESR);
1794 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1795 }
1796
1797 icr = apic_icr_read();
1798 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1799 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1800
1801 v = apic_read(APIC_LVTT);
1802 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1803
1804 if (maxlvt > 3) { /* PC is LVT#4. */
1805 v = apic_read(APIC_LVTPC);
1806 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1807 }
1808 v = apic_read(APIC_LVT0);
1809 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1810 v = apic_read(APIC_LVT1);
1811 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1812
1813 if (maxlvt > 2) { /* ERR is LVT#3. */
1814 v = apic_read(APIC_LVTERR);
1815 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1816 }
1817
1818 v = apic_read(APIC_TMICT);
1819 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1820 v = apic_read(APIC_TMCCT);
1821 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1822 v = apic_read(APIC_TDCR);
1823 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1824
1825 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1826 v = apic_read(APIC_EFEAT);
1827 maxlvt = (v >> 16) & 0xff;
1828 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1829 v = apic_read(APIC_ECTRL);
1830 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1831 for (i = 0; i < maxlvt; i++) {
1832 v = apic_read(APIC_EILVTn(i));
1833 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1834 }
1835 }
1836 printk("\n");
1837 }
1838
1839 __apicdebuginit(void) print_all_local_APICs(void)
1840 {
1841 int cpu;
1842
1843 preempt_disable();
1844 for_each_online_cpu(cpu)
1845 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1846 preempt_enable();
1847 }
1848
1849 __apicdebuginit(void) print_PIC(void)
1850 {
1851 unsigned int v;
1852 unsigned long flags;
1853
1854 if (apic_verbosity == APIC_QUIET)
1855 return;
1856
1857 printk(KERN_DEBUG "\nprinting PIC contents\n");
1858
1859 spin_lock_irqsave(&i8259A_lock, flags);
1860
1861 v = inb(0xa1) << 8 | inb(0x21);
1862 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1863
1864 v = inb(0xa0) << 8 | inb(0x20);
1865 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1866
1867 outb(0x0b,0xa0);
1868 outb(0x0b,0x20);
1869 v = inb(0xa0) << 8 | inb(0x20);
1870 outb(0x0a,0xa0);
1871 outb(0x0a,0x20);
1872
1873 spin_unlock_irqrestore(&i8259A_lock, flags);
1874
1875 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1876
1877 v = inb(0x4d1) << 8 | inb(0x4d0);
1878 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1879 }
1880
1881 __apicdebuginit(int) print_all_ICs(void)
1882 {
1883 print_PIC();
1884
1885 /* don't print out if apic is not there */
1886 if (!cpu_has_apic || disable_apic)
1887 return 0;
1888
1889 print_all_local_APICs();
1890 print_IO_APIC();
1891
1892 return 0;
1893 }
1894
1895 fs_initcall(print_all_ICs);
1896
1897
1898 /* Where if anywhere is the i8259 connect in external int mode */
1899 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1900
1901 void __init enable_IO_APIC(void)
1902 {
1903 union IO_APIC_reg_01 reg_01;
1904 int i8259_apic, i8259_pin;
1905 int apic;
1906 unsigned long flags;
1907
1908 /*
1909 * The number of IO-APIC IRQ registers (== #pins):
1910 */
1911 for (apic = 0; apic < nr_ioapics; apic++) {
1912 spin_lock_irqsave(&ioapic_lock, flags);
1913 reg_01.raw = io_apic_read(apic, 1);
1914 spin_unlock_irqrestore(&ioapic_lock, flags);
1915 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1916 }
1917 for(apic = 0; apic < nr_ioapics; apic++) {
1918 int pin;
1919 /* See if any of the pins is in ExtINT mode */
1920 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1921 struct IO_APIC_route_entry entry;
1922 entry = ioapic_read_entry(apic, pin);
1923
1924 /* If the interrupt line is enabled and in ExtInt mode
1925 * I have found the pin where the i8259 is connected.
1926 */
1927 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1928 ioapic_i8259.apic = apic;
1929 ioapic_i8259.pin = pin;
1930 goto found_i8259;
1931 }
1932 }
1933 }
1934 found_i8259:
1935 /* Look to see what if the MP table has reported the ExtINT */
1936 /* If we could not find the appropriate pin by looking at the ioapic
1937 * the i8259 probably is not connected the ioapic but give the
1938 * mptable a chance anyway.
1939 */
1940 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1941 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1942 /* Trust the MP table if nothing is setup in the hardware */
1943 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1944 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1945 ioapic_i8259.pin = i8259_pin;
1946 ioapic_i8259.apic = i8259_apic;
1947 }
1948 /* Complain if the MP table and the hardware disagree */
1949 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1950 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1951 {
1952 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1953 }
1954
1955 /*
1956 * Do not trust the IO-APIC being empty at bootup
1957 */
1958 clear_IO_APIC();
1959 }
1960
1961 /*
1962 * Not an __init, needed by the reboot code
1963 */
1964 void disable_IO_APIC(void)
1965 {
1966 /*
1967 * Clear the IO-APIC before rebooting:
1968 */
1969 clear_IO_APIC();
1970
1971 /*
1972 * If the i8259 is routed through an IOAPIC
1973 * Put that IOAPIC in virtual wire mode
1974 * so legacy interrupts can be delivered.
1975 *
1976 * With interrupt-remapping, for now we will use virtual wire A mode,
1977 * as virtual wire B is little complex (need to configure both
1978 * IOAPIC RTE aswell as interrupt-remapping table entry).
1979 * As this gets called during crash dump, keep this simple for now.
1980 */
1981 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1982 struct IO_APIC_route_entry entry;
1983
1984 memset(&entry, 0, sizeof(entry));
1985 entry.mask = 0; /* Enabled */
1986 entry.trigger = 0; /* Edge */
1987 entry.irr = 0;
1988 entry.polarity = 0; /* High */
1989 entry.delivery_status = 0;
1990 entry.dest_mode = 0; /* Physical */
1991 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1992 entry.vector = 0;
1993 entry.dest = read_apic_id();
1994
1995 /*
1996 * Add it to the IO-APIC irq-routing table:
1997 */
1998 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1999 }
2000
2001 /*
2002 * Use virtual wire A mode when interrupt remapping is enabled.
2003 */
2004 if (cpu_has_apic)
2005 disconnect_bsp_APIC(!intr_remapping_enabled &&
2006 ioapic_i8259.pin != -1);
2007 }
2008
2009 #ifdef CONFIG_X86_32
2010 /*
2011 * function to set the IO-APIC physical IDs based on the
2012 * values stored in the MPC table.
2013 *
2014 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2015 */
2016
2017 static void __init setup_ioapic_ids_from_mpc(void)
2018 {
2019 union IO_APIC_reg_00 reg_00;
2020 physid_mask_t phys_id_present_map;
2021 int apic_id;
2022 int i;
2023 unsigned char old_id;
2024 unsigned long flags;
2025
2026 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2027 return;
2028
2029 /*
2030 * Don't check I/O APIC IDs for xAPIC systems. They have
2031 * no meaning without the serial APIC bus.
2032 */
2033 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2034 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2035 return;
2036 /*
2037 * This is broken; anything with a real cpu count has to
2038 * circumvent this idiocy regardless.
2039 */
2040 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2041
2042 /*
2043 * Set the IOAPIC ID to the value stored in the MPC table.
2044 */
2045 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2046
2047 /* Read the register 0 value */
2048 spin_lock_irqsave(&ioapic_lock, flags);
2049 reg_00.raw = io_apic_read(apic_id, 0);
2050 spin_unlock_irqrestore(&ioapic_lock, flags);
2051
2052 old_id = mp_ioapics[apic_id].apicid;
2053
2054 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2055 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2056 apic_id, mp_ioapics[apic_id].apicid);
2057 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2058 reg_00.bits.ID);
2059 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2060 }
2061
2062 /*
2063 * Sanity check, is the ID really free? Every APIC in a
2064 * system must have a unique ID or we get lots of nice
2065 * 'stuck on smp_invalidate_needed IPI wait' messages.
2066 */
2067 if (apic->check_apicid_used(phys_id_present_map,
2068 mp_ioapics[apic_id].apicid)) {
2069 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2070 apic_id, mp_ioapics[apic_id].apicid);
2071 for (i = 0; i < get_physical_broadcast(); i++)
2072 if (!physid_isset(i, phys_id_present_map))
2073 break;
2074 if (i >= get_physical_broadcast())
2075 panic("Max APIC ID exceeded!\n");
2076 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2077 i);
2078 physid_set(i, phys_id_present_map);
2079 mp_ioapics[apic_id].apicid = i;
2080 } else {
2081 physid_mask_t tmp;
2082 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2083 apic_printk(APIC_VERBOSE, "Setting %d in the "
2084 "phys_id_present_map\n",
2085 mp_ioapics[apic_id].apicid);
2086 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2087 }
2088
2089
2090 /*
2091 * We need to adjust the IRQ routing table
2092 * if the ID changed.
2093 */
2094 if (old_id != mp_ioapics[apic_id].apicid)
2095 for (i = 0; i < mp_irq_entries; i++)
2096 if (mp_irqs[i].dstapic == old_id)
2097 mp_irqs[i].dstapic
2098 = mp_ioapics[apic_id].apicid;
2099
2100 /*
2101 * Read the right value from the MPC table and
2102 * write it into the ID register.
2103 */
2104 apic_printk(APIC_VERBOSE, KERN_INFO
2105 "...changing IO-APIC physical APIC ID to %d ...",
2106 mp_ioapics[apic_id].apicid);
2107
2108 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2109 spin_lock_irqsave(&ioapic_lock, flags);
2110 io_apic_write(apic_id, 0, reg_00.raw);
2111 spin_unlock_irqrestore(&ioapic_lock, flags);
2112
2113 /*
2114 * Sanity check
2115 */
2116 spin_lock_irqsave(&ioapic_lock, flags);
2117 reg_00.raw = io_apic_read(apic_id, 0);
2118 spin_unlock_irqrestore(&ioapic_lock, flags);
2119 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2120 printk("could not set ID!\n");
2121 else
2122 apic_printk(APIC_VERBOSE, " ok.\n");
2123 }
2124 }
2125 #endif
2126
2127 int no_timer_check __initdata;
2128
2129 static int __init notimercheck(char *s)
2130 {
2131 no_timer_check = 1;
2132 return 1;
2133 }
2134 __setup("no_timer_check", notimercheck);
2135
2136 /*
2137 * There is a nasty bug in some older SMP boards, their mptable lies
2138 * about the timer IRQ. We do the following to work around the situation:
2139 *
2140 * - timer IRQ defaults to IO-APIC IRQ
2141 * - if this function detects that timer IRQs are defunct, then we fall
2142 * back to ISA timer IRQs
2143 */
2144 static int __init timer_irq_works(void)
2145 {
2146 unsigned long t1 = jiffies;
2147 unsigned long flags;
2148
2149 if (no_timer_check)
2150 return 1;
2151
2152 local_save_flags(flags);
2153 local_irq_enable();
2154 /* Let ten ticks pass... */
2155 mdelay((10 * 1000) / HZ);
2156 local_irq_restore(flags);
2157
2158 /*
2159 * Expect a few ticks at least, to be sure some possible
2160 * glue logic does not lock up after one or two first
2161 * ticks in a non-ExtINT mode. Also the local APIC
2162 * might have cached one ExtINT interrupt. Finally, at
2163 * least one tick may be lost due to delays.
2164 */
2165
2166 /* jiffies wrap? */
2167 if (time_after(jiffies, t1 + 4))
2168 return 1;
2169 return 0;
2170 }
2171
2172 /*
2173 * In the SMP+IOAPIC case it might happen that there are an unspecified
2174 * number of pending IRQ events unhandled. These cases are very rare,
2175 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2176 * better to do it this way as thus we do not have to be aware of
2177 * 'pending' interrupts in the IRQ path, except at this point.
2178 */
2179 /*
2180 * Edge triggered needs to resend any interrupt
2181 * that was delayed but this is now handled in the device
2182 * independent code.
2183 */
2184
2185 /*
2186 * Starting up a edge-triggered IO-APIC interrupt is
2187 * nasty - we need to make sure that we get the edge.
2188 * If it is already asserted for some reason, we need
2189 * return 1 to indicate that is was pending.
2190 *
2191 * This is not complete - we should be able to fake
2192 * an edge even if it isn't on the 8259A...
2193 */
2194
2195 static unsigned int startup_ioapic_irq(unsigned int irq)
2196 {
2197 int was_pending = 0;
2198 unsigned long flags;
2199 struct irq_cfg *cfg;
2200
2201 spin_lock_irqsave(&ioapic_lock, flags);
2202 if (irq < NR_IRQS_LEGACY) {
2203 disable_8259A_irq(irq);
2204 if (i8259A_irq_pending(irq))
2205 was_pending = 1;
2206 }
2207 cfg = irq_cfg(irq);
2208 __unmask_IO_APIC_irq(cfg);
2209 spin_unlock_irqrestore(&ioapic_lock, flags);
2210
2211 return was_pending;
2212 }
2213
2214 #ifdef CONFIG_X86_64
2215 static int ioapic_retrigger_irq(unsigned int irq)
2216 {
2217
2218 struct irq_cfg *cfg = irq_cfg(irq);
2219 unsigned long flags;
2220
2221 spin_lock_irqsave(&vector_lock, flags);
2222 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2223 spin_unlock_irqrestore(&vector_lock, flags);
2224
2225 return 1;
2226 }
2227 #else
2228 static int ioapic_retrigger_irq(unsigned int irq)
2229 {
2230 apic->send_IPI_self(irq_cfg(irq)->vector);
2231
2232 return 1;
2233 }
2234 #endif
2235
2236 /*
2237 * Level and edge triggered IO-APIC interrupts need different handling,
2238 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2239 * handled with the level-triggered descriptor, but that one has slightly
2240 * more overhead. Level-triggered interrupts cannot be handled with the
2241 * edge-triggered handler, without risking IRQ storms and other ugly
2242 * races.
2243 */
2244
2245 #ifdef CONFIG_SMP
2246 static void send_cleanup_vector(struct irq_cfg *cfg)
2247 {
2248 cpumask_var_t cleanup_mask;
2249
2250 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2251 unsigned int i;
2252 cfg->move_cleanup_count = 0;
2253 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2254 cfg->move_cleanup_count++;
2255 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2256 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2257 } else {
2258 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2259 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2260 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2261 free_cpumask_var(cleanup_mask);
2262 }
2263 cfg->move_in_progress = 0;
2264 }
2265
2266 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2267 {
2268 int apic, pin;
2269 struct irq_pin_list *entry;
2270 u8 vector = cfg->vector;
2271
2272 entry = cfg->irq_2_pin;
2273 for (;;) {
2274 unsigned int reg;
2275
2276 if (!entry)
2277 break;
2278
2279 apic = entry->apic;
2280 pin = entry->pin;
2281 /*
2282 * With interrupt-remapping, destination information comes
2283 * from interrupt-remapping table entry.
2284 */
2285 if (!irq_remapped(irq))
2286 io_apic_write(apic, 0x11 + pin*2, dest);
2287 reg = io_apic_read(apic, 0x10 + pin*2);
2288 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2289 reg |= vector;
2290 io_apic_modify(apic, 0x10 + pin*2, reg);
2291 if (!entry->next)
2292 break;
2293 entry = entry->next;
2294 }
2295 }
2296
2297 static int
2298 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2299
2300 /*
2301 * Either sets desc->affinity to a valid value, and returns
2302 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2303 * leaves desc->affinity untouched.
2304 */
2305 static unsigned int
2306 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2307 {
2308 struct irq_cfg *cfg;
2309 unsigned int irq;
2310
2311 if (!cpumask_intersects(mask, cpu_online_mask))
2312 return BAD_APICID;
2313
2314 irq = desc->irq;
2315 cfg = desc->chip_data;
2316 if (assign_irq_vector(irq, cfg, mask))
2317 return BAD_APICID;
2318
2319 cpumask_copy(desc->affinity, mask);
2320
2321 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2322 }
2323
2324 static int
2325 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2326 {
2327 struct irq_cfg *cfg;
2328 unsigned long flags;
2329 unsigned int dest;
2330 unsigned int irq;
2331 int ret = -1;
2332
2333 irq = desc->irq;
2334 cfg = desc->chip_data;
2335
2336 spin_lock_irqsave(&ioapic_lock, flags);
2337 dest = set_desc_affinity(desc, mask);
2338 if (dest != BAD_APICID) {
2339 /* Only the high 8 bits are valid. */
2340 dest = SET_APIC_LOGICAL_ID(dest);
2341 __target_IO_APIC_irq(irq, dest, cfg);
2342 ret = 0;
2343 }
2344 spin_unlock_irqrestore(&ioapic_lock, flags);
2345
2346 return ret;
2347 }
2348
2349 static int
2350 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2351 {
2352 struct irq_desc *desc;
2353
2354 desc = irq_to_desc(irq);
2355
2356 return set_ioapic_affinity_irq_desc(desc, mask);
2357 }
2358
2359 #ifdef CONFIG_INTR_REMAP
2360
2361 /*
2362 * Migrate the IO-APIC irq in the presence of intr-remapping.
2363 *
2364 * For both level and edge triggered, irq migration is a simple atomic
2365 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2366 *
2367 * For level triggered, we eliminate the io-apic RTE modification (with the
2368 * updated vector information), by using a virtual vector (io-apic pin number).
2369 * Real vector that is used for interrupting cpu will be coming from
2370 * the interrupt-remapping table entry.
2371 */
2372 static int
2373 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2374 {
2375 struct irq_cfg *cfg;
2376 struct irte irte;
2377 unsigned int dest;
2378 unsigned int irq;
2379 int ret = -1;
2380
2381 if (!cpumask_intersects(mask, cpu_online_mask))
2382 return ret;
2383
2384 irq = desc->irq;
2385 if (get_irte(irq, &irte))
2386 return ret;
2387
2388 cfg = desc->chip_data;
2389 if (assign_irq_vector(irq, cfg, mask))
2390 return ret;
2391
2392 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2393
2394 irte.vector = cfg->vector;
2395 irte.dest_id = IRTE_DEST(dest);
2396
2397 /*
2398 * Modified the IRTE and flushes the Interrupt entry cache.
2399 */
2400 modify_irte(irq, &irte);
2401
2402 if (cfg->move_in_progress)
2403 send_cleanup_vector(cfg);
2404
2405 cpumask_copy(desc->affinity, mask);
2406
2407 return 0;
2408 }
2409
2410 /*
2411 * Migrates the IRQ destination in the process context.
2412 */
2413 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2414 const struct cpumask *mask)
2415 {
2416 return migrate_ioapic_irq_desc(desc, mask);
2417 }
2418 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2419 const struct cpumask *mask)
2420 {
2421 struct irq_desc *desc = irq_to_desc(irq);
2422
2423 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2424 }
2425 #else
2426 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2427 const struct cpumask *mask)
2428 {
2429 return 0;
2430 }
2431 #endif
2432
2433 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2434 {
2435 unsigned vector, me;
2436
2437 ack_APIC_irq();
2438 exit_idle();
2439 irq_enter();
2440
2441 me = smp_processor_id();
2442 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2443 unsigned int irq;
2444 unsigned int irr;
2445 struct irq_desc *desc;
2446 struct irq_cfg *cfg;
2447 irq = __get_cpu_var(vector_irq)[vector];
2448
2449 if (irq == -1)
2450 continue;
2451
2452 desc = irq_to_desc(irq);
2453 if (!desc)
2454 continue;
2455
2456 cfg = irq_cfg(irq);
2457 spin_lock(&desc->lock);
2458 if (!cfg->move_cleanup_count)
2459 goto unlock;
2460
2461 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2462 goto unlock;
2463
2464 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2465 /*
2466 * Check if the vector that needs to be cleanedup is
2467 * registered at the cpu's IRR. If so, then this is not
2468 * the best time to clean it up. Lets clean it up in the
2469 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2470 * to myself.
2471 */
2472 if (irr & (1 << (vector % 32))) {
2473 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2474 goto unlock;
2475 }
2476 __get_cpu_var(vector_irq)[vector] = -1;
2477 cfg->move_cleanup_count--;
2478 unlock:
2479 spin_unlock(&desc->lock);
2480 }
2481
2482 irq_exit();
2483 }
2484
2485 static void irq_complete_move(struct irq_desc **descp)
2486 {
2487 struct irq_desc *desc = *descp;
2488 struct irq_cfg *cfg = desc->chip_data;
2489 unsigned vector, me;
2490
2491 if (likely(!cfg->move_in_progress))
2492 return;
2493
2494 vector = ~get_irq_regs()->orig_ax;
2495 me = smp_processor_id();
2496
2497 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2498 send_cleanup_vector(cfg);
2499 }
2500 #else
2501 static inline void irq_complete_move(struct irq_desc **descp) {}
2502 #endif
2503
2504 static void ack_apic_edge(unsigned int irq)
2505 {
2506 struct irq_desc *desc = irq_to_desc(irq);
2507
2508 irq_complete_move(&desc);
2509 move_native_irq(irq);
2510 ack_APIC_irq();
2511 }
2512
2513 atomic_t irq_mis_count;
2514
2515 static void ack_apic_level(unsigned int irq)
2516 {
2517 struct irq_desc *desc = irq_to_desc(irq);
2518
2519 #ifdef CONFIG_X86_32
2520 unsigned long v;
2521 int i;
2522 #endif
2523 struct irq_cfg *cfg;
2524 int do_unmask_irq = 0;
2525
2526 irq_complete_move(&desc);
2527 #ifdef CONFIG_GENERIC_PENDING_IRQ
2528 /* If we are moving the irq we need to mask it */
2529 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2530 do_unmask_irq = 1;
2531 mask_IO_APIC_irq_desc(desc);
2532 }
2533 #endif
2534
2535 #ifdef CONFIG_X86_32
2536 /*
2537 * It appears there is an erratum which affects at least version 0x11
2538 * of I/O APIC (that's the 82093AA and cores integrated into various
2539 * chipsets). Under certain conditions a level-triggered interrupt is
2540 * erroneously delivered as edge-triggered one but the respective IRR
2541 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2542 * message but it will never arrive and further interrupts are blocked
2543 * from the source. The exact reason is so far unknown, but the
2544 * phenomenon was observed when two consecutive interrupt requests
2545 * from a given source get delivered to the same CPU and the source is
2546 * temporarily disabled in between.
2547 *
2548 * A workaround is to simulate an EOI message manually. We achieve it
2549 * by setting the trigger mode to edge and then to level when the edge
2550 * trigger mode gets detected in the TMR of a local APIC for a
2551 * level-triggered interrupt. We mask the source for the time of the
2552 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2553 * The idea is from Manfred Spraul. --macro
2554 */
2555 cfg = desc->chip_data;
2556 i = cfg->vector;
2557
2558 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2559 #endif
2560
2561 /*
2562 * We must acknowledge the irq before we move it or the acknowledge will
2563 * not propagate properly.
2564 */
2565 ack_APIC_irq();
2566
2567 /* Now we can move and renable the irq */
2568 if (unlikely(do_unmask_irq)) {
2569 /* Only migrate the irq if the ack has been received.
2570 *
2571 * On rare occasions the broadcast level triggered ack gets
2572 * delayed going to ioapics, and if we reprogram the
2573 * vector while Remote IRR is still set the irq will never
2574 * fire again.
2575 *
2576 * To prevent this scenario we read the Remote IRR bit
2577 * of the ioapic. This has two effects.
2578 * - On any sane system the read of the ioapic will
2579 * flush writes (and acks) going to the ioapic from
2580 * this cpu.
2581 * - We get to see if the ACK has actually been delivered.
2582 *
2583 * Based on failed experiments of reprogramming the
2584 * ioapic entry from outside of irq context starting
2585 * with masking the ioapic entry and then polling until
2586 * Remote IRR was clear before reprogramming the
2587 * ioapic I don't trust the Remote IRR bit to be
2588 * completey accurate.
2589 *
2590 * However there appears to be no other way to plug
2591 * this race, so if the Remote IRR bit is not
2592 * accurate and is causing problems then it is a hardware bug
2593 * and you can go talk to the chipset vendor about it.
2594 */
2595 cfg = desc->chip_data;
2596 if (!io_apic_level_ack_pending(cfg))
2597 move_masked_irq(irq);
2598 unmask_IO_APIC_irq_desc(desc);
2599 }
2600
2601 #ifdef CONFIG_X86_32
2602 if (!(v & (1 << (i & 0x1f)))) {
2603 atomic_inc(&irq_mis_count);
2604 spin_lock(&ioapic_lock);
2605 __mask_and_edge_IO_APIC_irq(cfg);
2606 __unmask_and_level_IO_APIC_irq(cfg);
2607 spin_unlock(&ioapic_lock);
2608 }
2609 #endif
2610 }
2611
2612 #ifdef CONFIG_INTR_REMAP
2613 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2614 {
2615 int apic, pin;
2616 struct irq_pin_list *entry;
2617
2618 entry = cfg->irq_2_pin;
2619 for (;;) {
2620
2621 if (!entry)
2622 break;
2623
2624 apic = entry->apic;
2625 pin = entry->pin;
2626 io_apic_eoi(apic, pin);
2627 entry = entry->next;
2628 }
2629 }
2630
2631 static void
2632 eoi_ioapic_irq(struct irq_desc *desc)
2633 {
2634 struct irq_cfg *cfg;
2635 unsigned long flags;
2636 unsigned int irq;
2637
2638 irq = desc->irq;
2639 cfg = desc->chip_data;
2640
2641 spin_lock_irqsave(&ioapic_lock, flags);
2642 __eoi_ioapic_irq(irq, cfg);
2643 spin_unlock_irqrestore(&ioapic_lock, flags);
2644 }
2645
2646 static void ir_ack_apic_edge(unsigned int irq)
2647 {
2648 ack_APIC_irq();
2649 }
2650
2651 static void ir_ack_apic_level(unsigned int irq)
2652 {
2653 struct irq_desc *desc = irq_to_desc(irq);
2654
2655 ack_APIC_irq();
2656 eoi_ioapic_irq(desc);
2657 }
2658 #endif /* CONFIG_INTR_REMAP */
2659
2660 static struct irq_chip ioapic_chip __read_mostly = {
2661 .name = "IO-APIC",
2662 .startup = startup_ioapic_irq,
2663 .mask = mask_IO_APIC_irq,
2664 .unmask = unmask_IO_APIC_irq,
2665 .ack = ack_apic_edge,
2666 .eoi = ack_apic_level,
2667 #ifdef CONFIG_SMP
2668 .set_affinity = set_ioapic_affinity_irq,
2669 #endif
2670 .retrigger = ioapic_retrigger_irq,
2671 };
2672
2673 static struct irq_chip ir_ioapic_chip __read_mostly = {
2674 .name = "IR-IO-APIC",
2675 .startup = startup_ioapic_irq,
2676 .mask = mask_IO_APIC_irq,
2677 .unmask = unmask_IO_APIC_irq,
2678 #ifdef CONFIG_INTR_REMAP
2679 .ack = ir_ack_apic_edge,
2680 .eoi = ir_ack_apic_level,
2681 #ifdef CONFIG_SMP
2682 .set_affinity = set_ir_ioapic_affinity_irq,
2683 #endif
2684 #endif
2685 .retrigger = ioapic_retrigger_irq,
2686 };
2687
2688 static inline void init_IO_APIC_traps(void)
2689 {
2690 int irq;
2691 struct irq_desc *desc;
2692 struct irq_cfg *cfg;
2693
2694 /*
2695 * NOTE! The local APIC isn't very good at handling
2696 * multiple interrupts at the same interrupt level.
2697 * As the interrupt level is determined by taking the
2698 * vector number and shifting that right by 4, we
2699 * want to spread these out a bit so that they don't
2700 * all fall in the same interrupt level.
2701 *
2702 * Also, we've got to be careful not to trash gate
2703 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2704 */
2705 for_each_irq_desc(irq, desc) {
2706 cfg = desc->chip_data;
2707 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2708 /*
2709 * Hmm.. We don't have an entry for this,
2710 * so default to an old-fashioned 8259
2711 * interrupt if we can..
2712 */
2713 if (irq < NR_IRQS_LEGACY)
2714 make_8259A_irq(irq);
2715 else
2716 /* Strange. Oh, well.. */
2717 desc->chip = &no_irq_chip;
2718 }
2719 }
2720 }
2721
2722 /*
2723 * The local APIC irq-chip implementation:
2724 */
2725
2726 static void mask_lapic_irq(unsigned int irq)
2727 {
2728 unsigned long v;
2729
2730 v = apic_read(APIC_LVT0);
2731 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2732 }
2733
2734 static void unmask_lapic_irq(unsigned int irq)
2735 {
2736 unsigned long v;
2737
2738 v = apic_read(APIC_LVT0);
2739 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2740 }
2741
2742 static void ack_lapic_irq(unsigned int irq)
2743 {
2744 ack_APIC_irq();
2745 }
2746
2747 static struct irq_chip lapic_chip __read_mostly = {
2748 .name = "local-APIC",
2749 .mask = mask_lapic_irq,
2750 .unmask = unmask_lapic_irq,
2751 .ack = ack_lapic_irq,
2752 };
2753
2754 static void lapic_register_intr(int irq, struct irq_desc *desc)
2755 {
2756 desc->status &= ~IRQ_LEVEL;
2757 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2758 "edge");
2759 }
2760
2761 static void __init setup_nmi(void)
2762 {
2763 /*
2764 * Dirty trick to enable the NMI watchdog ...
2765 * We put the 8259A master into AEOI mode and
2766 * unmask on all local APICs LVT0 as NMI.
2767 *
2768 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2769 * is from Maciej W. Rozycki - so we do not have to EOI from
2770 * the NMI handler or the timer interrupt.
2771 */
2772 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2773
2774 enable_NMI_through_LVT0();
2775
2776 apic_printk(APIC_VERBOSE, " done.\n");
2777 }
2778
2779 /*
2780 * This looks a bit hackish but it's about the only one way of sending
2781 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2782 * not support the ExtINT mode, unfortunately. We need to send these
2783 * cycles as some i82489DX-based boards have glue logic that keeps the
2784 * 8259A interrupt line asserted until INTA. --macro
2785 */
2786 static inline void __init unlock_ExtINT_logic(void)
2787 {
2788 int apic, pin, i;
2789 struct IO_APIC_route_entry entry0, entry1;
2790 unsigned char save_control, save_freq_select;
2791
2792 pin = find_isa_irq_pin(8, mp_INT);
2793 if (pin == -1) {
2794 WARN_ON_ONCE(1);
2795 return;
2796 }
2797 apic = find_isa_irq_apic(8, mp_INT);
2798 if (apic == -1) {
2799 WARN_ON_ONCE(1);
2800 return;
2801 }
2802
2803 entry0 = ioapic_read_entry(apic, pin);
2804 clear_IO_APIC_pin(apic, pin);
2805
2806 memset(&entry1, 0, sizeof(entry1));
2807
2808 entry1.dest_mode = 0; /* physical delivery */
2809 entry1.mask = 0; /* unmask IRQ now */
2810 entry1.dest = hard_smp_processor_id();
2811 entry1.delivery_mode = dest_ExtINT;
2812 entry1.polarity = entry0.polarity;
2813 entry1.trigger = 0;
2814 entry1.vector = 0;
2815
2816 ioapic_write_entry(apic, pin, entry1);
2817
2818 save_control = CMOS_READ(RTC_CONTROL);
2819 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2820 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2821 RTC_FREQ_SELECT);
2822 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2823
2824 i = 100;
2825 while (i-- > 0) {
2826 mdelay(10);
2827 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2828 i -= 10;
2829 }
2830
2831 CMOS_WRITE(save_control, RTC_CONTROL);
2832 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2833 clear_IO_APIC_pin(apic, pin);
2834
2835 ioapic_write_entry(apic, pin, entry0);
2836 }
2837
2838 static int disable_timer_pin_1 __initdata;
2839 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2840 static int __init disable_timer_pin_setup(char *arg)
2841 {
2842 disable_timer_pin_1 = 1;
2843 return 0;
2844 }
2845 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2846
2847 int timer_through_8259 __initdata;
2848
2849 /*
2850 * This code may look a bit paranoid, but it's supposed to cooperate with
2851 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2852 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2853 * fanatically on his truly buggy board.
2854 *
2855 * FIXME: really need to revamp this for all platforms.
2856 */
2857 static inline void __init check_timer(void)
2858 {
2859 struct irq_desc *desc = irq_to_desc(0);
2860 struct irq_cfg *cfg = desc->chip_data;
2861 int node = cpu_to_node(boot_cpu_id);
2862 int apic1, pin1, apic2, pin2;
2863 unsigned long flags;
2864 int no_pin1 = 0;
2865
2866 local_irq_save(flags);
2867
2868 /*
2869 * get/set the timer IRQ vector:
2870 */
2871 disable_8259A_irq(0);
2872 assign_irq_vector(0, cfg, apic->target_cpus());
2873
2874 /*
2875 * As IRQ0 is to be enabled in the 8259A, the virtual
2876 * wire has to be disabled in the local APIC. Also
2877 * timer interrupts need to be acknowledged manually in
2878 * the 8259A for the i82489DX when using the NMI
2879 * watchdog as that APIC treats NMIs as level-triggered.
2880 * The AEOI mode will finish them in the 8259A
2881 * automatically.
2882 */
2883 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2884 init_8259A(1);
2885 #ifdef CONFIG_X86_32
2886 {
2887 unsigned int ver;
2888
2889 ver = apic_read(APIC_LVR);
2890 ver = GET_APIC_VERSION(ver);
2891 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2892 }
2893 #endif
2894
2895 pin1 = find_isa_irq_pin(0, mp_INT);
2896 apic1 = find_isa_irq_apic(0, mp_INT);
2897 pin2 = ioapic_i8259.pin;
2898 apic2 = ioapic_i8259.apic;
2899
2900 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2901 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2902 cfg->vector, apic1, pin1, apic2, pin2);
2903
2904 /*
2905 * Some BIOS writers are clueless and report the ExtINTA
2906 * I/O APIC input from the cascaded 8259A as the timer
2907 * interrupt input. So just in case, if only one pin
2908 * was found above, try it both directly and through the
2909 * 8259A.
2910 */
2911 if (pin1 == -1) {
2912 if (intr_remapping_enabled)
2913 panic("BIOS bug: timer not connected to IO-APIC");
2914 pin1 = pin2;
2915 apic1 = apic2;
2916 no_pin1 = 1;
2917 } else if (pin2 == -1) {
2918 pin2 = pin1;
2919 apic2 = apic1;
2920 }
2921
2922 if (pin1 != -1) {
2923 /*
2924 * Ok, does IRQ0 through the IOAPIC work?
2925 */
2926 if (no_pin1) {
2927 add_pin_to_irq_node(cfg, node, apic1, pin1);
2928 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2929 } else {
2930 /* for edge trigger, setup_IO_APIC_irq already
2931 * leave it unmasked.
2932 * so only need to unmask if it is level-trigger
2933 * do we really have level trigger timer?
2934 */
2935 int idx;
2936 idx = find_irq_entry(apic1, pin1, mp_INT);
2937 if (idx != -1 && irq_trigger(idx))
2938 unmask_IO_APIC_irq_desc(desc);
2939 }
2940 if (timer_irq_works()) {
2941 if (nmi_watchdog == NMI_IO_APIC) {
2942 setup_nmi();
2943 enable_8259A_irq(0);
2944 }
2945 if (disable_timer_pin_1 > 0)
2946 clear_IO_APIC_pin(0, pin1);
2947 goto out;
2948 }
2949 if (intr_remapping_enabled)
2950 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2951 local_irq_disable();
2952 clear_IO_APIC_pin(apic1, pin1);
2953 if (!no_pin1)
2954 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2955 "8254 timer not connected to IO-APIC\n");
2956
2957 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2958 "(IRQ0) through the 8259A ...\n");
2959 apic_printk(APIC_QUIET, KERN_INFO
2960 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2961 /*
2962 * legacy devices should be connected to IO APIC #0
2963 */
2964 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2965 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2966 enable_8259A_irq(0);
2967 if (timer_irq_works()) {
2968 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2969 timer_through_8259 = 1;
2970 if (nmi_watchdog == NMI_IO_APIC) {
2971 disable_8259A_irq(0);
2972 setup_nmi();
2973 enable_8259A_irq(0);
2974 }
2975 goto out;
2976 }
2977 /*
2978 * Cleanup, just in case ...
2979 */
2980 local_irq_disable();
2981 disable_8259A_irq(0);
2982 clear_IO_APIC_pin(apic2, pin2);
2983 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2984 }
2985
2986 if (nmi_watchdog == NMI_IO_APIC) {
2987 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2988 "through the IO-APIC - disabling NMI Watchdog!\n");
2989 nmi_watchdog = NMI_NONE;
2990 }
2991 #ifdef CONFIG_X86_32
2992 timer_ack = 0;
2993 #endif
2994
2995 apic_printk(APIC_QUIET, KERN_INFO
2996 "...trying to set up timer as Virtual Wire IRQ...\n");
2997
2998 lapic_register_intr(0, desc);
2999 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3000 enable_8259A_irq(0);
3001
3002 if (timer_irq_works()) {
3003 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3004 goto out;
3005 }
3006 local_irq_disable();
3007 disable_8259A_irq(0);
3008 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3009 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3010
3011 apic_printk(APIC_QUIET, KERN_INFO
3012 "...trying to set up timer as ExtINT IRQ...\n");
3013
3014 init_8259A(0);
3015 make_8259A_irq(0);
3016 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3017
3018 unlock_ExtINT_logic();
3019
3020 if (timer_irq_works()) {
3021 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3022 goto out;
3023 }
3024 local_irq_disable();
3025 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3026 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3027 "report. Then try booting with the 'noapic' option.\n");
3028 out:
3029 local_irq_restore(flags);
3030 }
3031
3032 /*
3033 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3034 * to devices. However there may be an I/O APIC pin available for
3035 * this interrupt regardless. The pin may be left unconnected, but
3036 * typically it will be reused as an ExtINT cascade interrupt for
3037 * the master 8259A. In the MPS case such a pin will normally be
3038 * reported as an ExtINT interrupt in the MP table. With ACPI
3039 * there is no provision for ExtINT interrupts, and in the absence
3040 * of an override it would be treated as an ordinary ISA I/O APIC
3041 * interrupt, that is edge-triggered and unmasked by default. We
3042 * used to do this, but it caused problems on some systems because
3043 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3044 * the same ExtINT cascade interrupt to drive the local APIC of the
3045 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3046 * the I/O APIC in all cases now. No actual device should request
3047 * it anyway. --macro
3048 */
3049 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3050
3051 void __init setup_IO_APIC(void)
3052 {
3053
3054 /*
3055 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3056 */
3057
3058 io_apic_irqs = ~PIC_IRQS;
3059
3060 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3061 /*
3062 * Set up IO-APIC IRQ routing.
3063 */
3064 #ifdef CONFIG_X86_32
3065 if (!acpi_ioapic)
3066 setup_ioapic_ids_from_mpc();
3067 #endif
3068 sync_Arb_IDs();
3069 setup_IO_APIC_irqs();
3070 init_IO_APIC_traps();
3071 check_timer();
3072 }
3073
3074 /*
3075 * Called after all the initialization is done. If we didnt find any
3076 * APIC bugs then we can allow the modify fast path
3077 */
3078
3079 static int __init io_apic_bug_finalize(void)
3080 {
3081 if (sis_apic_bug == -1)
3082 sis_apic_bug = 0;
3083 return 0;
3084 }
3085
3086 late_initcall(io_apic_bug_finalize);
3087
3088 struct sysfs_ioapic_data {
3089 struct sys_device dev;
3090 struct IO_APIC_route_entry entry[0];
3091 };
3092 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3093
3094 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3095 {
3096 struct IO_APIC_route_entry *entry;
3097 struct sysfs_ioapic_data *data;
3098 int i;
3099
3100 data = container_of(dev, struct sysfs_ioapic_data, dev);
3101 entry = data->entry;
3102 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3103 *entry = ioapic_read_entry(dev->id, i);
3104
3105 return 0;
3106 }
3107
3108 static int ioapic_resume(struct sys_device *dev)
3109 {
3110 struct IO_APIC_route_entry *entry;
3111 struct sysfs_ioapic_data *data;
3112 unsigned long flags;
3113 union IO_APIC_reg_00 reg_00;
3114 int i;
3115
3116 data = container_of(dev, struct sysfs_ioapic_data, dev);
3117 entry = data->entry;
3118
3119 spin_lock_irqsave(&ioapic_lock, flags);
3120 reg_00.raw = io_apic_read(dev->id, 0);
3121 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3122 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3123 io_apic_write(dev->id, 0, reg_00.raw);
3124 }
3125 spin_unlock_irqrestore(&ioapic_lock, flags);
3126 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3127 ioapic_write_entry(dev->id, i, entry[i]);
3128
3129 return 0;
3130 }
3131
3132 static struct sysdev_class ioapic_sysdev_class = {
3133 .name = "ioapic",
3134 .suspend = ioapic_suspend,
3135 .resume = ioapic_resume,
3136 };
3137
3138 static int __init ioapic_init_sysfs(void)
3139 {
3140 struct sys_device * dev;
3141 int i, size, error;
3142
3143 error = sysdev_class_register(&ioapic_sysdev_class);
3144 if (error)
3145 return error;
3146
3147 for (i = 0; i < nr_ioapics; i++ ) {
3148 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3149 * sizeof(struct IO_APIC_route_entry);
3150 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3151 if (!mp_ioapic_data[i]) {
3152 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3153 continue;
3154 }
3155 dev = &mp_ioapic_data[i]->dev;
3156 dev->id = i;
3157 dev->cls = &ioapic_sysdev_class;
3158 error = sysdev_register(dev);
3159 if (error) {
3160 kfree(mp_ioapic_data[i]);
3161 mp_ioapic_data[i] = NULL;
3162 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3163 continue;
3164 }
3165 }
3166
3167 return 0;
3168 }
3169
3170 device_initcall(ioapic_init_sysfs);
3171
3172 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3173 /*
3174 * Dynamic irq allocate and deallocation
3175 */
3176 unsigned int create_irq_nr(unsigned int irq_want, int node)
3177 {
3178 /* Allocate an unused irq */
3179 unsigned int irq;
3180 unsigned int new;
3181 unsigned long flags;
3182 struct irq_cfg *cfg_new = NULL;
3183 struct irq_desc *desc_new = NULL;
3184
3185 irq = 0;
3186 if (irq_want < nr_irqs_gsi)
3187 irq_want = nr_irqs_gsi;
3188
3189 spin_lock_irqsave(&vector_lock, flags);
3190 for (new = irq_want; new < nr_irqs; new++) {
3191 desc_new = irq_to_desc_alloc_node(new, node);
3192 if (!desc_new) {
3193 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3194 continue;
3195 }
3196 cfg_new = desc_new->chip_data;
3197
3198 if (cfg_new->vector != 0)
3199 continue;
3200
3201 desc_new = move_irq_desc(desc_new, node);
3202
3203 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3204 irq = new;
3205 break;
3206 }
3207 spin_unlock_irqrestore(&vector_lock, flags);
3208
3209 if (irq > 0) {
3210 dynamic_irq_init(irq);
3211 /* restore it, in case dynamic_irq_init clear it */
3212 if (desc_new)
3213 desc_new->chip_data = cfg_new;
3214 }
3215 return irq;
3216 }
3217
3218 int create_irq(void)
3219 {
3220 int node = cpu_to_node(boot_cpu_id);
3221 unsigned int irq_want;
3222 int irq;
3223
3224 irq_want = nr_irqs_gsi;
3225 irq = create_irq_nr(irq_want, node);
3226
3227 if (irq == 0)
3228 irq = -1;
3229
3230 return irq;
3231 }
3232
3233 void destroy_irq(unsigned int irq)
3234 {
3235 unsigned long flags;
3236 struct irq_cfg *cfg;
3237 struct irq_desc *desc;
3238
3239 /* store it, in case dynamic_irq_cleanup clear it */
3240 desc = irq_to_desc(irq);
3241 cfg = desc->chip_data;
3242 dynamic_irq_cleanup(irq);
3243 /* connect back irq_cfg */
3244 if (desc)
3245 desc->chip_data = cfg;
3246
3247 free_irte(irq);
3248 spin_lock_irqsave(&vector_lock, flags);
3249 __clear_irq_vector(irq, cfg);
3250 spin_unlock_irqrestore(&vector_lock, flags);
3251 }
3252
3253 /*
3254 * MSI message composition
3255 */
3256 #ifdef CONFIG_PCI_MSI
3257 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3258 {
3259 struct irq_cfg *cfg;
3260 int err;
3261 unsigned dest;
3262
3263 if (disable_apic)
3264 return -ENXIO;
3265
3266 cfg = irq_cfg(irq);
3267 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3268 if (err)
3269 return err;
3270
3271 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3272
3273 if (irq_remapped(irq)) {
3274 struct irte irte;
3275 int ir_index;
3276 u16 sub_handle;
3277
3278 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3279 BUG_ON(ir_index == -1);
3280
3281 memset (&irte, 0, sizeof(irte));
3282
3283 irte.present = 1;
3284 irte.dst_mode = apic->irq_dest_mode;
3285 irte.trigger_mode = 0; /* edge */
3286 irte.dlvry_mode = apic->irq_delivery_mode;
3287 irte.vector = cfg->vector;
3288 irte.dest_id = IRTE_DEST(dest);
3289
3290 /* Set source-id of interrupt request */
3291 set_msi_sid(&irte, pdev);
3292
3293 modify_irte(irq, &irte);
3294
3295 msg->address_hi = MSI_ADDR_BASE_HI;
3296 msg->data = sub_handle;
3297 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3298 MSI_ADDR_IR_SHV |
3299 MSI_ADDR_IR_INDEX1(ir_index) |
3300 MSI_ADDR_IR_INDEX2(ir_index);
3301 } else {
3302 if (x2apic_enabled())
3303 msg->address_hi = MSI_ADDR_BASE_HI |
3304 MSI_ADDR_EXT_DEST_ID(dest);
3305 else
3306 msg->address_hi = MSI_ADDR_BASE_HI;
3307
3308 msg->address_lo =
3309 MSI_ADDR_BASE_LO |
3310 ((apic->irq_dest_mode == 0) ?
3311 MSI_ADDR_DEST_MODE_PHYSICAL:
3312 MSI_ADDR_DEST_MODE_LOGICAL) |
3313 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3314 MSI_ADDR_REDIRECTION_CPU:
3315 MSI_ADDR_REDIRECTION_LOWPRI) |
3316 MSI_ADDR_DEST_ID(dest);
3317
3318 msg->data =
3319 MSI_DATA_TRIGGER_EDGE |
3320 MSI_DATA_LEVEL_ASSERT |
3321 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3322 MSI_DATA_DELIVERY_FIXED:
3323 MSI_DATA_DELIVERY_LOWPRI) |
3324 MSI_DATA_VECTOR(cfg->vector);
3325 }
3326 return err;
3327 }
3328
3329 #ifdef CONFIG_SMP
3330 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3331 {
3332 struct irq_desc *desc = irq_to_desc(irq);
3333 struct irq_cfg *cfg;
3334 struct msi_msg msg;
3335 unsigned int dest;
3336
3337 dest = set_desc_affinity(desc, mask);
3338 if (dest == BAD_APICID)
3339 return -1;
3340
3341 cfg = desc->chip_data;
3342
3343 read_msi_msg_desc(desc, &msg);
3344
3345 msg.data &= ~MSI_DATA_VECTOR_MASK;
3346 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3347 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3348 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3349
3350 write_msi_msg_desc(desc, &msg);
3351
3352 return 0;
3353 }
3354 #ifdef CONFIG_INTR_REMAP
3355 /*
3356 * Migrate the MSI irq to another cpumask. This migration is
3357 * done in the process context using interrupt-remapping hardware.
3358 */
3359 static int
3360 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3361 {
3362 struct irq_desc *desc = irq_to_desc(irq);
3363 struct irq_cfg *cfg = desc->chip_data;
3364 unsigned int dest;
3365 struct irte irte;
3366
3367 if (get_irte(irq, &irte))
3368 return -1;
3369
3370 dest = set_desc_affinity(desc, mask);
3371 if (dest == BAD_APICID)
3372 return -1;
3373
3374 irte.vector = cfg->vector;
3375 irte.dest_id = IRTE_DEST(dest);
3376
3377 /*
3378 * atomically update the IRTE with the new destination and vector.
3379 */
3380 modify_irte(irq, &irte);
3381
3382 /*
3383 * After this point, all the interrupts will start arriving
3384 * at the new destination. So, time to cleanup the previous
3385 * vector allocation.
3386 */
3387 if (cfg->move_in_progress)
3388 send_cleanup_vector(cfg);
3389
3390 return 0;
3391 }
3392
3393 #endif
3394 #endif /* CONFIG_SMP */
3395
3396 /*
3397 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3398 * which implement the MSI or MSI-X Capability Structure.
3399 */
3400 static struct irq_chip msi_chip = {
3401 .name = "PCI-MSI",
3402 .unmask = unmask_msi_irq,
3403 .mask = mask_msi_irq,
3404 .ack = ack_apic_edge,
3405 #ifdef CONFIG_SMP
3406 .set_affinity = set_msi_irq_affinity,
3407 #endif
3408 .retrigger = ioapic_retrigger_irq,
3409 };
3410
3411 static struct irq_chip msi_ir_chip = {
3412 .name = "IR-PCI-MSI",
3413 .unmask = unmask_msi_irq,
3414 .mask = mask_msi_irq,
3415 #ifdef CONFIG_INTR_REMAP
3416 .ack = ir_ack_apic_edge,
3417 #ifdef CONFIG_SMP
3418 .set_affinity = ir_set_msi_irq_affinity,
3419 #endif
3420 #endif
3421 .retrigger = ioapic_retrigger_irq,
3422 };
3423
3424 /*
3425 * Map the PCI dev to the corresponding remapping hardware unit
3426 * and allocate 'nvec' consecutive interrupt-remapping table entries
3427 * in it.
3428 */
3429 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3430 {
3431 struct intel_iommu *iommu;
3432 int index;
3433
3434 iommu = map_dev_to_ir(dev);
3435 if (!iommu) {
3436 printk(KERN_ERR
3437 "Unable to map PCI %s to iommu\n", pci_name(dev));
3438 return -ENOENT;
3439 }
3440
3441 index = alloc_irte(iommu, irq, nvec);
3442 if (index < 0) {
3443 printk(KERN_ERR
3444 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3445 pci_name(dev));
3446 return -ENOSPC;
3447 }
3448 return index;
3449 }
3450
3451 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3452 {
3453 int ret;
3454 struct msi_msg msg;
3455
3456 ret = msi_compose_msg(dev, irq, &msg);
3457 if (ret < 0)
3458 return ret;
3459
3460 set_irq_msi(irq, msidesc);
3461 write_msi_msg(irq, &msg);
3462
3463 if (irq_remapped(irq)) {
3464 struct irq_desc *desc = irq_to_desc(irq);
3465 /*
3466 * irq migration in process context
3467 */
3468 desc->status |= IRQ_MOVE_PCNTXT;
3469 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3470 } else
3471 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3472
3473 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3474
3475 return 0;
3476 }
3477
3478 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3479 {
3480 unsigned int irq;
3481 int ret, sub_handle;
3482 struct msi_desc *msidesc;
3483 unsigned int irq_want;
3484 struct intel_iommu *iommu = NULL;
3485 int index = 0;
3486 int node;
3487
3488 /* x86 doesn't support multiple MSI yet */
3489 if (type == PCI_CAP_ID_MSI && nvec > 1)
3490 return 1;
3491
3492 node = dev_to_node(&dev->dev);
3493 irq_want = nr_irqs_gsi;
3494 sub_handle = 0;
3495 list_for_each_entry(msidesc, &dev->msi_list, list) {
3496 irq = create_irq_nr(irq_want, node);
3497 if (irq == 0)
3498 return -1;
3499 irq_want = irq + 1;
3500 if (!intr_remapping_enabled)
3501 goto no_ir;
3502
3503 if (!sub_handle) {
3504 /*
3505 * allocate the consecutive block of IRTE's
3506 * for 'nvec'
3507 */
3508 index = msi_alloc_irte(dev, irq, nvec);
3509 if (index < 0) {
3510 ret = index;
3511 goto error;
3512 }
3513 } else {
3514 iommu = map_dev_to_ir(dev);
3515 if (!iommu) {
3516 ret = -ENOENT;
3517 goto error;
3518 }
3519 /*
3520 * setup the mapping between the irq and the IRTE
3521 * base index, the sub_handle pointing to the
3522 * appropriate interrupt remap table entry.
3523 */
3524 set_irte_irq(irq, iommu, index, sub_handle);
3525 }
3526 no_ir:
3527 ret = setup_msi_irq(dev, msidesc, irq);
3528 if (ret < 0)
3529 goto error;
3530 sub_handle++;
3531 }
3532 return 0;
3533
3534 error:
3535 destroy_irq(irq);
3536 return ret;
3537 }
3538
3539 void arch_teardown_msi_irq(unsigned int irq)
3540 {
3541 destroy_irq(irq);
3542 }
3543
3544 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3545 #ifdef CONFIG_SMP
3546 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3547 {
3548 struct irq_desc *desc = irq_to_desc(irq);
3549 struct irq_cfg *cfg;
3550 struct msi_msg msg;
3551 unsigned int dest;
3552
3553 dest = set_desc_affinity(desc, mask);
3554 if (dest == BAD_APICID)
3555 return -1;
3556
3557 cfg = desc->chip_data;
3558
3559 dmar_msi_read(irq, &msg);
3560
3561 msg.data &= ~MSI_DATA_VECTOR_MASK;
3562 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3563 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3564 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3565
3566 dmar_msi_write(irq, &msg);
3567
3568 return 0;
3569 }
3570
3571 #endif /* CONFIG_SMP */
3572
3573 static struct irq_chip dmar_msi_type = {
3574 .name = "DMAR_MSI",
3575 .unmask = dmar_msi_unmask,
3576 .mask = dmar_msi_mask,
3577 .ack = ack_apic_edge,
3578 #ifdef CONFIG_SMP
3579 .set_affinity = dmar_msi_set_affinity,
3580 #endif
3581 .retrigger = ioapic_retrigger_irq,
3582 };
3583
3584 int arch_setup_dmar_msi(unsigned int irq)
3585 {
3586 int ret;
3587 struct msi_msg msg;
3588
3589 ret = msi_compose_msg(NULL, irq, &msg);
3590 if (ret < 0)
3591 return ret;
3592 dmar_msi_write(irq, &msg);
3593 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3594 "edge");
3595 return 0;
3596 }
3597 #endif
3598
3599 #ifdef CONFIG_HPET_TIMER
3600
3601 #ifdef CONFIG_SMP
3602 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3603 {
3604 struct irq_desc *desc = irq_to_desc(irq);
3605 struct irq_cfg *cfg;
3606 struct msi_msg msg;
3607 unsigned int dest;
3608
3609 dest = set_desc_affinity(desc, mask);
3610 if (dest == BAD_APICID)
3611 return -1;
3612
3613 cfg = desc->chip_data;
3614
3615 hpet_msi_read(irq, &msg);
3616
3617 msg.data &= ~MSI_DATA_VECTOR_MASK;
3618 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3619 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3620 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3621
3622 hpet_msi_write(irq, &msg);
3623
3624 return 0;
3625 }
3626
3627 #endif /* CONFIG_SMP */
3628
3629 static struct irq_chip hpet_msi_type = {
3630 .name = "HPET_MSI",
3631 .unmask = hpet_msi_unmask,
3632 .mask = hpet_msi_mask,
3633 .ack = ack_apic_edge,
3634 #ifdef CONFIG_SMP
3635 .set_affinity = hpet_msi_set_affinity,
3636 #endif
3637 .retrigger = ioapic_retrigger_irq,
3638 };
3639
3640 int arch_setup_hpet_msi(unsigned int irq)
3641 {
3642 int ret;
3643 struct msi_msg msg;
3644 struct irq_desc *desc = irq_to_desc(irq);
3645
3646 ret = msi_compose_msg(NULL, irq, &msg);
3647 if (ret < 0)
3648 return ret;
3649
3650 hpet_msi_write(irq, &msg);
3651 desc->status |= IRQ_MOVE_PCNTXT;
3652 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3653 "edge");
3654
3655 return 0;
3656 }
3657 #endif
3658
3659 #endif /* CONFIG_PCI_MSI */
3660 /*
3661 * Hypertransport interrupt support
3662 */
3663 #ifdef CONFIG_HT_IRQ
3664
3665 #ifdef CONFIG_SMP
3666
3667 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3668 {
3669 struct ht_irq_msg msg;
3670 fetch_ht_irq_msg(irq, &msg);
3671
3672 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3673 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3674
3675 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3676 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3677
3678 write_ht_irq_msg(irq, &msg);
3679 }
3680
3681 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3682 {
3683 struct irq_desc *desc = irq_to_desc(irq);
3684 struct irq_cfg *cfg;
3685 unsigned int dest;
3686
3687 dest = set_desc_affinity(desc, mask);
3688 if (dest == BAD_APICID)
3689 return -1;
3690
3691 cfg = desc->chip_data;
3692
3693 target_ht_irq(irq, dest, cfg->vector);
3694
3695 return 0;
3696 }
3697
3698 #endif
3699
3700 static struct irq_chip ht_irq_chip = {
3701 .name = "PCI-HT",
3702 .mask = mask_ht_irq,
3703 .unmask = unmask_ht_irq,
3704 .ack = ack_apic_edge,
3705 #ifdef CONFIG_SMP
3706 .set_affinity = set_ht_irq_affinity,
3707 #endif
3708 .retrigger = ioapic_retrigger_irq,
3709 };
3710
3711 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3712 {
3713 struct irq_cfg *cfg;
3714 int err;
3715
3716 if (disable_apic)
3717 return -ENXIO;
3718
3719 cfg = irq_cfg(irq);
3720 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3721 if (!err) {
3722 struct ht_irq_msg msg;
3723 unsigned dest;
3724
3725 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3726 apic->target_cpus());
3727
3728 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3729
3730 msg.address_lo =
3731 HT_IRQ_LOW_BASE |
3732 HT_IRQ_LOW_DEST_ID(dest) |
3733 HT_IRQ_LOW_VECTOR(cfg->vector) |
3734 ((apic->irq_dest_mode == 0) ?
3735 HT_IRQ_LOW_DM_PHYSICAL :
3736 HT_IRQ_LOW_DM_LOGICAL) |
3737 HT_IRQ_LOW_RQEOI_EDGE |
3738 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3739 HT_IRQ_LOW_MT_FIXED :
3740 HT_IRQ_LOW_MT_ARBITRATED) |
3741 HT_IRQ_LOW_IRQ_MASKED;
3742
3743 write_ht_irq_msg(irq, &msg);
3744
3745 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3746 handle_edge_irq, "edge");
3747
3748 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3749 }
3750 return err;
3751 }
3752 #endif /* CONFIG_HT_IRQ */
3753
3754 #ifdef CONFIG_X86_UV
3755 /*
3756 * Re-target the irq to the specified CPU and enable the specified MMR located
3757 * on the specified blade to allow the sending of MSIs to the specified CPU.
3758 */
3759 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3760 unsigned long mmr_offset)
3761 {
3762 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3763 struct irq_cfg *cfg;
3764 int mmr_pnode;
3765 unsigned long mmr_value;
3766 struct uv_IO_APIC_route_entry *entry;
3767 unsigned long flags;
3768 int err;
3769
3770 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3771
3772 cfg = irq_cfg(irq);
3773
3774 err = assign_irq_vector(irq, cfg, eligible_cpu);
3775 if (err != 0)
3776 return err;
3777
3778 spin_lock_irqsave(&vector_lock, flags);
3779 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3780 irq_name);
3781 spin_unlock_irqrestore(&vector_lock, flags);
3782
3783 mmr_value = 0;
3784 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3785 entry->vector = cfg->vector;
3786 entry->delivery_mode = apic->irq_delivery_mode;
3787 entry->dest_mode = apic->irq_dest_mode;
3788 entry->polarity = 0;
3789 entry->trigger = 0;
3790 entry->mask = 0;
3791 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3792
3793 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3794 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3795
3796 return irq;
3797 }
3798
3799 /*
3800 * Disable the specified MMR located on the specified blade so that MSIs are
3801 * longer allowed to be sent.
3802 */
3803 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3804 {
3805 unsigned long mmr_value;
3806 struct uv_IO_APIC_route_entry *entry;
3807 int mmr_pnode;
3808
3809 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3810
3811 mmr_value = 0;
3812 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3813 entry->mask = 1;
3814
3815 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3816 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3817 }
3818 #endif /* CONFIG_X86_64 */
3819
3820 int __init io_apic_get_redir_entries (int ioapic)
3821 {
3822 union IO_APIC_reg_01 reg_01;
3823 unsigned long flags;
3824
3825 spin_lock_irqsave(&ioapic_lock, flags);
3826 reg_01.raw = io_apic_read(ioapic, 1);
3827 spin_unlock_irqrestore(&ioapic_lock, flags);
3828
3829 return reg_01.bits.entries;
3830 }
3831
3832 void __init probe_nr_irqs_gsi(void)
3833 {
3834 int nr = 0;
3835
3836 nr = acpi_probe_gsi();
3837 if (nr > nr_irqs_gsi) {
3838 nr_irqs_gsi = nr;
3839 } else {
3840 /* for acpi=off or acpi is not compiled in */
3841 int idx;
3842
3843 nr = 0;
3844 for (idx = 0; idx < nr_ioapics; idx++)
3845 nr += io_apic_get_redir_entries(idx) + 1;
3846
3847 if (nr > nr_irqs_gsi)
3848 nr_irqs_gsi = nr;
3849 }
3850
3851 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3852 }
3853
3854 #ifdef CONFIG_SPARSE_IRQ
3855 int __init arch_probe_nr_irqs(void)
3856 {
3857 int nr;
3858
3859 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3860 nr_irqs = NR_VECTORS * nr_cpu_ids;
3861
3862 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3863 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3864 /*
3865 * for MSI and HT dyn irq
3866 */
3867 nr += nr_irqs_gsi * 16;
3868 #endif
3869 if (nr < nr_irqs)
3870 nr_irqs = nr;
3871
3872 return 0;
3873 }
3874 #endif
3875
3876 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3877 struct io_apic_irq_attr *irq_attr)
3878 {
3879 struct irq_desc *desc;
3880 struct irq_cfg *cfg;
3881 int node;
3882 int ioapic, pin;
3883 int trigger, polarity;
3884
3885 ioapic = irq_attr->ioapic;
3886 if (!IO_APIC_IRQ(irq)) {
3887 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3888 ioapic);
3889 return -EINVAL;
3890 }
3891
3892 if (dev)
3893 node = dev_to_node(dev);
3894 else
3895 node = cpu_to_node(boot_cpu_id);
3896
3897 desc = irq_to_desc_alloc_node(irq, node);
3898 if (!desc) {
3899 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3900 return 0;
3901 }
3902
3903 pin = irq_attr->ioapic_pin;
3904 trigger = irq_attr->trigger;
3905 polarity = irq_attr->polarity;
3906
3907 /*
3908 * IRQs < 16 are already in the irq_2_pin[] map
3909 */
3910 if (irq >= NR_IRQS_LEGACY) {
3911 cfg = desc->chip_data;
3912 add_pin_to_irq_node(cfg, node, ioapic, pin);
3913 }
3914
3915 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3916
3917 return 0;
3918 }
3919
3920 int io_apic_set_pci_routing(struct device *dev, int irq,
3921 struct io_apic_irq_attr *irq_attr)
3922 {
3923 int ioapic, pin;
3924 /*
3925 * Avoid pin reprogramming. PRTs typically include entries
3926 * with redundant pin->gsi mappings (but unique PCI devices);
3927 * we only program the IOAPIC on the first.
3928 */
3929 ioapic = irq_attr->ioapic;
3930 pin = irq_attr->ioapic_pin;
3931 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3932 pr_debug("Pin %d-%d already programmed\n",
3933 mp_ioapics[ioapic].apicid, pin);
3934 return 0;
3935 }
3936 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3937
3938 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3939 }
3940
3941 /* --------------------------------------------------------------------------
3942 ACPI-based IOAPIC Configuration
3943 -------------------------------------------------------------------------- */
3944
3945 #ifdef CONFIG_ACPI
3946
3947 #ifdef CONFIG_X86_32
3948 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3949 {
3950 union IO_APIC_reg_00 reg_00;
3951 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3952 physid_mask_t tmp;
3953 unsigned long flags;
3954 int i = 0;
3955
3956 /*
3957 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3958 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3959 * supports up to 16 on one shared APIC bus.
3960 *
3961 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3962 * advantage of new APIC bus architecture.
3963 */
3964
3965 if (physids_empty(apic_id_map))
3966 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3967
3968 spin_lock_irqsave(&ioapic_lock, flags);
3969 reg_00.raw = io_apic_read(ioapic, 0);
3970 spin_unlock_irqrestore(&ioapic_lock, flags);
3971
3972 if (apic_id >= get_physical_broadcast()) {
3973 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3974 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3975 apic_id = reg_00.bits.ID;
3976 }
3977
3978 /*
3979 * Every APIC in a system must have a unique ID or we get lots of nice
3980 * 'stuck on smp_invalidate_needed IPI wait' messages.
3981 */
3982 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3983
3984 for (i = 0; i < get_physical_broadcast(); i++) {
3985 if (!apic->check_apicid_used(apic_id_map, i))
3986 break;
3987 }
3988
3989 if (i == get_physical_broadcast())
3990 panic("Max apic_id exceeded!\n");
3991
3992 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3993 "trying %d\n", ioapic, apic_id, i);
3994
3995 apic_id = i;
3996 }
3997
3998 tmp = apic->apicid_to_cpu_present(apic_id);
3999 physids_or(apic_id_map, apic_id_map, tmp);
4000
4001 if (reg_00.bits.ID != apic_id) {
4002 reg_00.bits.ID = apic_id;
4003
4004 spin_lock_irqsave(&ioapic_lock, flags);
4005 io_apic_write(ioapic, 0, reg_00.raw);
4006 reg_00.raw = io_apic_read(ioapic, 0);
4007 spin_unlock_irqrestore(&ioapic_lock, flags);
4008
4009 /* Sanity check */
4010 if (reg_00.bits.ID != apic_id) {
4011 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4012 return -1;
4013 }
4014 }
4015
4016 apic_printk(APIC_VERBOSE, KERN_INFO
4017 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4018
4019 return apic_id;
4020 }
4021 #endif
4022
4023 int __init io_apic_get_version(int ioapic)
4024 {
4025 union IO_APIC_reg_01 reg_01;
4026 unsigned long flags;
4027
4028 spin_lock_irqsave(&ioapic_lock, flags);
4029 reg_01.raw = io_apic_read(ioapic, 1);
4030 spin_unlock_irqrestore(&ioapic_lock, flags);
4031
4032 return reg_01.bits.version;
4033 }
4034
4035 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4036 {
4037 int i;
4038
4039 if (skip_ioapic_setup)
4040 return -1;
4041
4042 for (i = 0; i < mp_irq_entries; i++)
4043 if (mp_irqs[i].irqtype == mp_INT &&
4044 mp_irqs[i].srcbusirq == bus_irq)
4045 break;
4046 if (i >= mp_irq_entries)
4047 return -1;
4048
4049 *trigger = irq_trigger(i);
4050 *polarity = irq_polarity(i);
4051 return 0;
4052 }
4053
4054 #endif /* CONFIG_ACPI */
4055
4056 /*
4057 * This function currently is only a helper for the i386 smp boot process where
4058 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4059 * so mask in all cases should simply be apic->target_cpus()
4060 */
4061 #ifdef CONFIG_SMP
4062 void __init setup_ioapic_dest(void)
4063 {
4064 int pin, ioapic = 0, irq, irq_entry;
4065 struct irq_desc *desc;
4066 const struct cpumask *mask;
4067
4068 if (skip_ioapic_setup == 1)
4069 return;
4070
4071 #ifdef CONFIG_ACPI
4072 if (!acpi_disabled && acpi_ioapic) {
4073 ioapic = mp_find_ioapic(0);
4074 if (ioapic < 0)
4075 ioapic = 0;
4076 }
4077 #endif
4078
4079 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4080 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4081 if (irq_entry == -1)
4082 continue;
4083 irq = pin_2_irq(irq_entry, ioapic, pin);
4084
4085 desc = irq_to_desc(irq);
4086
4087 /*
4088 * Honour affinities which have been set in early boot
4089 */
4090 if (desc->status &
4091 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4092 mask = desc->affinity;
4093 else
4094 mask = apic->target_cpus();
4095
4096 if (intr_remapping_enabled)
4097 set_ir_ioapic_affinity_irq_desc(desc, mask);
4098 else
4099 set_ioapic_affinity_irq_desc(desc, mask);
4100 }
4101
4102 }
4103 #endif
4104
4105 #define IOAPIC_RESOURCE_NAME_SIZE 11
4106
4107 static struct resource *ioapic_resources;
4108
4109 static struct resource * __init ioapic_setup_resources(void)
4110 {
4111 unsigned long n;
4112 struct resource *res;
4113 char *mem;
4114 int i;
4115
4116 if (nr_ioapics <= 0)
4117 return NULL;
4118
4119 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4120 n *= nr_ioapics;
4121
4122 mem = alloc_bootmem(n);
4123 res = (void *)mem;
4124
4125 if (mem != NULL) {
4126 mem += sizeof(struct resource) * nr_ioapics;
4127
4128 for (i = 0; i < nr_ioapics; i++) {
4129 res[i].name = mem;
4130 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4131 sprintf(mem, "IOAPIC %u", i);
4132 mem += IOAPIC_RESOURCE_NAME_SIZE;
4133 }
4134 }
4135
4136 ioapic_resources = res;
4137
4138 return res;
4139 }
4140
4141 void __init ioapic_init_mappings(void)
4142 {
4143 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4144 struct resource *ioapic_res;
4145 int i;
4146
4147 ioapic_res = ioapic_setup_resources();
4148 for (i = 0; i < nr_ioapics; i++) {
4149 if (smp_found_config) {
4150 ioapic_phys = mp_ioapics[i].apicaddr;
4151 #ifdef CONFIG_X86_32
4152 if (!ioapic_phys) {
4153 printk(KERN_ERR
4154 "WARNING: bogus zero IO-APIC "
4155 "address found in MPTABLE, "
4156 "disabling IO/APIC support!\n");
4157 smp_found_config = 0;
4158 skip_ioapic_setup = 1;
4159 goto fake_ioapic_page;
4160 }
4161 #endif
4162 } else {
4163 #ifdef CONFIG_X86_32
4164 fake_ioapic_page:
4165 #endif
4166 ioapic_phys = (unsigned long)
4167 alloc_bootmem_pages(PAGE_SIZE);
4168 ioapic_phys = __pa(ioapic_phys);
4169 }
4170 set_fixmap_nocache(idx, ioapic_phys);
4171 apic_printk(APIC_VERBOSE,
4172 "mapped IOAPIC to %08lx (%08lx)\n",
4173 __fix_to_virt(idx), ioapic_phys);
4174 idx++;
4175
4176 if (ioapic_res != NULL) {
4177 ioapic_res->start = ioapic_phys;
4178 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4179 ioapic_res++;
4180 }
4181 }
4182 }
4183
4184 void __init ioapic_insert_resources(void)
4185 {
4186 int i;
4187 struct resource *r = ioapic_resources;
4188
4189 if (!r) {
4190 if (nr_ioapics > 0)
4191 printk(KERN_ERR
4192 "IO APIC resources couldn't be allocated.\n");
4193 return;
4194 }
4195
4196 for (i = 0; i < nr_ioapics; i++) {
4197 insert_resource(&iomem_resource, r);
4198 r++;
4199 }
4200 }
Linux kernel - Deliverables
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