2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
40 #include <linux/bootmem.h>
41 #include <linux/dmar.h>
42 #include <linux/hpet.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
54 #include <asm/msidef.h>
55 #include <asm/hypertransport.h>
56 #include <asm/setup.h>
57 #include <asm/irq_remapping.h>
59 #include <asm/hw_irq.h>
63 #define __apicdebuginit(type) static type __init
65 #define for_each_irq_pin(entry, head) \
66 for (entry = head; entry; entry = entry->next)
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug
= -1;
74 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
75 static DEFINE_RAW_SPINLOCK(vector_lock
);
77 static struct ioapic
{
79 * # of IRQ routing registers
83 * Saved state during suspend/resume, or while enabling intr-remap.
85 struct IO_APIC_route_entry
*saved_registers
;
87 struct mpc_ioapic mp_config
;
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi gsi_config
;
90 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
91 } ioapics
[MAX_IO_APICS
];
93 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
95 int mpc_ioapic_id(int ioapic_idx
)
97 return ioapics
[ioapic_idx
].mp_config
.apicid
;
100 unsigned int mpc_ioapic_addr(int ioapic_idx
)
102 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
105 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
107 return &ioapics
[ioapic_idx
].gsi_config
;
112 /* The one past the highest gsi number used */
115 /* MP IRQ source entries */
116 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
118 /* # of MP IRQ source entries */
122 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
125 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
128 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
130 int skip_ioapic_setup
;
133 * disable_ioapic_support() - disables ioapic support at runtime
135 void disable_ioapic_support(void)
139 noioapicreroute
= -1;
141 skip_ioapic_setup
= 1;
144 static int __init
parse_noapic(char *str
)
146 /* disable IO-APIC */
147 disable_ioapic_support();
150 early_param("noapic", parse_noapic
);
152 static int io_apic_setup_irq_pin(unsigned int irq
, int node
,
153 struct io_apic_irq_attr
*attr
);
155 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
156 void mp_save_irq(struct mpc_intsrc
*m
)
160 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
161 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
162 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
163 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
165 for (i
= 0; i
< mp_irq_entries
; i
++) {
166 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
170 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
171 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
172 panic("Max # of irq sources exceeded!!\n");
175 struct irq_pin_list
{
177 struct irq_pin_list
*next
;
180 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
182 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
186 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
187 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
189 int __init
arch_early_irq_init(void)
194 if (!legacy_pic
->nr_legacy_irqs
)
197 for (i
= 0; i
< nr_ioapics
; i
++) {
198 ioapics
[i
].saved_registers
=
199 kzalloc(sizeof(struct IO_APIC_route_entry
) *
200 ioapics
[i
].nr_registers
, GFP_KERNEL
);
201 if (!ioapics
[i
].saved_registers
)
202 pr_err("IOAPIC %d: suspend/resume impossible!\n", i
);
206 count
= ARRAY_SIZE(irq_cfgx
);
207 node
= cpu_to_node(0);
209 for (i
= 0; i
< count
; i
++) {
210 irq_set_chip_data(i
, &cfg
[i
]);
211 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
212 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
214 * For legacy IRQ's, start with assigning irq0 to irq15 to
215 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
217 if (i
< legacy_pic
->nr_legacy_irqs
) {
218 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
219 cpumask_setall(cfg
[i
].domain
);
226 static struct irq_cfg
*irq_cfg(unsigned int irq
)
228 return irq_get_chip_data(irq
);
231 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
235 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
238 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
240 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
244 free_cpumask_var(cfg
->domain
);
250 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
254 irq_set_chip_data(at
, NULL
);
255 free_cpumask_var(cfg
->domain
);
256 free_cpumask_var(cfg
->old_domain
);
260 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
262 int res
= irq_alloc_desc_at(at
, node
);
268 cfg
= irq_get_chip_data(at
);
273 cfg
= alloc_irq_cfg(at
, node
);
275 irq_set_chip_data(at
, cfg
);
283 unsigned int unused
[3];
285 unsigned int unused2
[11];
289 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
291 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
292 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
295 void io_apic_eoi(unsigned int apic
, unsigned int vector
)
297 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
298 writel(vector
, &io_apic
->eoi
);
301 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
303 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
304 writel(reg
, &io_apic
->index
);
305 return readl(&io_apic
->data
);
308 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
310 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
312 writel(reg
, &io_apic
->index
);
313 writel(value
, &io_apic
->data
);
317 * Re-write a value: to be used for read-modify-write
318 * cycles where the read already set up the index register.
320 * Older SiS APIC requires we rewrite the index register
322 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
324 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
327 writel(reg
, &io_apic
->index
);
328 writel(value
, &io_apic
->data
);
332 struct { u32 w1
, w2
; };
333 struct IO_APIC_route_entry entry
;
336 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
338 union entry_union eu
;
340 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
341 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
346 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
348 union entry_union eu
;
351 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
352 eu
.entry
= __ioapic_read_entry(apic
, pin
);
353 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
359 * When we write a new IO APIC routing entry, we need to write the high
360 * word first! If the mask bit in the low word is clear, we will enable
361 * the interrupt, and we need to make sure the entry is fully populated
362 * before that happens.
364 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
366 union entry_union eu
= {{0, 0}};
369 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
370 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
373 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
377 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
378 __ioapic_write_entry(apic
, pin
, e
);
379 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
383 * When we mask an IO APIC routing entry, we need to write the low
384 * word first, in order to set the mask bit before we change the
387 static void ioapic_mask_entry(int apic
, int pin
)
390 union entry_union eu
= { .entry
.mask
= 1 };
392 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
393 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
394 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
395 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
399 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
400 * shared ISA-space IRQs, so we have to support them. We are super
401 * fast in the common case, and fast for shared ISA-space IRQs.
403 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
405 struct irq_pin_list
**last
, *entry
;
407 /* don't allow duplicates */
408 last
= &cfg
->irq_2_pin
;
409 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
410 if (entry
->apic
== apic
&& entry
->pin
== pin
)
415 entry
= alloc_irq_pin_list(node
);
417 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
428 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
430 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
431 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
435 * Reroute an IRQ to a different pin.
437 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
438 int oldapic
, int oldpin
,
439 int newapic
, int newpin
)
441 struct irq_pin_list
*entry
;
443 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
444 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
445 entry
->apic
= newapic
;
447 /* every one is different, right? */
452 /* old apic/pin didn't exist, so just add new ones */
453 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
456 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
457 int mask_and
, int mask_or
,
458 void (*final
)(struct irq_pin_list
*entry
))
460 unsigned int reg
, pin
;
463 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
466 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
471 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
472 int mask_and
, int mask_or
,
473 void (*final
)(struct irq_pin_list
*entry
))
475 struct irq_pin_list
*entry
;
477 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
478 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
481 static void io_apic_sync(struct irq_pin_list
*entry
)
484 * Synchronize the IO-APIC and the CPU by doing
485 * a dummy read from the IO-APIC
487 struct io_apic __iomem
*io_apic
;
489 io_apic
= io_apic_base(entry
->apic
);
490 readl(&io_apic
->data
);
493 static void mask_ioapic(struct irq_cfg
*cfg
)
497 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
498 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
499 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
502 static void mask_ioapic_irq(struct irq_data
*data
)
504 mask_ioapic(data
->chip_data
);
507 static void __unmask_ioapic(struct irq_cfg
*cfg
)
509 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
512 static void unmask_ioapic(struct irq_cfg
*cfg
)
516 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
517 __unmask_ioapic(cfg
);
518 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
521 static void unmask_ioapic_irq(struct irq_data
*data
)
523 unmask_ioapic(data
->chip_data
);
527 * IO-APIC versions below 0x20 don't support EOI register.
528 * For the record, here is the information about various versions:
530 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
531 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
534 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
535 * version as 0x2. This is an error with documentation and these ICH chips
536 * use io-apic's of version 0x20.
538 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
539 * Otherwise, we simulate the EOI message manually by changing the trigger
540 * mode to edge and then back to level, with RTE being masked during this.
542 void native_eoi_ioapic_pin(int apic
, int pin
, int vector
)
544 if (mpc_ioapic_ver(apic
) >= 0x20) {
545 io_apic_eoi(apic
, vector
);
547 struct IO_APIC_route_entry entry
, entry1
;
549 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
552 * Mask the entry and change the trigger mode to edge.
555 entry1
.trigger
= IOAPIC_EDGE
;
557 __ioapic_write_entry(apic
, pin
, entry1
);
560 * Restore the previous level triggered entry.
562 __ioapic_write_entry(apic
, pin
, entry
);
566 void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
568 struct irq_pin_list
*entry
;
571 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
572 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
573 x86_io_apic_ops
.eoi_ioapic_pin(entry
->apic
, entry
->pin
,
575 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
578 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
580 struct IO_APIC_route_entry entry
;
582 /* Check delivery_mode to be sure we're not clearing an SMI pin */
583 entry
= ioapic_read_entry(apic
, pin
);
584 if (entry
.delivery_mode
== dest_SMI
)
588 * Make sure the entry is masked and re-read the contents to check
589 * if it is a level triggered pin and if the remote-IRR is set.
593 ioapic_write_entry(apic
, pin
, entry
);
594 entry
= ioapic_read_entry(apic
, pin
);
601 * Make sure the trigger mode is set to level. Explicit EOI
602 * doesn't clear the remote-IRR if the trigger mode is not
605 if (!entry
.trigger
) {
606 entry
.trigger
= IOAPIC_LEVEL
;
607 ioapic_write_entry(apic
, pin
, entry
);
610 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
611 x86_io_apic_ops
.eoi_ioapic_pin(apic
, pin
, entry
.vector
);
612 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
616 * Clear the rest of the bits in the IO-APIC RTE except for the mask
619 ioapic_mask_entry(apic
, pin
);
620 entry
= ioapic_read_entry(apic
, pin
);
622 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
623 mpc_ioapic_id(apic
), pin
);
626 static void clear_IO_APIC (void)
630 for (apic
= 0; apic
< nr_ioapics
; apic
++)
631 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
632 clear_IO_APIC_pin(apic
, pin
);
637 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
638 * specific CPU-side IRQs.
642 static int pirq_entries
[MAX_PIRQS
] = {
643 [0 ... MAX_PIRQS
- 1] = -1
646 static int __init
ioapic_pirq_setup(char *str
)
649 int ints
[MAX_PIRQS
+1];
651 get_options(str
, ARRAY_SIZE(ints
), ints
);
653 apic_printk(APIC_VERBOSE
, KERN_INFO
654 "PIRQ redirection, working around broken MP-BIOS.\n");
656 if (ints
[0] < MAX_PIRQS
)
659 for (i
= 0; i
< max
; i
++) {
660 apic_printk(APIC_VERBOSE
, KERN_DEBUG
661 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
663 * PIRQs are mapped upside down, usually.
665 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
670 __setup("pirq=", ioapic_pirq_setup
);
671 #endif /* CONFIG_X86_32 */
674 * Saves all the IO-APIC RTE's
676 int save_ioapic_entries(void)
681 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
682 if (!ioapics
[apic
].saved_registers
) {
687 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
688 ioapics
[apic
].saved_registers
[pin
] =
689 ioapic_read_entry(apic
, pin
);
696 * Mask all IO APIC entries.
698 void mask_ioapic_entries(void)
702 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
703 if (!ioapics
[apic
].saved_registers
)
706 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
707 struct IO_APIC_route_entry entry
;
709 entry
= ioapics
[apic
].saved_registers
[pin
];
712 ioapic_write_entry(apic
, pin
, entry
);
719 * Restore IO APIC entries which was saved in the ioapic structure.
721 int restore_ioapic_entries(void)
725 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
726 if (!ioapics
[apic
].saved_registers
)
729 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
730 ioapic_write_entry(apic
, pin
,
731 ioapics
[apic
].saved_registers
[pin
]);
737 * Find the IRQ entry number of a certain pin.
739 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
743 for (i
= 0; i
< mp_irq_entries
; i
++)
744 if (mp_irqs
[i
].irqtype
== type
&&
745 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
746 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
747 mp_irqs
[i
].dstirq
== pin
)
754 * Find the pin to which IRQ[irq] (ISA) is connected
756 static int __init
find_isa_irq_pin(int irq
, int type
)
760 for (i
= 0; i
< mp_irq_entries
; i
++) {
761 int lbus
= mp_irqs
[i
].srcbus
;
763 if (test_bit(lbus
, mp_bus_not_pci
) &&
764 (mp_irqs
[i
].irqtype
== type
) &&
765 (mp_irqs
[i
].srcbusirq
== irq
))
767 return mp_irqs
[i
].dstirq
;
772 static int __init
find_isa_irq_apic(int irq
, int type
)
776 for (i
= 0; i
< mp_irq_entries
; i
++) {
777 int lbus
= mp_irqs
[i
].srcbus
;
779 if (test_bit(lbus
, mp_bus_not_pci
) &&
780 (mp_irqs
[i
].irqtype
== type
) &&
781 (mp_irqs
[i
].srcbusirq
== irq
))
785 if (i
< mp_irq_entries
) {
788 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
789 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
798 * EISA Edge/Level control register, ELCR
800 static int EISA_ELCR(unsigned int irq
)
802 if (irq
< legacy_pic
->nr_legacy_irqs
) {
803 unsigned int port
= 0x4d0 + (irq
>> 3);
804 return (inb(port
) >> (irq
& 7)) & 1;
806 apic_printk(APIC_VERBOSE
, KERN_INFO
807 "Broken MPtable reports ISA irq %d\n", irq
);
813 /* ISA interrupts are always polarity zero edge triggered,
814 * when listed as conforming in the MP table. */
816 #define default_ISA_trigger(idx) (0)
817 #define default_ISA_polarity(idx) (0)
819 /* EISA interrupts are always polarity zero and can be edge or level
820 * trigger depending on the ELCR value. If an interrupt is listed as
821 * EISA conforming in the MP table, that means its trigger type must
822 * be read in from the ELCR */
824 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
825 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
827 /* PCI interrupts are always polarity one level triggered,
828 * when listed as conforming in the MP table. */
830 #define default_PCI_trigger(idx) (1)
831 #define default_PCI_polarity(idx) (1)
833 static int irq_polarity(int idx
)
835 int bus
= mp_irqs
[idx
].srcbus
;
839 * Determine IRQ line polarity (high active or low active):
841 switch (mp_irqs
[idx
].irqflag
& 3)
843 case 0: /* conforms, ie. bus-type dependent polarity */
844 if (test_bit(bus
, mp_bus_not_pci
))
845 polarity
= default_ISA_polarity(idx
);
847 polarity
= default_PCI_polarity(idx
);
849 case 1: /* high active */
854 case 2: /* reserved */
856 pr_warn("broken BIOS!!\n");
860 case 3: /* low active */
865 default: /* invalid */
867 pr_warn("broken BIOS!!\n");
875 static int irq_trigger(int idx
)
877 int bus
= mp_irqs
[idx
].srcbus
;
881 * Determine IRQ trigger mode (edge or level sensitive):
883 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
885 case 0: /* conforms, ie. bus-type dependent */
886 if (test_bit(bus
, mp_bus_not_pci
))
887 trigger
= default_ISA_trigger(idx
);
889 trigger
= default_PCI_trigger(idx
);
891 switch (mp_bus_id_to_type
[bus
]) {
892 case MP_BUS_ISA
: /* ISA pin */
894 /* set before the switch */
897 case MP_BUS_EISA
: /* EISA pin */
899 trigger
= default_EISA_trigger(idx
);
902 case MP_BUS_PCI
: /* PCI pin */
904 /* set before the switch */
909 pr_warn("broken BIOS!!\n");
921 case 2: /* reserved */
923 pr_warn("broken BIOS!!\n");
932 default: /* invalid */
934 pr_warn("broken BIOS!!\n");
942 static int pin_2_irq(int idx
, int apic
, int pin
)
945 int bus
= mp_irqs
[idx
].srcbus
;
946 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(apic
);
949 * Debugging check, we are in big trouble if this message pops up!
951 if (mp_irqs
[idx
].dstirq
!= pin
)
952 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
954 if (test_bit(bus
, mp_bus_not_pci
)) {
955 irq
= mp_irqs
[idx
].srcbusirq
;
957 u32 gsi
= gsi_cfg
->gsi_base
+ pin
;
959 if (gsi
>= NR_IRQS_LEGACY
)
967 * PCI IRQ command line redirection. Yes, limits are hardcoded.
969 if ((pin
>= 16) && (pin
<= 23)) {
970 if (pirq_entries
[pin
-16] != -1) {
971 if (!pirq_entries
[pin
-16]) {
972 apic_printk(APIC_VERBOSE
, KERN_DEBUG
973 "disabling PIRQ%d\n", pin
-16);
975 irq
= pirq_entries
[pin
-16];
976 apic_printk(APIC_VERBOSE
, KERN_DEBUG
977 "using PIRQ%d -> IRQ %d\n",
988 * Find a specific PCI IRQ entry.
989 * Not an __init, possibly needed by modules
991 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
992 struct io_apic_irq_attr
*irq_attr
)
994 int ioapic_idx
, i
, best_guess
= -1;
996 apic_printk(APIC_DEBUG
,
997 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
999 if (test_bit(bus
, mp_bus_not_pci
)) {
1000 apic_printk(APIC_VERBOSE
,
1001 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1004 for (i
= 0; i
< mp_irq_entries
; i
++) {
1005 int lbus
= mp_irqs
[i
].srcbus
;
1007 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1008 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1009 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1012 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1013 !mp_irqs
[i
].irqtype
&&
1015 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1016 int irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
);
1018 if (!(ioapic_idx
|| IO_APIC_IRQ(irq
)))
1021 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1022 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1029 * Use the first all-but-pin matching entry as a
1030 * best-guess fuzzy result for broken mptables.
1032 if (best_guess
< 0) {
1033 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1043 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1045 void lock_vector_lock(void)
1047 /* Used to the online set of cpus does not change
1048 * during assign_irq_vector.
1050 raw_spin_lock(&vector_lock
);
1053 void unlock_vector_lock(void)
1055 raw_spin_unlock(&vector_lock
);
1059 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1062 * NOTE! The local APIC isn't very good at handling
1063 * multiple interrupts at the same interrupt level.
1064 * As the interrupt level is determined by taking the
1065 * vector number and shifting that right by 4, we
1066 * want to spread these out a bit so that they don't
1067 * all fall in the same interrupt level.
1069 * Also, we've got to be careful not to trash gate
1070 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1072 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1073 static int current_offset
= VECTOR_OFFSET_START
% 16;
1075 cpumask_var_t tmp_mask
;
1077 if (cfg
->move_in_progress
)
1080 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1083 /* Only try and allocate irqs on cpus that are present */
1085 cpumask_clear(cfg
->old_domain
);
1086 cpu
= cpumask_first_and(mask
, cpu_online_mask
);
1087 while (cpu
< nr_cpu_ids
) {
1088 int new_cpu
, vector
, offset
;
1090 apic
->vector_allocation_domain(cpu
, tmp_mask
, mask
);
1092 if (cpumask_subset(tmp_mask
, cfg
->domain
)) {
1094 if (cpumask_equal(tmp_mask
, cfg
->domain
))
1097 * New cpumask using the vector is a proper subset of
1098 * the current in use mask. So cleanup the vector
1099 * allocation for the members that are not used anymore.
1101 cpumask_andnot(cfg
->old_domain
, cfg
->domain
, tmp_mask
);
1102 cfg
->move_in_progress
=
1103 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1104 cpumask_and(cfg
->domain
, cfg
->domain
, tmp_mask
);
1108 vector
= current_vector
;
1109 offset
= current_offset
;
1112 if (vector
>= first_system_vector
) {
1113 offset
= (offset
+ 1) % 16;
1114 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1117 if (unlikely(current_vector
== vector
)) {
1118 cpumask_or(cfg
->old_domain
, cfg
->old_domain
, tmp_mask
);
1119 cpumask_andnot(tmp_mask
, mask
, cfg
->old_domain
);
1120 cpu
= cpumask_first_and(tmp_mask
, cpu_online_mask
);
1124 if (test_bit(vector
, used_vectors
))
1127 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
) {
1128 if (per_cpu(vector_irq
, new_cpu
)[vector
] > VECTOR_UNDEFINED
)
1132 current_vector
= vector
;
1133 current_offset
= offset
;
1135 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1136 cfg
->move_in_progress
=
1137 cpumask_intersects(cfg
->old_domain
, cpu_online_mask
);
1139 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1140 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1141 cfg
->vector
= vector
;
1142 cpumask_copy(cfg
->domain
, tmp_mask
);
1146 free_cpumask_var(tmp_mask
);
1150 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1153 unsigned long flags
;
1155 raw_spin_lock_irqsave(&vector_lock
, flags
);
1156 err
= __assign_irq_vector(irq
, cfg
, mask
);
1157 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1161 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1165 BUG_ON(!cfg
->vector
);
1167 vector
= cfg
->vector
;
1168 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1169 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1172 cpumask_clear(cfg
->domain
);
1174 if (likely(!cfg
->move_in_progress
))
1176 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1177 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1178 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1180 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1184 cfg
->move_in_progress
= 0;
1187 void __setup_vector_irq(int cpu
)
1189 /* Initialize vector_irq on a new cpu */
1191 struct irq_cfg
*cfg
;
1194 * vector_lock will make sure that we don't run into irq vector
1195 * assignments that might be happening on another cpu in parallel,
1196 * while we setup our initial vector to irq mappings.
1198 raw_spin_lock(&vector_lock
);
1199 /* Mark the inuse vectors */
1200 for_each_active_irq(irq
) {
1201 cfg
= irq_get_chip_data(irq
);
1205 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1207 vector
= cfg
->vector
;
1208 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1210 /* Mark the free vectors */
1211 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1212 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1213 if (irq
<= VECTOR_UNDEFINED
)
1217 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1218 per_cpu(vector_irq
, cpu
)[vector
] = VECTOR_UNDEFINED
;
1220 raw_spin_unlock(&vector_lock
);
1223 static struct irq_chip ioapic_chip
;
1225 #ifdef CONFIG_X86_32
1226 static inline int IO_APIC_irq_trigger(int irq
)
1230 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1231 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1232 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1233 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1234 return irq_trigger(idx
);
1238 * nonexistent IRQs are edge default
1243 static inline int IO_APIC_irq_trigger(int irq
)
1249 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1250 unsigned long trigger
)
1252 struct irq_chip
*chip
= &ioapic_chip
;
1253 irq_flow_handler_t hdl
;
1256 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1257 trigger
== IOAPIC_LEVEL
) {
1258 irq_set_status_flags(irq
, IRQ_LEVEL
);
1261 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1265 if (setup_remapped_irq(irq
, cfg
, chip
))
1266 fasteoi
= trigger
!= 0;
1268 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1269 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1270 fasteoi
? "fasteoi" : "edge");
1273 int native_setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1274 unsigned int destination
, int vector
,
1275 struct io_apic_irq_attr
*attr
)
1277 memset(entry
, 0, sizeof(*entry
));
1279 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1280 entry
->dest_mode
= apic
->irq_dest_mode
;
1281 entry
->dest
= destination
;
1282 entry
->vector
= vector
;
1283 entry
->mask
= 0; /* enable IRQ */
1284 entry
->trigger
= attr
->trigger
;
1285 entry
->polarity
= attr
->polarity
;
1288 * Mask level triggered irqs.
1289 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1297 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1298 struct io_apic_irq_attr
*attr
)
1300 struct IO_APIC_route_entry entry
;
1303 if (!IO_APIC_IRQ(irq
))
1306 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1309 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1311 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1312 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1313 __clear_irq_vector(irq
, cfg
);
1318 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1319 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1320 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1321 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1322 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1324 if (x86_io_apic_ops
.setup_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1325 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1326 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1327 __clear_irq_vector(irq
, cfg
);
1332 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1333 if (irq
< legacy_pic
->nr_legacy_irqs
)
1334 legacy_pic
->mask(irq
);
1336 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1339 static bool __init
io_apic_pin_not_connected(int idx
, int ioapic_idx
, int pin
)
1344 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" apic %d pin %d not connected\n",
1345 mpc_ioapic_id(ioapic_idx
), pin
);
1349 static void __init
__io_apic_setup_irqs(unsigned int ioapic_idx
)
1351 int idx
, node
= cpu_to_node(0);
1352 struct io_apic_irq_attr attr
;
1353 unsigned int pin
, irq
;
1355 for (pin
= 0; pin
< ioapics
[ioapic_idx
].nr_registers
; pin
++) {
1356 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1357 if (io_apic_pin_not_connected(idx
, ioapic_idx
, pin
))
1360 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1362 if ((ioapic_idx
> 0) && (irq
> 16))
1366 * Skip the timer IRQ if there's a quirk handler
1367 * installed and if it returns 1:
1369 if (apic
->multi_timer_check
&&
1370 apic
->multi_timer_check(ioapic_idx
, irq
))
1373 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1376 io_apic_setup_irq_pin(irq
, node
, &attr
);
1380 static void __init
setup_IO_APIC_irqs(void)
1382 unsigned int ioapic_idx
;
1384 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1386 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1387 __io_apic_setup_irqs(ioapic_idx
);
1391 * for the gsit that is not in first ioapic
1392 * but could not use acpi_register_gsi()
1393 * like some special sci in IBM x3330
1395 void setup_IO_APIC_irq_extra(u32 gsi
)
1397 int ioapic_idx
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1398 struct io_apic_irq_attr attr
;
1401 * Convert 'gsi' to 'ioapic.pin'.
1403 ioapic_idx
= mp_find_ioapic(gsi
);
1407 pin
= mp_find_ioapic_pin(ioapic_idx
, gsi
);
1408 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1412 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1414 /* Only handle the non legacy irqs on secondary ioapics */
1415 if (ioapic_idx
== 0 || irq
< NR_IRQS_LEGACY
)
1418 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1421 io_apic_setup_irq_pin_once(irq
, node
, &attr
);
1425 * Set up the timer pin, possibly with the 8259A-master behind.
1427 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1428 unsigned int pin
, int vector
)
1430 struct IO_APIC_route_entry entry
;
1433 memset(&entry
, 0, sizeof(entry
));
1436 * We use logical delivery to get the timer IRQ
1439 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1440 apic
->target_cpus(), &dest
)))
1443 entry
.dest_mode
= apic
->irq_dest_mode
;
1444 entry
.mask
= 0; /* don't mask IRQ for edge */
1446 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1449 entry
.vector
= vector
;
1452 * The timer IRQ doesn't have to know that behind the
1453 * scene we may have a 8259A-master in AEOI mode ...
1455 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1459 * Add it to the IO-APIC irq-routing table:
1461 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1464 void native_io_apic_print_entries(unsigned int apic
, unsigned int nr_entries
)
1468 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n");
1470 for (i
= 0; i
<= nr_entries
; i
++) {
1471 struct IO_APIC_route_entry entry
;
1473 entry
= ioapic_read_entry(apic
, i
);
1475 pr_debug(" %02x %02X ", i
, entry
.dest
);
1476 pr_cont("%1d %1d %1d %1d %1d "
1482 entry
.delivery_status
,
1484 entry
.delivery_mode
,
1489 void intel_ir_io_apic_print_entries(unsigned int apic
,
1490 unsigned int nr_entries
)
1494 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n");
1496 for (i
= 0; i
<= nr_entries
; i
++) {
1497 struct IR_IO_APIC_route_entry
*ir_entry
;
1498 struct IO_APIC_route_entry entry
;
1500 entry
= ioapic_read_entry(apic
, i
);
1502 ir_entry
= (struct IR_IO_APIC_route_entry
*)&entry
;
1504 pr_debug(" %02x %04X ", i
, ir_entry
->index
);
1505 pr_cont("%1d %1d %1d %1d %1d "
1506 "%1d %1d %X %02X\n",
1512 ir_entry
->delivery_status
,
1519 void ioapic_zap_locks(void)
1521 raw_spin_lock_init(&ioapic_lock
);
1524 __apicdebuginit(void) print_IO_APIC(int ioapic_idx
)
1526 union IO_APIC_reg_00 reg_00
;
1527 union IO_APIC_reg_01 reg_01
;
1528 union IO_APIC_reg_02 reg_02
;
1529 union IO_APIC_reg_03 reg_03
;
1530 unsigned long flags
;
1532 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1533 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1534 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1535 if (reg_01
.bits
.version
>= 0x10)
1536 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1537 if (reg_01
.bits
.version
>= 0x20)
1538 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1539 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1541 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1542 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1543 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1544 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1545 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1547 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1548 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1549 reg_01
.bits
.entries
);
1551 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1552 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1553 reg_01
.bits
.version
);
1556 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1557 * but the value of reg_02 is read as the previous read register
1558 * value, so ignore it if reg_02 == reg_01.
1560 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1561 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1562 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1566 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1567 * or reg_03, but the value of reg_0[23] is read as the previous read
1568 * register value, so ignore it if reg_03 == reg_0[12].
1570 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1571 reg_03
.raw
!= reg_01
.raw
) {
1572 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1573 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1576 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1578 x86_io_apic_ops
.print_entries(ioapic_idx
, reg_01
.bits
.entries
);
1581 __apicdebuginit(void) print_IO_APICs(void)
1584 struct irq_cfg
*cfg
;
1586 struct irq_chip
*chip
;
1588 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1589 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1590 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1591 mpc_ioapic_id(ioapic_idx
),
1592 ioapics
[ioapic_idx
].nr_registers
);
1595 * We are a bit conservative about what we expect. We have to
1596 * know about every hardware change ASAP.
1598 printk(KERN_INFO
"testing the IO APIC.......................\n");
1600 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1601 print_IO_APIC(ioapic_idx
);
1603 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1604 for_each_active_irq(irq
) {
1605 struct irq_pin_list
*entry
;
1607 chip
= irq_get_chip(irq
);
1608 if (chip
!= &ioapic_chip
)
1611 cfg
= irq_get_chip_data(irq
);
1614 entry
= cfg
->irq_2_pin
;
1617 printk(KERN_DEBUG
"IRQ%d ", irq
);
1618 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1619 pr_cont("-> %d:%d", entry
->apic
, entry
->pin
);
1623 printk(KERN_INFO
".................................... done.\n");
1626 __apicdebuginit(void) print_APIC_field(int base
)
1632 for (i
= 0; i
< 8; i
++)
1633 pr_cont("%08x", apic_read(base
+ i
*0x10));
1638 __apicdebuginit(void) print_local_APIC(void *dummy
)
1640 unsigned int i
, v
, ver
, maxlvt
;
1643 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1644 smp_processor_id(), hard_smp_processor_id());
1645 v
= apic_read(APIC_ID
);
1646 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1647 v
= apic_read(APIC_LVR
);
1648 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1649 ver
= GET_APIC_VERSION(v
);
1650 maxlvt
= lapic_get_maxlvt();
1652 v
= apic_read(APIC_TASKPRI
);
1653 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1655 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1656 if (!APIC_XAPIC(ver
)) {
1657 v
= apic_read(APIC_ARBPRI
);
1658 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1659 v
& APIC_ARBPRI_MASK
);
1661 v
= apic_read(APIC_PROCPRI
);
1662 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1666 * Remote read supported only in the 82489DX and local APIC for
1667 * Pentium processors.
1669 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1670 v
= apic_read(APIC_RRR
);
1671 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1674 v
= apic_read(APIC_LDR
);
1675 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1676 if (!x2apic_enabled()) {
1677 v
= apic_read(APIC_DFR
);
1678 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1680 v
= apic_read(APIC_SPIV
);
1681 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1683 printk(KERN_DEBUG
"... APIC ISR field:\n");
1684 print_APIC_field(APIC_ISR
);
1685 printk(KERN_DEBUG
"... APIC TMR field:\n");
1686 print_APIC_field(APIC_TMR
);
1687 printk(KERN_DEBUG
"... APIC IRR field:\n");
1688 print_APIC_field(APIC_IRR
);
1690 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1691 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1692 apic_write(APIC_ESR
, 0);
1694 v
= apic_read(APIC_ESR
);
1695 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1698 icr
= apic_icr_read();
1699 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1700 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1702 v
= apic_read(APIC_LVTT
);
1703 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1705 if (maxlvt
> 3) { /* PC is LVT#4. */
1706 v
= apic_read(APIC_LVTPC
);
1707 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1709 v
= apic_read(APIC_LVT0
);
1710 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1711 v
= apic_read(APIC_LVT1
);
1712 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1714 if (maxlvt
> 2) { /* ERR is LVT#3. */
1715 v
= apic_read(APIC_LVTERR
);
1716 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1719 v
= apic_read(APIC_TMICT
);
1720 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1721 v
= apic_read(APIC_TMCCT
);
1722 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1723 v
= apic_read(APIC_TDCR
);
1724 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1726 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1727 v
= apic_read(APIC_EFEAT
);
1728 maxlvt
= (v
>> 16) & 0xff;
1729 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1730 v
= apic_read(APIC_ECTRL
);
1731 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1732 for (i
= 0; i
< maxlvt
; i
++) {
1733 v
= apic_read(APIC_EILVTn(i
));
1734 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1740 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1748 for_each_online_cpu(cpu
) {
1751 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1756 __apicdebuginit(void) print_PIC(void)
1759 unsigned long flags
;
1761 if (!legacy_pic
->nr_legacy_irqs
)
1764 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1766 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1768 v
= inb(0xa1) << 8 | inb(0x21);
1769 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1771 v
= inb(0xa0) << 8 | inb(0x20);
1772 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1776 v
= inb(0xa0) << 8 | inb(0x20);
1780 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1782 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1784 v
= inb(0x4d1) << 8 | inb(0x4d0);
1785 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1788 static int __initdata show_lapic
= 1;
1789 static __init
int setup_show_lapic(char *arg
)
1793 if (strcmp(arg
, "all") == 0) {
1794 show_lapic
= CONFIG_NR_CPUS
;
1796 get_option(&arg
, &num
);
1803 __setup("show_lapic=", setup_show_lapic
);
1805 __apicdebuginit(int) print_ICs(void)
1807 if (apic_verbosity
== APIC_QUIET
)
1812 /* don't print out if apic is not there */
1813 if (!cpu_has_apic
&& !apic_from_smp_config())
1816 print_local_APICs(show_lapic
);
1822 late_initcall(print_ICs
);
1825 /* Where if anywhere is the i8259 connect in external int mode */
1826 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1828 void __init
enable_IO_APIC(void)
1830 int i8259_apic
, i8259_pin
;
1833 if (!legacy_pic
->nr_legacy_irqs
)
1836 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1838 /* See if any of the pins is in ExtINT mode */
1839 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1840 struct IO_APIC_route_entry entry
;
1841 entry
= ioapic_read_entry(apic
, pin
);
1843 /* If the interrupt line is enabled and in ExtInt mode
1844 * I have found the pin where the i8259 is connected.
1846 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1847 ioapic_i8259
.apic
= apic
;
1848 ioapic_i8259
.pin
= pin
;
1854 /* Look to see what if the MP table has reported the ExtINT */
1855 /* If we could not find the appropriate pin by looking at the ioapic
1856 * the i8259 probably is not connected the ioapic but give the
1857 * mptable a chance anyway.
1859 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1860 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1861 /* Trust the MP table if nothing is setup in the hardware */
1862 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1863 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1864 ioapic_i8259
.pin
= i8259_pin
;
1865 ioapic_i8259
.apic
= i8259_apic
;
1867 /* Complain if the MP table and the hardware disagree */
1868 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1869 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1871 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1875 * Do not trust the IO-APIC being empty at bootup
1880 void native_disable_io_apic(void)
1883 * If the i8259 is routed through an IOAPIC
1884 * Put that IOAPIC in virtual wire mode
1885 * so legacy interrupts can be delivered.
1887 if (ioapic_i8259
.pin
!= -1) {
1888 struct IO_APIC_route_entry entry
;
1890 memset(&entry
, 0, sizeof(entry
));
1891 entry
.mask
= 0; /* Enabled */
1892 entry
.trigger
= 0; /* Edge */
1894 entry
.polarity
= 0; /* High */
1895 entry
.delivery_status
= 0;
1896 entry
.dest_mode
= 0; /* Physical */
1897 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1899 entry
.dest
= read_apic_id();
1902 * Add it to the IO-APIC irq-routing table:
1904 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1907 if (cpu_has_apic
|| apic_from_smp_config())
1908 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1913 * Not an __init, needed by the reboot code
1915 void disable_IO_APIC(void)
1918 * Clear the IO-APIC before rebooting:
1922 if (!legacy_pic
->nr_legacy_irqs
)
1925 x86_io_apic_ops
.disable();
1928 #ifdef CONFIG_X86_32
1930 * function to set the IO-APIC physical IDs based on the
1931 * values stored in the MPC table.
1933 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1935 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1937 union IO_APIC_reg_00 reg_00
;
1938 physid_mask_t phys_id_present_map
;
1941 unsigned char old_id
;
1942 unsigned long flags
;
1945 * This is broken; anything with a real cpu count has to
1946 * circumvent this idiocy regardless.
1948 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
1951 * Set the IOAPIC ID to the value stored in the MPC table.
1953 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++) {
1954 /* Read the register 0 value */
1955 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1956 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1957 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1959 old_id
= mpc_ioapic_id(ioapic_idx
);
1961 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
1962 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1963 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1964 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1966 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
1970 * Sanity check, is the ID really free? Every APIC in a
1971 * system must have a unique ID or we get lots of nice
1972 * 'stuck on smp_invalidate_needed IPI wait' messages.
1974 if (apic
->check_apicid_used(&phys_id_present_map
,
1975 mpc_ioapic_id(ioapic_idx
))) {
1976 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1977 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
1978 for (i
= 0; i
< get_physical_broadcast(); i
++)
1979 if (!physid_isset(i
, phys_id_present_map
))
1981 if (i
>= get_physical_broadcast())
1982 panic("Max APIC ID exceeded!\n");
1983 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1985 physid_set(i
, phys_id_present_map
);
1986 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
1989 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
1991 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1992 "phys_id_present_map\n",
1993 mpc_ioapic_id(ioapic_idx
));
1994 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1998 * We need to adjust the IRQ routing table
1999 * if the ID changed.
2001 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
2002 for (i
= 0; i
< mp_irq_entries
; i
++)
2003 if (mp_irqs
[i
].dstapic
== old_id
)
2005 = mpc_ioapic_id(ioapic_idx
);
2008 * Update the ID register according to the right value
2009 * from the MPC table if they are different.
2011 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
2014 apic_printk(APIC_VERBOSE
, KERN_INFO
2015 "...changing IO-APIC physical APIC ID to %d ...",
2016 mpc_ioapic_id(ioapic_idx
));
2018 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2019 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2020 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2021 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2026 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2027 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2028 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2029 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
2030 pr_cont("could not set ID!\n");
2032 apic_printk(APIC_VERBOSE
, " ok.\n");
2036 void __init
setup_ioapic_ids_from_mpc(void)
2042 * Don't check I/O APIC IDs for xAPIC systems. They have
2043 * no meaning without the serial APIC bus.
2045 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2046 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2048 setup_ioapic_ids_from_mpc_nocheck();
2052 int no_timer_check __initdata
;
2054 static int __init
notimercheck(char *s
)
2059 __setup("no_timer_check", notimercheck
);
2062 * There is a nasty bug in some older SMP boards, their mptable lies
2063 * about the timer IRQ. We do the following to work around the situation:
2065 * - timer IRQ defaults to IO-APIC IRQ
2066 * - if this function detects that timer IRQs are defunct, then we fall
2067 * back to ISA timer IRQs
2069 static int __init
timer_irq_works(void)
2071 unsigned long t1
= jiffies
;
2072 unsigned long flags
;
2077 local_save_flags(flags
);
2079 /* Let ten ticks pass... */
2080 mdelay((10 * 1000) / HZ
);
2081 local_irq_restore(flags
);
2084 * Expect a few ticks at least, to be sure some possible
2085 * glue logic does not lock up after one or two first
2086 * ticks in a non-ExtINT mode. Also the local APIC
2087 * might have cached one ExtINT interrupt. Finally, at
2088 * least one tick may be lost due to delays.
2092 if (time_after(jiffies
, t1
+ 4))
2098 * In the SMP+IOAPIC case it might happen that there are an unspecified
2099 * number of pending IRQ events unhandled. These cases are very rare,
2100 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2101 * better to do it this way as thus we do not have to be aware of
2102 * 'pending' interrupts in the IRQ path, except at this point.
2105 * Edge triggered needs to resend any interrupt
2106 * that was delayed but this is now handled in the device
2111 * Starting up a edge-triggered IO-APIC interrupt is
2112 * nasty - we need to make sure that we get the edge.
2113 * If it is already asserted for some reason, we need
2114 * return 1 to indicate that is was pending.
2116 * This is not complete - we should be able to fake
2117 * an edge even if it isn't on the 8259A...
2120 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2122 int was_pending
= 0, irq
= data
->irq
;
2123 unsigned long flags
;
2125 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2126 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2127 legacy_pic
->mask(irq
);
2128 if (legacy_pic
->irq_pending(irq
))
2131 __unmask_ioapic(data
->chip_data
);
2132 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2137 static int ioapic_retrigger_irq(struct irq_data
*data
)
2139 struct irq_cfg
*cfg
= data
->chip_data
;
2140 unsigned long flags
;
2143 raw_spin_lock_irqsave(&vector_lock
, flags
);
2144 cpu
= cpumask_first_and(cfg
->domain
, cpu_online_mask
);
2145 apic
->send_IPI_mask(cpumask_of(cpu
), cfg
->vector
);
2146 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2152 * Level and edge triggered IO-APIC interrupts need different handling,
2153 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2154 * handled with the level-triggered descriptor, but that one has slightly
2155 * more overhead. Level-triggered interrupts cannot be handled with the
2156 * edge-triggered handler, without risking IRQ storms and other ugly
2161 void send_cleanup_vector(struct irq_cfg
*cfg
)
2163 cpumask_var_t cleanup_mask
;
2165 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2167 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2168 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2170 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2171 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2172 free_cpumask_var(cleanup_mask
);
2174 cfg
->move_in_progress
= 0;
2177 asmlinkage __visible
void smp_irq_move_cleanup_interrupt(void)
2179 unsigned vector
, me
;
2185 me
= smp_processor_id();
2186 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2189 struct irq_desc
*desc
;
2190 struct irq_cfg
*cfg
;
2191 irq
= __this_cpu_read(vector_irq
[vector
]);
2193 if (irq
<= VECTOR_UNDEFINED
)
2196 desc
= irq_to_desc(irq
);
2204 raw_spin_lock(&desc
->lock
);
2207 * Check if the irq migration is in progress. If so, we
2208 * haven't received the cleanup request yet for this irq.
2210 if (cfg
->move_in_progress
)
2213 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2216 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2218 * Check if the vector that needs to be cleanedup is
2219 * registered at the cpu's IRR. If so, then this is not
2220 * the best time to clean it up. Lets clean it up in the
2221 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2224 if (irr
& (1 << (vector
% 32))) {
2225 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2228 __this_cpu_write(vector_irq
[vector
], -1);
2230 raw_spin_unlock(&desc
->lock
);
2236 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2240 if (likely(!cfg
->move_in_progress
))
2243 me
= smp_processor_id();
2245 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2246 send_cleanup_vector(cfg
);
2249 static void irq_complete_move(struct irq_cfg
*cfg
)
2251 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2254 void irq_force_complete_move(int irq
)
2256 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
2261 __irq_complete_move(cfg
, cfg
->vector
);
2264 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2267 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2270 struct irq_pin_list
*entry
;
2271 u8 vector
= cfg
->vector
;
2273 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2279 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2280 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2281 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2283 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2288 * Either sets data->affinity to a valid value, and returns
2289 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2290 * leaves data->affinity untouched.
2292 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2293 unsigned int *dest_id
)
2295 struct irq_cfg
*cfg
= data
->chip_data
;
2296 unsigned int irq
= data
->irq
;
2299 if (!config_enabled(CONFIG_SMP
))
2302 if (!cpumask_intersects(mask
, cpu_online_mask
))
2305 err
= assign_irq_vector(irq
, cfg
, mask
);
2309 err
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
, dest_id
);
2311 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
2312 pr_err("Failed to recover vector for irq %d\n", irq
);
2316 cpumask_copy(data
->affinity
, mask
);
2322 int native_ioapic_set_affinity(struct irq_data
*data
,
2323 const struct cpumask
*mask
,
2326 unsigned int dest
, irq
= data
->irq
;
2327 unsigned long flags
;
2330 if (!config_enabled(CONFIG_SMP
))
2333 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2334 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2336 /* Only the high 8 bits are valid. */
2337 dest
= SET_APIC_LOGICAL_ID(dest
);
2338 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2339 ret
= IRQ_SET_MASK_OK_NOCOPY
;
2341 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2345 static void ack_apic_edge(struct irq_data
*data
)
2347 irq_complete_move(data
->chip_data
);
2352 atomic_t irq_mis_count
;
2354 #ifdef CONFIG_GENERIC_PENDING_IRQ
2355 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
2357 struct irq_pin_list
*entry
;
2358 unsigned long flags
;
2360 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2361 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2366 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
2367 /* Is the remote IRR bit set? */
2368 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
2369 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2373 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2378 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2380 /* If we are moving the irq we need to mask it */
2381 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2388 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2389 struct irq_cfg
*cfg
, bool masked
)
2391 if (unlikely(masked
)) {
2392 /* Only migrate the irq if the ack has been received.
2394 * On rare occasions the broadcast level triggered ack gets
2395 * delayed going to ioapics, and if we reprogram the
2396 * vector while Remote IRR is still set the irq will never
2399 * To prevent this scenario we read the Remote IRR bit
2400 * of the ioapic. This has two effects.
2401 * - On any sane system the read of the ioapic will
2402 * flush writes (and acks) going to the ioapic from
2404 * - We get to see if the ACK has actually been delivered.
2406 * Based on failed experiments of reprogramming the
2407 * ioapic entry from outside of irq context starting
2408 * with masking the ioapic entry and then polling until
2409 * Remote IRR was clear before reprogramming the
2410 * ioapic I don't trust the Remote IRR bit to be
2411 * completey accurate.
2413 * However there appears to be no other way to plug
2414 * this race, so if the Remote IRR bit is not
2415 * accurate and is causing problems then it is a hardware bug
2416 * and you can go talk to the chipset vendor about it.
2418 if (!io_apic_level_ack_pending(cfg
))
2419 irq_move_masked_irq(data
);
2424 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2428 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2429 struct irq_cfg
*cfg
, bool masked
)
2434 static void ack_apic_level(struct irq_data
*data
)
2436 struct irq_cfg
*cfg
= data
->chip_data
;
2437 int i
, irq
= data
->irq
;
2441 irq_complete_move(cfg
);
2442 masked
= ioapic_irqd_mask(data
, cfg
);
2445 * It appears there is an erratum which affects at least version 0x11
2446 * of I/O APIC (that's the 82093AA and cores integrated into various
2447 * chipsets). Under certain conditions a level-triggered interrupt is
2448 * erroneously delivered as edge-triggered one but the respective IRR
2449 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2450 * message but it will never arrive and further interrupts are blocked
2451 * from the source. The exact reason is so far unknown, but the
2452 * phenomenon was observed when two consecutive interrupt requests
2453 * from a given source get delivered to the same CPU and the source is
2454 * temporarily disabled in between.
2456 * A workaround is to simulate an EOI message manually. We achieve it
2457 * by setting the trigger mode to edge and then to level when the edge
2458 * trigger mode gets detected in the TMR of a local APIC for a
2459 * level-triggered interrupt. We mask the source for the time of the
2460 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2461 * The idea is from Manfred Spraul. --macro
2463 * Also in the case when cpu goes offline, fixup_irqs() will forward
2464 * any unhandled interrupt on the offlined cpu to the new cpu
2465 * destination that is handling the corresponding interrupt. This
2466 * interrupt forwarding is done via IPI's. Hence, in this case also
2467 * level-triggered io-apic interrupt will be seen as an edge
2468 * interrupt in the IRR. And we can't rely on the cpu's EOI
2469 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2470 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2471 * supporting EOI register, we do an explicit EOI to clear the
2472 * remote IRR and on IO-APIC's which don't have an EOI register,
2473 * we use the above logic (mask+edge followed by unmask+level) from
2474 * Manfred Spraul to clear the remote IRR.
2477 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2480 * We must acknowledge the irq before we move it or the acknowledge will
2481 * not propagate properly.
2486 * Tail end of clearing remote IRR bit (either by delivering the EOI
2487 * message via io-apic EOI register write or simulating it using
2488 * mask+edge followed by unnask+level logic) manually when the
2489 * level triggered interrupt is seen as the edge triggered interrupt
2492 if (!(v
& (1 << (i
& 0x1f)))) {
2493 atomic_inc(&irq_mis_count
);
2495 eoi_ioapic_irq(irq
, cfg
);
2498 ioapic_irqd_unmask(data
, cfg
, masked
);
2501 static struct irq_chip ioapic_chip __read_mostly
= {
2503 .irq_startup
= startup_ioapic_irq
,
2504 .irq_mask
= mask_ioapic_irq
,
2505 .irq_unmask
= unmask_ioapic_irq
,
2506 .irq_ack
= ack_apic_edge
,
2507 .irq_eoi
= ack_apic_level
,
2508 .irq_set_affinity
= native_ioapic_set_affinity
,
2509 .irq_retrigger
= ioapic_retrigger_irq
,
2512 static inline void init_IO_APIC_traps(void)
2514 struct irq_cfg
*cfg
;
2518 * NOTE! The local APIC isn't very good at handling
2519 * multiple interrupts at the same interrupt level.
2520 * As the interrupt level is determined by taking the
2521 * vector number and shifting that right by 4, we
2522 * want to spread these out a bit so that they don't
2523 * all fall in the same interrupt level.
2525 * Also, we've got to be careful not to trash gate
2526 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2528 for_each_active_irq(irq
) {
2529 cfg
= irq_get_chip_data(irq
);
2530 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2532 * Hmm.. We don't have an entry for this,
2533 * so default to an old-fashioned 8259
2534 * interrupt if we can..
2536 if (irq
< legacy_pic
->nr_legacy_irqs
)
2537 legacy_pic
->make_irq(irq
);
2539 /* Strange. Oh, well.. */
2540 irq_set_chip(irq
, &no_irq_chip
);
2546 * The local APIC irq-chip implementation:
2549 static void mask_lapic_irq(struct irq_data
*data
)
2553 v
= apic_read(APIC_LVT0
);
2554 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2557 static void unmask_lapic_irq(struct irq_data
*data
)
2561 v
= apic_read(APIC_LVT0
);
2562 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2565 static void ack_lapic_irq(struct irq_data
*data
)
2570 static struct irq_chip lapic_chip __read_mostly
= {
2571 .name
= "local-APIC",
2572 .irq_mask
= mask_lapic_irq
,
2573 .irq_unmask
= unmask_lapic_irq
,
2574 .irq_ack
= ack_lapic_irq
,
2577 static void lapic_register_intr(int irq
)
2579 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2580 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2585 * This looks a bit hackish but it's about the only one way of sending
2586 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2587 * not support the ExtINT mode, unfortunately. We need to send these
2588 * cycles as some i82489DX-based boards have glue logic that keeps the
2589 * 8259A interrupt line asserted until INTA. --macro
2591 static inline void __init
unlock_ExtINT_logic(void)
2594 struct IO_APIC_route_entry entry0
, entry1
;
2595 unsigned char save_control
, save_freq_select
;
2597 pin
= find_isa_irq_pin(8, mp_INT
);
2602 apic
= find_isa_irq_apic(8, mp_INT
);
2608 entry0
= ioapic_read_entry(apic
, pin
);
2609 clear_IO_APIC_pin(apic
, pin
);
2611 memset(&entry1
, 0, sizeof(entry1
));
2613 entry1
.dest_mode
= 0; /* physical delivery */
2614 entry1
.mask
= 0; /* unmask IRQ now */
2615 entry1
.dest
= hard_smp_processor_id();
2616 entry1
.delivery_mode
= dest_ExtINT
;
2617 entry1
.polarity
= entry0
.polarity
;
2621 ioapic_write_entry(apic
, pin
, entry1
);
2623 save_control
= CMOS_READ(RTC_CONTROL
);
2624 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2625 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2627 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2632 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2636 CMOS_WRITE(save_control
, RTC_CONTROL
);
2637 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2638 clear_IO_APIC_pin(apic
, pin
);
2640 ioapic_write_entry(apic
, pin
, entry0
);
2643 static int disable_timer_pin_1 __initdata
;
2644 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2645 static int __init
disable_timer_pin_setup(char *arg
)
2647 disable_timer_pin_1
= 1;
2650 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2652 int timer_through_8259 __initdata
;
2655 * This code may look a bit paranoid, but it's supposed to cooperate with
2656 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2657 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2658 * fanatically on his truly buggy board.
2660 * FIXME: really need to revamp this for all platforms.
2662 static inline void __init
check_timer(void)
2664 struct irq_cfg
*cfg
= irq_get_chip_data(0);
2665 int node
= cpu_to_node(0);
2666 int apic1
, pin1
, apic2
, pin2
;
2667 unsigned long flags
;
2670 local_irq_save(flags
);
2673 * get/set the timer IRQ vector:
2675 legacy_pic
->mask(0);
2676 assign_irq_vector(0, cfg
, apic
->target_cpus());
2679 * As IRQ0 is to be enabled in the 8259A, the virtual
2680 * wire has to be disabled in the local APIC. Also
2681 * timer interrupts need to be acknowledged manually in
2682 * the 8259A for the i82489DX when using the NMI
2683 * watchdog as that APIC treats NMIs as level-triggered.
2684 * The AEOI mode will finish them in the 8259A
2687 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2688 legacy_pic
->init(1);
2690 pin1
= find_isa_irq_pin(0, mp_INT
);
2691 apic1
= find_isa_irq_apic(0, mp_INT
);
2692 pin2
= ioapic_i8259
.pin
;
2693 apic2
= ioapic_i8259
.apic
;
2695 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2696 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2697 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2700 * Some BIOS writers are clueless and report the ExtINTA
2701 * I/O APIC input from the cascaded 8259A as the timer
2702 * interrupt input. So just in case, if only one pin
2703 * was found above, try it both directly and through the
2707 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2711 } else if (pin2
== -1) {
2718 * Ok, does IRQ0 through the IOAPIC work?
2721 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2722 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2724 /* for edge trigger, setup_ioapic_irq already
2725 * leave it unmasked.
2726 * so only need to unmask if it is level-trigger
2727 * do we really have level trigger timer?
2730 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2731 if (idx
!= -1 && irq_trigger(idx
))
2734 if (timer_irq_works()) {
2735 if (disable_timer_pin_1
> 0)
2736 clear_IO_APIC_pin(0, pin1
);
2739 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2740 local_irq_disable();
2741 clear_IO_APIC_pin(apic1
, pin1
);
2743 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2744 "8254 timer not connected to IO-APIC\n");
2746 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2747 "(IRQ0) through the 8259A ...\n");
2748 apic_printk(APIC_QUIET
, KERN_INFO
2749 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2751 * legacy devices should be connected to IO APIC #0
2753 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2754 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2755 legacy_pic
->unmask(0);
2756 if (timer_irq_works()) {
2757 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2758 timer_through_8259
= 1;
2762 * Cleanup, just in case ...
2764 local_irq_disable();
2765 legacy_pic
->mask(0);
2766 clear_IO_APIC_pin(apic2
, pin2
);
2767 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2770 apic_printk(APIC_QUIET
, KERN_INFO
2771 "...trying to set up timer as Virtual Wire IRQ...\n");
2773 lapic_register_intr(0);
2774 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2775 legacy_pic
->unmask(0);
2777 if (timer_irq_works()) {
2778 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2781 local_irq_disable();
2782 legacy_pic
->mask(0);
2783 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2784 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2786 apic_printk(APIC_QUIET
, KERN_INFO
2787 "...trying to set up timer as ExtINT IRQ...\n");
2789 legacy_pic
->init(0);
2790 legacy_pic
->make_irq(0);
2791 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2793 unlock_ExtINT_logic();
2795 if (timer_irq_works()) {
2796 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2799 local_irq_disable();
2800 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2801 if (x2apic_preenabled
)
2802 apic_printk(APIC_QUIET
, KERN_INFO
2803 "Perhaps problem with the pre-enabled x2apic mode\n"
2804 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2805 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2806 "report. Then try booting with the 'noapic' option.\n");
2808 local_irq_restore(flags
);
2812 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2813 * to devices. However there may be an I/O APIC pin available for
2814 * this interrupt regardless. The pin may be left unconnected, but
2815 * typically it will be reused as an ExtINT cascade interrupt for
2816 * the master 8259A. In the MPS case such a pin will normally be
2817 * reported as an ExtINT interrupt in the MP table. With ACPI
2818 * there is no provision for ExtINT interrupts, and in the absence
2819 * of an override it would be treated as an ordinary ISA I/O APIC
2820 * interrupt, that is edge-triggered and unmasked by default. We
2821 * used to do this, but it caused problems on some systems because
2822 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2823 * the same ExtINT cascade interrupt to drive the local APIC of the
2824 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2825 * the I/O APIC in all cases now. No actual device should request
2826 * it anyway. --macro
2828 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2830 void __init
setup_IO_APIC(void)
2834 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2836 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
2838 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2840 * Set up IO-APIC IRQ routing.
2842 x86_init
.mpparse
.setup_ioapic_ids();
2845 setup_IO_APIC_irqs();
2846 init_IO_APIC_traps();
2847 if (legacy_pic
->nr_legacy_irqs
)
2852 * Called after all the initialization is done. If we didn't find any
2853 * APIC bugs then we can allow the modify fast path
2856 static int __init
io_apic_bug_finalize(void)
2858 if (sis_apic_bug
== -1)
2863 late_initcall(io_apic_bug_finalize
);
2865 static void resume_ioapic_id(int ioapic_idx
)
2867 unsigned long flags
;
2868 union IO_APIC_reg_00 reg_00
;
2870 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2871 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2872 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
2873 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2874 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2876 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2879 static void ioapic_resume(void)
2883 for (ioapic_idx
= nr_ioapics
- 1; ioapic_idx
>= 0; ioapic_idx
--)
2884 resume_ioapic_id(ioapic_idx
);
2886 restore_ioapic_entries();
2889 static struct syscore_ops ioapic_syscore_ops
= {
2890 .suspend
= save_ioapic_entries
,
2891 .resume
= ioapic_resume
,
2894 static int __init
ioapic_init_ops(void)
2896 register_syscore_ops(&ioapic_syscore_ops
);
2901 device_initcall(ioapic_init_ops
);
2904 * Dynamic irq allocate and deallocation. Should be replaced by irq domains!
2906 int arch_setup_hwirq(unsigned int irq
, int node
)
2908 struct irq_cfg
*cfg
;
2909 unsigned long flags
;
2912 cfg
= alloc_irq_cfg(irq
, node
);
2916 raw_spin_lock_irqsave(&vector_lock
, flags
);
2917 ret
= __assign_irq_vector(irq
, cfg
, apic
->target_cpus());
2918 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2921 irq_set_chip_data(irq
, cfg
);
2923 free_irq_cfg(irq
, cfg
);
2927 void arch_teardown_hwirq(unsigned int irq
)
2929 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
2930 unsigned long flags
;
2932 free_remapped_irq(irq
);
2933 raw_spin_lock_irqsave(&vector_lock
, flags
);
2934 __clear_irq_vector(irq
, cfg
);
2935 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2936 free_irq_cfg(irq
, cfg
);
2940 * MSI message composition
2942 void native_compose_msi_msg(struct pci_dev
*pdev
,
2943 unsigned int irq
, unsigned int dest
,
2944 struct msi_msg
*msg
, u8 hpet_id
)
2946 struct irq_cfg
*cfg
= irq_cfg(irq
);
2948 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2950 if (x2apic_enabled())
2951 msg
->address_hi
|= MSI_ADDR_EXT_DEST_ID(dest
);
2955 ((apic
->irq_dest_mode
== 0) ?
2956 MSI_ADDR_DEST_MODE_PHYSICAL
:
2957 MSI_ADDR_DEST_MODE_LOGICAL
) |
2958 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
2959 MSI_ADDR_REDIRECTION_CPU
:
2960 MSI_ADDR_REDIRECTION_LOWPRI
) |
2961 MSI_ADDR_DEST_ID(dest
);
2964 MSI_DATA_TRIGGER_EDGE
|
2965 MSI_DATA_LEVEL_ASSERT
|
2966 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
2967 MSI_DATA_DELIVERY_FIXED
:
2968 MSI_DATA_DELIVERY_LOWPRI
) |
2969 MSI_DATA_VECTOR(cfg
->vector
);
2972 #ifdef CONFIG_PCI_MSI
2973 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
2974 struct msi_msg
*msg
, u8 hpet_id
)
2976 struct irq_cfg
*cfg
;
2984 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
2988 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
2989 apic
->target_cpus(), &dest
);
2993 x86_msi
.compose_msi_msg(pdev
, irq
, dest
, msg
, hpet_id
);
2999 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3001 struct irq_cfg
*cfg
= data
->chip_data
;
3005 if (__ioapic_set_affinity(data
, mask
, &dest
))
3008 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3010 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3011 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3012 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3013 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3015 __write_msi_msg(data
->msi_desc
, &msg
);
3017 return IRQ_SET_MASK_OK_NOCOPY
;
3021 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3022 * which implement the MSI or MSI-X Capability Structure.
3024 static struct irq_chip msi_chip
= {
3026 .irq_unmask
= unmask_msi_irq
,
3027 .irq_mask
= mask_msi_irq
,
3028 .irq_ack
= ack_apic_edge
,
3029 .irq_set_affinity
= msi_set_affinity
,
3030 .irq_retrigger
= ioapic_retrigger_irq
,
3033 int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
,
3034 unsigned int irq_base
, unsigned int irq_offset
)
3036 struct irq_chip
*chip
= &msi_chip
;
3038 unsigned int irq
= irq_base
+ irq_offset
;
3041 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3045 irq_set_msi_desc_off(irq_base
, irq_offset
, msidesc
);
3048 * MSI-X message is written per-IRQ, the offset is always 0.
3049 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ.
3052 write_msi_msg(irq
, &msg
);
3054 setup_remapped_irq(irq
, irq_get_chip_data(irq
), chip
);
3056 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3058 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3063 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3065 struct msi_desc
*msidesc
;
3069 /* Multiple MSI vectors only supported with interrupt remapping */
3070 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3073 node
= dev_to_node(&dev
->dev
);
3075 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3076 irq
= irq_alloc_hwirq(node
);
3080 ret
= setup_msi_irq(dev
, msidesc
, irq
, 0);
3082 irq_free_hwirq(irq
);
3090 void native_teardown_msi_irq(unsigned int irq
)
3092 irq_free_hwirq(irq
);
3095 #ifdef CONFIG_DMAR_TABLE
3097 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3100 struct irq_cfg
*cfg
= data
->chip_data
;
3101 unsigned int dest
, irq
= data
->irq
;
3104 if (__ioapic_set_affinity(data
, mask
, &dest
))
3107 dmar_msi_read(irq
, &msg
);
3109 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3110 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3111 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3112 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3113 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3115 dmar_msi_write(irq
, &msg
);
3117 return IRQ_SET_MASK_OK_NOCOPY
;
3120 static struct irq_chip dmar_msi_type
= {
3122 .irq_unmask
= dmar_msi_unmask
,
3123 .irq_mask
= dmar_msi_mask
,
3124 .irq_ack
= ack_apic_edge
,
3125 .irq_set_affinity
= dmar_msi_set_affinity
,
3126 .irq_retrigger
= ioapic_retrigger_irq
,
3129 int arch_setup_dmar_msi(unsigned int irq
)
3134 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3137 dmar_msi_write(irq
, &msg
);
3138 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3144 #ifdef CONFIG_HPET_TIMER
3146 static int hpet_msi_set_affinity(struct irq_data
*data
,
3147 const struct cpumask
*mask
, bool force
)
3149 struct irq_cfg
*cfg
= data
->chip_data
;
3153 if (__ioapic_set_affinity(data
, mask
, &dest
))
3156 hpet_msi_read(data
->handler_data
, &msg
);
3158 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3159 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3160 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3161 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3163 hpet_msi_write(data
->handler_data
, &msg
);
3165 return IRQ_SET_MASK_OK_NOCOPY
;
3168 static struct irq_chip hpet_msi_type
= {
3170 .irq_unmask
= hpet_msi_unmask
,
3171 .irq_mask
= hpet_msi_mask
,
3172 .irq_ack
= ack_apic_edge
,
3173 .irq_set_affinity
= hpet_msi_set_affinity
,
3174 .irq_retrigger
= ioapic_retrigger_irq
,
3177 int default_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3179 struct irq_chip
*chip
= &hpet_msi_type
;
3183 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3187 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3188 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3189 setup_remapped_irq(irq
, irq_get_chip_data(irq
), chip
);
3191 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3196 #endif /* CONFIG_PCI_MSI */
3198 * Hypertransport interrupt support
3200 #ifdef CONFIG_HT_IRQ
3202 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3204 struct ht_irq_msg msg
;
3205 fetch_ht_irq_msg(irq
, &msg
);
3207 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3208 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3210 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3211 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3213 write_ht_irq_msg(irq
, &msg
);
3217 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3219 struct irq_cfg
*cfg
= data
->chip_data
;
3222 if (__ioapic_set_affinity(data
, mask
, &dest
))
3225 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3226 return IRQ_SET_MASK_OK_NOCOPY
;
3229 static struct irq_chip ht_irq_chip
= {
3231 .irq_mask
= mask_ht_irq
,
3232 .irq_unmask
= unmask_ht_irq
,
3233 .irq_ack
= ack_apic_edge
,
3234 .irq_set_affinity
= ht_set_affinity
,
3235 .irq_retrigger
= ioapic_retrigger_irq
,
3238 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3240 struct irq_cfg
*cfg
;
3241 struct ht_irq_msg msg
;
3249 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3253 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3254 apic
->target_cpus(), &dest
);
3258 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3262 HT_IRQ_LOW_DEST_ID(dest
) |
3263 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3264 ((apic
->irq_dest_mode
== 0) ?
3265 HT_IRQ_LOW_DM_PHYSICAL
:
3266 HT_IRQ_LOW_DM_LOGICAL
) |
3267 HT_IRQ_LOW_RQEOI_EDGE
|
3268 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3269 HT_IRQ_LOW_MT_FIXED
:
3270 HT_IRQ_LOW_MT_ARBITRATED
) |
3271 HT_IRQ_LOW_IRQ_MASKED
;
3273 write_ht_irq_msg(irq
, &msg
);
3275 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3276 handle_edge_irq
, "edge");
3278 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3282 #endif /* CONFIG_HT_IRQ */
3285 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3287 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3292 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3294 setup_ioapic_irq(irq
, cfg
, attr
);
3298 int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
3299 struct io_apic_irq_attr
*attr
)
3301 unsigned int ioapic_idx
= attr
->ioapic
, pin
= attr
->ioapic_pin
;
3303 struct IO_APIC_route_entry orig_entry
;
3305 /* Avoid redundant programming */
3306 if (test_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
)) {
3307 pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx
), pin
);
3308 orig_entry
= ioapic_read_entry(attr
->ioapic
, pin
);
3309 if (attr
->trigger
== orig_entry
.trigger
&& attr
->polarity
== orig_entry
.polarity
)
3313 ret
= io_apic_setup_irq_pin(irq
, node
, attr
);
3315 set_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
);
3319 static int __init
io_apic_get_redir_entries(int ioapic
)
3321 union IO_APIC_reg_01 reg_01
;
3322 unsigned long flags
;
3324 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3325 reg_01
.raw
= io_apic_read(ioapic
, 1);
3326 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3328 /* The register returns the maximum index redir index
3329 * supported, which is one less than the total number of redir
3332 return reg_01
.bits
.entries
+ 1;
3335 static void __init
probe_nr_irqs_gsi(void)
3339 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3340 if (nr
> nr_irqs_gsi
)
3343 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3346 unsigned int arch_dynirq_lower_bound(unsigned int from
)
3348 return from
< nr_irqs_gsi
? nr_irqs_gsi
: from
;
3351 int __init
arch_probe_nr_irqs(void)
3355 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3356 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3358 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3359 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3361 * for MSI and HT dyn irq
3363 nr
+= nr_irqs_gsi
* 16;
3368 return NR_IRQS_LEGACY
;
3371 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3372 struct io_apic_irq_attr
*irq_attr
)
3376 if (!IO_APIC_IRQ(irq
)) {
3377 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3382 node
= dev
? dev_to_node(dev
) : cpu_to_node(0);
3384 return io_apic_setup_irq_pin_once(irq
, node
, irq_attr
);
3387 #ifdef CONFIG_X86_32
3388 static int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3390 union IO_APIC_reg_00 reg_00
;
3391 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3393 unsigned long flags
;
3397 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3398 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3399 * supports up to 16 on one shared APIC bus.
3401 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3402 * advantage of new APIC bus architecture.
3405 if (physids_empty(apic_id_map
))
3406 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3408 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3409 reg_00
.raw
= io_apic_read(ioapic
, 0);
3410 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3412 if (apic_id
>= get_physical_broadcast()) {
3413 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3414 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3415 apic_id
= reg_00
.bits
.ID
;
3419 * Every APIC in a system must have a unique ID or we get lots of nice
3420 * 'stuck on smp_invalidate_needed IPI wait' messages.
3422 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3424 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3425 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3429 if (i
== get_physical_broadcast())
3430 panic("Max apic_id exceeded!\n");
3432 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3433 "trying %d\n", ioapic
, apic_id
, i
);
3438 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3439 physids_or(apic_id_map
, apic_id_map
, tmp
);
3441 if (reg_00
.bits
.ID
!= apic_id
) {
3442 reg_00
.bits
.ID
= apic_id
;
3444 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3445 io_apic_write(ioapic
, 0, reg_00
.raw
);
3446 reg_00
.raw
= io_apic_read(ioapic
, 0);
3447 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3450 if (reg_00
.bits
.ID
!= apic_id
) {
3451 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3457 apic_printk(APIC_VERBOSE
, KERN_INFO
3458 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3463 static u8 __init
io_apic_unique_id(u8 id
)
3465 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3466 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3467 return io_apic_get_unique_id(nr_ioapics
, id
);
3472 static u8 __init
io_apic_unique_id(u8 id
)
3475 DECLARE_BITMAP(used
, 256);
3477 bitmap_zero(used
, 256);
3478 for (i
= 0; i
< nr_ioapics
; i
++) {
3479 __set_bit(mpc_ioapic_id(i
), used
);
3481 if (!test_bit(id
, used
))
3483 return find_first_zero_bit(used
, 256);
3487 static int __init
io_apic_get_version(int ioapic
)
3489 union IO_APIC_reg_01 reg_01
;
3490 unsigned long flags
;
3492 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3493 reg_01
.raw
= io_apic_read(ioapic
, 1);
3494 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3496 return reg_01
.bits
.version
;
3499 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3501 int ioapic
, pin
, idx
;
3503 if (skip_ioapic_setup
)
3506 ioapic
= mp_find_ioapic(gsi
);
3510 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3514 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3518 *trigger
= irq_trigger(idx
);
3519 *polarity
= irq_polarity(idx
);
3524 * This function currently is only a helper for the i386 smp boot process where
3525 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3526 * so mask in all cases should simply be apic->target_cpus()
3529 void __init
setup_ioapic_dest(void)
3531 int pin
, ioapic
, irq
, irq_entry
;
3532 const struct cpumask
*mask
;
3533 struct irq_data
*idata
;
3535 if (skip_ioapic_setup
== 1)
3538 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
3539 for (pin
= 0; pin
< ioapics
[ioapic
].nr_registers
; pin
++) {
3540 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3541 if (irq_entry
== -1)
3543 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3545 if ((ioapic
> 0) && (irq
> 16))
3548 idata
= irq_get_irq_data(irq
);
3551 * Honour affinities which have been set in early boot
3553 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3554 mask
= idata
->affinity
;
3556 mask
= apic
->target_cpus();
3558 x86_io_apic_ops
.set_affinity(idata
, mask
, false);
3564 #define IOAPIC_RESOURCE_NAME_SIZE 11
3566 static struct resource
*ioapic_resources
;
3568 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
3571 struct resource
*res
;
3575 if (nr_ioapics
<= 0)
3578 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3581 mem
= alloc_bootmem(n
);
3584 mem
+= sizeof(struct resource
) * nr_ioapics
;
3586 for (i
= 0; i
< nr_ioapics
; i
++) {
3588 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3589 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3590 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3593 ioapic_resources
= res
;
3598 void __init
native_io_apic_init_mappings(void)
3600 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3601 struct resource
*ioapic_res
;
3604 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
3605 for (i
= 0; i
< nr_ioapics
; i
++) {
3606 if (smp_found_config
) {
3607 ioapic_phys
= mpc_ioapic_addr(i
);
3608 #ifdef CONFIG_X86_32
3611 "WARNING: bogus zero IO-APIC "
3612 "address found in MPTABLE, "
3613 "disabling IO/APIC support!\n");
3614 smp_found_config
= 0;
3615 skip_ioapic_setup
= 1;
3616 goto fake_ioapic_page
;
3620 #ifdef CONFIG_X86_32
3623 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3624 ioapic_phys
= __pa(ioapic_phys
);
3626 set_fixmap_nocache(idx
, ioapic_phys
);
3627 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3628 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3632 ioapic_res
->start
= ioapic_phys
;
3633 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3637 probe_nr_irqs_gsi();
3640 void __init
ioapic_insert_resources(void)
3643 struct resource
*r
= ioapic_resources
;
3648 "IO APIC resources couldn't be allocated.\n");
3652 for (i
= 0; i
< nr_ioapics
; i
++) {
3653 insert_resource(&iomem_resource
, r
);
3658 int mp_find_ioapic(u32 gsi
)
3662 if (nr_ioapics
== 0)
3665 /* Find the IOAPIC that manages this GSI. */
3666 for (i
= 0; i
< nr_ioapics
; i
++) {
3667 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
3668 if ((gsi
>= gsi_cfg
->gsi_base
)
3669 && (gsi
<= gsi_cfg
->gsi_end
))
3673 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3677 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3679 struct mp_ioapic_gsi
*gsi_cfg
;
3681 if (WARN_ON(ioapic
== -1))
3684 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3685 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
3688 return gsi
- gsi_cfg
->gsi_base
;
3691 static __init
int bad_ioapic(unsigned long address
)
3693 if (nr_ioapics
>= MAX_IO_APICS
) {
3694 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3695 MAX_IO_APICS
, nr_ioapics
);
3699 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3705 static __init
int bad_ioapic_register(int idx
)
3707 union IO_APIC_reg_00 reg_00
;
3708 union IO_APIC_reg_01 reg_01
;
3709 union IO_APIC_reg_02 reg_02
;
3711 reg_00
.raw
= io_apic_read(idx
, 0);
3712 reg_01
.raw
= io_apic_read(idx
, 1);
3713 reg_02
.raw
= io_apic_read(idx
, 2);
3715 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
3716 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3717 mpc_ioapic_addr(idx
));
3724 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
3728 struct mp_ioapic_gsi
*gsi_cfg
;
3730 if (bad_ioapic(address
))
3735 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
3736 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
3737 ioapics
[idx
].mp_config
.apicaddr
= address
;
3739 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
3741 if (bad_ioapic_register(idx
)) {
3742 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3746 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(id
);
3747 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
3750 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3751 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3753 entries
= io_apic_get_redir_entries(idx
);
3754 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
3755 gsi_cfg
->gsi_base
= gsi_base
;
3756 gsi_cfg
->gsi_end
= gsi_base
+ entries
- 1;
3759 * The number of IO-APIC IRQ registers (== #pins):
3761 ioapics
[idx
].nr_registers
= entries
;
3763 if (gsi_cfg
->gsi_end
>= gsi_top
)
3764 gsi_top
= gsi_cfg
->gsi_end
+ 1;
3766 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3767 idx
, mpc_ioapic_id(idx
),
3768 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
3769 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3774 /* Enable IOAPIC early just for system timer */
3775 void __init
pre_init_apic_IRQ0(void)
3777 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
3779 printk(KERN_INFO
"Early APIC setup for system timer0\n");
3781 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
3782 &phys_cpu_present_map
);
3786 io_apic_setup_irq_pin(0, 0, &attr
);
3787 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,