2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr
;
55 DEFINE_PER_CPU(u16
, x86_bios_cpu_apicid
) = BAD_APICID
;
56 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
59 * Knob to control our willingness to enable the local APIC.
61 * -1=force-disable, +1=force-enable
63 static int enable_local_apic __initdata
;
65 /* Local APIC timer verification ok */
66 static int local_apic_timer_verify_ok
;
67 /* Disable local APIC timer from the kernel commandline or via dmi quirk
68 or using CPU MSR check */
69 int local_apic_timer_disabled
;
70 /* Local APIC timer works in C2 */
71 int local_apic_timer_c2_ok
;
72 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
75 * Debug level, exported for io_apic.c
81 static unsigned int calibration_result
;
83 static int lapic_next_event(unsigned long delta
,
84 struct clock_event_device
*evt
);
85 static void lapic_timer_setup(enum clock_event_mode mode
,
86 struct clock_event_device
*evt
);
87 static void lapic_timer_broadcast(cpumask_t mask
);
88 static void apic_pm_activate(void);
91 * The local apic timer can be used for any function which is CPU local.
93 static struct clock_event_device lapic_clockevent
= {
95 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
96 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
98 .set_mode
= lapic_timer_setup
,
99 .set_next_event
= lapic_next_event
,
100 .broadcast
= lapic_timer_broadcast
,
104 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
106 /* Local APIC was disabled by the BIOS and enabled by the kernel */
107 static int enabled_via_apicbase
;
109 static unsigned long apic_phys
;
112 * Get the LAPIC version
114 static inline int lapic_get_version(void)
116 return GET_APIC_VERSION(apic_read(APIC_LVR
));
120 * Check, if the APIC is integrated or a separate chip
122 static inline int lapic_is_integrated(void)
124 return APIC_INTEGRATED(lapic_get_version());
128 * Check, whether this is a modern or a first generation APIC
130 static int modern_apic(void)
132 /* AMD systems use old APIC versions, so check the CPU */
133 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
134 boot_cpu_data
.x86
>= 0xf)
136 return lapic_get_version() >= 0x14;
139 void apic_wait_icr_idle(void)
141 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
145 u32
safe_apic_wait_icr_idle(void)
152 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
156 } while (timeout
++ < 1000);
162 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
164 void __cpuinit
enable_NMI_through_LVT0(void)
166 unsigned int v
= APIC_DM_NMI
;
168 /* Level triggered for 82489DX */
169 if (!lapic_is_integrated())
170 v
|= APIC_LVT_LEVEL_TRIGGER
;
171 apic_write_around(APIC_LVT0
, v
);
175 * get_physical_broadcast - Get number of physical broadcast IDs
177 int get_physical_broadcast(void)
179 return modern_apic() ? 0xff : 0xf;
183 * lapic_get_maxlvt - get the maximum number of local vector table entries
185 int lapic_get_maxlvt(void)
187 unsigned int v
= apic_read(APIC_LVR
);
189 /* 82489DXs do not report # of LVT entries. */
190 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
197 /* Clock divisor is set to 16 */
198 #define APIC_DIVISOR 16
201 * This function sets up the local APIC timer, with a timeout of
202 * 'clocks' APIC bus clock. During calibration we actually call
203 * this function twice on the boot CPU, once with a bogus timeout
204 * value, second time for real. The other (noncalibrating) CPUs
205 * call this function only once, with the real, calibrated value.
207 * We do reads before writes even if unnecessary, to get around the
208 * P5 APIC double write bug.
210 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
212 unsigned int lvtt_value
, tmp_value
;
214 lvtt_value
= LOCAL_TIMER_VECTOR
;
216 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
217 if (!lapic_is_integrated())
218 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
221 lvtt_value
|= APIC_LVT_MASKED
;
223 apic_write_around(APIC_LVTT
, lvtt_value
);
228 tmp_value
= apic_read(APIC_TDCR
);
229 apic_write_around(APIC_TDCR
, (tmp_value
230 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
234 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
238 * Program the next event, relative to now
240 static int lapic_next_event(unsigned long delta
,
241 struct clock_event_device
*evt
)
243 apic_write_around(APIC_TMICT
, delta
);
248 * Setup the lapic timer in periodic or oneshot mode
250 static void lapic_timer_setup(enum clock_event_mode mode
,
251 struct clock_event_device
*evt
)
256 /* Lapic used for broadcast ? */
257 if (!local_apic_timer_verify_ok
)
260 local_irq_save(flags
);
263 case CLOCK_EVT_MODE_PERIODIC
:
264 case CLOCK_EVT_MODE_ONESHOT
:
265 __setup_APIC_LVTT(calibration_result
,
266 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
268 case CLOCK_EVT_MODE_UNUSED
:
269 case CLOCK_EVT_MODE_SHUTDOWN
:
270 v
= apic_read(APIC_LVTT
);
271 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
272 apic_write_around(APIC_LVTT
, v
);
274 case CLOCK_EVT_MODE_RESUME
:
275 /* Nothing to do here */
279 local_irq_restore(flags
);
283 * Local APIC timer broadcast function
285 static void lapic_timer_broadcast(cpumask_t mask
)
288 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
293 * Setup the local APIC timer for this CPU. Copy the initilized values
294 * of the boot CPU and register the clock event in the framework.
296 static void __devinit
setup_APIC_timer(void)
298 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
300 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
301 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
303 clockevents_register_device(levt
);
307 * In this functions we calibrate APIC bus clocks to the external timer.
309 * We want to do the calibration only once since we want to have local timer
310 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
313 * This was previously done by reading the PIT/HPET and waiting for a wrap
314 * around to find out, that a tick has elapsed. I have a box, where the PIT
315 * readout is broken, so it never gets out of the wait loop again. This was
316 * also reported by others.
318 * Monitoring the jiffies value is inaccurate and the clockevents
319 * infrastructure allows us to do a simple substitution of the interrupt
322 * The calibration routine also uses the pm_timer when possible, as the PIT
323 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
324 * back to normal later in the boot process).
327 #define LAPIC_CAL_LOOPS (HZ/10)
329 static __initdata
int lapic_cal_loops
= -1;
330 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
331 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
332 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
333 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
336 * Temporary interrupt handler.
338 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
340 unsigned long long tsc
= 0;
341 long tapic
= apic_read(APIC_TMCCT
);
342 unsigned long pm
= acpi_pm_read_early();
347 switch (lapic_cal_loops
++) {
349 lapic_cal_t1
= tapic
;
350 lapic_cal_tsc1
= tsc
;
352 lapic_cal_j1
= jiffies
;
355 case LAPIC_CAL_LOOPS
:
356 lapic_cal_t2
= tapic
;
357 lapic_cal_tsc2
= tsc
;
358 if (pm
< lapic_cal_pm1
)
359 pm
+= ACPI_PM_OVRRUN
;
361 lapic_cal_j2
= jiffies
;
367 * Setup the boot APIC
369 * Calibrate and verify the result.
371 void __init
setup_boot_APIC_clock(void)
373 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
374 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
375 const long pm_thresh
= pm_100ms
/100;
376 void (*real_handler
)(struct clock_event_device
*dev
);
377 unsigned long deltaj
;
379 int pm_referenced
= 0;
382 * The local apic timer can be disabled via the kernel
383 * commandline or from the CPU detection code. Register the lapic
384 * timer as a dummy clock event source on SMP systems, so the
385 * broadcast mechanism is used. On UP systems simply ignore it.
387 if (local_apic_timer_disabled
) {
388 /* No broadcast on UP ! */
389 if (num_possible_cpus() > 1) {
390 lapic_clockevent
.mult
= 1;
396 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
397 "calibrating APIC timer ...\n");
401 /* Replace the global interrupt handler */
402 real_handler
= global_clock_event
->event_handler
;
403 global_clock_event
->event_handler
= lapic_cal_handler
;
406 * Setup the APIC counter to 1e9. There is no way the lapic
407 * can underflow in the 100ms detection time frame
409 __setup_APIC_LVTT(1000000000, 0, 0);
411 /* Let the interrupts run */
414 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
419 /* Restore the real event handler */
420 global_clock_event
->event_handler
= real_handler
;
422 /* Build delta t1-t2 as apic timer counts down */
423 delta
= lapic_cal_t1
- lapic_cal_t2
;
424 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
426 /* Check, if the PM timer is available */
427 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
428 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
434 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
436 if (deltapm
> (pm_100ms
- pm_thresh
) &&
437 deltapm
< (pm_100ms
+ pm_thresh
)) {
438 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
440 res
= (((u64
) deltapm
) * mult
) >> 22;
441 do_div(res
, 1000000);
442 printk(KERN_WARNING
"APIC calibration not consistent "
443 "with PM Timer: %ldms instead of 100ms\n",
445 /* Correct the lapic counter value */
446 res
= (((u64
) delta
) * pm_100ms
);
447 do_div(res
, deltapm
);
448 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
449 "%lu (%ld)\n", (unsigned long) res
, delta
);
455 /* Calculate the scaled math multiplication factor */
456 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
457 lapic_clockevent
.shift
);
458 lapic_clockevent
.max_delta_ns
=
459 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
460 lapic_clockevent
.min_delta_ns
=
461 clockevent_delta2ns(0xF, &lapic_clockevent
);
463 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
465 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
466 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
467 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
471 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
472 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
474 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
475 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
478 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
480 calibration_result
/ (1000000 / HZ
),
481 calibration_result
% (1000000 / HZ
));
483 local_apic_timer_verify_ok
= 1;
486 * Do a sanity check on the APIC calibration result
488 if (calibration_result
< (1000000 / HZ
)) {
491 "APIC frequency too slow, disabling apic timer\n");
492 /* No broadcast on UP ! */
493 if (num_possible_cpus() > 1)
498 /* We trust the pm timer based calibration */
499 if (!pm_referenced
) {
500 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
503 * Setup the apic timer manually
505 levt
->event_handler
= lapic_cal_handler
;
506 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
507 lapic_cal_loops
= -1;
509 /* Let the interrupts run */
512 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
517 /* Stop the lapic timer */
518 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
523 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
524 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
526 /* Check, if the jiffies result is consistent */
527 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
528 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
530 local_apic_timer_verify_ok
= 0;
534 if (!local_apic_timer_verify_ok
) {
536 "APIC timer disabled due to verification failure.\n");
537 /* No broadcast on UP ! */
538 if (num_possible_cpus() == 1)
542 * If nmi_watchdog is set to IO_APIC, we need the
543 * PIT/HPET going. Otherwise register lapic as a dummy
546 if (nmi_watchdog
!= NMI_IO_APIC
)
547 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
549 printk(KERN_WARNING
"APIC timer registered as dummy,"
550 " due to nmi_watchdog=1!\n");
553 /* Setup the lapic or request the broadcast */
557 void __devinit
setup_secondary_APIC_clock(void)
563 * The guts of the apic timer interrupt
565 static void local_apic_timer_interrupt(void)
567 int cpu
= smp_processor_id();
568 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
571 * Normally we should not be here till LAPIC has been initialized but
572 * in some cases like kdump, its possible that there is a pending LAPIC
573 * timer interrupt from previous kernel's context and is delivered in
574 * new kernel the moment interrupts are enabled.
576 * Interrupts are enabled early and LAPIC is setup much later, hence
577 * its possible that when we get here evt->event_handler is NULL.
578 * Check for event_handler being NULL and discard the interrupt as
581 if (!evt
->event_handler
) {
583 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
585 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
590 * the NMI deadlock-detector uses this.
592 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
594 evt
->event_handler(evt
);
598 * Local APIC timer interrupt. This is the most natural way for doing
599 * local interrupts, but local timer interrupts can be emulated by
600 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
602 * [ if a single-CPU system runs an SMP kernel then we call the local
603 * interrupt as well. Thus we cannot inline the local irq ... ]
605 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
607 struct pt_regs
*old_regs
= set_irq_regs(regs
);
610 * NOTE! We'd better ACK the irq immediately,
611 * because timer handling can be slow.
615 * update_process_times() expects us to have done irq_enter().
616 * Besides, if we don't timer interrupts ignore the global
617 * interrupt lock, which is the WrongThing (tm) to do.
620 local_apic_timer_interrupt();
623 set_irq_regs(old_regs
);
626 int setup_profiling_timer(unsigned int multiplier
)
632 * Setup extended LVT, AMD specific (K8, family 10h)
634 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
635 * MCE interrupts are supported. Thus MCE offset must be set to 0.
638 #define APIC_EILVT_LVTOFF_MCE 0
639 #define APIC_EILVT_LVTOFF_IBS 1
641 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
643 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
644 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
648 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
650 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
651 return APIC_EILVT_LVTOFF_MCE
;
654 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
656 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
657 return APIC_EILVT_LVTOFF_IBS
;
661 * Local APIC start and shutdown
665 * clear_local_APIC - shutdown the local APIC
667 * This is called, when a CPU is disabled and before rebooting, so the state of
668 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
669 * leftovers during boot.
671 void clear_local_APIC(void)
676 /* APIC hasn't been mapped yet */
680 maxlvt
= lapic_get_maxlvt();
682 * Masking an LVT entry can trigger a local APIC error
683 * if the vector is zero. Mask LVTERR first to prevent this.
686 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
687 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
690 * Careful: we have to set masks only first to deassert
691 * any level-triggered sources.
693 v
= apic_read(APIC_LVTT
);
694 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
695 v
= apic_read(APIC_LVT0
);
696 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
697 v
= apic_read(APIC_LVT1
);
698 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
700 v
= apic_read(APIC_LVTPC
);
701 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
704 /* lets not touch this if we didn't frob it */
705 #ifdef CONFIG_X86_MCE_P4THERMAL
707 v
= apic_read(APIC_LVTTHMR
);
708 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
712 * Clean APIC state for other OSs:
714 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
715 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
716 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
718 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
720 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
722 #ifdef CONFIG_X86_MCE_P4THERMAL
724 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
726 /* Integrated APIC (!82489DX) ? */
727 if (lapic_is_integrated()) {
729 /* Clear ESR due to Pentium errata 3AP and 11AP */
730 apic_write(APIC_ESR
, 0);
736 * disable_local_APIC - clear and disable the local APIC
738 void disable_local_APIC(void)
745 * Disable APIC (implies clearing of registers
748 value
= apic_read(APIC_SPIV
);
749 value
&= ~APIC_SPIV_APIC_ENABLED
;
750 apic_write_around(APIC_SPIV
, value
);
753 * When LAPIC was disabled by the BIOS and enabled by the kernel,
754 * restore the disabled state.
756 if (enabled_via_apicbase
) {
759 rdmsr(MSR_IA32_APICBASE
, l
, h
);
760 l
&= ~MSR_IA32_APICBASE_ENABLE
;
761 wrmsr(MSR_IA32_APICBASE
, l
, h
);
766 * If Linux enabled the LAPIC against the BIOS default disable it down before
767 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
768 * not power-off. Additionally clear all LVT entries before disable_local_APIC
769 * for the case where Linux didn't enable the LAPIC.
771 void lapic_shutdown(void)
778 local_irq_save(flags
);
781 if (enabled_via_apicbase
)
782 disable_local_APIC();
784 local_irq_restore(flags
);
788 * This is to verify that we're looking at a real local APIC.
789 * Check these against your board if the CPUs aren't getting
790 * started for no apparent reason.
792 int __init
verify_local_APIC(void)
794 unsigned int reg0
, reg1
;
797 * The version register is read-only in a real APIC.
799 reg0
= apic_read(APIC_LVR
);
800 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
801 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
802 reg1
= apic_read(APIC_LVR
);
803 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
806 * The two version reads above should print the same
807 * numbers. If the second one is different, then we
808 * poke at a non-APIC.
814 * Check if the version looks reasonably.
816 reg1
= GET_APIC_VERSION(reg0
);
817 if (reg1
== 0x00 || reg1
== 0xff)
819 reg1
= lapic_get_maxlvt();
820 if (reg1
< 0x02 || reg1
== 0xff)
824 * The ID register is read/write in a real APIC.
826 reg0
= apic_read(APIC_ID
);
827 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
830 * The next two are just to see if we have sane values.
831 * They're only really relevant if we're in Virtual Wire
832 * compatibility mode, but most boxes are anymore.
834 reg0
= apic_read(APIC_LVT0
);
835 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
836 reg1
= apic_read(APIC_LVT1
);
837 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
843 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
845 void __init
sync_Arb_IDs(void)
848 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
851 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
856 apic_wait_icr_idle();
858 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
859 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
864 * An initial setup of the virtual wire mode.
866 void __init
init_bsp_APIC(void)
871 * Don't do the setup now if we have a SMP BIOS as the
872 * through-I/O-APIC virtual wire mode might be active.
874 if (smp_found_config
|| !cpu_has_apic
)
878 * Do not trust the local APIC being empty at bootup.
885 value
= apic_read(APIC_SPIV
);
886 value
&= ~APIC_VECTOR_MASK
;
887 value
|= APIC_SPIV_APIC_ENABLED
;
889 /* This bit is reserved on P4/Xeon and should be cleared */
890 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
891 (boot_cpu_data
.x86
== 15))
892 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
894 value
|= APIC_SPIV_FOCUS_DISABLED
;
895 value
|= SPURIOUS_APIC_VECTOR
;
896 apic_write_around(APIC_SPIV
, value
);
899 * Set up the virtual wire mode.
901 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
903 if (!lapic_is_integrated()) /* 82489DX */
904 value
|= APIC_LVT_LEVEL_TRIGGER
;
905 apic_write_around(APIC_LVT1
, value
);
908 static void __cpuinit
lapic_setup_esr(void)
910 unsigned long oldvalue
, value
, maxlvt
;
911 if (lapic_is_integrated() && !esr_disable
) {
913 maxlvt
= lapic_get_maxlvt();
914 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
915 apic_write(APIC_ESR
, 0);
916 oldvalue
= apic_read(APIC_ESR
);
918 /* enables sending errors */
919 value
= ERROR_APIC_VECTOR
;
920 apic_write_around(APIC_LVTERR
, value
);
922 * spec says clear errors after enabling vector.
925 apic_write(APIC_ESR
, 0);
926 value
= apic_read(APIC_ESR
);
927 if (value
!= oldvalue
)
928 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
929 "vector: 0x%08lx after: 0x%08lx\n",
934 * Something untraceable is creating bad interrupts on
935 * secondary quads ... for the moment, just leave the
936 * ESR disabled - we can't do anything useful with the
937 * errors anyway - mbligh
939 printk(KERN_INFO
"Leaving ESR disabled.\n");
941 printk(KERN_INFO
"No ESR for 82489DX.\n");
947 * setup_local_APIC - setup the local APIC
949 void __cpuinit
setup_local_APIC(void)
951 unsigned long value
, integrated
;
954 /* Pound the ESR really hard over the head with a big hammer - mbligh */
956 apic_write(APIC_ESR
, 0);
957 apic_write(APIC_ESR
, 0);
958 apic_write(APIC_ESR
, 0);
959 apic_write(APIC_ESR
, 0);
962 integrated
= lapic_is_integrated();
965 * Double-check whether this APIC is really registered.
967 if (!apic_id_registered())
971 * Intel recommends to set DFR, LDR and TPR before enabling
972 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
973 * document number 292116). So here it goes...
978 * Set Task Priority to 'accept all'. We never change this
981 value
= apic_read(APIC_TASKPRI
);
982 value
&= ~APIC_TPRI_MASK
;
983 apic_write_around(APIC_TASKPRI
, value
);
986 * After a crash, we no longer service the interrupts and a pending
987 * interrupt from previous kernel might still have ISR bit set.
989 * Most probably by now CPU has serviced that pending interrupt and
990 * it might not have done the ack_APIC_irq() because it thought,
991 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
992 * does not clear the ISR bit and cpu thinks it has already serivced
993 * the interrupt. Hence a vector might get locked. It was noticed
994 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
996 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
997 value
= apic_read(APIC_ISR
+ i
*0x10);
998 for (j
= 31; j
>= 0; j
--) {
1005 * Now that we are all set up, enable the APIC
1007 value
= apic_read(APIC_SPIV
);
1008 value
&= ~APIC_VECTOR_MASK
;
1012 value
|= APIC_SPIV_APIC_ENABLED
;
1015 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1016 * certain networking cards. If high frequency interrupts are
1017 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1018 * entry is masked/unmasked at a high rate as well then sooner or
1019 * later IOAPIC line gets 'stuck', no more interrupts are received
1020 * from the device. If focus CPU is disabled then the hang goes
1023 * [ This bug can be reproduced easily with a level-triggered
1024 * PCI Ne2000 networking cards and PII/PIII processors, dual
1028 * Actually disabling the focus CPU check just makes the hang less
1029 * frequent as it makes the interrupt distributon model be more
1030 * like LRU than MRU (the short-term load is more even across CPUs).
1031 * See also the comment in end_level_ioapic_irq(). --macro
1034 /* Enable focus processor (bit==0) */
1035 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1038 * Set spurious IRQ vector
1040 value
|= SPURIOUS_APIC_VECTOR
;
1041 apic_write_around(APIC_SPIV
, value
);
1044 * Set up LVT0, LVT1:
1046 * set up through-local-APIC on the BP's LINT0. This is not
1047 * strictly necessary in pure symmetric-IO mode, but sometimes
1048 * we delegate interrupts to the 8259A.
1051 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1053 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1054 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1055 value
= APIC_DM_EXTINT
;
1056 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1057 smp_processor_id());
1059 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1060 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1061 smp_processor_id());
1063 apic_write_around(APIC_LVT0
, value
);
1066 * only the BP should see the LINT1 NMI signal, obviously.
1068 if (!smp_processor_id())
1069 value
= APIC_DM_NMI
;
1071 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1072 if (!integrated
) /* 82489DX */
1073 value
|= APIC_LVT_LEVEL_TRIGGER
;
1074 apic_write_around(APIC_LVT1
, value
);
1077 void __cpuinit
end_local_APIC_setup(void)
1079 unsigned long value
;
1082 /* Disable the local apic timer */
1083 value
= apic_read(APIC_LVTT
);
1084 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1085 apic_write_around(APIC_LVTT
, value
);
1087 setup_apic_nmi_watchdog(NULL
);
1092 * Detect and initialize APIC
1094 static int __init
detect_init_APIC(void)
1098 /* Disabled by kernel option? */
1099 if (enable_local_apic
< 0)
1102 switch (boot_cpu_data
.x86_vendor
) {
1103 case X86_VENDOR_AMD
:
1104 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1105 (boot_cpu_data
.x86
== 15))
1108 case X86_VENDOR_INTEL
:
1109 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1110 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1117 if (!cpu_has_apic
) {
1119 * Over-ride BIOS and try to enable the local APIC only if
1120 * "lapic" specified.
1122 if (enable_local_apic
<= 0) {
1123 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1124 "you can enable it with \"lapic\"\n");
1128 * Some BIOSes disable the local APIC in the APIC_BASE
1129 * MSR. This can only be done in software for Intel P6 or later
1130 * and AMD K7 (Model > 1) or later.
1132 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1133 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1135 "Local APIC disabled by BIOS -- reenabling.\n");
1136 l
&= ~MSR_IA32_APICBASE_BASE
;
1137 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1138 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1139 enabled_via_apicbase
= 1;
1143 * The APIC feature bit should now be enabled
1146 features
= cpuid_edx(1);
1147 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1148 printk(KERN_WARNING
"Could not enable APIC!\n");
1151 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1152 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1154 /* The BIOS may have set up the APIC at some other address */
1155 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1156 if (l
& MSR_IA32_APICBASE_ENABLE
)
1157 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1159 if (nmi_watchdog
!= NMI_NONE
&& nmi_watchdog
!= NMI_DISABLED
)
1160 nmi_watchdog
= NMI_LOCAL_APIC
;
1162 printk(KERN_INFO
"Found and enabled local APIC!\n");
1169 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1174 * init_apic_mappings - initialize APIC mappings
1176 void __init
init_apic_mappings(void)
1179 * If no local APIC can be found then set up a fake all
1180 * zeroes page to simulate the local APIC and another
1181 * one for the IO-APIC.
1183 if (!smp_found_config
&& detect_init_APIC()) {
1184 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1185 apic_phys
= __pa(apic_phys
);
1187 apic_phys
= mp_lapic_addr
;
1189 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1190 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1194 * Fetch the APIC ID of the BSP in case we have a
1195 * default configuration (or the MP table is broken).
1197 if (boot_cpu_physical_apicid
== -1U)
1198 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
1200 #ifdef CONFIG_X86_IO_APIC
1202 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1205 for (i
= 0; i
< nr_ioapics
; i
++) {
1206 if (smp_found_config
) {
1207 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
1210 "WARNING: bogus zero IO-APIC "
1211 "address found in MPTABLE, "
1212 "disabling IO/APIC support!\n");
1213 smp_found_config
= 0;
1214 skip_ioapic_setup
= 1;
1215 goto fake_ioapic_page
;
1219 ioapic_phys
= (unsigned long)
1220 alloc_bootmem_pages(PAGE_SIZE
);
1221 ioapic_phys
= __pa(ioapic_phys
);
1223 set_fixmap_nocache(idx
, ioapic_phys
);
1224 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1225 __fix_to_virt(idx
), ioapic_phys
);
1233 * This initializes the IO-APIC and APIC hardware if this is
1237 int apic_version
[MAX_APICS
];
1239 int __init
APIC_init_uniprocessor(void)
1241 if (enable_local_apic
< 0)
1242 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1244 if (!smp_found_config
&& !cpu_has_apic
)
1248 * Complain if the BIOS pretends there is one.
1250 if (!cpu_has_apic
&&
1251 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1252 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1253 boot_cpu_physical_apicid
);
1254 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1258 verify_local_APIC();
1263 * Hack: In case of kdump, after a crash, kernel might be booting
1264 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1265 * might be zero if read from MP tables. Get it from LAPIC.
1267 #ifdef CONFIG_CRASH_DUMP
1268 boot_cpu_physical_apicid
= GET_APIC_ID(read_apic_id());
1270 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1274 end_local_APIC_setup();
1275 #ifdef CONFIG_X86_IO_APIC
1276 if (smp_found_config
)
1277 if (!skip_ioapic_setup
&& nr_ioapics
)
1286 * Local APIC interrupts
1290 * This interrupt should _never_ happen with our APIC/SMP architecture
1292 void smp_spurious_interrupt(struct pt_regs
*regs
)
1298 * Check if this really is a spurious interrupt and ACK it
1299 * if it is a vectored one. Just in case...
1300 * Spurious interrupts should not be ACKed.
1302 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1303 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1306 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1307 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1308 "should never happen.\n", smp_processor_id());
1309 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1314 * This interrupt should never happen with our APIC/SMP architecture
1316 void smp_error_interrupt(struct pt_regs
*regs
)
1318 unsigned long v
, v1
;
1321 /* First tickle the hardware, only then report what went on. -- REW */
1322 v
= apic_read(APIC_ESR
);
1323 apic_write(APIC_ESR
, 0);
1324 v1
= apic_read(APIC_ESR
);
1326 atomic_inc(&irq_err_count
);
1328 /* Here is what the APIC error bits mean:
1331 2: Send accept error
1332 3: Receive accept error
1334 5: Send illegal vector
1335 6: Received illegal vector
1336 7: Illegal register address
1338 printk(KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1339 smp_processor_id(), v
, v1
);
1344 void __init
smp_intr_init(void)
1347 * IRQ0 must be given a fixed assignment and initialized,
1348 * because it's used before the IO-APIC is set up.
1350 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1353 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1354 * IPI, driven by wakeup.
1356 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1358 /* IPI for invalidation */
1359 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1361 /* IPI for generic function call */
1362 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1367 * Initialize APIC interrupts
1369 void __init
apic_intr_init(void)
1374 /* self generated IPI for local APIC timer */
1375 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1377 /* IPI vectors for APIC spurious and error interrupts */
1378 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1379 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1381 /* thermal monitor LVT interrupt */
1382 #ifdef CONFIG_X86_MCE_P4THERMAL
1383 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1388 * connect_bsp_APIC - attach the APIC to the interrupt system
1390 void __init
connect_bsp_APIC(void)
1394 * Do not trust the local APIC being empty at bootup.
1398 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1399 * local APIC to INT and NMI lines.
1401 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1402 "enabling APIC mode.\n");
1410 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1411 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1413 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1416 void disconnect_bsp_APIC(int virt_wire_setup
)
1420 * Put the board back into PIC mode (has an effect only on
1421 * certain older boards). Note that APIC interrupts, including
1422 * IPIs, won't work beyond this point! The only exception are
1425 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1426 "entering PIC mode.\n");
1430 /* Go back to Virtual Wire compatibility mode */
1431 unsigned long value
;
1433 /* For the spurious interrupt use vector F, and enable it */
1434 value
= apic_read(APIC_SPIV
);
1435 value
&= ~APIC_VECTOR_MASK
;
1436 value
|= APIC_SPIV_APIC_ENABLED
;
1438 apic_write_around(APIC_SPIV
, value
);
1440 if (!virt_wire_setup
) {
1442 * For LVT0 make it edge triggered, active high,
1443 * external and enabled
1445 value
= apic_read(APIC_LVT0
);
1446 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1447 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1448 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1449 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1450 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1451 apic_write_around(APIC_LVT0
, value
);
1454 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1458 * For LVT1 make it edge triggered, active high, nmi and
1461 value
= apic_read(APIC_LVT1
);
1463 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1464 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1465 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1466 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1467 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1468 apic_write_around(APIC_LVT1
, value
);
1472 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
1474 void __cpuinit
generic_processor_info(int apicid
, int version
)
1478 physid_mask_t phys_cpu
;
1483 if (version
== 0x0) {
1484 printk(KERN_WARNING
"BIOS bug, APIC version is 0 for CPU#%d! "
1485 "fixing up to 0x10. (tell your hw vendor)\n",
1489 apic_version
[apicid
] = version
;
1491 phys_cpu
= apicid_to_cpu_present(apicid
);
1492 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, phys_cpu
);
1494 if (num_processors
>= NR_CPUS
) {
1495 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1496 " Processor ignored.\n", NR_CPUS
);
1500 if (num_processors
>= maxcpus
) {
1501 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1502 " Processor ignored.\n", maxcpus
);
1507 cpus_complement(tmp_map
, cpu_present_map
);
1508 cpu
= first_cpu(tmp_map
);
1510 if (apicid
== boot_cpu_physical_apicid
)
1512 * x86_bios_cpu_apicid is required to have processors listed
1513 * in same order as logical cpu numbers. Hence the first
1514 * entry is BSP, and so on.
1519 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1520 * but we need to work other dependencies like SMP_SUSPEND etc
1521 * before this can be done without some confusion.
1522 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1523 * - Ashok Raj <ashok.raj@intel.com>
1525 if (num_processors
> 8) {
1526 switch (boot_cpu_data
.x86_vendor
) {
1527 case X86_VENDOR_INTEL
:
1528 if (!APIC_XAPIC(version
)) {
1532 /* If P4 and above fall through */
1533 case X86_VENDOR_AMD
:
1538 /* are we being called early in kernel startup? */
1539 if (x86_cpu_to_apicid_early_ptr
) {
1540 u16
*cpu_to_apicid
= x86_cpu_to_apicid_early_ptr
;
1541 u16
*bios_cpu_apicid
= x86_bios_cpu_apicid_early_ptr
;
1543 cpu_to_apicid
[cpu
] = apicid
;
1544 bios_cpu_apicid
[cpu
] = apicid
;
1546 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1547 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1550 cpu_set(cpu
, cpu_possible_map
);
1551 cpu_set(cpu
, cpu_present_map
);
1561 /* r/w apic fields */
1562 unsigned int apic_id
;
1563 unsigned int apic_taskpri
;
1564 unsigned int apic_ldr
;
1565 unsigned int apic_dfr
;
1566 unsigned int apic_spiv
;
1567 unsigned int apic_lvtt
;
1568 unsigned int apic_lvtpc
;
1569 unsigned int apic_lvt0
;
1570 unsigned int apic_lvt1
;
1571 unsigned int apic_lvterr
;
1572 unsigned int apic_tmict
;
1573 unsigned int apic_tdcr
;
1574 unsigned int apic_thmr
;
1577 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1579 unsigned long flags
;
1582 if (!apic_pm_state
.active
)
1585 maxlvt
= lapic_get_maxlvt();
1587 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1588 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1589 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1590 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1591 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1592 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1594 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1595 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1596 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1597 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1598 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1599 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1600 #ifdef CONFIG_X86_MCE_P4THERMAL
1602 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1605 local_irq_save(flags
);
1606 disable_local_APIC();
1607 local_irq_restore(flags
);
1611 static int lapic_resume(struct sys_device
*dev
)
1614 unsigned long flags
;
1617 if (!apic_pm_state
.active
)
1620 maxlvt
= lapic_get_maxlvt();
1622 local_irq_save(flags
);
1625 * Make sure the APICBASE points to the right address
1627 * FIXME! This will be wrong if we ever support suspend on
1628 * SMP! We'll need to do this as part of the CPU restore!
1630 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1631 l
&= ~MSR_IA32_APICBASE_BASE
;
1632 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1633 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1635 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1636 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1637 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1638 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1639 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1640 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1641 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1642 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1643 #ifdef CONFIG_X86_MCE_P4THERMAL
1645 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1648 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1649 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1650 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1651 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1652 apic_write(APIC_ESR
, 0);
1653 apic_read(APIC_ESR
);
1654 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1655 apic_write(APIC_ESR
, 0);
1656 apic_read(APIC_ESR
);
1657 local_irq_restore(flags
);
1662 * This device has no shutdown method - fully functioning local APICs
1663 * are needed on every CPU up until machine_halt/restart/poweroff.
1666 static struct sysdev_class lapic_sysclass
= {
1668 .resume
= lapic_resume
,
1669 .suspend
= lapic_suspend
,
1672 static struct sys_device device_lapic
= {
1674 .cls
= &lapic_sysclass
,
1677 static void __devinit
apic_pm_activate(void)
1679 apic_pm_state
.active
= 1;
1682 static int __init
init_lapic_sysfs(void)
1688 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1690 error
= sysdev_class_register(&lapic_sysclass
);
1692 error
= sysdev_register(&device_lapic
);
1695 device_initcall(init_lapic_sysfs
);
1697 #else /* CONFIG_PM */
1699 static void apic_pm_activate(void) { }
1701 #endif /* CONFIG_PM */
1704 * APIC command line parameters
1706 static int __init
parse_lapic(char *arg
)
1708 enable_local_apic
= 1;
1711 early_param("lapic", parse_lapic
);
1713 static int __init
parse_nolapic(char *arg
)
1715 enable_local_apic
= -1;
1716 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1719 early_param("nolapic", parse_nolapic
);
1721 static int __init
parse_disable_lapic_timer(char *arg
)
1723 local_apic_timer_disabled
= 1;
1726 early_param("nolapic_timer", parse_disable_lapic_timer
);
1728 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1730 local_apic_timer_c2_ok
= 1;
1733 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1735 static int __init
apic_set_verbosity(char *str
)
1737 if (strcmp("debug", str
) == 0)
1738 apic_verbosity
= APIC_DEBUG
;
1739 else if (strcmp("verbose", str
) == 0)
1740 apic_verbosity
= APIC_VERBOSE
;
1743 __setup("apic=", apic_set_verbosity
);