1 #include <linux/export.h>
2 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
13 #include <asm/pci-direct.h>
14 #include <asm/delay.h>
17 # include <asm/mmconfig.h>
18 # include <asm/cacheflush.h>
24 * nodes_per_socket: Stores the number of nodes per socket.
25 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
26 * Node Identifiers[10:8]
28 static u32 nodes_per_socket
= 1;
30 static inline int rdmsrl_amd_safe(unsigned msr
, unsigned long long *p
)
35 WARN_ONCE((boot_cpu_data
.x86
!= 0xf),
36 "%s should only be used on K8!\n", __func__
);
41 err
= rdmsr_safe_regs(gprs
);
43 *p
= gprs
[0] | ((u64
)gprs
[2] << 32);
48 static inline int wrmsrl_amd_safe(unsigned msr
, unsigned long long val
)
52 WARN_ONCE((boot_cpu_data
.x86
!= 0xf),
53 "%s should only be used on K8!\n", __func__
);
60 return wrmsr_safe_regs(gprs
);
64 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
65 * misexecution of code under Linux. Owners of such processors should
66 * contact AMD for precise details and a CPU swap.
68 * See http://www.multimania.com/poulot/k6bug.html
69 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
70 * (Publication # 21266 Issue Date: August 1998)
72 * The following test is erm.. interesting. AMD neglected to up
73 * the chip setting when fixing the bug but they also tweaked some
74 * performance at the same time..
77 extern __visible
void vide(void);
78 __asm__(".globl vide\n"
79 ".type vide, @function\n"
83 static void init_amd_k5(struct cpuinfo_x86
*c
)
87 * General Systems BIOSen alias the cpu frequency registers
88 * of the Elan at 0x000df000. Unfortunately, one of the Linux
89 * drivers subsequently pokes it, and changes the CPU speed.
90 * Workaround : Remove the unneeded alias.
92 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
93 #define CBAR_ENB (0x80000000)
94 #define CBAR_KEY (0X000000CB)
95 if (c
->x86_model
== 9 || c
->x86_model
== 10) {
96 if (inl(CBAR
) & CBAR_ENB
)
97 outl(0 | CBAR_KEY
, CBAR
);
102 static void init_amd_k6(struct cpuinfo_x86
*c
)
106 int mbytes
= get_num_physpages() >> (20-PAGE_SHIFT
);
108 if (c
->x86_model
< 6) {
109 /* Based on AMD doc 20734R - June 2000 */
110 if (c
->x86_model
== 0) {
111 clear_cpu_cap(c
, X86_FEATURE_APIC
);
112 set_cpu_cap(c
, X86_FEATURE_PGE
);
117 if (c
->x86_model
== 6 && c
->x86_mask
== 1) {
118 const int K6_BUG_LOOP
= 1000000;
120 void (*f_vide
)(void);
123 pr_info("AMD K6 stepping B detected - ");
126 * It looks like AMD fixed the 2.6.2 bug and improved indirect
127 * calls at the same time.
138 if (d
> 20*K6_BUG_LOOP
)
139 pr_cont("system stability may be impaired when more than 32 MB are used.\n");
141 pr_cont("probably OK (after B9730xxxx).\n");
144 /* K6 with old style WHCR */
145 if (c
->x86_model
< 8 ||
146 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
147 /* We can only write allocate on the low 508Mb */
151 rdmsr(MSR_K6_WHCR
, l
, h
);
152 if ((l
&0x0000FFFF) == 0) {
154 l
= (1<<0)|((mbytes
/4)<<1);
155 local_irq_save(flags
);
157 wrmsr(MSR_K6_WHCR
, l
, h
);
158 local_irq_restore(flags
);
159 pr_info("Enabling old style K6 write allocation for %d Mb\n",
165 if ((c
->x86_model
== 8 && c
->x86_mask
> 7) ||
166 c
->x86_model
== 9 || c
->x86_model
== 13) {
167 /* The more serious chips .. */
172 rdmsr(MSR_K6_WHCR
, l
, h
);
173 if ((l
&0xFFFF0000) == 0) {
175 l
= ((mbytes
>>2)<<22)|(1<<16);
176 local_irq_save(flags
);
178 wrmsr(MSR_K6_WHCR
, l
, h
);
179 local_irq_restore(flags
);
180 pr_info("Enabling new style K6 write allocation for %d Mb\n",
187 if (c
->x86_model
== 10) {
188 /* AMD Geode LX is model 10 */
189 /* placeholder for any needed mods */
195 static void init_amd_k7(struct cpuinfo_x86
*c
)
201 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 * If the BIOS didn't enable it already, enable it here.
205 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
206 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
207 pr_info("Enabling disabled K7/SSE Support.\n");
208 msr_clear_bit(MSR_K7_HWCR
, 15);
209 set_cpu_cap(c
, X86_FEATURE_XMM
);
214 * It's been determined by AMD that Athlons since model 8 stepping 1
215 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
216 * As per AMD technical note 27212 0.2
218 if ((c
->x86_model
== 8 && c
->x86_mask
>= 1) || (c
->x86_model
> 8)) {
219 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
220 if ((l
& 0xfff00000) != 0x20000000) {
221 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
222 l
, ((l
& 0x000fffff)|0x20000000));
223 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
227 set_cpu_cap(c
, X86_FEATURE_K7
);
229 /* calling is from identify_secondary_cpu() ? */
234 * Certain Athlons might work (for various values of 'work') in SMP
235 * but they are not certified as MP capable.
237 /* Athlon 660/661 is valid. */
238 if ((c
->x86_model
== 6) && ((c
->x86_mask
== 0) ||
242 /* Duron 670 is valid */
243 if ((c
->x86_model
== 7) && (c
->x86_mask
== 0))
247 * Athlon 662, Duron 671, and Athlon >model 7 have capability
248 * bit. It's worth noting that the A5 stepping (662) of some
249 * Athlon XP's have the MP bit set.
250 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
253 if (((c
->x86_model
== 6) && (c
->x86_mask
>= 2)) ||
254 ((c
->x86_model
== 7) && (c
->x86_mask
>= 1)) ||
256 if (cpu_has(c
, X86_FEATURE_MP
))
259 /* If we get here, not a certified SMP capable AMD system. */
262 * Don't taint if we are running SMP kernel on a single non-MP
265 WARN_ONCE(1, "WARNING: This combination of AMD"
266 " processors is not suitable for SMP.\n");
267 add_taint(TAINT_CPU_OUT_OF_SPEC
, LOCKDEP_NOW_UNRELIABLE
);
273 * To workaround broken NUMA config. Read the comment in
274 * srat_detect_node().
276 static int nearby_node(int apicid
)
280 for (i
= apicid
- 1; i
>= 0; i
--) {
281 node
= __apicid_to_node
[i
];
282 if (node
!= NUMA_NO_NODE
&& node_online(node
))
285 for (i
= apicid
+ 1; i
< MAX_LOCAL_APIC
; i
++) {
286 node
= __apicid_to_node
[i
];
287 if (node
!= NUMA_NO_NODE
&& node_online(node
))
290 return first_node(node_online_map
); /* Shouldn't happen */
295 * Fixup core topology information for
296 * (1) AMD multi-node processors
297 * Assumption: Number of cores in each internal node is the same.
298 * (2) AMD processors supporting compute units
301 static void amd_get_topology(struct cpuinfo_x86
*c
)
304 int cpu
= smp_processor_id();
306 /* get information required for multi-node processors */
307 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
308 u32 eax
, ebx
, ecx
, edx
;
310 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
313 /* get compute unit information */
314 smp_num_siblings
= ((ebx
>> 8) & 3) + 1;
315 c
->x86_max_cores
/= smp_num_siblings
;
316 c
->cpu_core_id
= ebx
& 0xff;
317 } else if (cpu_has(c
, X86_FEATURE_NODEID_MSR
)) {
320 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
325 /* fixup multi-node processor information */
326 if (nodes_per_socket
> 1) {
329 set_cpu_cap(c
, X86_FEATURE_AMD_DCM
);
330 cus_per_node
= c
->x86_max_cores
/ nodes_per_socket
;
332 /* store NodeID, use llc_shared_map to store sibling info */
333 per_cpu(cpu_llc_id
, cpu
) = node_id
;
335 /* core id has to be in the [0 .. cores_per_node - 1] range */
336 c
->cpu_core_id
%= cus_per_node
;
342 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
343 * Assumes number of cores is a power of two.
345 static void amd_detect_cmp(struct cpuinfo_x86
*c
)
349 int cpu
= smp_processor_id();
350 unsigned int socket_id
, core_complex_id
;
352 bits
= c
->x86_coreid_bits
;
353 /* Low order bits define the core id (index of core in socket) */
354 c
->cpu_core_id
= c
->initial_apicid
& ((1 << bits
)-1);
355 /* Convert the initial APIC ID into the socket ID */
356 c
->phys_proc_id
= c
->initial_apicid
>> bits
;
357 /* use socket ID also for last level cache */
358 per_cpu(cpu_llc_id
, cpu
) = c
->phys_proc_id
;
362 * Fix percpu cpu_llc_id here as LLC topology is different
363 * for Fam17h systems.
365 if (c
->x86
!= 0x17 || !cpuid_edx(0x80000006))
368 socket_id
= (c
->apicid
>> bits
) - 1;
369 core_complex_id
= (c
->apicid
& ((1 << bits
) - 1)) >> 3;
371 per_cpu(cpu_llc_id
, cpu
) = (socket_id
<< 3) | core_complex_id
;
375 u16
amd_get_nb_id(int cpu
)
379 id
= per_cpu(cpu_llc_id
, cpu
);
383 EXPORT_SYMBOL_GPL(amd_get_nb_id
);
385 u32
amd_get_nodes_per_socket(void)
387 return nodes_per_socket
;
389 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket
);
391 static void srat_detect_node(struct cpuinfo_x86
*c
)
394 int cpu
= smp_processor_id();
396 unsigned apicid
= c
->apicid
;
398 node
= numa_cpu_node(cpu
);
399 if (node
== NUMA_NO_NODE
)
400 node
= per_cpu(cpu_llc_id
, cpu
);
403 * On multi-fabric platform (e.g. Numascale NumaChip) a
404 * platform-specific handler needs to be called to fixup some
407 if (x86_cpuinit
.fixup_cpu_id
)
408 x86_cpuinit
.fixup_cpu_id(c
, node
);
410 if (!node_online(node
)) {
412 * Two possibilities here:
414 * - The CPU is missing memory and no node was created. In
415 * that case try picking one from a nearby CPU.
417 * - The APIC IDs differ from the HyperTransport node IDs
418 * which the K8 northbridge parsing fills in. Assume
419 * they are all increased by a constant offset, but in
420 * the same order as the HT nodeids. If that doesn't
421 * result in a usable node fall back to the path for the
424 * This workaround operates directly on the mapping between
425 * APIC ID and NUMA node, assuming certain relationship
426 * between APIC ID, HT node ID and NUMA topology. As going
427 * through CPU mapping may alter the outcome, directly
428 * access __apicid_to_node[].
430 int ht_nodeid
= c
->initial_apicid
;
432 if (__apicid_to_node
[ht_nodeid
] != NUMA_NO_NODE
)
433 node
= __apicid_to_node
[ht_nodeid
];
434 /* Pick a nearby node */
435 if (!node_online(node
))
436 node
= nearby_node(apicid
);
438 numa_set_node(cpu
, node
);
442 static void early_init_amd_mc(struct cpuinfo_x86
*c
)
447 /* Multi core CPU? */
448 if (c
->extended_cpuid_level
< 0x80000008)
451 ecx
= cpuid_ecx(0x80000008);
453 c
->x86_max_cores
= (ecx
& 0xff) + 1;
455 /* CPU telling us the core id bits shift? */
456 bits
= (ecx
>> 12) & 0xF;
458 /* Otherwise recompute */
460 while ((1 << bits
) < c
->x86_max_cores
)
464 c
->x86_coreid_bits
= bits
;
468 static void bsp_init_amd(struct cpuinfo_x86
*c
)
473 unsigned long long tseg
;
476 * Split up direct mapping around the TSEG SMM area.
477 * Don't do it for gbpages because there seems very little
478 * benefit in doing so.
480 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR
, &tseg
)) {
481 unsigned long pfn
= tseg
>> PAGE_SHIFT
;
483 pr_debug("tseg: %010llx\n", tseg
);
484 if (pfn_range_is_mapped(pfn
, pfn
+ 1))
485 set_memory_4k((unsigned long)__va(tseg
), 1);
490 if (cpu_has(c
, X86_FEATURE_CONSTANT_TSC
)) {
493 (c
->x86
== 0x10 && c
->x86_model
>= 0x2)) {
496 rdmsrl(MSR_K7_HWCR
, val
);
497 if (!(val
& BIT(24)))
498 pr_warn(FW_BUG
"TSC doesn't count with P0 frequency!\n");
502 if (c
->x86
== 0x15) {
503 unsigned long upperbit
;
506 cpuid
= cpuid_edx(0x80000005);
507 assoc
= cpuid
>> 16 & 0xff;
508 upperbit
= ((cpuid
>> 24) << 10) / assoc
;
510 va_align
.mask
= (upperbit
- 1) & PAGE_MASK
;
511 va_align
.flags
= ALIGN_VA_32
| ALIGN_VA_64
;
513 /* A random value per boot for bit slice [12:upper_bit) */
514 va_align
.bits
= get_random_int() & va_align
.mask
;
517 if (cpu_has(c
, X86_FEATURE_MWAITX
))
520 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
523 ecx
= cpuid_ecx(0x8000001e);
524 nodes_per_socket
= ((ecx
>> 8) & 7) + 1;
525 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR
)) {
528 rdmsrl(MSR_FAM10H_NODE_ID
, value
);
529 nodes_per_socket
= ((value
>> 3) & 7) + 1;
533 static void early_init_amd(struct cpuinfo_x86
*c
)
535 early_init_amd_mc(c
);
538 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
539 * with P/T states and does not stop in deep C-states
541 if (c
->x86_power
& (1 << 8)) {
542 set_cpu_cap(c
, X86_FEATURE_CONSTANT_TSC
);
543 set_cpu_cap(c
, X86_FEATURE_NONSTOP_TSC
);
544 if (!check_tsc_unstable())
545 set_sched_clock_stable();
548 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
549 if (c
->x86_power
& BIT(12))
550 set_cpu_cap(c
, X86_FEATURE_ACC_POWER
);
553 set_cpu_cap(c
, X86_FEATURE_SYSCALL32
);
555 /* Set MTRR capability flag if appropriate */
557 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
558 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
559 set_cpu_cap(c
, X86_FEATURE_K6_MTRR
);
561 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
563 * ApicID can always be treated as an 8-bit value for AMD APIC versions
564 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
565 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
568 if (boot_cpu_has(X86_FEATURE_APIC
)) {
570 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
571 else if (c
->x86
>= 0xf) {
572 /* check CPU config space for extended APIC ID */
575 val
= read_pci_config(0, 24, 0, 0x68);
576 if ((val
>> 17 & 0x3) == 0x3)
577 set_cpu_cap(c
, X86_FEATURE_EXTD_APICID
);
583 * This is only needed to tell the kernel whether to use VMCALL
584 * and VMMCALL. VMMCALL is never executed except under virt, so
585 * we can set it unconditionally.
587 set_cpu_cap(c
, X86_FEATURE_VMMCALL
);
589 /* F16h erratum 793, CVE-2013-6885 */
590 if (c
->x86
== 0x16 && c
->x86_model
<= 0xf)
591 msr_set_bit(MSR_AMD64_LS_CFG
, 15);
594 static const int amd_erratum_383
[];
595 static const int amd_erratum_400
[];
596 static bool cpu_has_amd_erratum(struct cpuinfo_x86
*cpu
, const int *erratum
);
598 static void init_amd_k8(struct cpuinfo_x86
*c
)
603 /* On C+ stepping K8 rep microcode works well for copy/memset */
604 level
= cpuid_eax(1);
605 if ((level
>= 0x0f48 && level
< 0x0f50) || level
>= 0x0f58)
606 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
609 * Some BIOSes incorrectly force this feature, but only K8 revision D
610 * (model = 0x14) and later actually support it.
611 * (AMD Erratum #110, docId: 25759).
613 if (c
->x86_model
< 0x14 && cpu_has(c
, X86_FEATURE_LAHF_LM
)) {
614 clear_cpu_cap(c
, X86_FEATURE_LAHF_LM
);
615 if (!rdmsrl_amd_safe(0xc001100d, &value
)) {
616 value
&= ~BIT_64(32);
617 wrmsrl_amd_safe(0xc001100d, value
);
621 if (!c
->x86_model_id
[0])
622 strcpy(c
->x86_model_id
, "Hammer");
626 * Disable TLB flush filter by setting HWCR.FFDIS on K8
627 * bit 6 of msr C001_0015
629 * Errata 63 for SH-B3 steppings
630 * Errata 122 for all steppings (F+ have it disabled by default)
632 msr_set_bit(MSR_K7_HWCR
, 6);
634 set_cpu_bug(c
, X86_BUG_SWAPGS_FENCE
);
637 static void init_amd_gh(struct cpuinfo_x86
*c
)
640 /* do this for boot cpu */
641 if (c
== &boot_cpu_data
)
642 check_enable_amd_mmconf_dmi();
644 fam10h_check_enable_mmcfg();
648 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
649 * is always needed when GART is enabled, even in a kernel which has no
650 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
651 * If it doesn't, we do it here as suggested by the BKDG.
653 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
655 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
658 * On family 10h BIOS may not have properly enabled WC+ support, causing
659 * it to be converted to CD memtype. This may result in performance
660 * degradation for certain nested-paging guests. Prevent this conversion
661 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
663 * NOTE: we want to use the _safe accessors so as not to #GP kvm
664 * guests on older kvm hosts.
666 msr_clear_bit(MSR_AMD64_BU_CFG2
, 24);
668 if (cpu_has_amd_erratum(c
, amd_erratum_383
))
669 set_cpu_bug(c
, X86_BUG_AMD_TLB_MMATCH
);
672 #define MSR_AMD64_DE_CFG 0xC0011029
674 static void init_amd_ln(struct cpuinfo_x86
*c
)
677 * Apply erratum 665 fix unconditionally so machines without a BIOS
680 msr_set_bit(MSR_AMD64_DE_CFG
, 31);
683 static void init_amd_bd(struct cpuinfo_x86
*c
)
687 /* re-enable TopologyExtensions if switched off by BIOS */
688 if ((c
->x86_model
>= 0x10) && (c
->x86_model
<= 0x6f) &&
689 !cpu_has(c
, X86_FEATURE_TOPOEXT
)) {
691 if (msr_set_bit(0xc0011005, 54) > 0) {
692 rdmsrl(0xc0011005, value
);
693 if (value
& BIT_64(54)) {
694 set_cpu_cap(c
, X86_FEATURE_TOPOEXT
);
695 pr_info_once(FW_INFO
"CPU: Re-enabling disabled Topology Extensions Support.\n");
701 * The way access filter has a performance penalty on some workloads.
702 * Disable it on the affected CPUs.
704 if ((c
->x86_model
>= 0x02) && (c
->x86_model
< 0x20)) {
705 if (!rdmsrl_safe(MSR_F15H_IC_CFG
, &value
) && !(value
& 0x1E)) {
707 wrmsrl_safe(MSR_F15H_IC_CFG
, value
);
712 static void init_amd(struct cpuinfo_x86
*c
)
719 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
720 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
722 clear_cpu_cap(c
, 0*32+31);
725 set_cpu_cap(c
, X86_FEATURE_REP_GOOD
);
727 /* get apicid instead of initial apic id from cpuid */
728 c
->apicid
= hard_smp_processor_id();
730 /* K6s reports MCEs but don't actually have all the MSRs */
732 clear_cpu_cap(c
, X86_FEATURE_MCE
);
735 case 4: init_amd_k5(c
); break;
736 case 5: init_amd_k6(c
); break;
737 case 6: init_amd_k7(c
); break;
738 case 0xf: init_amd_k8(c
); break;
739 case 0x10: init_amd_gh(c
); break;
740 case 0x12: init_amd_ln(c
); break;
741 case 0x15: init_amd_bd(c
); break;
744 /* Enable workaround for FXSAVE leak */
746 set_cpu_bug(c
, X86_BUG_FXSAVE_LEAK
);
748 cpu_detect_cache_sizes(c
);
750 /* Multi core CPU? */
751 if (c
->extended_cpuid_level
>= 0x80000008) {
760 init_amd_cacheinfo(c
);
763 set_cpu_cap(c
, X86_FEATURE_K8
);
765 if (cpu_has(c
, X86_FEATURE_XMM2
)) {
766 /* MFENCE stops RDTSC speculation */
767 set_cpu_cap(c
, X86_FEATURE_MFENCE_RDTSC
);
771 * Family 0x12 and above processors have APIC timer
772 * running in deep C states.
775 set_cpu_cap(c
, X86_FEATURE_ARAT
);
777 if (cpu_has_amd_erratum(c
, amd_erratum_400
))
778 set_cpu_bug(c
, X86_BUG_AMD_APIC_C1E
);
780 rdmsr_safe(MSR_AMD64_PATCH_LEVEL
, &c
->microcode
, &dummy
);
782 /* 3DNow or LM implies PREFETCHW */
783 if (!cpu_has(c
, X86_FEATURE_3DNOWPREFETCH
))
784 if (cpu_has(c
, X86_FEATURE_3DNOW
) || cpu_has(c
, X86_FEATURE_LM
))
785 set_cpu_cap(c
, X86_FEATURE_3DNOWPREFETCH
);
787 /* AMD CPUs don't reset SS attributes on SYSRET */
788 set_cpu_bug(c
, X86_BUG_SYSRET_SS_ATTRS
);
792 static unsigned int amd_size_cache(struct cpuinfo_x86
*c
, unsigned int size
)
794 /* AMD errata T13 (order #21922) */
797 if (c
->x86_model
== 3 && c
->x86_mask
== 0)
799 /* Tbird rev A1/A2 */
800 if (c
->x86_model
== 4 &&
801 (c
->x86_mask
== 0 || c
->x86_mask
== 1))
808 static void cpu_detect_tlb_amd(struct cpuinfo_x86
*c
)
810 u32 ebx
, eax
, ecx
, edx
;
816 if (c
->extended_cpuid_level
< 0x80000006)
819 cpuid(0x80000006, &eax
, &ebx
, &ecx
, &edx
);
821 tlb_lld_4k
[ENTRIES
] = (ebx
>> 16) & mask
;
822 tlb_lli_4k
[ENTRIES
] = ebx
& mask
;
825 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
826 * characteristics from the CPUID function 0x80000005 instead.
829 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
833 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
834 if (!((eax
>> 16) & mask
))
835 tlb_lld_2m
[ENTRIES
] = (cpuid_eax(0x80000005) >> 16) & 0xff;
837 tlb_lld_2m
[ENTRIES
] = (eax
>> 16) & mask
;
839 /* a 4M entry uses two 2M entries */
840 tlb_lld_4m
[ENTRIES
] = tlb_lld_2m
[ENTRIES
] >> 1;
842 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
845 if (c
->x86
== 0x15 && c
->x86_model
<= 0x1f) {
846 tlb_lli_2m
[ENTRIES
] = 1024;
848 cpuid(0x80000005, &eax
, &ebx
, &ecx
, &edx
);
849 tlb_lli_2m
[ENTRIES
] = eax
& 0xff;
852 tlb_lli_2m
[ENTRIES
] = eax
& mask
;
854 tlb_lli_4m
[ENTRIES
] = tlb_lli_2m
[ENTRIES
] >> 1;
857 static const struct cpu_dev amd_cpu_dev
= {
859 .c_ident
= { "AuthenticAMD" },
862 { .family
= 4, .model_names
=
873 .legacy_cache_size
= amd_size_cache
,
875 .c_early_init
= early_init_amd
,
876 .c_detect_tlb
= cpu_detect_tlb_amd
,
877 .c_bsp_init
= bsp_init_amd
,
879 .c_x86_vendor
= X86_VENDOR_AMD
,
882 cpu_dev_register(amd_cpu_dev
);
885 * AMD errata checking
887 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
888 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
889 * have an OSVW id assigned, which it takes as first argument. Both take a
890 * variable number of family-specific model-stepping ranges created by
895 * const int amd_erratum_319[] =
896 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
897 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
898 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
901 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
902 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
903 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
904 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
905 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
906 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
907 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
909 static const int amd_erratum_400
[] =
910 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
911 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
913 static const int amd_erratum_383
[] =
914 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
917 static bool cpu_has_amd_erratum(struct cpuinfo_x86
*cpu
, const int *erratum
)
919 int osvw_id
= *erratum
++;
923 if (osvw_id
>= 0 && osvw_id
< 65536 &&
924 cpu_has(cpu
, X86_FEATURE_OSVW
)) {
927 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH
, osvw_len
);
928 if (osvw_id
< osvw_len
) {
931 rdmsrl(MSR_AMD64_OSVW_STATUS
+ (osvw_id
>> 6),
933 return osvw_bits
& (1ULL << (osvw_id
& 0x3f));
937 /* OSVW unavailable or ID unknown, match family-model-stepping range */
938 ms
= (cpu
->x86_model
<< 4) | cpu
->x86_mask
;
939 while ((range
= *erratum
++))
940 if ((cpu
->x86
== AMD_MODEL_RANGE_FAMILY(range
)) &&
941 (ms
>= AMD_MODEL_RANGE_START(range
)) &&
942 (ms
<= AMD_MODEL_RANGE_END(range
)))
948 void set_dr_addr_mask(unsigned long mask
, int dr
)
950 if (!boot_cpu_has(X86_FEATURE_BPEXT
))
955 wrmsr(MSR_F16H_DR0_ADDR_MASK
, mask
, 0);
960 wrmsr(MSR_F16H_DR1_ADDR_MASK
- 1 + dr
, mask
, 0);