arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/ds.h>
  16 #include <asm/bugs.h>
  17
  18 #include "cpu.h"
  19
  20 #ifdef CONFIG_X86_LOCAL_APIC
  21 #include <asm/mpspec.h>
  22 #include <asm/apic.h>
  23 #include <mach_apic.h>
  24 #endif
  25
  26 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  27 {
  28         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  29         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  30                 c->x86_cache_alignment = 128;
  31         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  32                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  33                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  34 }
  35
  36 /*
  37  *      Early probe support logic for ppro memory erratum #50
  38  *
  39  *      This is called before we do cpu ident work
  40  */
  41
  42 int __cpuinit ppro_with_ram_bug(void)
  43 {
  44         /* Uses data from early_cpu_detect now */
  45         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  46             boot_cpu_data.x86 == 6 &&
  47             boot_cpu_data.x86_model == 1 &&
  48             boot_cpu_data.x86_mask < 8) {
  49                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  50                 return 1;
  51         }
  52         return 0;
  53 }
  54
  55
  56 /*
  57  * P4 Xeon errata 037 workaround.
  58  * Hardware prefetcher may cause stale data to be loaded into the cache.
  59  */
  60 static void __cpuinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
  61 {
  62         unsigned long lo, hi;
  63
  64         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
  65                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
  66                 if ((lo & (1<<9)) == 0) {
  67                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
  68                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
  69                         lo |= (1<<9);   /* Disable hw prefetching */
  70                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  71                 }
  72         }
  73 }
  74
  75
  76 /*
  77  * find out the number of processor cores on the die
  78  */
  79 static int __cpuinit num_cpu_cores(struct cpuinfo_x86 *c)
  80 {
  81         unsigned int eax, ebx, ecx, edx;
  82
  83         if (c->cpuid_level < 4)
  84                 return 1;
  85
  86         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
  87         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
  88         if (eax & 0x1f)
  89                 return ((eax >> 26) + 1);
  90         else
  91                 return 1;
  92 }
  93
  94 #ifdef CONFIG_X86_F00F_BUG
  95 static void __cpuinit trap_init_f00f_bug(void)
  96 {
  97         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
  98
  99         /*
 100          * Update the IDT descriptor and reload the IDT so that
 101          * it uses the read-only mapped virtual address.
 102          */
 103         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 104         load_idt(&idt_descr);
 105 }
 106 #endif
 107
 108 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 109 {
 110         unsigned int l2 = 0;
 111         char *p = NULL;
 112
 113         early_init_intel(c);
 114
 115 #ifdef CONFIG_X86_F00F_BUG
 116         /*
 117          * All current models of Pentium and Pentium with MMX technology CPUs
 118          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 119          * Note that the workaround only should be initialized once...
 120          */
 121         c->f00f_bug = 0;
 122         if (!paravirt_enabled() && c->x86 == 5) {
 123                 static int f00f_workaround_enabled;
 124
 125                 c->f00f_bug = 1;
 126                 if (!f00f_workaround_enabled) {
 127                         trap_init_f00f_bug();
 128                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 129                         f00f_workaround_enabled = 1;
 130                 }
 131         }
 132 #endif
 133
 134         l2 = init_intel_cacheinfo(c);
 135         if (c->cpuid_level > 9) {
 136                 unsigned eax = cpuid_eax(10);
 137                 /* Check for version and the number of counters */
 138                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 139                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 140         }
 141
 142         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
 143         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 144                 clear_cpu_cap(c, X86_FEATURE_SEP);
 145
 146         /*
 147          * Names for the Pentium II/Celeron processors
 148          * detectable only by also checking the cache size.
 149          * Dixon is NOT a Celeron.
 150          */
 151         if (c->x86 == 6) {
 152                 switch (c->x86_model) {
 153                 case 5:
 154                         if (c->x86_mask == 0) {
 155                                 if (l2 == 0)
 156                                         p = "Celeron (Covington)";
 157                                 else if (l2 == 256)
 158                                         p = "Mobile Pentium II (Dixon)";
 159                         }
 160                         break;
 161
 162                 case 6:
 163                         if (l2 == 128)
 164                                 p = "Celeron (Mendocino)";
 165                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 166                                 p = "Celeron-A";
 167                         break;
 168
 169                 case 8:
 170                         if (l2 == 128)
 171                                 p = "Celeron (Coppermine)";
 172                         break;
 173                 }
 174         }
 175
 176         if (p)
 177                 strcpy(c->x86_model_id, p);
 178
 179         c->x86_max_cores = num_cpu_cores(c);
 180
 181         detect_ht(c);
 182
 183         /* Work around errata */
 184         Intel_errata_workarounds(c);
 185
 186 #ifdef CONFIG_X86_INTEL_USERCOPY
 187         /*
 188          * Set up the preferred alignment for movsl bulk memory moves
 189          */
 190         switch (c->x86) {
 191         case 4:         /* 486: untested */
 192                 break;
 193         case 5:         /* Old Pentia: untested */
 194                 break;
 195         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 196                 movsl_mask.mask = 7;
 197                 break;
 198         case 15:        /* P4 is OK down to 8-byte alignment */
 199                 movsl_mask.mask = 7;
 200                 break;
 201         }
 202 #endif
 203
 204         if (cpu_has_xmm2)
 205                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 206         if (c->x86 == 15) {
 207                 set_cpu_cap(c, X86_FEATURE_P4);
 208         }
 209         if (c->x86 == 6)
 210                 set_cpu_cap(c, X86_FEATURE_P3);
 211         if (cpu_has_ds) {
 212                 unsigned int l1;
 213                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 214                 if (!(l1 & (1<<11)))
 215                         set_cpu_cap(c, X86_FEATURE_BTS);
 216                 if (!(l1 & (1<<12)))
 217                         set_cpu_cap(c, X86_FEATURE_PEBS);
 218         }
 219
 220         if (cpu_has_bts)
 221                 ds_init_intel(c);
 222
 223         /*
 224          * See if we have a good local APIC by checking for buggy Pentia,
 225          * i.e. all B steppings and the C2 stepping of P54C when using their
 226          * integrated APIC (see 11AP erratum in "Pentium Processor
 227          * Specification Update").
 228          */
 229         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 230             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 231                 set_cpu_cap(c, X86_FEATURE_11AP);
 232
 233 #ifdef CONFIG_X86_NUMAQ
 234         numaq_tsc_disable();
 235 #endif
 236 }
 237
 238 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 239 {
 240         /*
 241          * Intel PIII Tualatin. This comes in two flavours.
 242          * One has 256kb of cache, the other 512. We have no way
 243          * to determine which, so we use a boottime override
 244          * for the 512kb model, and assume 256 otherwise.
 245          */
 246         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 247                 size = 256;
 248         return size;
 249 }
 250
 251 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 252         .c_vendor       = "Intel",
 253         .c_ident        = { "GenuineIntel" },
 254         .c_models = {
 255                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 256                   {
 257                           [0] = "486 DX-25/33",
 258                           [1] = "486 DX-50",
 259                           [2] = "486 SX",
 260                           [3] = "486 DX/2",
 261                           [4] = "486 SL",
 262                           [5] = "486 SX/2",
 263                           [7] = "486 DX/2-WB",
 264                           [8] = "486 DX/4",
 265                           [9] = "486 DX/4-WB"
 266                   }
 267                 },
 268                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 269                   {
 270                           [0] = "Pentium 60/66 A-step",
 271                           [1] = "Pentium 60/66",
 272                           [2] = "Pentium 75 - 200",
 273                           [3] = "OverDrive PODP5V83",
 274                           [4] = "Pentium MMX",
 275                           [7] = "Mobile Pentium 75 - 200",
 276                           [8] = "Mobile Pentium MMX"
 277                   }
 278                 },
 279                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 280                   {
 281                           [0] = "Pentium Pro A-step",
 282                           [1] = "Pentium Pro",
 283                           [3] = "Pentium II (Klamath)",
 284                           [4] = "Pentium II (Deschutes)",
 285                           [5] = "Pentium II (Deschutes)",
 286                           [6] = "Mobile Pentium II",
 287                           [7] = "Pentium III (Katmai)",
 288                           [8] = "Pentium III (Coppermine)",
 289                           [10] = "Pentium III (Cascades)",
 290                           [11] = "Pentium III (Tualatin)",
 291                   }
 292                 },
 293                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 294                   {
 295                           [0] = "Pentium 4 (Unknown)",
 296                           [1] = "Pentium 4 (Willamette)",
 297                           [2] = "Pentium 4 (Northwood)",
 298                           [4] = "Pentium 4 (Foster)",
 299                           [5] = "Pentium 4 (Foster)",
 300                   }
 301                 },
 302         },
 303         .c_early_init   = early_init_intel,
 304         .c_init         = init_intel,
 305         .c_size_cache   = intel_size_cache,
 306 };
 307
 308 cpu_vendor_dev_register(X86_VENDOR_INTEL, &intel_cpu_dev);
 309
 310 #ifndef CONFIG_X86_CMPXCHG
 311 unsigned long cmpxchg_386_u8(volatile void *ptr, u8 old, u8 new)
 312 {
 313         u8 prev;
 314         unsigned long flags;
 315
 316         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 317         local_irq_save(flags);
 318         prev = *(u8 *)ptr;
 319         if (prev == old)
 320                 *(u8 *)ptr = new;
 321         local_irq_restore(flags);
 322         return prev;
 323 }
 324 EXPORT_SYMBOL(cmpxchg_386_u8);
 325
 326 unsigned long cmpxchg_386_u16(volatile void *ptr, u16 old, u16 new)
 327 {
 328         u16 prev;
 329         unsigned long flags;
 330
 331         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 332         local_irq_save(flags);
 333         prev = *(u16 *)ptr;
 334         if (prev == old)
 335                 *(u16 *)ptr = new;
 336         local_irq_restore(flags);
 337         return prev;
 338 }
 339 EXPORT_SYMBOL(cmpxchg_386_u16);
 340
 341 unsigned long cmpxchg_386_u32(volatile void *ptr, u32 old, u32 new)
 342 {
 343         u32 prev;
 344         unsigned long flags;
 345
 346         /* Poor man's cmpxchg for 386. Unsuitable for SMP */
 347         local_irq_save(flags);
 348         prev = *(u32 *)ptr;
 349         if (prev == old)
 350                 *(u32 *)ptr = new;
 351         local_irq_restore(flags);
 352         return prev;
 353 }
 354 EXPORT_SYMBOL(cmpxchg_386_u32);
 355 #endif
 356
 357 #ifndef CONFIG_X86_CMPXCHG64
 358 unsigned long long cmpxchg_486_u64(volatile void *ptr, u64 old, u64 new)
 359 {
 360         u64 prev;
 361         unsigned long flags;
 362
 363         /* Poor man's cmpxchg8b for 386 and 486. Unsuitable for SMP */
 364         local_irq_save(flags);
 365         prev = *(u64 *)ptr;
 366         if (prev == old)
 367                 *(u64 *)ptr = new;
 368         local_irq_restore(flags);
 369         return prev;
 370 }
 371 EXPORT_SYMBOL(cmpxchg_486_u64);
 372 #endif
 373
 374 /* arch_initcall(intel_cpu_init); */
 375