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Merge branch 'linus' into x86/urgent, to refresh the tree
[deliverable/linux.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/kernel.h>
2
3 #include <linux/string.h>
4 #include <linux/bitops.h>
5 #include <linux/smp.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9 #include <linux/uaccess.h>
10
11 #include <asm/cpufeature.h>
12 #include <asm/pgtable.h>
13 #include <asm/msr.h>
14 #include <asm/bugs.h>
15 #include <asm/cpu.h>
16
17 #ifdef CONFIG_X86_64
18 #include <linux/topology.h>
19 #endif
20
21 #include "cpu.h"
22
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
25 #include <asm/apic.h>
26 #endif
27
28 /*
29 * Just in case our CPU detection goes bad, or you have a weird system,
30 * allow a way to override the automatic disabling of MPX.
31 */
32 static int forcempx;
33
34 static int __init forcempx_setup(char *__unused)
35 {
36 forcempx = 1;
37
38 return 1;
39 }
40 __setup("intel-skd-046-workaround=disable", forcempx_setup);
41
42 void check_mpx_erratum(struct cpuinfo_x86 *c)
43 {
44 if (forcempx)
45 return;
46 /*
47 * Turn off the MPX feature on CPUs where SMEP is not
48 * available or disabled.
49 *
50 * Works around Intel Erratum SKD046: "Branch Instructions
51 * May Initialize MPX Bound Registers Incorrectly".
52 *
53 * This might falsely disable MPX on systems without
54 * SMEP, like Atom processors without SMEP. But there
55 * is no such hardware known at the moment.
56 */
57 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
58 setup_clear_cpu_cap(X86_FEATURE_MPX);
59 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
60 }
61 }
62
63 static void early_init_intel(struct cpuinfo_x86 *c)
64 {
65 u64 misc_enable;
66
67 /* Unmask CPUID levels if masked: */
68 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
69 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
70 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
71 c->cpuid_level = cpuid_eax(0);
72 get_cpu_cap(c);
73 }
74 }
75
76 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
77 (c->x86 == 0x6 && c->x86_model >= 0x0e))
78 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
79
80 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
81 unsigned lower_word;
82
83 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
84 /* Required by the SDM */
85 sync_core();
86 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
87 }
88
89 /*
90 * Atom erratum AAE44/AAF40/AAG38/AAH41:
91 *
92 * A race condition between speculative fetches and invalidating
93 * a large page. This is worked around in microcode, but we
94 * need the microcode to have already been loaded... so if it is
95 * not, recommend a BIOS update and disable large pages.
96 */
97 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
98 c->microcode < 0x20e) {
99 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
100 clear_cpu_cap(c, X86_FEATURE_PSE);
101 }
102
103 #ifdef CONFIG_X86_64
104 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
105 #else
106 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
107 if (c->x86 == 15 && c->x86_cache_alignment == 64)
108 c->x86_cache_alignment = 128;
109 #endif
110
111 /* CPUID workaround for 0F33/0F34 CPU */
112 if (c->x86 == 0xF && c->x86_model == 0x3
113 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
114 c->x86_phys_bits = 36;
115
116 /*
117 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
118 * with P/T states and does not stop in deep C-states.
119 *
120 * It is also reliable across cores and sockets. (but not across
121 * cabinets - we turn it off in that case explicitly.)
122 */
123 if (c->x86_power & (1 << 8)) {
124 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
125 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
126 if (!check_tsc_unstable())
127 set_sched_clock_stable();
128 }
129
130 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
131 if (c->x86 == 6) {
132 switch (c->x86_model) {
133 case 0x27: /* Penwell */
134 case 0x35: /* Cloverview */
135 case 0x4a: /* Merrifield */
136 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
137 break;
138 default:
139 break;
140 }
141 }
142
143 /*
144 * There is a known erratum on Pentium III and Core Solo
145 * and Core Duo CPUs.
146 * " Page with PAT set to WC while associated MTRR is UC
147 * may consolidate to UC "
148 * Because of this erratum, it is better to stick with
149 * setting WC in MTRR rather than using PAT on these CPUs.
150 *
151 * Enable PAT WC only on P4, Core 2 or later CPUs.
152 */
153 if (c->x86 == 6 && c->x86_model < 15)
154 clear_cpu_cap(c, X86_FEATURE_PAT);
155
156 #ifdef CONFIG_KMEMCHECK
157 /*
158 * P4s have a "fast strings" feature which causes single-
159 * stepping REP instructions to only generate a #DB on
160 * cache-line boundaries.
161 *
162 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
163 * (model 2) with the same problem.
164 */
165 if (c->x86 == 15)
166 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
167 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
168 pr_info("kmemcheck: Disabling fast string operations\n");
169 #endif
170
171 /*
172 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
173 * clear the fast string and enhanced fast string CPU capabilities.
174 */
175 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
176 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
177 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
178 pr_info("Disabled fast string operations\n");
179 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
180 setup_clear_cpu_cap(X86_FEATURE_ERMS);
181 }
182 }
183
184 /*
185 * Intel Quark Core DevMan_001.pdf section 6.4.11
186 * "The operating system also is required to invalidate (i.e., flush)
187 * the TLB when any changes are made to any of the page table entries.
188 * The operating system must reload CR3 to cause the TLB to be flushed"
189 *
190 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
191 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
192 * to be modified.
193 */
194 if (c->x86 == 5 && c->x86_model == 9) {
195 pr_info("Disabling PGE capability bit\n");
196 setup_clear_cpu_cap(X86_FEATURE_PGE);
197 }
198
199 if (c->cpuid_level >= 0x00000001) {
200 u32 eax, ebx, ecx, edx;
201
202 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
203 /*
204 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
205 * apicids which are reserved per package. Store the resulting
206 * shift value for the package management code.
207 */
208 if (edx & (1U << 28))
209 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
210 }
211
212 check_mpx_erratum(c);
213 }
214
215 #ifdef CONFIG_X86_32
216 /*
217 * Early probe support logic for ppro memory erratum #50
218 *
219 * This is called before we do cpu ident work
220 */
221
222 int ppro_with_ram_bug(void)
223 {
224 /* Uses data from early_cpu_detect now */
225 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
226 boot_cpu_data.x86 == 6 &&
227 boot_cpu_data.x86_model == 1 &&
228 boot_cpu_data.x86_mask < 8) {
229 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
230 return 1;
231 }
232 return 0;
233 }
234
235 static void intel_smp_check(struct cpuinfo_x86 *c)
236 {
237 /* calling is from identify_secondary_cpu() ? */
238 if (!c->cpu_index)
239 return;
240
241 /*
242 * Mask B, Pentium, but not Pentium MMX
243 */
244 if (c->x86 == 5 &&
245 c->x86_mask >= 1 && c->x86_mask <= 4 &&
246 c->x86_model <= 3) {
247 /*
248 * Remember we have B step Pentia with bugs
249 */
250 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
251 "with B stepping processors.\n");
252 }
253 }
254
255 static int forcepae;
256 static int __init forcepae_setup(char *__unused)
257 {
258 forcepae = 1;
259 return 1;
260 }
261 __setup("forcepae", forcepae_setup);
262
263 static void intel_workarounds(struct cpuinfo_x86 *c)
264 {
265 #ifdef CONFIG_X86_F00F_BUG
266 /*
267 * All models of Pentium and Pentium with MMX technology CPUs
268 * have the F0 0F bug, which lets nonprivileged users lock up the
269 * system. Announce that the fault handler will be checking for it.
270 * The Quark is also family 5, but does not have the same bug.
271 */
272 clear_cpu_bug(c, X86_BUG_F00F);
273 if (c->x86 == 5 && c->x86_model < 9) {
274 static int f00f_workaround_enabled;
275
276 set_cpu_bug(c, X86_BUG_F00F);
277 if (!f00f_workaround_enabled) {
278 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
279 f00f_workaround_enabled = 1;
280 }
281 }
282 #endif
283
284 /*
285 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
286 * model 3 mask 3
287 */
288 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
289 clear_cpu_cap(c, X86_FEATURE_SEP);
290
291 /*
292 * PAE CPUID issue: many Pentium M report no PAE but may have a
293 * functionally usable PAE implementation.
294 * Forcefully enable PAE if kernel parameter "forcepae" is present.
295 */
296 if (forcepae) {
297 pr_warn("PAE forced!\n");
298 set_cpu_cap(c, X86_FEATURE_PAE);
299 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
300 }
301
302 /*
303 * P4 Xeon errata 037 workaround.
304 * Hardware prefetcher may cause stale data to be loaded into the cache.
305 */
306 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
307 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
308 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
309 > 0) {
310 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
311 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
312 }
313 }
314
315 /*
316 * See if we have a good local APIC by checking for buggy Pentia,
317 * i.e. all B steppings and the C2 stepping of P54C when using their
318 * integrated APIC (see 11AP erratum in "Pentium Processor
319 * Specification Update").
320 */
321 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
322 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
323 set_cpu_bug(c, X86_BUG_11AP);
324
325
326 #ifdef CONFIG_X86_INTEL_USERCOPY
327 /*
328 * Set up the preferred alignment for movsl bulk memory moves
329 */
330 switch (c->x86) {
331 case 4: /* 486: untested */
332 break;
333 case 5: /* Old Pentia: untested */
334 break;
335 case 6: /* PII/PIII only like movsl with 8-byte alignment */
336 movsl_mask.mask = 7;
337 break;
338 case 15: /* P4 is OK down to 8-byte alignment */
339 movsl_mask.mask = 7;
340 break;
341 }
342 #endif
343
344 intel_smp_check(c);
345 }
346 #else
347 static void intel_workarounds(struct cpuinfo_x86 *c)
348 {
349 }
350 #endif
351
352 static void srat_detect_node(struct cpuinfo_x86 *c)
353 {
354 #ifdef CONFIG_NUMA
355 unsigned node;
356 int cpu = smp_processor_id();
357
358 /* Don't do the funky fallback heuristics the AMD version employs
359 for now. */
360 node = numa_cpu_node(cpu);
361 if (node == NUMA_NO_NODE || !node_online(node)) {
362 /* reuse the value from init_cpu_to_node() */
363 node = cpu_to_node(cpu);
364 }
365 numa_set_node(cpu, node);
366 #endif
367 }
368
369 /*
370 * find out the number of processor cores on the die
371 */
372 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
373 {
374 unsigned int eax, ebx, ecx, edx;
375
376 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
377 return 1;
378
379 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
380 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
381 if (eax & 0x1f)
382 return (eax >> 26) + 1;
383 else
384 return 1;
385 }
386
387 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
388 {
389 /* Intel VMX MSR indicated features */
390 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
391 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
392 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
393 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
394 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
395 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
396
397 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
398
399 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
400 clear_cpu_cap(c, X86_FEATURE_VNMI);
401 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
402 clear_cpu_cap(c, X86_FEATURE_EPT);
403 clear_cpu_cap(c, X86_FEATURE_VPID);
404
405 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
406 msr_ctl = vmx_msr_high | vmx_msr_low;
407 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
408 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
409 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
410 set_cpu_cap(c, X86_FEATURE_VNMI);
411 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
412 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
413 vmx_msr_low, vmx_msr_high);
414 msr_ctl2 = vmx_msr_high | vmx_msr_low;
415 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
416 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
417 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
418 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
419 set_cpu_cap(c, X86_FEATURE_EPT);
420 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
421 set_cpu_cap(c, X86_FEATURE_VPID);
422 }
423 }
424
425 static void init_intel_energy_perf(struct cpuinfo_x86 *c)
426 {
427 u64 epb;
428
429 /*
430 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
431 * (x86_energy_perf_policy(8) is available to change it at run-time.)
432 */
433 if (!cpu_has(c, X86_FEATURE_EPB))
434 return;
435
436 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
437 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
438 return;
439
440 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
441 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
442 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
443 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
444 }
445
446 static void intel_bsp_resume(struct cpuinfo_x86 *c)
447 {
448 /*
449 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
450 * so reinitialize it properly like during bootup:
451 */
452 init_intel_energy_perf(c);
453 }
454
455 static void init_intel(struct cpuinfo_x86 *c)
456 {
457 unsigned int l2 = 0;
458
459 early_init_intel(c);
460
461 intel_workarounds(c);
462
463 /*
464 * Detect the extended topology information if available. This
465 * will reinitialise the initial_apicid which will be used
466 * in init_intel_cacheinfo()
467 */
468 detect_extended_topology(c);
469
470 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
471 /*
472 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
473 * detection.
474 */
475 c->x86_max_cores = intel_num_cpu_cores(c);
476 #ifdef CONFIG_X86_32
477 detect_ht(c);
478 #endif
479 }
480
481 l2 = init_intel_cacheinfo(c);
482
483 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
484 if (l2 == 0) {
485 cpu_detect_cache_sizes(c);
486 l2 = c->x86_cache_size;
487 }
488
489 if (c->cpuid_level > 9) {
490 unsigned eax = cpuid_eax(10);
491 /* Check for version and the number of counters */
492 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
493 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
494 }
495
496 if (cpu_has(c, X86_FEATURE_XMM2))
497 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
498
499 if (boot_cpu_has(X86_FEATURE_DS)) {
500 unsigned int l1;
501 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
502 if (!(l1 & (1<<11)))
503 set_cpu_cap(c, X86_FEATURE_BTS);
504 if (!(l1 & (1<<12)))
505 set_cpu_cap(c, X86_FEATURE_PEBS);
506 }
507
508 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
509 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
510 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
511
512 #ifdef CONFIG_X86_64
513 if (c->x86 == 15)
514 c->x86_cache_alignment = c->x86_clflush_size * 2;
515 if (c->x86 == 6)
516 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
517 #else
518 /*
519 * Names for the Pentium II/Celeron processors
520 * detectable only by also checking the cache size.
521 * Dixon is NOT a Celeron.
522 */
523 if (c->x86 == 6) {
524 char *p = NULL;
525
526 switch (c->x86_model) {
527 case 5:
528 if (l2 == 0)
529 p = "Celeron (Covington)";
530 else if (l2 == 256)
531 p = "Mobile Pentium II (Dixon)";
532 break;
533
534 case 6:
535 if (l2 == 128)
536 p = "Celeron (Mendocino)";
537 else if (c->x86_mask == 0 || c->x86_mask == 5)
538 p = "Celeron-A";
539 break;
540
541 case 8:
542 if (l2 == 128)
543 p = "Celeron (Coppermine)";
544 break;
545 }
546
547 if (p)
548 strcpy(c->x86_model_id, p);
549 }
550
551 if (c->x86 == 15)
552 set_cpu_cap(c, X86_FEATURE_P4);
553 if (c->x86 == 6)
554 set_cpu_cap(c, X86_FEATURE_P3);
555 #endif
556
557 /* Work around errata */
558 srat_detect_node(c);
559
560 if (cpu_has(c, X86_FEATURE_VMX))
561 detect_vmx_virtcap(c);
562
563 init_intel_energy_perf(c);
564 }
565
566 #ifdef CONFIG_X86_32
567 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
568 {
569 /*
570 * Intel PIII Tualatin. This comes in two flavours.
571 * One has 256kb of cache, the other 512. We have no way
572 * to determine which, so we use a boottime override
573 * for the 512kb model, and assume 256 otherwise.
574 */
575 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
576 size = 256;
577
578 /*
579 * Intel Quark SoC X1000 contains a 4-way set associative
580 * 16K cache with a 16 byte cache line and 256 lines per tag
581 */
582 if ((c->x86 == 5) && (c->x86_model == 9))
583 size = 16;
584 return size;
585 }
586 #endif
587
588 #define TLB_INST_4K 0x01
589 #define TLB_INST_4M 0x02
590 #define TLB_INST_2M_4M 0x03
591
592 #define TLB_INST_ALL 0x05
593 #define TLB_INST_1G 0x06
594
595 #define TLB_DATA_4K 0x11
596 #define TLB_DATA_4M 0x12
597 #define TLB_DATA_2M_4M 0x13
598 #define TLB_DATA_4K_4M 0x14
599
600 #define TLB_DATA_1G 0x16
601
602 #define TLB_DATA0_4K 0x21
603 #define TLB_DATA0_4M 0x22
604 #define TLB_DATA0_2M_4M 0x23
605
606 #define STLB_4K 0x41
607 #define STLB_4K_2M 0x42
608
609 static const struct _tlb_table intel_tlb_table[] = {
610 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
611 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
612 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
613 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
614 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
615 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
616 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
617 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
618 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
619 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
620 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
621 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
622 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
623 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
624 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
625 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
626 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
627 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
628 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
629 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
630 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
631 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
632 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
633 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
634 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
635 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
636 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
637 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
638 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
639 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
640 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
641 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
642 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
643 { 0x00, 0, 0 }
644 };
645
646 static void intel_tlb_lookup(const unsigned char desc)
647 {
648 unsigned char k;
649 if (desc == 0)
650 return;
651
652 /* look up this descriptor in the table */
653 for (k = 0; intel_tlb_table[k].descriptor != desc && \
654 intel_tlb_table[k].descriptor != 0; k++)
655 ;
656
657 if (intel_tlb_table[k].tlb_type == 0)
658 return;
659
660 switch (intel_tlb_table[k].tlb_type) {
661 case STLB_4K:
662 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
663 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
664 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
665 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
666 break;
667 case STLB_4K_2M:
668 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
669 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
670 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
671 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
672 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
673 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
674 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
675 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
676 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
677 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
678 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
679 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
680 break;
681 case TLB_INST_ALL:
682 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
683 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
684 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
685 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
686 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
687 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
688 break;
689 case TLB_INST_4K:
690 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
691 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
692 break;
693 case TLB_INST_4M:
694 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
695 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
696 break;
697 case TLB_INST_2M_4M:
698 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
699 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
700 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
701 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
702 break;
703 case TLB_DATA_4K:
704 case TLB_DATA0_4K:
705 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
706 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
707 break;
708 case TLB_DATA_4M:
709 case TLB_DATA0_4M:
710 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
711 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
712 break;
713 case TLB_DATA_2M_4M:
714 case TLB_DATA0_2M_4M:
715 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
716 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
717 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
718 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
719 break;
720 case TLB_DATA_4K_4M:
721 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
722 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
723 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
724 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
725 break;
726 case TLB_DATA_1G:
727 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
728 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
729 break;
730 }
731 }
732
733 static void intel_detect_tlb(struct cpuinfo_x86 *c)
734 {
735 int i, j, n;
736 unsigned int regs[4];
737 unsigned char *desc = (unsigned char *)regs;
738
739 if (c->cpuid_level < 2)
740 return;
741
742 /* Number of times to iterate */
743 n = cpuid_eax(2) & 0xFF;
744
745 for (i = 0 ; i < n ; i++) {
746 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
747
748 /* If bit 31 is set, this is an unknown format */
749 for (j = 0 ; j < 3 ; j++)
750 if (regs[j] & (1 << 31))
751 regs[j] = 0;
752
753 /* Byte 0 is level count, not a descriptor */
754 for (j = 1 ; j < 16 ; j++)
755 intel_tlb_lookup(desc[j]);
756 }
757 }
758
759 static const struct cpu_dev intel_cpu_dev = {
760 .c_vendor = "Intel",
761 .c_ident = { "GenuineIntel" },
762 #ifdef CONFIG_X86_32
763 .legacy_models = {
764 { .family = 4, .model_names =
765 {
766 [0] = "486 DX-25/33",
767 [1] = "486 DX-50",
768 [2] = "486 SX",
769 [3] = "486 DX/2",
770 [4] = "486 SL",
771 [5] = "486 SX/2",
772 [7] = "486 DX/2-WB",
773 [8] = "486 DX/4",
774 [9] = "486 DX/4-WB"
775 }
776 },
777 { .family = 5, .model_names =
778 {
779 [0] = "Pentium 60/66 A-step",
780 [1] = "Pentium 60/66",
781 [2] = "Pentium 75 - 200",
782 [3] = "OverDrive PODP5V83",
783 [4] = "Pentium MMX",
784 [7] = "Mobile Pentium 75 - 200",
785 [8] = "Mobile Pentium MMX",
786 [9] = "Quark SoC X1000",
787 }
788 },
789 { .family = 6, .model_names =
790 {
791 [0] = "Pentium Pro A-step",
792 [1] = "Pentium Pro",
793 [3] = "Pentium II (Klamath)",
794 [4] = "Pentium II (Deschutes)",
795 [5] = "Pentium II (Deschutes)",
796 [6] = "Mobile Pentium II",
797 [7] = "Pentium III (Katmai)",
798 [8] = "Pentium III (Coppermine)",
799 [10] = "Pentium III (Cascades)",
800 [11] = "Pentium III (Tualatin)",
801 }
802 },
803 { .family = 15, .model_names =
804 {
805 [0] = "Pentium 4 (Unknown)",
806 [1] = "Pentium 4 (Willamette)",
807 [2] = "Pentium 4 (Northwood)",
808 [4] = "Pentium 4 (Foster)",
809 [5] = "Pentium 4 (Foster)",
810 }
811 },
812 },
813 .legacy_cache_size = intel_size_cache,
814 #endif
815 .c_detect_tlb = intel_detect_tlb,
816 .c_early_init = early_init_intel,
817 .c_init = init_intel,
818 .c_bsp_resume = intel_bsp_resume,
819 .c_x86_vendor = X86_VENDOR_INTEL,
820 };
821
822 cpu_dev_register(intel_cpu_dev);
823
Linux kernel - Deliverables
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