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x86: Quark: Comment setup_arch() to document TLB/PGE bug
[deliverable/linux.git] / arch / x86 / kernel / cpu / intel.c
1 #include <linux/kernel.h>
2
3 #include <linux/string.h>
4 #include <linux/bitops.h>
5 #include <linux/smp.h>
6 #include <linux/sched.h>
7 #include <linux/thread_info.h>
8 #include <linux/module.h>
9 #include <linux/uaccess.h>
10
11 #include <asm/processor.h>
12 #include <asm/pgtable.h>
13 #include <asm/msr.h>
14 #include <asm/bugs.h>
15 #include <asm/cpu.h>
16
17 #ifdef CONFIG_X86_64
18 #include <linux/topology.h>
19 #endif
20
21 #include "cpu.h"
22
23 #ifdef CONFIG_X86_LOCAL_APIC
24 #include <asm/mpspec.h>
25 #include <asm/apic.h>
26 #endif
27
28 static void early_init_intel(struct cpuinfo_x86 *c)
29 {
30 u64 misc_enable;
31
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
36 c->cpuid_level = cpuid_eax(0);
37 get_cpu_cap(c);
38 }
39 }
40
41 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
42 (c->x86 == 0x6 && c->x86_model >= 0x0e))
43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
44
45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
46 unsigned lower_word;
47
48 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
49 /* Required by the SDM */
50 sync_core();
51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
52 }
53
54 /*
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
56 *
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
61 */
62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
63 c->microcode < 0x20e) {
64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c, X86_FEATURE_PSE);
66 }
67
68 #ifdef CONFIG_X86_64
69 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
70 #else
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c->x86 == 15 && c->x86_cache_alignment == 64)
73 c->x86_cache_alignment = 128;
74 #endif
75
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c->x86 == 0xF && c->x86_model == 0x3
78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
79 c->x86_phys_bits = 36;
80
81 /*
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
84 *
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
87 */
88 if (c->x86_power & (1 << 8)) {
89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
93 }
94
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
96 if (c->x86 == 6) {
97 switch (c->x86_model) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
101 break;
102 default:
103 break;
104 }
105 }
106
107 /*
108 * There is a known erratum on Pentium III and Core Solo
109 * and Core Duo CPUs.
110 * " Page with PAT set to WC while associated MTRR is UC
111 * may consolidate to UC "
112 * Because of this erratum, it is better to stick with
113 * setting WC in MTRR rather than using PAT on these CPUs.
114 *
115 * Enable PAT WC only on P4, Core 2 or later CPUs.
116 */
117 if (c->x86 == 6 && c->x86_model < 15)
118 clear_cpu_cap(c, X86_FEATURE_PAT);
119
120 #ifdef CONFIG_KMEMCHECK
121 /*
122 * P4s have a "fast strings" feature which causes single-
123 * stepping REP instructions to only generate a #DB on
124 * cache-line boundaries.
125 *
126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
127 * (model 2) with the same problem.
128 */
129 if (c->x86 == 15)
130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
132 pr_info("kmemcheck: Disabling fast string operations\n");
133 #endif
134
135 /*
136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
137 * clear the fast string and enhanced fast string CPU capabilities.
138 */
139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
142 printk(KERN_INFO "Disabled fast string operations\n");
143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
144 setup_clear_cpu_cap(X86_FEATURE_ERMS);
145 }
146 }
147
148 /*
149 * Intel Quark Core DevMan_001.pdf section 6.4.11
150 * "The operating system also is required to invalidate (i.e., flush)
151 * the TLB when any changes are made to any of the page table entries.
152 * The operating system must reload CR3 to cause the TLB to be flushed"
153 *
154 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
155 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
156 * to be modified
157 */
158 if (c->x86 == 5 && c->x86_model == 9) {
159 pr_info("Disabling PGE capability bit\n");
160 setup_clear_cpu_cap(X86_FEATURE_PGE);
161 }
162 }
163
164 #ifdef CONFIG_X86_32
165 /*
166 * Early probe support logic for ppro memory erratum #50
167 *
168 * This is called before we do cpu ident work
169 */
170
171 int ppro_with_ram_bug(void)
172 {
173 /* Uses data from early_cpu_detect now */
174 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
175 boot_cpu_data.x86 == 6 &&
176 boot_cpu_data.x86_model == 1 &&
177 boot_cpu_data.x86_mask < 8) {
178 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
179 return 1;
180 }
181 return 0;
182 }
183
184 static void intel_smp_check(struct cpuinfo_x86 *c)
185 {
186 /* calling is from identify_secondary_cpu() ? */
187 if (!c->cpu_index)
188 return;
189
190 /*
191 * Mask B, Pentium, but not Pentium MMX
192 */
193 if (c->x86 == 5 &&
194 c->x86_mask >= 1 && c->x86_mask <= 4 &&
195 c->x86_model <= 3) {
196 /*
197 * Remember we have B step Pentia with bugs
198 */
199 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
200 "with B stepping processors.\n");
201 }
202 }
203
204 static int forcepae;
205 static int __init forcepae_setup(char *__unused)
206 {
207 forcepae = 1;
208 return 1;
209 }
210 __setup("forcepae", forcepae_setup);
211
212 static void intel_workarounds(struct cpuinfo_x86 *c)
213 {
214 #ifdef CONFIG_X86_F00F_BUG
215 /*
216 * All current models of Pentium and Pentium with MMX technology CPUs
217 * have the F0 0F bug, which lets nonprivileged users lock up the
218 * system. Announce that the fault handler will be checking for it.
219 */
220 clear_cpu_bug(c, X86_BUG_F00F);
221 if (!paravirt_enabled() && c->x86 == 5) {
222 static int f00f_workaround_enabled;
223
224 set_cpu_bug(c, X86_BUG_F00F);
225 if (!f00f_workaround_enabled) {
226 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
227 f00f_workaround_enabled = 1;
228 }
229 }
230 #endif
231
232 /*
233 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
234 * model 3 mask 3
235 */
236 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
237 clear_cpu_cap(c, X86_FEATURE_SEP);
238
239 /*
240 * PAE CPUID issue: many Pentium M report no PAE but may have a
241 * functionally usable PAE implementation.
242 * Forcefully enable PAE if kernel parameter "forcepae" is present.
243 */
244 if (forcepae) {
245 printk(KERN_WARNING "PAE forced!\n");
246 set_cpu_cap(c, X86_FEATURE_PAE);
247 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
248 }
249
250 /*
251 * P4 Xeon errata 037 workaround.
252 * Hardware prefetcher may cause stale data to be loaded into the cache.
253 */
254 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
255 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
256 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
257 > 0) {
258 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
259 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
260 }
261 }
262
263 /*
264 * See if we have a good local APIC by checking for buggy Pentia,
265 * i.e. all B steppings and the C2 stepping of P54C when using their
266 * integrated APIC (see 11AP erratum in "Pentium Processor
267 * Specification Update").
268 */
269 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
270 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
271 set_cpu_bug(c, X86_BUG_11AP);
272
273
274 #ifdef CONFIG_X86_INTEL_USERCOPY
275 /*
276 * Set up the preferred alignment for movsl bulk memory moves
277 */
278 switch (c->x86) {
279 case 4: /* 486: untested */
280 break;
281 case 5: /* Old Pentia: untested */
282 break;
283 case 6: /* PII/PIII only like movsl with 8-byte alignment */
284 movsl_mask.mask = 7;
285 break;
286 case 15: /* P4 is OK down to 8-byte alignment */
287 movsl_mask.mask = 7;
288 break;
289 }
290 #endif
291
292 intel_smp_check(c);
293 }
294 #else
295 static void intel_workarounds(struct cpuinfo_x86 *c)
296 {
297 }
298 #endif
299
300 static void srat_detect_node(struct cpuinfo_x86 *c)
301 {
302 #ifdef CONFIG_NUMA
303 unsigned node;
304 int cpu = smp_processor_id();
305
306 /* Don't do the funky fallback heuristics the AMD version employs
307 for now. */
308 node = numa_cpu_node(cpu);
309 if (node == NUMA_NO_NODE || !node_online(node)) {
310 /* reuse the value from init_cpu_to_node() */
311 node = cpu_to_node(cpu);
312 }
313 numa_set_node(cpu, node);
314 #endif
315 }
316
317 /*
318 * find out the number of processor cores on the die
319 */
320 static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
321 {
322 unsigned int eax, ebx, ecx, edx;
323
324 if (c->cpuid_level < 4)
325 return 1;
326
327 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
328 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
329 if (eax & 0x1f)
330 return (eax >> 26) + 1;
331 else
332 return 1;
333 }
334
335 static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
336 {
337 /* Intel VMX MSR indicated features */
338 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
339 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
340 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
341 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
342 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
343 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
344
345 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
346
347 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
348 clear_cpu_cap(c, X86_FEATURE_VNMI);
349 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
350 clear_cpu_cap(c, X86_FEATURE_EPT);
351 clear_cpu_cap(c, X86_FEATURE_VPID);
352
353 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
354 msr_ctl = vmx_msr_high | vmx_msr_low;
355 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
356 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
357 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
358 set_cpu_cap(c, X86_FEATURE_VNMI);
359 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
360 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
361 vmx_msr_low, vmx_msr_high);
362 msr_ctl2 = vmx_msr_high | vmx_msr_low;
363 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
364 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
365 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
366 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
367 set_cpu_cap(c, X86_FEATURE_EPT);
368 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
369 set_cpu_cap(c, X86_FEATURE_VPID);
370 }
371 }
372
373 static void init_intel(struct cpuinfo_x86 *c)
374 {
375 unsigned int l2 = 0;
376
377 early_init_intel(c);
378
379 intel_workarounds(c);
380
381 /*
382 * Detect the extended topology information if available. This
383 * will reinitialise the initial_apicid which will be used
384 * in init_intel_cacheinfo()
385 */
386 detect_extended_topology(c);
387
388 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
389 /*
390 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
391 * detection.
392 */
393 c->x86_max_cores = intel_num_cpu_cores(c);
394 #ifdef CONFIG_X86_32
395 detect_ht(c);
396 #endif
397 }
398
399 l2 = init_intel_cacheinfo(c);
400 if (c->cpuid_level > 9) {
401 unsigned eax = cpuid_eax(10);
402 /* Check for version and the number of counters */
403 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
404 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
405 }
406
407 if (cpu_has_xmm2)
408 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
409 if (cpu_has_ds) {
410 unsigned int l1;
411 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
412 if (!(l1 & (1<<11)))
413 set_cpu_cap(c, X86_FEATURE_BTS);
414 if (!(l1 & (1<<12)))
415 set_cpu_cap(c, X86_FEATURE_PEBS);
416 }
417
418 if (c->x86 == 6 && cpu_has_clflush &&
419 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
420 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
421
422 #ifdef CONFIG_X86_64
423 if (c->x86 == 15)
424 c->x86_cache_alignment = c->x86_clflush_size * 2;
425 if (c->x86 == 6)
426 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
427 #else
428 /*
429 * Names for the Pentium II/Celeron processors
430 * detectable only by also checking the cache size.
431 * Dixon is NOT a Celeron.
432 */
433 if (c->x86 == 6) {
434 char *p = NULL;
435
436 switch (c->x86_model) {
437 case 5:
438 if (l2 == 0)
439 p = "Celeron (Covington)";
440 else if (l2 == 256)
441 p = "Mobile Pentium II (Dixon)";
442 break;
443
444 case 6:
445 if (l2 == 128)
446 p = "Celeron (Mendocino)";
447 else if (c->x86_mask == 0 || c->x86_mask == 5)
448 p = "Celeron-A";
449 break;
450
451 case 8:
452 if (l2 == 128)
453 p = "Celeron (Coppermine)";
454 break;
455 }
456
457 if (p)
458 strcpy(c->x86_model_id, p);
459 }
460
461 if (c->x86 == 15)
462 set_cpu_cap(c, X86_FEATURE_P4);
463 if (c->x86 == 6)
464 set_cpu_cap(c, X86_FEATURE_P3);
465 #endif
466
467 /* Work around errata */
468 srat_detect_node(c);
469
470 if (cpu_has(c, X86_FEATURE_VMX))
471 detect_vmx_virtcap(c);
472
473 /*
474 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
475 * x86_energy_perf_policy(8) is available to change it at run-time
476 */
477 if (cpu_has(c, X86_FEATURE_EPB)) {
478 u64 epb;
479
480 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
481 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
482 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
483 " Set to 'normal', was 'performance'\n"
484 "ENERGY_PERF_BIAS: View and update with"
485 " x86_energy_perf_policy(8)\n");
486 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
487 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
488 }
489 }
490 }
491
492 #ifdef CONFIG_X86_32
493 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
494 {
495 /*
496 * Intel PIII Tualatin. This comes in two flavours.
497 * One has 256kb of cache, the other 512. We have no way
498 * to determine which, so we use a boottime override
499 * for the 512kb model, and assume 256 otherwise.
500 */
501 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
502 size = 256;
503 return size;
504 }
505 #endif
506
507 #define TLB_INST_4K 0x01
508 #define TLB_INST_4M 0x02
509 #define TLB_INST_2M_4M 0x03
510
511 #define TLB_INST_ALL 0x05
512 #define TLB_INST_1G 0x06
513
514 #define TLB_DATA_4K 0x11
515 #define TLB_DATA_4M 0x12
516 #define TLB_DATA_2M_4M 0x13
517 #define TLB_DATA_4K_4M 0x14
518
519 #define TLB_DATA_1G 0x16
520
521 #define TLB_DATA0_4K 0x21
522 #define TLB_DATA0_4M 0x22
523 #define TLB_DATA0_2M_4M 0x23
524
525 #define STLB_4K 0x41
526 #define STLB_4K_2M 0x42
527
528 static const struct _tlb_table intel_tlb_table[] = {
529 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
530 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
531 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
532 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
533 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
534 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
535 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
536 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
537 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
538 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
539 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
540 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
541 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
542 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
543 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
544 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
545 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
546 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
547 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
548 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
549 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
550 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
551 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
552 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
553 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
554 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
555 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
556 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
557 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
558 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
559 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
560 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
561 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
562 { 0x00, 0, 0 }
563 };
564
565 static void intel_tlb_lookup(const unsigned char desc)
566 {
567 unsigned char k;
568 if (desc == 0)
569 return;
570
571 /* look up this descriptor in the table */
572 for (k = 0; intel_tlb_table[k].descriptor != desc && \
573 intel_tlb_table[k].descriptor != 0; k++)
574 ;
575
576 if (intel_tlb_table[k].tlb_type == 0)
577 return;
578
579 switch (intel_tlb_table[k].tlb_type) {
580 case STLB_4K:
581 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
582 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
583 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
584 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
585 break;
586 case STLB_4K_2M:
587 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
588 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
589 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
590 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
591 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
592 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
593 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
594 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
595 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
596 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
597 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
598 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
599 break;
600 case TLB_INST_ALL:
601 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
602 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
603 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
604 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
605 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
606 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
607 break;
608 case TLB_INST_4K:
609 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
610 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
611 break;
612 case TLB_INST_4M:
613 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
614 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
615 break;
616 case TLB_INST_2M_4M:
617 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
618 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
619 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
620 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
621 break;
622 case TLB_DATA_4K:
623 case TLB_DATA0_4K:
624 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
625 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
626 break;
627 case TLB_DATA_4M:
628 case TLB_DATA0_4M:
629 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
630 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
631 break;
632 case TLB_DATA_2M_4M:
633 case TLB_DATA0_2M_4M:
634 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
635 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
636 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
637 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
638 break;
639 case TLB_DATA_4K_4M:
640 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
641 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
642 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
643 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
644 break;
645 case TLB_DATA_1G:
646 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
647 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
648 break;
649 }
650 }
651
652 static void intel_detect_tlb(struct cpuinfo_x86 *c)
653 {
654 int i, j, n;
655 unsigned int regs[4];
656 unsigned char *desc = (unsigned char *)regs;
657
658 if (c->cpuid_level < 2)
659 return;
660
661 /* Number of times to iterate */
662 n = cpuid_eax(2) & 0xFF;
663
664 for (i = 0 ; i < n ; i++) {
665 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
666
667 /* If bit 31 is set, this is an unknown format */
668 for (j = 0 ; j < 3 ; j++)
669 if (regs[j] & (1 << 31))
670 regs[j] = 0;
671
672 /* Byte 0 is level count, not a descriptor */
673 for (j = 1 ; j < 16 ; j++)
674 intel_tlb_lookup(desc[j]);
675 }
676 }
677
678 static const struct cpu_dev intel_cpu_dev = {
679 .c_vendor = "Intel",
680 .c_ident = { "GenuineIntel" },
681 #ifdef CONFIG_X86_32
682 .legacy_models = {
683 { .family = 4, .model_names =
684 {
685 [0] = "486 DX-25/33",
686 [1] = "486 DX-50",
687 [2] = "486 SX",
688 [3] = "486 DX/2",
689 [4] = "486 SL",
690 [5] = "486 SX/2",
691 [7] = "486 DX/2-WB",
692 [8] = "486 DX/4",
693 [9] = "486 DX/4-WB"
694 }
695 },
696 { .family = 5, .model_names =
697 {
698 [0] = "Pentium 60/66 A-step",
699 [1] = "Pentium 60/66",
700 [2] = "Pentium 75 - 200",
701 [3] = "OverDrive PODP5V83",
702 [4] = "Pentium MMX",
703 [7] = "Mobile Pentium 75 - 200",
704 [8] = "Mobile Pentium MMX"
705 }
706 },
707 { .family = 6, .model_names =
708 {
709 [0] = "Pentium Pro A-step",
710 [1] = "Pentium Pro",
711 [3] = "Pentium II (Klamath)",
712 [4] = "Pentium II (Deschutes)",
713 [5] = "Pentium II (Deschutes)",
714 [6] = "Mobile Pentium II",
715 [7] = "Pentium III (Katmai)",
716 [8] = "Pentium III (Coppermine)",
717 [10] = "Pentium III (Cascades)",
718 [11] = "Pentium III (Tualatin)",
719 }
720 },
721 { .family = 15, .model_names =
722 {
723 [0] = "Pentium 4 (Unknown)",
724 [1] = "Pentium 4 (Willamette)",
725 [2] = "Pentium 4 (Northwood)",
726 [4] = "Pentium 4 (Foster)",
727 [5] = "Pentium 4 (Foster)",
728 }
729 },
730 },
731 .legacy_cache_size = intel_size_cache,
732 #endif
733 .c_detect_tlb = intel_detect_tlb,
734 .c_early_init = early_init_intel,
735 .c_init = init_intel,
736 .c_x86_vendor = X86_VENDOR_INTEL,
737 };
738
739 cpu_dev_register(intel_cpu_dev);
740
Linux kernel - Deliverables
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