2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <linux/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/hw_irq.h>
47 #include "mce-internal.h"
49 #define CREATE_TRACE_POINTS
50 #include <trace/events/mce.h>
52 int mce_disabled __read_mostly
;
54 #define MISC_MCELOG_MINOR 227
56 #define SPINUNIT 100 /* 100ns */
60 DEFINE_PER_CPU(unsigned, mce_exception_count
);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant __read_mostly
= 1;
70 static int banks __read_mostly
;
71 static int rip_msr __read_mostly
;
72 static int mce_bootlog __read_mostly
= -1;
73 static int monarch_timeout __read_mostly
= -1;
74 static int mce_panic_timeout __read_mostly
;
75 static int mce_dont_log_ce __read_mostly
;
76 int mce_cmci_disabled __read_mostly
;
77 int mce_ignore_ce __read_mostly
;
78 int mce_ser __read_mostly
;
80 struct mce_bank
*mce_banks __read_mostly
;
82 /* User mode helper program triggered by machine check event */
83 static unsigned long mce_need_notify
;
84 static char mce_helper
[128];
85 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
87 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
88 static DEFINE_PER_CPU(struct mce
, mces_seen
);
89 static int cpu_missing
;
92 * CPU/chipset specific EDAC code can register a notifier call here to print
93 * MCE errors in a human-readable form.
95 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
96 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain
);
98 static int default_decode_mce(struct notifier_block
*nb
, unsigned long val
,
101 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
102 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
107 static struct notifier_block mce_dec_nb
= {
108 .notifier_call
= default_decode_mce
,
112 /* MCA banks polled by the period polling timer for corrected events */
113 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
114 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
117 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
119 /* Do initial initialization of a struct mce */
120 void mce_setup(struct mce
*m
)
122 memset(m
, 0, sizeof(struct mce
));
123 m
->cpu
= m
->extcpu
= smp_processor_id();
125 /* We hope get_seconds stays lockless */
126 m
->time
= get_seconds();
127 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
128 m
->cpuid
= cpuid_eax(1);
130 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
132 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
133 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
136 DEFINE_PER_CPU(struct mce
, injectm
);
137 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
140 * Lockless MCE logging infrastructure.
141 * This avoids deadlocks on printk locks without having to break locks. Also
142 * separate MCEs from kernel messages to avoid bogus bug reports.
145 static struct mce_log mcelog
= {
146 .signature
= MCE_LOG_SIGNATURE
,
148 .recordlen
= sizeof(struct mce
),
151 void mce_log(struct mce
*mce
)
153 unsigned next
, entry
;
155 /* Emit the trace record: */
156 trace_mce_record(mce
);
161 entry
= rcu_dereference(mcelog
.next
);
164 * When the buffer fills up discard new entries.
165 * Assume that the earlier errors are the more
168 if (entry
>= MCE_LOG_LEN
) {
169 set_bit(MCE_OVERFLOW
,
170 (unsigned long *)&mcelog
.flags
);
173 /* Old left over entry. Skip: */
174 if (mcelog
.entry
[entry
].finished
) {
182 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
185 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
187 mcelog
.entry
[entry
].finished
= 1;
191 set_bit(0, &mce_need_notify
);
194 static void print_mce(struct mce
*m
)
196 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
197 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
200 pr_emerg("RIP%s %02x:<%016Lx> ",
201 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
204 if (m
->cs
== __KERNEL_CS
)
205 print_symbol("{%s}", m
->ip
);
209 pr_emerg("TSC %llx ", m
->tsc
);
211 pr_cont("ADDR %llx ", m
->addr
);
213 pr_cont("MISC %llx ", m
->misc
);
216 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
217 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
);
220 * Print out human-readable details about the MCE error,
221 * (if the CPU has an implementation for that)
223 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
226 static void print_mce_head(void)
228 pr_emerg("\nHARDWARE ERROR\n");
231 static void print_mce_tail(void)
233 pr_emerg("This is not a software problem!\n");
236 #define PANIC_TIMEOUT 5 /* 5 seconds */
238 static atomic_t mce_paniced
;
240 static int fake_panic
;
241 static atomic_t mce_fake_paniced
;
243 /* Panic in progress. Enable interrupts and wait for final IPI */
244 static void wait_for_panic(void)
246 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
250 while (timeout
-- > 0)
252 if (panic_timeout
== 0)
253 panic_timeout
= mce_panic_timeout
;
254 panic("Panicing machine check CPU died");
257 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
263 * Make sure only one CPU runs in machine check panic
265 if (atomic_inc_return(&mce_paniced
) > 1)
272 /* Don't log too much for fake panic */
273 if (atomic_inc_return(&mce_fake_paniced
) > 1)
277 /* First print corrected ones that are still unlogged */
278 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
279 struct mce
*m
= &mcelog
.entry
[i
];
280 if (!(m
->status
& MCI_STATUS_VAL
))
282 if (!(m
->status
& MCI_STATUS_UC
))
285 /* Now print uncorrected but with the final one last */
286 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
287 struct mce
*m
= &mcelog
.entry
[i
];
288 if (!(m
->status
& MCI_STATUS_VAL
))
290 if (!(m
->status
& MCI_STATUS_UC
))
292 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
298 printk(KERN_EMERG
"Some CPUs didn't answer in synchronization\n");
301 printk(KERN_EMERG
"Machine check: %s\n", exp
);
303 if (panic_timeout
== 0)
304 panic_timeout
= mce_panic_timeout
;
307 printk(KERN_EMERG
"Fake kernel panic: %s\n", msg
);
310 /* Support code for software error injection */
312 static int msr_to_offset(u32 msr
)
314 unsigned bank
= __get_cpu_var(injectm
.bank
);
317 return offsetof(struct mce
, ip
);
318 if (msr
== MSR_IA32_MCx_STATUS(bank
))
319 return offsetof(struct mce
, status
);
320 if (msr
== MSR_IA32_MCx_ADDR(bank
))
321 return offsetof(struct mce
, addr
);
322 if (msr
== MSR_IA32_MCx_MISC(bank
))
323 return offsetof(struct mce
, misc
);
324 if (msr
== MSR_IA32_MCG_STATUS
)
325 return offsetof(struct mce
, mcgstatus
);
329 /* MSR access wrappers used for error injection */
330 static u64
mce_rdmsrl(u32 msr
)
334 if (__get_cpu_var(injectm
).finished
) {
335 int offset
= msr_to_offset(msr
);
339 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
342 if (rdmsrl_safe(msr
, &v
)) {
343 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
345 * Return zero in case the access faulted. This should
346 * not happen normally but can happen if the CPU does
347 * something weird, or if the code is buggy.
355 static void mce_wrmsrl(u32 msr
, u64 v
)
357 if (__get_cpu_var(injectm
).finished
) {
358 int offset
= msr_to_offset(msr
);
361 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
368 * Simple lockless ring to communicate PFNs from the exception handler with the
369 * process context work function. This is vastly simplified because there's
370 * only a single reader and a single writer.
372 #define MCE_RING_SIZE 16 /* we use one entry less */
375 unsigned short start
;
377 unsigned long ring
[MCE_RING_SIZE
];
379 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
381 /* Runs with CPU affinity in workqueue */
382 static int mce_ring_empty(void)
384 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
386 return r
->start
== r
->end
;
389 static int mce_ring_get(unsigned long *pfn
)
396 r
= &__get_cpu_var(mce_ring
);
397 if (r
->start
== r
->end
)
399 *pfn
= r
->ring
[r
->start
];
400 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
407 /* Always runs in MCE context with preempt off */
408 static int mce_ring_add(unsigned long pfn
)
410 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
413 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
414 if (next
== r
->start
)
416 r
->ring
[r
->end
] = pfn
;
422 int mce_available(struct cpuinfo_x86
*c
)
426 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
429 static void mce_schedule_work(void)
431 if (!mce_ring_empty()) {
432 struct work_struct
*work
= &__get_cpu_var(mce_work
);
433 if (!work_pending(work
))
439 * Get the address of the instruction at the time of the machine check
442 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
445 if (regs
&& (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
))) {
453 m
->ip
= mce_rdmsrl(rip_msr
);
456 #ifdef CONFIG_X86_LOCAL_APIC
458 * Called after interrupts have been reenabled again
459 * when a MCE happened during an interrupts off region
462 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
473 static void mce_report_event(struct pt_regs
*regs
)
475 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
478 * Triggering the work queue here is just an insurance
479 * policy in case the syscall exit notify handler
480 * doesn't run soon enough or ends up running on the
481 * wrong CPU (can happen when audit sleeps)
487 #ifdef CONFIG_X86_LOCAL_APIC
489 * Without APIC do not notify. The event will be picked
496 * When interrupts are disabled we cannot use
497 * kernel services safely. Trigger an self interrupt
498 * through the APIC to instead do the notification
499 * after interrupts are reenabled again.
501 apic
->send_IPI_self(MCE_SELF_VECTOR
);
504 * Wait for idle afterwards again so that we don't leave the
505 * APIC in a non idle state because the normal APIC writes
508 apic_wait_icr_idle();
512 DEFINE_PER_CPU(unsigned, mce_poll_count
);
515 * Poll for corrected events or events that happened before reset.
516 * Those are just logged through /dev/mcelog.
518 * This is executed in standard interrupt context.
520 * Note: spec recommends to panic for fatal unsignalled
521 * errors here. However this would be quite problematic --
522 * we would need to reimplement the Monarch handling and
523 * it would mess up the exclusion between exception handler
524 * and poll hander -- * so we skip this for now.
525 * These cases should not happen anyways, or only when the CPU
526 * is already totally * confused. In this case it's likely it will
527 * not fully execute the machine check handler either.
529 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
534 __get_cpu_var(mce_poll_count
)++;
538 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
539 for (i
= 0; i
< banks
; i
++) {
540 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
549 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
550 if (!(m
.status
& MCI_STATUS_VAL
))
554 * Uncorrected or signalled events are handled by the exception
555 * handler when it is enabled, so don't process those here.
557 * TBD do the same check for MCI_STATUS_EN here?
559 if (!(flags
& MCP_UC
) &&
560 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
563 if (m
.status
& MCI_STATUS_MISCV
)
564 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
565 if (m
.status
& MCI_STATUS_ADDRV
)
566 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
568 if (!(flags
& MCP_TIMESTAMP
))
571 * Don't get the IP here because it's unlikely to
572 * have anything to do with the actual error location.
574 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
) {
576 add_taint(TAINT_MACHINE_CHECK
);
580 * Clear state for this bank.
582 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
586 * Don't clear MCG_STATUS here because it's only defined for
592 EXPORT_SYMBOL_GPL(machine_check_poll
);
595 * Do a quick check if any of the events requires a panic.
596 * This decides if we keep the events around or clear them.
598 static int mce_no_way_out(struct mce
*m
, char **msg
)
602 for (i
= 0; i
< banks
; i
++) {
603 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
604 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
611 * Variable to establish order between CPUs while scanning.
612 * Each CPU spins initially until executing is equal its number.
614 static atomic_t mce_executing
;
617 * Defines order of CPUs on entry. First CPU becomes Monarch.
619 static atomic_t mce_callin
;
622 * Check if a timeout waiting for other CPUs happened.
624 static int mce_timed_out(u64
*t
)
627 * The others already did panic for some reason.
628 * Bail out like in a timeout.
629 * rmb() to tell the compiler that system_state
630 * might have been modified by someone else.
633 if (atomic_read(&mce_paniced
))
635 if (!monarch_timeout
)
637 if ((s64
)*t
< SPINUNIT
) {
638 /* CHECKME: Make panic default for 1 too? */
640 mce_panic("Timeout synchronizing machine check over CPUs",
647 touch_nmi_watchdog();
652 * The Monarch's reign. The Monarch is the CPU who entered
653 * the machine check handler first. It waits for the others to
654 * raise the exception too and then grades them. When any
655 * error is fatal panic. Only then let the others continue.
657 * The other CPUs entering the MCE handler will be controlled by the
658 * Monarch. They are called Subjects.
660 * This way we prevent any potential data corruption in a unrecoverable case
661 * and also makes sure always all CPU's errors are examined.
663 * Also this detects the case of a machine check event coming from outer
664 * space (not detected by any CPUs) In this case some external agent wants
665 * us to shut down, so panic too.
667 * The other CPUs might still decide to panic if the handler happens
668 * in a unrecoverable place, but in this case the system is in a semi-stable
669 * state and won't corrupt anything by itself. It's ok to let the others
670 * continue for a bit first.
672 * All the spin loops have timeouts; when a timeout happens a CPU
673 * typically elects itself to be Monarch.
675 static void mce_reign(void)
678 struct mce
*m
= NULL
;
679 int global_worst
= 0;
684 * This CPU is the Monarch and the other CPUs have run
685 * through their handlers.
686 * Grade the severity of the errors of all the CPUs.
688 for_each_possible_cpu(cpu
) {
689 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
691 if (severity
> global_worst
) {
693 global_worst
= severity
;
694 m
= &per_cpu(mces_seen
, cpu
);
699 * Cannot recover? Panic here then.
700 * This dumps all the mces in the log buffer and stops the
703 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
704 mce_panic("Fatal Machine check", m
, msg
);
707 * For UC somewhere we let the CPU who detects it handle it.
708 * Also must let continue the others, otherwise the handling
709 * CPU could deadlock on a lock.
713 * No machine check event found. Must be some external
714 * source or one CPU is hung. Panic.
716 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
717 mce_panic("Machine check from unknown source", NULL
, NULL
);
720 * Now clear all the mces_seen so that they don't reappear on
723 for_each_possible_cpu(cpu
)
724 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
727 static atomic_t global_nwo
;
730 * Start of Monarch synchronization. This waits until all CPUs have
731 * entered the exception handler and then determines if any of them
732 * saw a fatal event that requires panic. Then it executes them
733 * in the entry order.
734 * TBD double check parallel CPU hotunplug
736 static int mce_start(int *no_way_out
)
739 int cpus
= num_online_cpus();
740 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
745 atomic_add(*no_way_out
, &global_nwo
);
747 * global_nwo should be updated before mce_callin
750 order
= atomic_inc_return(&mce_callin
);
755 while (atomic_read(&mce_callin
) != cpus
) {
756 if (mce_timed_out(&timeout
)) {
757 atomic_set(&global_nwo
, 0);
764 * mce_callin should be read before global_nwo
770 * Monarch: Starts executing now, the others wait.
772 atomic_set(&mce_executing
, 1);
775 * Subject: Now start the scanning loop one by one in
776 * the original callin order.
777 * This way when there are any shared banks it will be
778 * only seen by one CPU before cleared, avoiding duplicates.
780 while (atomic_read(&mce_executing
) < order
) {
781 if (mce_timed_out(&timeout
)) {
782 atomic_set(&global_nwo
, 0);
790 * Cache the global no_way_out state.
792 *no_way_out
= atomic_read(&global_nwo
);
798 * Synchronize between CPUs after main scanning loop.
799 * This invokes the bulk of the Monarch processing.
801 static int mce_end(int order
)
804 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
812 * Allow others to run.
814 atomic_inc(&mce_executing
);
817 /* CHECKME: Can this race with a parallel hotplug? */
818 int cpus
= num_online_cpus();
821 * Monarch: Wait for everyone to go through their scanning
824 while (atomic_read(&mce_executing
) <= cpus
) {
825 if (mce_timed_out(&timeout
))
835 * Subject: Wait for Monarch to finish.
837 while (atomic_read(&mce_executing
) != 0) {
838 if (mce_timed_out(&timeout
))
844 * Don't reset anything. That's done by the Monarch.
850 * Reset all global state.
853 atomic_set(&global_nwo
, 0);
854 atomic_set(&mce_callin
, 0);
858 * Let others run again.
860 atomic_set(&mce_executing
, 0);
865 * Check if the address reported by the CPU is in a format we can parse.
866 * It would be possible to add code for most other cases, but all would
867 * be somewhat complicated (e.g. segment offset would require an instruction
868 * parser). So only support physical addresses upto page granuality for now.
870 static int mce_usable_address(struct mce
*m
)
872 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
874 if ((m
->misc
& 0x3f) > PAGE_SHIFT
)
876 if (((m
->misc
>> 6) & 7) != MCM_ADDR_PHYS
)
881 static void mce_clear_state(unsigned long *toclear
)
885 for (i
= 0; i
< banks
; i
++) {
886 if (test_bit(i
, toclear
))
887 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
892 * The actual machine check handler. This only handles real
893 * exceptions when something got corrupted coming in through int 18.
895 * This is executed in NMI context not subject to normal locking rules. This
896 * implies that most kernel services cannot be safely used. Don't even
897 * think about putting a printk in there!
899 * On Intel systems this is entered on all CPUs in parallel through
900 * MCE broadcast. However some CPUs might be broken beyond repair,
901 * so be always careful when synchronizing with others.
903 void do_machine_check(struct pt_regs
*regs
, long error_code
)
905 struct mce m
, *final
;
910 * Establish sequential order between the CPUs entering the machine
915 * If no_way_out gets set, there is no safe way to recover from this
916 * MCE. If tolerant is cranked up, we'll try anyway.
920 * If kill_it gets set, there might be a way to recover from this
924 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
925 char *msg
= "Unknown";
927 atomic_inc(&mce_entry
);
929 __get_cpu_var(mce_exception_count
)++;
931 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
932 18, SIGKILL
) == NOTIFY_STOP
)
939 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
940 final
= &__get_cpu_var(mces_seen
);
943 no_way_out
= mce_no_way_out(&m
, &msg
);
948 * When no restart IP must always kill or panic.
950 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
954 * Go through all the banks in exclusion of the other CPUs.
955 * This way we don't report duplicated events on shared banks
956 * because the first one to see it will clear it.
958 order
= mce_start(&no_way_out
);
959 for (i
= 0; i
< banks
; i
++) {
960 __clear_bit(i
, toclear
);
961 if (!mce_banks
[i
].ctl
)
968 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
969 if ((m
.status
& MCI_STATUS_VAL
) == 0)
973 * Non uncorrected or non signaled errors are handled by
974 * machine_check_poll. Leave them alone, unless this panics.
976 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
981 * Set taint even when machine check was not enabled.
983 add_taint(TAINT_MACHINE_CHECK
);
985 severity
= mce_severity(&m
, tolerant
, NULL
);
988 * When machine check was for corrected handler don't touch,
989 * unless we're panicing.
991 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
993 __set_bit(i
, toclear
);
994 if (severity
== MCE_NO_SEVERITY
) {
996 * Machine check event was not enabled. Clear, but
1003 * Kill on action required.
1005 if (severity
== MCE_AR_SEVERITY
)
1008 if (m
.status
& MCI_STATUS_MISCV
)
1009 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
1010 if (m
.status
& MCI_STATUS_ADDRV
)
1011 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
1014 * Action optional error. Queue address for later processing.
1015 * When the ring overflows we just ignore the AO error.
1016 * RED-PEN add some logging mechanism when
1017 * usable_address or mce_add_ring fails.
1018 * RED-PEN don't ignore overflow for tolerant == 0
1020 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1021 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1023 mce_get_rip(&m
, regs
);
1026 if (severity
> worst
) {
1033 mce_clear_state(toclear
);
1036 * Do most of the synchronization with other CPUs.
1037 * When there's any problem use only local no_way_out state.
1039 if (mce_end(order
) < 0)
1040 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1043 * If we have decided that we just CAN'T continue, and the user
1044 * has not set tolerant to an insane level, give up and die.
1046 * This is mainly used in the case when the system doesn't
1047 * support MCE broadcasting or it has been disabled.
1049 if (no_way_out
&& tolerant
< 3)
1050 mce_panic("Fatal machine check on current CPU", final
, msg
);
1053 * If the error seems to be unrecoverable, something should be
1054 * done. Try to kill as little as possible. If we can kill just
1055 * one task, do that. If the user has set the tolerance very
1056 * high, don't try to do anything at all.
1059 if (kill_it
&& tolerant
< 3)
1060 force_sig(SIGBUS
, current
);
1062 /* notify userspace ASAP */
1063 set_thread_flag(TIF_MCE_NOTIFY
);
1066 mce_report_event(regs
);
1067 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1069 atomic_dec(&mce_entry
);
1072 EXPORT_SYMBOL_GPL(do_machine_check
);
1074 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1075 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1077 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1081 * Called after mce notification in process context. This code
1082 * is allowed to sleep. Call the high level VM handler to process
1083 * any corrupted pages.
1084 * Assume that the work queue code only calls this one at a time
1086 * Note we don't disable preemption, so this code might run on the wrong
1087 * CPU. In this case the event is picked up by the scheduled work queue.
1088 * This is merely a fast path to expedite processing in some common
1091 void mce_notify_process(void)
1095 while (mce_ring_get(&pfn
))
1096 memory_failure(pfn
, MCE_VECTOR
);
1099 static void mce_process_work(struct work_struct
*dummy
)
1101 mce_notify_process();
1104 #ifdef CONFIG_X86_MCE_INTEL
1106 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1107 * @cpu: The CPU on which the event occurred.
1108 * @status: Event status information
1110 * This function should be called by the thermal interrupt after the
1111 * event has been processed and the decision was made to log the event
1114 * The status parameter will be saved to the 'status' field of 'struct mce'
1115 * and historically has been the register value of the
1116 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1118 void mce_log_therm_throt_event(__u64 status
)
1123 m
.bank
= MCE_THERMAL_BANK
;
1127 #endif /* CONFIG_X86_MCE_INTEL */
1130 * Periodic polling timer for "silent" machine check errors. If the
1131 * poller finds an MCE, poll 2x faster. When the poller finds no more
1132 * errors, poll 2x slower (up to check_interval seconds).
1134 static int check_interval
= 5 * 60; /* 5 minutes */
1136 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1137 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1139 static void mce_start_timer(unsigned long data
)
1141 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1144 WARN_ON(smp_processor_id() != data
);
1146 if (mce_available(¤t_cpu_data
)) {
1147 machine_check_poll(MCP_TIMESTAMP
,
1148 &__get_cpu_var(mce_poll_banks
));
1152 * Alert userspace if needed. If we logged an MCE, reduce the
1153 * polling interval, otherwise increase the polling interval.
1155 n
= &__get_cpu_var(mce_next_interval
);
1156 if (mce_notify_irq())
1157 *n
= max(*n
/2, HZ
/100);
1159 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1161 t
->expires
= jiffies
+ *n
;
1162 add_timer_on(t
, smp_processor_id());
1165 static void mce_do_trigger(struct work_struct
*work
)
1167 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1170 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1173 * Notify the user(s) about new machine check events.
1174 * Can be called from interrupt context, but not from machine check/NMI
1177 int mce_notify_irq(void)
1179 /* Not more than two messages every minute */
1180 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1182 clear_thread_flag(TIF_MCE_NOTIFY
);
1184 if (test_and_clear_bit(0, &mce_need_notify
)) {
1185 wake_up_interruptible(&mce_wait
);
1188 * There is no risk of missing notifications because
1189 * work_pending is always cleared before the function is
1192 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1193 schedule_work(&mce_trigger_work
);
1195 if (__ratelimit(&ratelimit
))
1196 printk(KERN_INFO
"Machine check events logged\n");
1202 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1204 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1208 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1211 for (i
= 0; i
< banks
; i
++) {
1212 struct mce_bank
*b
= &mce_banks
[i
];
1221 * Initialize Machine Checks for a CPU.
1223 static int __cpuinit
__mcheck_cpu_cap_init(void)
1228 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1230 b
= cap
& MCG_BANKCNT_MASK
;
1232 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1234 if (b
> MAX_NR_BANKS
) {
1236 "MCE: Using only %u machine check banks out of %u\n",
1241 /* Don't support asymmetric configurations today */
1242 WARN_ON(banks
!= 0 && b
!= banks
);
1245 int err
= __mcheck_cpu_mce_banks_init();
1251 /* Use accurate RIP reporting if available. */
1252 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1253 rip_msr
= MSR_IA32_MCG_EIP
;
1255 if (cap
& MCG_SER_P
)
1261 static void __mcheck_cpu_init_generic(void)
1263 mce_banks_t all_banks
;
1268 * Log the machine checks left over from the previous reset.
1270 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1271 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1273 set_in_cr4(X86_CR4_MCE
);
1275 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1276 if (cap
& MCG_CTL_P
)
1277 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1279 for (i
= 0; i
< banks
; i
++) {
1280 struct mce_bank
*b
= &mce_banks
[i
];
1284 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1285 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1289 /* Add per CPU specific workarounds here */
1290 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1292 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1293 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1297 /* This should be disabled by the BIOS, but isn't always */
1298 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1299 if (c
->x86
== 15 && banks
> 4) {
1301 * disable GART TBL walk error reporting, which
1302 * trips off incorrectly with the IOMMU & 3ware
1305 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1307 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1309 * Lots of broken BIOS around that don't clear them
1310 * by default and leave crap in there. Don't log:
1315 * Various K7s with broken bank 0 around. Always disable
1318 if (c
->x86
== 6 && banks
> 0)
1319 mce_banks
[0].ctl
= 0;
1322 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1324 * SDM documents that on family 6 bank 0 should not be written
1325 * because it aliases to another special BIOS controlled
1327 * But it's not aliased anymore on model 0x1a+
1328 * Don't ignore bank 0 completely because there could be a
1329 * valid event later, merely don't write CTL0.
1332 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1333 mce_banks
[0].init
= 0;
1336 * All newer Intel systems support MCE broadcasting. Enable
1337 * synchronization with a one second timeout.
1339 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1340 monarch_timeout
< 0)
1341 monarch_timeout
= USEC_PER_SEC
;
1344 * There are also broken BIOSes on some Pentium M and
1347 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1350 if (monarch_timeout
< 0)
1351 monarch_timeout
= 0;
1352 if (mce_bootlog
!= 0)
1353 mce_panic_timeout
= 30;
1358 static void __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1362 switch (c
->x86_vendor
) {
1363 case X86_VENDOR_INTEL
:
1364 intel_p5_mcheck_init(c
);
1366 case X86_VENDOR_CENTAUR
:
1367 winchip_mcheck_init(c
);
1372 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1374 switch (c
->x86_vendor
) {
1375 case X86_VENDOR_INTEL
:
1376 mce_intel_feature_init(c
);
1378 case X86_VENDOR_AMD
:
1379 mce_amd_feature_init(c
);
1386 static void __mcheck_cpu_init_timer(void)
1388 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1389 int *n
= &__get_cpu_var(mce_next_interval
);
1391 setup_timer(t
, mce_start_timer
, smp_processor_id());
1396 *n
= check_interval
* HZ
;
1399 t
->expires
= round_jiffies(jiffies
+ *n
);
1400 add_timer_on(t
, smp_processor_id());
1403 /* Handle unconfigured int18 (should never happen) */
1404 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1406 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1407 smp_processor_id());
1410 /* Call the installed machine check handler for this CPU setup. */
1411 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1412 unexpected_machine_check
;
1415 * Called for each booted CPU to set up machine checks.
1416 * Must be called with preempt off:
1418 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1423 __mcheck_cpu_ancient_init(c
);
1425 if (!mce_available(c
))
1428 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1433 machine_check_vector
= do_machine_check
;
1435 __mcheck_cpu_init_generic();
1436 __mcheck_cpu_init_vendor(c
);
1437 __mcheck_cpu_init_timer();
1438 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1443 * Character device to read and clear the MCE log.
1446 static DEFINE_SPINLOCK(mce_state_lock
);
1447 static int open_count
; /* #times opened */
1448 static int open_exclu
; /* already open exclusive? */
1450 static int mce_open(struct inode
*inode
, struct file
*file
)
1452 spin_lock(&mce_state_lock
);
1454 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
1455 spin_unlock(&mce_state_lock
);
1460 if (file
->f_flags
& O_EXCL
)
1464 spin_unlock(&mce_state_lock
);
1466 return nonseekable_open(inode
, file
);
1469 static int mce_release(struct inode
*inode
, struct file
*file
)
1471 spin_lock(&mce_state_lock
);
1476 spin_unlock(&mce_state_lock
);
1481 static void collect_tscs(void *data
)
1483 unsigned long *cpu_tsc
= (unsigned long *)data
;
1485 rdtscll(cpu_tsc
[smp_processor_id()]);
1488 static DEFINE_MUTEX(mce_read_mutex
);
1490 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
1493 char __user
*buf
= ubuf
;
1494 unsigned long *cpu_tsc
;
1495 unsigned prev
, next
;
1498 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1502 mutex_lock(&mce_read_mutex
);
1503 next
= rcu_dereference(mcelog
.next
);
1505 /* Only supports full reads right now */
1506 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
1507 mutex_unlock(&mce_read_mutex
);
1516 for (i
= prev
; i
< next
; i
++) {
1517 unsigned long start
= jiffies
;
1519 while (!mcelog
.entry
[i
].finished
) {
1520 if (time_after_eq(jiffies
, start
+ 2)) {
1521 memset(mcelog
.entry
+ i
, 0,
1522 sizeof(struct mce
));
1528 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
1529 sizeof(struct mce
));
1530 buf
+= sizeof(struct mce
);
1535 memset(mcelog
.entry
+ prev
, 0,
1536 (next
- prev
) * sizeof(struct mce
));
1538 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1539 } while (next
!= prev
);
1541 synchronize_sched();
1544 * Collect entries that were still getting written before the
1547 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1549 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1550 if (mcelog
.entry
[i
].finished
&&
1551 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1552 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1553 sizeof(struct mce
));
1555 buf
+= sizeof(struct mce
);
1556 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1559 mutex_unlock(&mce_read_mutex
);
1562 return err
? -EFAULT
: buf
- ubuf
;
1565 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1567 poll_wait(file
, &mce_wait
, wait
);
1568 if (rcu_dereference(mcelog
.next
))
1569 return POLLIN
| POLLRDNORM
;
1573 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1575 int __user
*p
= (int __user
*)arg
;
1577 if (!capable(CAP_SYS_ADMIN
))
1581 case MCE_GET_RECORD_LEN
:
1582 return put_user(sizeof(struct mce
), p
);
1583 case MCE_GET_LOG_LEN
:
1584 return put_user(MCE_LOG_LEN
, p
);
1585 case MCE_GETCLEAR_FLAGS
: {
1589 flags
= mcelog
.flags
;
1590 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1592 return put_user(flags
, p
);
1599 /* Modified in mce-inject.c, so not static or const */
1600 struct file_operations mce_chrdev_ops
= {
1602 .release
= mce_release
,
1605 .unlocked_ioctl
= mce_ioctl
,
1607 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1609 static struct miscdevice mce_log_device
= {
1616 * mce=off Disables machine check
1617 * mce=no_cmci Disables CMCI
1618 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1619 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1620 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1621 * monarchtimeout is how long to wait for other CPUs on machine
1622 * check, or 0 to not wait
1623 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1624 * mce=nobootlog Don't log MCEs from before booting.
1626 static int __init
mcheck_enable(char *str
)
1634 if (!strcmp(str
, "off"))
1636 else if (!strcmp(str
, "no_cmci"))
1637 mce_cmci_disabled
= 1;
1638 else if (!strcmp(str
, "dont_log_ce"))
1639 mce_dont_log_ce
= 1;
1640 else if (!strcmp(str
, "ignore_ce"))
1642 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1643 mce_bootlog
= (str
[0] == 'b');
1644 else if (isdigit(str
[0])) {
1645 get_option(&str
, &tolerant
);
1648 get_option(&str
, &monarch_timeout
);
1651 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1657 __setup("mce", mcheck_enable
);
1659 int __init
mcheck_init(void)
1661 atomic_notifier_chain_register(&x86_mce_decoder_chain
, &mce_dec_nb
);
1663 mcheck_intel_therm_init();
1673 * Disable machine checks on suspend and shutdown. We can't really handle
1676 static int mce_disable_error_reporting(void)
1680 for (i
= 0; i
< banks
; i
++) {
1681 struct mce_bank
*b
= &mce_banks
[i
];
1684 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1689 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1691 return mce_disable_error_reporting();
1694 static int mce_shutdown(struct sys_device
*dev
)
1696 return mce_disable_error_reporting();
1700 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1701 * Only one CPU is active at this time, the others get re-added later using
1704 static int mce_resume(struct sys_device
*dev
)
1706 __mcheck_cpu_init_generic();
1707 __mcheck_cpu_init_vendor(¤t_cpu_data
);
1712 static void mce_cpu_restart(void *data
)
1714 del_timer_sync(&__get_cpu_var(mce_timer
));
1715 if (!mce_available(¤t_cpu_data
))
1717 __mcheck_cpu_init_generic();
1718 __mcheck_cpu_init_timer();
1721 /* Reinit MCEs after user configuration changes */
1722 static void mce_restart(void)
1724 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1727 /* Toggle features for corrected errors */
1728 static void mce_disable_ce(void *all
)
1730 if (!mce_available(¤t_cpu_data
))
1733 del_timer_sync(&__get_cpu_var(mce_timer
));
1737 static void mce_enable_ce(void *all
)
1739 if (!mce_available(¤t_cpu_data
))
1744 __mcheck_cpu_init_timer();
1747 static struct sysdev_class mce_sysclass
= {
1748 .suspend
= mce_suspend
,
1749 .shutdown
= mce_shutdown
,
1750 .resume
= mce_resume
,
1751 .name
= "machinecheck",
1754 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1757 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1759 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1761 return container_of(attr
, struct mce_bank
, attr
);
1764 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1767 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1770 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1771 const char *buf
, size_t size
)
1775 if (strict_strtoull(buf
, 0, &new) < 0)
1778 attr_to_bank(attr
)->ctl
= new;
1785 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1787 strcpy(buf
, mce_helper
);
1789 return strlen(mce_helper
) + 1;
1792 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1793 const char *buf
, size_t siz
)
1797 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1798 mce_helper
[sizeof(mce_helper
)-1] = 0;
1799 p
= strchr(mce_helper
, '\n');
1804 return strlen(mce_helper
) + !!p
;
1807 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1808 struct sysdev_attribute
*attr
,
1809 const char *buf
, size_t size
)
1813 if (strict_strtoull(buf
, 0, &new) < 0)
1816 if (mce_ignore_ce
^ !!new) {
1818 /* disable ce features */
1819 on_each_cpu(mce_disable_ce
, (void *)1, 1);
1822 /* enable ce features */
1824 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1830 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1831 struct sysdev_attribute
*attr
,
1832 const char *buf
, size_t size
)
1836 if (strict_strtoull(buf
, 0, &new) < 0)
1839 if (mce_cmci_disabled
^ !!new) {
1842 on_each_cpu(mce_disable_ce
, NULL
, 1);
1843 mce_cmci_disabled
= 1;
1846 mce_cmci_disabled
= 0;
1847 on_each_cpu(mce_enable_ce
, NULL
, 1);
1853 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1854 struct sysdev_attribute
*attr
,
1855 const char *buf
, size_t size
)
1857 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1862 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1863 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1864 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1865 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1867 static struct sysdev_ext_attribute attr_check_interval
= {
1868 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1869 store_int_with_restart
),
1873 static struct sysdev_ext_attribute attr_ignore_ce
= {
1874 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1878 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1879 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1883 static struct sysdev_attribute
*mce_attrs
[] = {
1884 &attr_tolerant
.attr
,
1885 &attr_check_interval
.attr
,
1887 &attr_monarch_timeout
.attr
,
1888 &attr_dont_log_ce
.attr
,
1889 &attr_ignore_ce
.attr
,
1890 &attr_cmci_disabled
.attr
,
1894 static cpumask_var_t mce_dev_initialized
;
1896 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1897 static __cpuinit
int mce_create_device(unsigned int cpu
)
1902 if (!mce_available(&boot_cpu_data
))
1905 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1906 per_cpu(mce_dev
, cpu
).id
= cpu
;
1907 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1909 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1913 for (i
= 0; mce_attrs
[i
]; i
++) {
1914 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1918 for (j
= 0; j
< banks
; j
++) {
1919 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1920 &mce_banks
[j
].attr
);
1924 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1929 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[j
].attr
);
1932 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1934 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1939 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1943 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1946 for (i
= 0; mce_attrs
[i
]; i
++)
1947 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1949 for (i
= 0; i
< banks
; i
++)
1950 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[i
].attr
);
1952 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1953 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1956 /* Make sure there are no machine checks on offlined CPUs. */
1957 static void __cpuinit
mce_disable_cpu(void *h
)
1959 unsigned long action
= *(unsigned long *)h
;
1962 if (!mce_available(¤t_cpu_data
))
1965 if (!(action
& CPU_TASKS_FROZEN
))
1967 for (i
= 0; i
< banks
; i
++) {
1968 struct mce_bank
*b
= &mce_banks
[i
];
1971 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1975 static void __cpuinit
mce_reenable_cpu(void *h
)
1977 unsigned long action
= *(unsigned long *)h
;
1980 if (!mce_available(¤t_cpu_data
))
1983 if (!(action
& CPU_TASKS_FROZEN
))
1985 for (i
= 0; i
< banks
; i
++) {
1986 struct mce_bank
*b
= &mce_banks
[i
];
1989 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1993 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1994 static int __cpuinit
1995 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1997 unsigned int cpu
= (unsigned long)hcpu
;
1998 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2002 case CPU_ONLINE_FROZEN
:
2003 mce_create_device(cpu
);
2004 if (threshold_cpu_callback
)
2005 threshold_cpu_callback(action
, cpu
);
2008 case CPU_DEAD_FROZEN
:
2009 if (threshold_cpu_callback
)
2010 threshold_cpu_callback(action
, cpu
);
2011 mce_remove_device(cpu
);
2013 case CPU_DOWN_PREPARE
:
2014 case CPU_DOWN_PREPARE_FROZEN
:
2016 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2018 case CPU_DOWN_FAILED
:
2019 case CPU_DOWN_FAILED_FROZEN
:
2020 if (!mce_ignore_ce
&& check_interval
) {
2021 t
->expires
= round_jiffies(jiffies
+
2022 __get_cpu_var(mce_next_interval
));
2023 add_timer_on(t
, cpu
);
2025 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2028 /* intentionally ignoring frozen here */
2029 cmci_rediscover(cpu
);
2035 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2036 .notifier_call
= mce_cpu_callback
,
2039 static __init
void mce_init_banks(void)
2043 for (i
= 0; i
< banks
; i
++) {
2044 struct mce_bank
*b
= &mce_banks
[i
];
2045 struct sysdev_attribute
*a
= &b
->attr
;
2047 a
->attr
.name
= b
->attrname
;
2048 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2050 a
->attr
.mode
= 0644;
2051 a
->show
= show_bank
;
2052 a
->store
= set_bank
;
2056 static __init
int mcheck_init_device(void)
2061 if (!mce_available(&boot_cpu_data
))
2064 zalloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
2068 err
= sysdev_class_register(&mce_sysclass
);
2072 for_each_online_cpu(i
) {
2073 err
= mce_create_device(i
);
2078 register_hotcpu_notifier(&mce_cpu_notifier
);
2079 misc_register(&mce_log_device
);
2084 device_initcall(mcheck_init_device
);
2087 * Old style boot options parsing. Only for compatibility.
2089 static int __init
mcheck_disable(char *str
)
2094 __setup("nomce", mcheck_disable
);
2096 #ifdef CONFIG_DEBUG_FS
2097 struct dentry
*mce_get_debugfs_dir(void)
2099 static struct dentry
*dmce
;
2102 dmce
= debugfs_create_dir("mce", NULL
);
2107 static void mce_reset(void)
2110 atomic_set(&mce_fake_paniced
, 0);
2111 atomic_set(&mce_executing
, 0);
2112 atomic_set(&mce_callin
, 0);
2113 atomic_set(&global_nwo
, 0);
2116 static int fake_panic_get(void *data
, u64
*val
)
2122 static int fake_panic_set(void *data
, u64 val
)
2129 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2130 fake_panic_set
, "%llu\n");
2132 static int __init
mcheck_debugfs_init(void)
2134 struct dentry
*dmce
, *ffake_panic
;
2136 dmce
= mce_get_debugfs_dir();
2139 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2146 late_initcall(mcheck_debugfs_init
);