2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/init.h>
30 #include <linux/kmod.h>
31 #include <linux/poll.h>
32 #include <linux/nmi.h>
33 #include <linux/cpu.h>
34 #include <linux/smp.h>
37 #include <asm/processor.h>
38 #include <asm/hw_irq.h>
45 #include "mce-internal.h"
48 /* Handle unconfigured int18 (should never happen) */
49 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
51 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
55 /* Call the installed machine check handler for this CPU setup. */
56 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
57 unexpected_machine_check
;
61 #ifdef CONFIG_X86_NEW_MCE
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count
);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant
= 1;
81 static unsigned long notify_user
;
83 static int mce_bootlog
= -1;
84 static int monarch_timeout
= -1;
85 static int mce_panic_timeout
;
87 static char trigger
[128];
88 static char *trigger_argv
[2] = { trigger
, NULL
};
90 static unsigned long dont_init_banks
;
92 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
93 static DEFINE_PER_CPU(struct mce
, mces_seen
);
94 static int cpu_missing
;
97 /* MCA banks polled by the period polling timer for corrected events */
98 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
99 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
102 static inline int skip_bank_init(int i
)
104 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
107 /* Do initial initialization of a struct mce */
108 void mce_setup(struct mce
*m
)
110 memset(m
, 0, sizeof(struct mce
));
111 m
->cpu
= m
->extcpu
= smp_processor_id();
113 /* We hope get_seconds stays lockless */
114 m
->time
= get_seconds();
115 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
116 m
->cpuid
= cpuid_eax(1);
118 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
120 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
121 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
124 DEFINE_PER_CPU(struct mce
, injectm
);
125 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
128 * Lockless MCE logging infrastructure.
129 * This avoids deadlocks on printk locks without having to break locks. Also
130 * separate MCEs from kernel messages to avoid bogus bug reports.
133 static struct mce_log mcelog
= {
134 .signature
= MCE_LOG_SIGNATURE
,
136 .recordlen
= sizeof(struct mce
),
139 void mce_log(struct mce
*mce
)
141 unsigned next
, entry
;
146 entry
= rcu_dereference(mcelog
.next
);
149 * When the buffer fills up discard new entries.
150 * Assume that the earlier errors are the more
153 if (entry
>= MCE_LOG_LEN
) {
154 set_bit(MCE_OVERFLOW
,
155 (unsigned long *)&mcelog
.flags
);
158 /* Old left over entry. Skip: */
159 if (mcelog
.entry
[entry
].finished
) {
167 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
170 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
172 mcelog
.entry
[entry
].finished
= 1;
176 set_bit(0, ¬ify_user
);
179 static void print_mce(struct mce
*m
, int *first
)
182 printk(KERN_EMERG
"\n" KERN_EMERG
"HARDWARE ERROR\n");
186 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
187 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
189 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
190 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
192 if (m
->cs
== __KERNEL_CS
)
193 print_symbol("{%s}", m
->ip
);
196 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
198 printk("ADDR %llx ", m
->addr
);
200 printk("MISC %llx ", m
->misc
);
202 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
203 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
207 static void print_mce_tail(void)
209 printk(KERN_EMERG
"This is not a software problem!\n"
210 KERN_EMERG
"Run through mcelog --ascii to decode and contact your hardware vendor\n");
213 #define PANIC_TIMEOUT 5 /* 5 seconds */
215 static atomic_t mce_paniced
;
217 /* Panic in progress. Enable interrupts and wait for final IPI */
218 static void wait_for_panic(void)
220 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
223 while (timeout
-- > 0)
225 if (panic_timeout
== 0)
226 panic_timeout
= mce_panic_timeout
;
227 panic("Panicing machine check CPU died");
230 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
236 * Make sure only one CPU runs in machine check panic
238 if (atomic_add_return(1, &mce_paniced
) > 1)
244 /* First print corrected ones that are still unlogged */
245 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
246 struct mce
*m
= &mcelog
.entry
[i
];
247 if ((m
->status
& MCI_STATUS_VAL
) &&
248 !(m
->status
& MCI_STATUS_UC
))
249 print_mce(m
, &first
);
251 /* Now print uncorrected but with the final one last */
252 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
253 struct mce
*m
= &mcelog
.entry
[i
];
254 if (!(m
->status
& MCI_STATUS_VAL
))
256 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
257 print_mce(m
, &first
);
260 print_mce(final
, &first
);
262 printk(KERN_EMERG
"Some CPUs didn't answer in synchronization\n");
265 printk(KERN_EMERG
"Machine check: %s\n", exp
);
266 if (panic_timeout
== 0)
267 panic_timeout
= mce_panic_timeout
;
271 /* Support code for software error injection */
273 static int msr_to_offset(u32 msr
)
275 unsigned bank
= __get_cpu_var(injectm
.bank
);
277 return offsetof(struct mce
, ip
);
278 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
279 return offsetof(struct mce
, status
);
280 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
281 return offsetof(struct mce
, addr
);
282 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
283 return offsetof(struct mce
, misc
);
284 if (msr
== MSR_IA32_MCG_STATUS
)
285 return offsetof(struct mce
, mcgstatus
);
289 /* MSR access wrappers used for error injection */
290 static u64
mce_rdmsrl(u32 msr
)
293 if (__get_cpu_var(injectm
).finished
) {
294 int offset
= msr_to_offset(msr
);
297 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
303 static void mce_wrmsrl(u32 msr
, u64 v
)
305 if (__get_cpu_var(injectm
).finished
) {
306 int offset
= msr_to_offset(msr
);
308 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
314 int mce_available(struct cpuinfo_x86
*c
)
318 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
322 * Get the address of the instruction at the time of the machine check
325 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
328 if (regs
&& (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
))) {
336 m
->ip
= mce_rdmsrl(rip_msr
);
339 #ifdef CONFIG_X86_LOCAL_APIC
341 * Called after interrupts have been reenabled again
342 * when a MCE happened during an interrupts off region
345 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
355 static void mce_report_event(struct pt_regs
*regs
)
357 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
362 #ifdef CONFIG_X86_LOCAL_APIC
364 * Without APIC do not notify. The event will be picked
371 * When interrupts are disabled we cannot use
372 * kernel services safely. Trigger an self interrupt
373 * through the APIC to instead do the notification
374 * after interrupts are reenabled again.
376 apic
->send_IPI_self(MCE_SELF_VECTOR
);
379 * Wait for idle afterwards again so that we don't leave the
380 * APIC in a non idle state because the normal APIC writes
383 apic_wait_icr_idle();
387 DEFINE_PER_CPU(unsigned, mce_poll_count
);
390 * Poll for corrected events or events that happened before reset.
391 * Those are just logged through /dev/mcelog.
393 * This is executed in standard interrupt context.
395 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
400 __get_cpu_var(mce_poll_count
)++;
404 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
405 for (i
= 0; i
< banks
; i
++) {
406 if (!bank
[i
] || !test_bit(i
, *b
))
415 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
416 if (!(m
.status
& MCI_STATUS_VAL
))
420 * Uncorrected events are handled by the exception handler
421 * when it is enabled. But when the exception is disabled log
424 * TBD do the same check for MCI_STATUS_EN here?
426 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
429 if (m
.status
& MCI_STATUS_MISCV
)
430 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
431 if (m
.status
& MCI_STATUS_ADDRV
)
432 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
434 if (!(flags
& MCP_TIMESTAMP
))
437 * Don't get the IP here because it's unlikely to
438 * have anything to do with the actual error location.
440 if (!(flags
& MCP_DONTLOG
)) {
442 add_taint(TAINT_MACHINE_CHECK
);
446 * Clear state for this bank.
448 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
452 * Don't clear MCG_STATUS here because it's only defined for
458 EXPORT_SYMBOL_GPL(machine_check_poll
);
461 * Do a quick check if any of the events requires a panic.
462 * This decides if we keep the events around or clear them.
464 static int mce_no_way_out(struct mce
*m
, char **msg
)
468 for (i
= 0; i
< banks
; i
++) {
469 m
->status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
470 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
477 * Variable to establish order between CPUs while scanning.
478 * Each CPU spins initially until executing is equal its number.
480 static atomic_t mce_executing
;
483 * Defines order of CPUs on entry. First CPU becomes Monarch.
485 static atomic_t mce_callin
;
488 * Check if a timeout waiting for other CPUs happened.
490 static int mce_timed_out(u64
*t
)
493 * The others already did panic for some reason.
494 * Bail out like in a timeout.
495 * rmb() to tell the compiler that system_state
496 * might have been modified by someone else.
499 if (atomic_read(&mce_paniced
))
501 if (!monarch_timeout
)
503 if ((s64
)*t
< SPINUNIT
) {
504 /* CHECKME: Make panic default for 1 too? */
506 mce_panic("Timeout synchronizing machine check over CPUs",
513 touch_nmi_watchdog();
518 * The Monarch's reign. The Monarch is the CPU who entered
519 * the machine check handler first. It waits for the others to
520 * raise the exception too and then grades them. When any
521 * error is fatal panic. Only then let the others continue.
523 * The other CPUs entering the MCE handler will be controlled by the
524 * Monarch. They are called Subjects.
526 * This way we prevent any potential data corruption in a unrecoverable case
527 * and also makes sure always all CPU's errors are examined.
529 * Also this detects the case of an machine check event coming from outer
530 * space (not detected by any CPUs) In this case some external agent wants
531 * us to shut down, so panic too.
533 * The other CPUs might still decide to panic if the handler happens
534 * in a unrecoverable place, but in this case the system is in a semi-stable
535 * state and won't corrupt anything by itself. It's ok to let the others
536 * continue for a bit first.
538 * All the spin loops have timeouts; when a timeout happens a CPU
539 * typically elects itself to be Monarch.
541 static void mce_reign(void)
544 struct mce
*m
= NULL
;
545 int global_worst
= 0;
550 * This CPU is the Monarch and the other CPUs have run
551 * through their handlers.
552 * Grade the severity of the errors of all the CPUs.
554 for_each_possible_cpu(cpu
) {
555 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
557 if (severity
> global_worst
) {
559 global_worst
= severity
;
560 m
= &per_cpu(mces_seen
, cpu
);
565 * Cannot recover? Panic here then.
566 * This dumps all the mces in the log buffer and stops the
569 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
570 mce_panic("Fatal Machine check", m
, msg
);
573 * For UC somewhere we let the CPU who detects it handle it.
574 * Also must let continue the others, otherwise the handling
575 * CPU could deadlock on a lock.
579 * No machine check event found. Must be some external
580 * source or one CPU is hung. Panic.
582 if (!m
&& tolerant
< 3)
583 mce_panic("Machine check from unknown source", NULL
, NULL
);
586 * Now clear all the mces_seen so that they don't reappear on
589 for_each_possible_cpu(cpu
)
590 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
593 static atomic_t global_nwo
;
596 * Start of Monarch synchronization. This waits until all CPUs have
597 * entered the exception handler and then determines if any of them
598 * saw a fatal event that requires panic. Then it executes them
599 * in the entry order.
600 * TBD double check parallel CPU hotunplug
602 static int mce_start(int no_way_out
, int *order
)
605 int cpus
= num_online_cpus();
606 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
613 atomic_add(no_way_out
, &global_nwo
);
618 while (atomic_read(&mce_callin
) != cpus
) {
619 if (mce_timed_out(&timeout
)) {
620 atomic_set(&global_nwo
, 0);
628 * Cache the global no_way_out state.
630 nwo
= atomic_read(&global_nwo
);
633 * Monarch starts executing now, the others wait.
636 atomic_set(&mce_executing
, 1);
641 * Now start the scanning loop one by one
642 * in the original callin order.
643 * This way when there are any shared banks it will
644 * be only seen by one CPU before cleared, avoiding duplicates.
646 while (atomic_read(&mce_executing
) < *order
) {
647 if (mce_timed_out(&timeout
)) {
648 atomic_set(&global_nwo
, 0);
658 * Synchronize between CPUs after main scanning loop.
659 * This invokes the bulk of the Monarch processing.
661 static int mce_end(int order
)
664 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
672 * Allow others to run.
674 atomic_inc(&mce_executing
);
677 /* CHECKME: Can this race with a parallel hotplug? */
678 int cpus
= num_online_cpus();
681 * Monarch: Wait for everyone to go through their scanning
684 while (atomic_read(&mce_executing
) <= cpus
) {
685 if (mce_timed_out(&timeout
))
695 * Subject: Wait for Monarch to finish.
697 while (atomic_read(&mce_executing
) != 0) {
698 if (mce_timed_out(&timeout
))
704 * Don't reset anything. That's done by the Monarch.
710 * Reset all global state.
713 atomic_set(&global_nwo
, 0);
714 atomic_set(&mce_callin
, 0);
718 * Let others run again.
720 atomic_set(&mce_executing
, 0);
724 static void mce_clear_state(unsigned long *toclear
)
728 for (i
= 0; i
< banks
; i
++) {
729 if (test_bit(i
, toclear
))
730 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
735 * The actual machine check handler. This only handles real
736 * exceptions when something got corrupted coming in through int 18.
738 * This is executed in NMI context not subject to normal locking rules. This
739 * implies that most kernel services cannot be safely used. Don't even
740 * think about putting a printk in there!
742 * On Intel systems this is entered on all CPUs in parallel through
743 * MCE broadcast. However some CPUs might be broken beyond repair,
744 * so be always careful when synchronizing with others.
746 void do_machine_check(struct pt_regs
*regs
, long error_code
)
748 struct mce m
, *final
;
753 * Establish sequential order between the CPUs entering the machine
759 * If no_way_out gets set, there is no safe way to recover from this
760 * MCE. If tolerant is cranked up, we'll try anyway.
764 * If kill_it gets set, there might be a way to recover from this
768 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
769 char *msg
= "Unknown";
771 atomic_inc(&mce_entry
);
773 __get_cpu_var(mce_exception_count
)++;
775 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
776 18, SIGKILL
) == NOTIFY_STOP
)
781 order
= atomic_add_return(1, &mce_callin
);
784 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
785 no_way_out
= mce_no_way_out(&m
, &msg
);
787 final
= &__get_cpu_var(mces_seen
);
793 * Go through all the banks in exclusion of the other CPUs.
794 * This way we don't report duplicated events on shared banks
795 * because the first one to see it will clear it.
797 no_way_out
= mce_start(no_way_out
, &order
);
798 for (i
= 0; i
< banks
; i
++) {
799 __clear_bit(i
, toclear
);
807 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
808 if ((m
.status
& MCI_STATUS_VAL
) == 0)
812 * Non uncorrected errors are handled by machine_check_poll
813 * Leave them alone, unless this panics.
815 if ((m
.status
& MCI_STATUS_UC
) == 0 && !no_way_out
)
819 * Set taint even when machine check was not enabled.
821 add_taint(TAINT_MACHINE_CHECK
);
823 __set_bit(i
, toclear
);
825 if (m
.status
& MCI_STATUS_EN
) {
827 * If this error was uncorrectable and there was
828 * an overflow, we're in trouble. If no overflow,
829 * we might get away with just killing a task.
831 if (m
.status
& MCI_STATUS_UC
)
835 * Machine check event was not enabled. Clear, but
841 if (m
.status
& MCI_STATUS_MISCV
)
842 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
843 if (m
.status
& MCI_STATUS_ADDRV
)
844 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
846 mce_get_rip(&m
, regs
);
849 severity
= mce_severity(&m
, tolerant
, NULL
);
850 if (severity
> worst
) {
857 mce_clear_state(toclear
);
860 * Do most of the synchronization with other CPUs.
861 * When there's any problem use only local no_way_out state.
863 if (mce_end(order
) < 0)
864 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
867 * If we have decided that we just CAN'T continue, and the user
868 * has not set tolerant to an insane level, give up and die.
870 * This is mainly used in the case when the system doesn't
871 * support MCE broadcasting or it has been disabled.
873 if (no_way_out
&& tolerant
< 3)
874 mce_panic("Fatal machine check on current CPU", final
, msg
);
877 * If the error seems to be unrecoverable, something should be
878 * done. Try to kill as little as possible. If we can kill just
879 * one task, do that. If the user has set the tolerance very
880 * high, don't try to do anything at all.
882 if (kill_it
&& tolerant
< 3) {
886 * If the EIPV bit is set, it means the saved IP is the
887 * instruction which caused the MCE.
889 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
890 user_space
= final
->ip
&& (final
->cs
& 3);
893 * If we know that the error was in user space, send a
894 * SIGBUS. Otherwise, panic if tolerance is low.
896 * force_sig() takes an awful lot of locks and has a slight
897 * risk of deadlocking.
900 force_sig(SIGBUS
, current
);
901 } else if (panic_on_oops
|| tolerant
< 2) {
902 mce_panic("Uncorrected machine check", final
, msg
);
906 /* notify userspace ASAP */
907 set_thread_flag(TIF_MCE_NOTIFY
);
910 mce_report_event(regs
);
911 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
913 atomic_dec(&mce_entry
);
916 EXPORT_SYMBOL_GPL(do_machine_check
);
918 #ifdef CONFIG_X86_MCE_INTEL
920 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
921 * @cpu: The CPU on which the event occurred.
922 * @status: Event status information
924 * This function should be called by the thermal interrupt after the
925 * event has been processed and the decision was made to log the event
928 * The status parameter will be saved to the 'status' field of 'struct mce'
929 * and historically has been the register value of the
930 * MSR_IA32_THERMAL_STATUS (Intel) msr.
932 void mce_log_therm_throt_event(__u64 status
)
937 m
.bank
= MCE_THERMAL_BANK
;
941 #endif /* CONFIG_X86_MCE_INTEL */
944 * Periodic polling timer for "silent" machine check errors. If the
945 * poller finds an MCE, poll 2x faster. When the poller finds no more
946 * errors, poll 2x slower (up to check_interval seconds).
948 static int check_interval
= 5 * 60; /* 5 minutes */
950 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
951 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
953 static void mcheck_timer(unsigned long data
)
955 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
958 WARN_ON(smp_processor_id() != data
);
960 if (mce_available(¤t_cpu_data
)) {
961 machine_check_poll(MCP_TIMESTAMP
,
962 &__get_cpu_var(mce_poll_banks
));
966 * Alert userspace if needed. If we logged an MCE, reduce the
967 * polling interval, otherwise increase the polling interval.
969 n
= &__get_cpu_var(next_interval
);
970 if (mce_notify_user())
971 *n
= max(*n
/2, HZ
/100);
973 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
975 t
->expires
= jiffies
+ *n
;
979 static void mce_do_trigger(struct work_struct
*work
)
981 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
984 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
987 * Notify the user(s) about new machine check events.
988 * Can be called from interrupt context, but not from machine check/NMI
991 int mce_notify_user(void)
993 /* Not more than two messages every minute */
994 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
996 clear_thread_flag(TIF_MCE_NOTIFY
);
998 if (test_and_clear_bit(0, ¬ify_user
)) {
999 wake_up_interruptible(&mce_wait
);
1002 * There is no risk of missing notifications because
1003 * work_pending is always cleared before the function is
1006 if (trigger
[0] && !work_pending(&mce_trigger_work
))
1007 schedule_work(&mce_trigger_work
);
1009 if (__ratelimit(&ratelimit
))
1010 printk(KERN_INFO
"Machine check events logged\n");
1016 EXPORT_SYMBOL_GPL(mce_notify_user
);
1019 * Initialize Machine Checks for a CPU.
1021 static int mce_cap_init(void)
1026 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1028 b
= cap
& MCG_BANKCNT_MASK
;
1029 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1031 if (b
> MAX_NR_BANKS
) {
1033 "MCE: Using only %u machine check banks out of %u\n",
1038 /* Don't support asymmetric configurations today */
1039 WARN_ON(banks
!= 0 && b
!= banks
);
1042 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
1045 memset(bank
, 0xff, banks
* sizeof(u64
));
1048 /* Use accurate RIP reporting if available. */
1049 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1050 rip_msr
= MSR_IA32_MCG_EIP
;
1055 static void mce_init(void)
1057 mce_banks_t all_banks
;
1062 * Log the machine checks left over from the previous reset.
1064 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1065 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1067 set_in_cr4(X86_CR4_MCE
);
1069 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1070 if (cap
& MCG_CTL_P
)
1071 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1073 for (i
= 0; i
< banks
; i
++) {
1074 if (skip_bank_init(i
))
1076 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
1077 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
1081 /* Add per CPU specific workarounds here */
1082 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
1084 /* This should be disabled by the BIOS, but isn't always */
1085 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1086 if (c
->x86
== 15 && banks
> 4) {
1088 * disable GART TBL walk error reporting, which
1089 * trips off incorrectly with the IOMMU & 3ware
1092 clear_bit(10, (unsigned long *)&bank
[4]);
1094 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1096 * Lots of broken BIOS around that don't clear them
1097 * by default and leave crap in there. Don't log:
1102 * Various K7s with broken bank 0 around. Always disable
1109 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1111 * SDM documents that on family 6 bank 0 should not be written
1112 * because it aliases to another special BIOS controlled
1114 * But it's not aliased anymore on model 0x1a+
1115 * Don't ignore bank 0 completely because there could be a
1116 * valid event later, merely don't write CTL0.
1119 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
1120 __set_bit(0, &dont_init_banks
);
1123 * All newer Intel systems support MCE broadcasting. Enable
1124 * synchronization with a one second timeout.
1126 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1127 monarch_timeout
< 0)
1128 monarch_timeout
= USEC_PER_SEC
;
1130 if (monarch_timeout
< 0)
1131 monarch_timeout
= 0;
1132 if (mce_bootlog
!= 0)
1133 mce_panic_timeout
= 30;
1136 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
1140 switch (c
->x86_vendor
) {
1141 case X86_VENDOR_INTEL
:
1142 if (mce_p5_enabled())
1143 intel_p5_mcheck_init(c
);
1145 case X86_VENDOR_CENTAUR
:
1146 winchip_mcheck_init(c
);
1151 static void mce_cpu_features(struct cpuinfo_x86
*c
)
1153 switch (c
->x86_vendor
) {
1154 case X86_VENDOR_INTEL
:
1155 mce_intel_feature_init(c
);
1157 case X86_VENDOR_AMD
:
1158 mce_amd_feature_init(c
);
1165 static void mce_init_timer(void)
1167 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1168 int *n
= &__get_cpu_var(next_interval
);
1170 *n
= check_interval
* HZ
;
1173 setup_timer(t
, mcheck_timer
, smp_processor_id());
1174 t
->expires
= round_jiffies(jiffies
+ *n
);
1179 * Called for each booted CPU to set up machine checks.
1180 * Must be called with preempt off:
1182 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
1187 mce_ancient_init(c
);
1189 if (!mce_available(c
))
1192 if (mce_cap_init() < 0) {
1198 machine_check_vector
= do_machine_check
;
1201 mce_cpu_features(c
);
1206 * Character device to read and clear the MCE log.
1209 static DEFINE_SPINLOCK(mce_state_lock
);
1210 static int open_count
; /* #times opened */
1211 static int open_exclu
; /* already open exclusive? */
1213 static int mce_open(struct inode
*inode
, struct file
*file
)
1215 spin_lock(&mce_state_lock
);
1217 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
1218 spin_unlock(&mce_state_lock
);
1223 if (file
->f_flags
& O_EXCL
)
1227 spin_unlock(&mce_state_lock
);
1229 return nonseekable_open(inode
, file
);
1232 static int mce_release(struct inode
*inode
, struct file
*file
)
1234 spin_lock(&mce_state_lock
);
1239 spin_unlock(&mce_state_lock
);
1244 static void collect_tscs(void *data
)
1246 unsigned long *cpu_tsc
= (unsigned long *)data
;
1248 rdtscll(cpu_tsc
[smp_processor_id()]);
1251 static DEFINE_MUTEX(mce_read_mutex
);
1253 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
1256 char __user
*buf
= ubuf
;
1257 unsigned long *cpu_tsc
;
1258 unsigned prev
, next
;
1261 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1265 mutex_lock(&mce_read_mutex
);
1266 next
= rcu_dereference(mcelog
.next
);
1268 /* Only supports full reads right now */
1269 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
1270 mutex_unlock(&mce_read_mutex
);
1279 for (i
= prev
; i
< next
; i
++) {
1280 unsigned long start
= jiffies
;
1282 while (!mcelog
.entry
[i
].finished
) {
1283 if (time_after_eq(jiffies
, start
+ 2)) {
1284 memset(mcelog
.entry
+ i
, 0,
1285 sizeof(struct mce
));
1291 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
1292 sizeof(struct mce
));
1293 buf
+= sizeof(struct mce
);
1298 memset(mcelog
.entry
+ prev
, 0,
1299 (next
- prev
) * sizeof(struct mce
));
1301 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1302 } while (next
!= prev
);
1304 synchronize_sched();
1307 * Collect entries that were still getting written before the
1310 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1312 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1313 if (mcelog
.entry
[i
].finished
&&
1314 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1315 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1316 sizeof(struct mce
));
1318 buf
+= sizeof(struct mce
);
1319 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1322 mutex_unlock(&mce_read_mutex
);
1325 return err
? -EFAULT
: buf
- ubuf
;
1328 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1330 poll_wait(file
, &mce_wait
, wait
);
1331 if (rcu_dereference(mcelog
.next
))
1332 return POLLIN
| POLLRDNORM
;
1336 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1338 int __user
*p
= (int __user
*)arg
;
1340 if (!capable(CAP_SYS_ADMIN
))
1344 case MCE_GET_RECORD_LEN
:
1345 return put_user(sizeof(struct mce
), p
);
1346 case MCE_GET_LOG_LEN
:
1347 return put_user(MCE_LOG_LEN
, p
);
1348 case MCE_GETCLEAR_FLAGS
: {
1352 flags
= mcelog
.flags
;
1353 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1355 return put_user(flags
, p
);
1362 /* Modified in mce-inject.c, so not static or const */
1363 struct file_operations mce_chrdev_ops
= {
1365 .release
= mce_release
,
1368 .unlocked_ioctl
= mce_ioctl
,
1370 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1372 static struct miscdevice mce_log_device
= {
1379 * mce=off disables machine check
1380 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1381 * monarchtimeout is how long to wait for other CPUs on machine
1382 * check, or 0 to not wait
1383 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1384 * mce=nobootlog Don't log MCEs from before booting.
1386 static int __init
mcheck_enable(char *str
)
1392 if (!strcmp(str
, "off"))
1394 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1395 mce_bootlog
= (str
[0] == 'b');
1396 else if (isdigit(str
[0])) {
1397 get_option(&str
, &tolerant
);
1400 get_option(&str
, &monarch_timeout
);
1403 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1409 __setup("mce", mcheck_enable
);
1416 * Disable machine checks on suspend and shutdown. We can't really handle
1419 static int mce_disable(void)
1423 for (i
= 0; i
< banks
; i
++) {
1424 if (!skip_bank_init(i
))
1425 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1430 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1432 return mce_disable();
1435 static int mce_shutdown(struct sys_device
*dev
)
1437 return mce_disable();
1441 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1442 * Only one CPU is active at this time, the others get re-added later using
1445 static int mce_resume(struct sys_device
*dev
)
1448 mce_cpu_features(¤t_cpu_data
);
1453 static void mce_cpu_restart(void *data
)
1455 del_timer_sync(&__get_cpu_var(mce_timer
));
1456 if (mce_available(¤t_cpu_data
))
1461 /* Reinit MCEs after user configuration changes */
1462 static void mce_restart(void)
1464 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1467 static struct sysdev_class mce_sysclass
= {
1468 .suspend
= mce_suspend
,
1469 .shutdown
= mce_shutdown
,
1470 .resume
= mce_resume
,
1471 .name
= "machinecheck",
1474 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1477 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1479 static struct sysdev_attribute
*bank_attrs
;
1481 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1484 u64 b
= bank
[attr
- bank_attrs
];
1486 return sprintf(buf
, "%llx\n", b
);
1489 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1490 const char *buf
, size_t size
)
1494 if (strict_strtoull(buf
, 0, &new) < 0)
1497 bank
[attr
- bank_attrs
] = new;
1504 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1506 strcpy(buf
, trigger
);
1508 return strlen(trigger
) + 1;
1511 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1512 const char *buf
, size_t siz
)
1517 strncpy(trigger
, buf
, sizeof(trigger
));
1518 trigger
[sizeof(trigger
)-1] = 0;
1519 len
= strlen(trigger
);
1520 p
= strchr(trigger
, '\n');
1528 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1529 struct sysdev_attribute
*attr
,
1530 const char *buf
, size_t size
)
1532 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1537 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1538 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1539 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1541 static struct sysdev_ext_attribute attr_check_interval
= {
1542 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1543 store_int_with_restart
),
1547 static struct sysdev_attribute
*mce_attrs
[] = {
1548 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1549 &attr_monarch_timeout
.attr
,
1553 static cpumask_var_t mce_dev_initialized
;
1555 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1556 static __cpuinit
int mce_create_device(unsigned int cpu
)
1561 if (!mce_available(&boot_cpu_data
))
1564 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1565 per_cpu(mce_dev
, cpu
).id
= cpu
;
1566 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1568 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1572 for (i
= 0; mce_attrs
[i
]; i
++) {
1573 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1577 for (i
= 0; i
< banks
; i
++) {
1578 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1583 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1588 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1591 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1593 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1598 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1602 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1605 for (i
= 0; mce_attrs
[i
]; i
++)
1606 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1608 for (i
= 0; i
< banks
; i
++)
1609 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1611 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1612 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1615 /* Make sure there are no machine checks on offlined CPUs. */
1616 static void mce_disable_cpu(void *h
)
1618 unsigned long action
= *(unsigned long *)h
;
1621 if (!mce_available(¤t_cpu_data
))
1623 if (!(action
& CPU_TASKS_FROZEN
))
1625 for (i
= 0; i
< banks
; i
++) {
1626 if (!skip_bank_init(i
))
1627 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1631 static void mce_reenable_cpu(void *h
)
1633 unsigned long action
= *(unsigned long *)h
;
1636 if (!mce_available(¤t_cpu_data
))
1639 if (!(action
& CPU_TASKS_FROZEN
))
1641 for (i
= 0; i
< banks
; i
++) {
1642 if (!skip_bank_init(i
))
1643 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1647 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1648 static int __cpuinit
1649 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1651 unsigned int cpu
= (unsigned long)hcpu
;
1652 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1656 case CPU_ONLINE_FROZEN
:
1657 mce_create_device(cpu
);
1658 if (threshold_cpu_callback
)
1659 threshold_cpu_callback(action
, cpu
);
1662 case CPU_DEAD_FROZEN
:
1663 if (threshold_cpu_callback
)
1664 threshold_cpu_callback(action
, cpu
);
1665 mce_remove_device(cpu
);
1667 case CPU_DOWN_PREPARE
:
1668 case CPU_DOWN_PREPARE_FROZEN
:
1670 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1672 case CPU_DOWN_FAILED
:
1673 case CPU_DOWN_FAILED_FROZEN
:
1674 t
->expires
= round_jiffies(jiffies
+
1675 __get_cpu_var(next_interval
));
1676 add_timer_on(t
, cpu
);
1677 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1680 /* intentionally ignoring frozen here */
1681 cmci_rediscover(cpu
);
1687 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1688 .notifier_call
= mce_cpu_callback
,
1691 static __init
int mce_init_banks(void)
1695 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1700 for (i
= 0; i
< banks
; i
++) {
1701 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1703 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1707 a
->attr
.mode
= 0644;
1708 a
->show
= show_bank
;
1709 a
->store
= set_bank
;
1715 kfree(bank_attrs
[i
].attr
.name
);
1722 static __init
int mce_init_device(void)
1727 if (!mce_available(&boot_cpu_data
))
1730 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1732 err
= mce_init_banks();
1736 err
= sysdev_class_register(&mce_sysclass
);
1740 for_each_online_cpu(i
) {
1741 err
= mce_create_device(i
);
1746 register_hotcpu_notifier(&mce_cpu_notifier
);
1747 misc_register(&mce_log_device
);
1752 device_initcall(mce_init_device
);
1754 #else /* CONFIG_X86_OLD_MCE: */
1757 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1759 /* This has to be run for each processor */
1760 void mcheck_init(struct cpuinfo_x86
*c
)
1762 if (mce_disabled
== 1)
1765 switch (c
->x86_vendor
) {
1766 case X86_VENDOR_AMD
:
1770 case X86_VENDOR_INTEL
:
1772 intel_p5_mcheck_init(c
);
1774 intel_p6_mcheck_init(c
);
1776 intel_p4_mcheck_init(c
);
1779 case X86_VENDOR_CENTAUR
:
1781 winchip_mcheck_init(c
);
1787 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1790 static int __init
mcheck_enable(char *str
)
1796 __setup("mce", mcheck_enable
);
1798 #endif /* CONFIG_X86_OLD_MCE */
1801 * Old style boot options parsing. Only for compatibility.
1803 static int __init
mcheck_disable(char *str
)
1808 __setup("nomce", mcheck_disable
);