2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/errno.h>
21 #include <linux/sched.h>
22 #include <linux/sysfs.h>
23 #include <linux/slab.h>
24 #include <linux/init.h>
25 #include <linux/cpu.h>
26 #include <linux/smp.h>
28 #include <asm/amd_nb.h>
36 #define THRESHOLD_MAX 0xFFF
37 #define INT_TYPE_APIC 0x00020000
38 #define MASK_VALID_HI 0x80000000
39 #define MASK_CNTP_HI 0x40000000
40 #define MASK_LOCKED_HI 0x20000000
41 #define MASK_LVTOFF_HI 0x00F00000
42 #define MASK_COUNT_EN_HI 0x00080000
43 #define MASK_INT_TYPE_HI 0x00060000
44 #define MASK_OVERFLOW_HI 0x00010000
45 #define MASK_ERR_COUNT_HI 0x00000FFF
46 #define MASK_BLKPTR_LO 0xFF000000
47 #define MCG_XBLK_ADDR 0xC0000400
49 static DEFINE_PER_CPU(struct threshold_bank
* [NR_BANKS
], threshold_banks
);
51 static unsigned char shared_bank
[NR_BANKS
] = {
55 static DEFINE_PER_CPU(unsigned char, bank_map
); /* see which banks are on */
57 static void amd_threshold_interrupt(void);
63 struct thresh_restart
{
64 struct threshold_block
*b
;
71 static bool lvt_interrupt_supported(unsigned int bank
, u32 msr_high_bits
)
74 * bank 4 supports APIC LVT interrupts implicitly since forever.
80 * IntP: interrupt present; if this bit is set, the thresholding
81 * bank can generate APIC LVT interrupts
83 return msr_high_bits
& BIT(28);
86 static int lvt_off_valid(struct threshold_block
*b
, int apic
, u32 lo
, u32 hi
)
88 int msr
= (hi
& MASK_LVTOFF_HI
) >> 20;
91 pr_err(FW_BUG
"cpu %d, failed to setup threshold interrupt "
92 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b
->cpu
,
93 b
->bank
, b
->block
, b
->address
, hi
, lo
);
98 pr_err(FW_BUG
"cpu %d, invalid threshold interrupt offset %d "
99 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
100 b
->cpu
, apic
, b
->bank
, b
->block
, b
->address
, hi
, lo
);
108 * Called via smp_call_function_single(), must be called with correct
111 static void threshold_restart_bank(void *_tr
)
113 struct thresh_restart
*tr
= _tr
;
116 rdmsr(tr
->b
->address
, lo
, hi
);
118 if (tr
->b
->threshold_limit
< (hi
& THRESHOLD_MAX
))
119 tr
->reset
= 1; /* limit cannot be lower than err count */
121 if (tr
->reset
) { /* reset err count and overflow bit */
123 (hi
& ~(MASK_ERR_COUNT_HI
| MASK_OVERFLOW_HI
)) |
124 (THRESHOLD_MAX
- tr
->b
->threshold_limit
);
125 } else if (tr
->old_limit
) { /* change limit w/o reset */
126 int new_count
= (hi
& THRESHOLD_MAX
) +
127 (tr
->old_limit
- tr
->b
->threshold_limit
);
129 hi
= (hi
& ~MASK_ERR_COUNT_HI
) |
130 (new_count
& THRESHOLD_MAX
);
134 hi
&= ~MASK_INT_TYPE_HI
;
136 if (!tr
->b
->interrupt_capable
)
139 if (tr
->set_lvt_off
) {
140 if (lvt_off_valid(tr
->b
, tr
->lvt_off
, lo
, hi
)) {
141 /* set new lvt offset */
142 hi
&= ~MASK_LVTOFF_HI
;
143 hi
|= tr
->lvt_off
<< 20;
147 if (tr
->b
->interrupt_enable
)
152 hi
|= MASK_COUNT_EN_HI
;
153 wrmsr(tr
->b
->address
, lo
, hi
);
156 static void mce_threshold_block_init(struct threshold_block
*b
, int offset
)
158 struct thresh_restart tr
= {
164 b
->threshold_limit
= THRESHOLD_MAX
;
165 threshold_restart_bank(&tr
);
168 static int setup_APIC_mce(int reserved
, int new)
170 if (reserved
< 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR
,
171 APIC_EILVT_MSG_FIX
, 0))
177 /* cpu init entry point, called from mce.c with preempt off */
178 void mce_amd_feature_init(struct cpuinfo_x86
*c
)
180 struct threshold_block b
;
181 unsigned int cpu
= smp_processor_id();
182 u32 low
= 0, high
= 0, address
= 0;
183 unsigned int bank
, block
;
186 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
187 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
189 address
= MSR_IA32_MC0_MISC
+ bank
* 4;
190 else if (block
== 1) {
191 address
= (low
& MASK_BLKPTR_LO
) >> 21;
195 address
+= MCG_XBLK_ADDR
;
199 if (rdmsr_safe(address
, &low
, &high
))
202 if (!(high
& MASK_VALID_HI
))
205 if (!(high
& MASK_CNTP_HI
) ||
206 (high
& MASK_LOCKED_HI
))
210 per_cpu(bank_map
, cpu
) |= (1 << bank
);
212 memset(&b
, 0, sizeof(b
));
217 b
.interrupt_capable
= lvt_interrupt_supported(bank
, high
);
219 if (b
.interrupt_capable
) {
220 int new = (high
& MASK_LVTOFF_HI
) >> 20;
221 offset
= setup_APIC_mce(offset
, new);
224 mce_threshold_block_init(&b
, offset
);
225 mce_threshold_vector
= amd_threshold_interrupt
;
231 * APIC Interrupt Handler
235 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
236 * the interrupt goes off when error_count reaches threshold_limit.
237 * the handler will simply log mcelog w/ software defined bank number.
239 static void amd_threshold_interrupt(void)
241 u32 low
= 0, high
= 0, address
= 0;
242 unsigned int bank
, block
;
247 /* assume first bank caused it */
248 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
249 if (!(per_cpu(bank_map
, m
.cpu
) & (1 << bank
)))
251 for (block
= 0; block
< NR_BLOCKS
; ++block
) {
253 address
= MSR_IA32_MC0_MISC
+ bank
* 4;
254 } else if (block
== 1) {
255 address
= (low
& MASK_BLKPTR_LO
) >> 21;
258 address
+= MCG_XBLK_ADDR
;
263 if (rdmsr_safe(address
, &low
, &high
))
266 if (!(high
& MASK_VALID_HI
)) {
273 if (!(high
& MASK_CNTP_HI
) ||
274 (high
& MASK_LOCKED_HI
))
278 * Log the machine check that caused the threshold
281 machine_check_poll(MCP_TIMESTAMP
,
282 &__get_cpu_var(mce_poll_banks
));
284 if (high
& MASK_OVERFLOW_HI
) {
285 rdmsrl(address
, m
.misc
);
286 rdmsrl(MSR_IA32_MC0_STATUS
+ bank
* 4,
288 m
.bank
= K8_MCE_THRESHOLD_BASE
302 struct threshold_attr
{
303 struct attribute attr
;
304 ssize_t (*show
) (struct threshold_block
*, char *);
305 ssize_t (*store
) (struct threshold_block
*, const char *, size_t count
);
308 #define SHOW_FIELDS(name) \
309 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
311 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
313 SHOW_FIELDS(interrupt_enable
)
314 SHOW_FIELDS(threshold_limit
)
317 store_interrupt_enable(struct threshold_block
*b
, const char *buf
, size_t size
)
319 struct thresh_restart tr
;
322 if (!b
->interrupt_capable
)
325 if (strict_strtoul(buf
, 0, &new) < 0)
328 b
->interrupt_enable
= !!new;
330 memset(&tr
, 0, sizeof(tr
));
333 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
339 store_threshold_limit(struct threshold_block
*b
, const char *buf
, size_t size
)
341 struct thresh_restart tr
;
344 if (strict_strtoul(buf
, 0, &new) < 0)
347 if (new > THRESHOLD_MAX
)
352 memset(&tr
, 0, sizeof(tr
));
353 tr
.old_limit
= b
->threshold_limit
;
354 b
->threshold_limit
= new;
357 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
362 struct threshold_block_cross_cpu
{
363 struct threshold_block
*tb
;
367 static void local_error_count_handler(void *_tbcc
)
369 struct threshold_block_cross_cpu
*tbcc
= _tbcc
;
370 struct threshold_block
*b
= tbcc
->tb
;
373 rdmsr(b
->address
, low
, high
);
374 tbcc
->retval
= (high
& 0xFFF) - (THRESHOLD_MAX
- b
->threshold_limit
);
377 static ssize_t
show_error_count(struct threshold_block
*b
, char *buf
)
379 struct threshold_block_cross_cpu tbcc
= { .tb
= b
, };
381 smp_call_function_single(b
->cpu
, local_error_count_handler
, &tbcc
, 1);
382 return sprintf(buf
, "%lu\n", tbcc
.retval
);
385 static ssize_t
store_error_count(struct threshold_block
*b
,
386 const char *buf
, size_t count
)
388 struct thresh_restart tr
= { .b
= b
, .reset
= 1, .old_limit
= 0 };
390 smp_call_function_single(b
->cpu
, threshold_restart_bank
, &tr
, 1);
394 #define RW_ATTR(val) \
395 static struct threshold_attr val = { \
396 .attr = {.name = __stringify(val), .mode = 0644 }, \
397 .show = show_## val, \
398 .store = store_## val, \
401 RW_ATTR(interrupt_enable
);
402 RW_ATTR(threshold_limit
);
403 RW_ATTR(error_count
);
405 static struct attribute
*default_attrs
[] = {
406 &threshold_limit
.attr
,
408 NULL
, /* possibly interrupt_enable if supported, see below */
412 #define to_block(k) container_of(k, struct threshold_block, kobj)
413 #define to_attr(a) container_of(a, struct threshold_attr, attr)
415 static ssize_t
show(struct kobject
*kobj
, struct attribute
*attr
, char *buf
)
417 struct threshold_block
*b
= to_block(kobj
);
418 struct threshold_attr
*a
= to_attr(attr
);
421 ret
= a
->show
? a
->show(b
, buf
) : -EIO
;
426 static ssize_t
store(struct kobject
*kobj
, struct attribute
*attr
,
427 const char *buf
, size_t count
)
429 struct threshold_block
*b
= to_block(kobj
);
430 struct threshold_attr
*a
= to_attr(attr
);
433 ret
= a
->store
? a
->store(b
, buf
, count
) : -EIO
;
438 static const struct sysfs_ops threshold_ops
= {
443 static struct kobj_type threshold_ktype
= {
444 .sysfs_ops
= &threshold_ops
,
445 .default_attrs
= default_attrs
,
448 static __cpuinit
int allocate_threshold_blocks(unsigned int cpu
,
453 struct threshold_block
*b
= NULL
;
457 if ((bank
>= NR_BANKS
) || (block
>= NR_BLOCKS
))
460 if (rdmsr_safe_on_cpu(cpu
, address
, &low
, &high
))
463 if (!(high
& MASK_VALID_HI
)) {
470 if (!(high
& MASK_CNTP_HI
) ||
471 (high
& MASK_LOCKED_HI
))
474 b
= kzalloc(sizeof(struct threshold_block
), GFP_KERNEL
);
481 b
->address
= address
;
482 b
->interrupt_enable
= 0;
483 b
->interrupt_capable
= lvt_interrupt_supported(bank
, high
);
484 b
->threshold_limit
= THRESHOLD_MAX
;
486 if (b
->interrupt_capable
)
487 threshold_ktype
.default_attrs
[2] = &interrupt_enable
.attr
;
489 threshold_ktype
.default_attrs
[2] = NULL
;
491 INIT_LIST_HEAD(&b
->miscj
);
493 if (per_cpu(threshold_banks
, cpu
)[bank
]->blocks
) {
495 &per_cpu(threshold_banks
, cpu
)[bank
]->blocks
->miscj
);
497 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= b
;
500 err
= kobject_init_and_add(&b
->kobj
, &threshold_ktype
,
501 per_cpu(threshold_banks
, cpu
)[bank
]->kobj
,
507 address
= (low
& MASK_BLKPTR_LO
) >> 21;
510 address
+= MCG_XBLK_ADDR
;
515 err
= allocate_threshold_blocks(cpu
, bank
, ++block
, address
);
520 kobject_uevent(&b
->kobj
, KOBJ_ADD
);
526 kobject_put(&b
->kobj
);
533 static __cpuinit
int __threshold_add_blocks(struct threshold_bank
*b
)
535 struct list_head
*head
= &b
->blocks
->miscj
;
536 struct threshold_block
*pos
= NULL
;
537 struct threshold_block
*tmp
= NULL
;
540 err
= kobject_add(&b
->blocks
->kobj
, b
->kobj
, b
->blocks
->kobj
.name
);
544 list_for_each_entry_safe(pos
, tmp
, head
, miscj
) {
546 err
= kobject_add(&pos
->kobj
, b
->kobj
, pos
->kobj
.name
);
548 list_for_each_entry_safe_reverse(pos
, tmp
, head
, miscj
)
549 kobject_del(&pos
->kobj
);
557 static __cpuinit
int threshold_create_bank(unsigned int cpu
, unsigned int bank
)
559 struct device
*dev
= per_cpu(mce_device
, cpu
);
560 struct amd_northbridge
*nb
= NULL
;
561 struct threshold_bank
*b
= NULL
;
565 sprintf(name
, "threshold_bank%i", bank
);
567 if (shared_bank
[bank
]) {
569 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
572 /* threshold descriptor already initialized on this node? */
576 err
= kobject_add(b
->kobj
, &dev
->kobj
, name
);
580 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
581 atomic_inc(&b
->cpus
);
583 err
= __threshold_add_blocks(b
);
589 b
= kzalloc(sizeof(struct threshold_bank
), GFP_KERNEL
);
595 b
->kobj
= kobject_create_and_add(name
, &dev
->kobj
);
601 per_cpu(threshold_banks
, cpu
)[bank
] = b
;
603 if (shared_bank
[bank
]) {
604 atomic_set(&b
->cpus
, 1);
606 /* nb is already initialized, see above */
611 err
= allocate_threshold_blocks(cpu
, bank
, 0,
612 MSR_IA32_MC0_MISC
+ bank
* 4);
623 /* create dir/files for all valid threshold banks */
624 static __cpuinit
int threshold_create_device(unsigned int cpu
)
629 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
630 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
632 err
= threshold_create_bank(cpu
, bank
);
640 static void deallocate_threshold_block(unsigned int cpu
,
643 struct threshold_block
*pos
= NULL
;
644 struct threshold_block
*tmp
= NULL
;
645 struct threshold_bank
*head
= per_cpu(threshold_banks
, cpu
)[bank
];
650 list_for_each_entry_safe(pos
, tmp
, &head
->blocks
->miscj
, miscj
) {
651 kobject_put(&pos
->kobj
);
652 list_del(&pos
->miscj
);
656 kfree(per_cpu(threshold_banks
, cpu
)[bank
]->blocks
);
657 per_cpu(threshold_banks
, cpu
)[bank
]->blocks
= NULL
;
660 static void __threshold_remove_blocks(struct threshold_bank
*b
)
662 struct threshold_block
*pos
= NULL
;
663 struct threshold_block
*tmp
= NULL
;
665 kobject_del(b
->kobj
);
667 list_for_each_entry_safe(pos
, tmp
, &b
->blocks
->miscj
, miscj
)
668 kobject_del(&pos
->kobj
);
671 static void threshold_remove_bank(unsigned int cpu
, int bank
)
673 struct amd_northbridge
*nb
;
674 struct threshold_bank
*b
;
676 b
= per_cpu(threshold_banks
, cpu
)[bank
];
683 if (shared_bank
[bank
]) {
684 if (!atomic_dec_and_test(&b
->cpus
)) {
685 __threshold_remove_blocks(b
);
686 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
690 * the last CPU on this node using the shared bank is
691 * going away, remove that bank now.
693 nb
= node_to_amd_nb(amd_get_nb_id(cpu
));
698 deallocate_threshold_block(cpu
, bank
);
701 kobject_del(b
->kobj
);
702 kobject_put(b
->kobj
);
704 per_cpu(threshold_banks
, cpu
)[bank
] = NULL
;
707 static void threshold_remove_device(unsigned int cpu
)
711 for (bank
= 0; bank
< NR_BANKS
; ++bank
) {
712 if (!(per_cpu(bank_map
, cpu
) & (1 << bank
)))
714 threshold_remove_bank(cpu
, bank
);
718 /* get notified when a cpu comes on/off */
719 static void __cpuinit
720 amd_64_threshold_cpu_callback(unsigned long action
, unsigned int cpu
)
724 case CPU_ONLINE_FROZEN
:
725 threshold_create_device(cpu
);
728 case CPU_DEAD_FROZEN
:
729 threshold_remove_device(cpu
);
736 static __init
int threshold_init_device(void)
740 /* to hit CPUs online before the notifier is up */
741 for_each_online_cpu(lcpu
) {
742 int err
= threshold_create_device(lcpu
);
747 threshold_cpu_callback
= amd_64_threshold_cpu_callback
;
751 device_initcall(threshold_init_device
);