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perf_counter: x86: fixup nmi_watchdog vs perf_counter boo-boo
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_counter.c
1 /*
2 * Performance counter x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 *
10 * For licencing details see kernel-base/COPYING
11 */
12
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22
23 #include <asm/apic.h>
24 #include <asm/stacktrace.h>
25 #include <asm/nmi.h>
26
27 static u64 perf_counter_mask __read_mostly;
28
29 struct cpu_hw_counters {
30 struct perf_counter *counters[X86_PMC_IDX_MAX];
31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33 unsigned long interrupts;
34 u64 throttle_ctrl;
35 int enabled;
36 };
37
38 /*
39 * struct x86_pmu - generic x86 pmu
40 */
41 struct x86_pmu {
42 const char *name;
43 int version;
44 int (*handle_irq)(struct pt_regs *, int);
45 u64 (*save_disable_all)(void);
46 void (*restore_all)(u64);
47 void (*enable)(struct hw_perf_counter *, int);
48 void (*disable)(struct hw_perf_counter *, int);
49 unsigned eventsel;
50 unsigned perfctr;
51 u64 (*event_map)(int);
52 u64 (*raw_event)(u64);
53 int max_events;
54 int num_counters;
55 int num_counters_fixed;
56 int counter_bits;
57 u64 counter_mask;
58 u64 max_period;
59 };
60
61 static struct x86_pmu x86_pmu __read_mostly;
62
63 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
64 .enabled = 1,
65 };
66
67 /*
68 * Intel PerfMon v3. Used on Core2 and later.
69 */
70 static const u64 intel_perfmon_event_map[] =
71 {
72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
79 };
80
81 static u64 intel_pmu_event_map(int event)
82 {
83 return intel_perfmon_event_map[event];
84 }
85
86 static u64 intel_pmu_raw_event(u64 event)
87 {
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
91
92 #define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK)
96
97 return event & CORE_EVNTSEL_MASK;
98 }
99
100 /*
101 * AMD Performance Monitor K7 and later.
102 */
103 static const u64 amd_perfmon_event_map[] =
104 {
105 [PERF_COUNT_CPU_CYCLES] = 0x0076,
106 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
107 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
108 [PERF_COUNT_CACHE_MISSES] = 0x0081,
109 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
110 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
111 };
112
113 static u64 amd_pmu_event_map(int event)
114 {
115 return amd_perfmon_event_map[event];
116 }
117
118 static u64 amd_pmu_raw_event(u64 event)
119 {
120 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
122 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
123
124 #define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \
127 K7_EVNTSEL_COUNTER_MASK)
128
129 return event & K7_EVNTSEL_MASK;
130 }
131
132 /*
133 * Propagate counter elapsed time into the generic counter.
134 * Can only be executed on the CPU where the counter is active.
135 * Returns the delta events processed.
136 */
137 static u64
138 x86_perf_counter_update(struct perf_counter *counter,
139 struct hw_perf_counter *hwc, int idx)
140 {
141 u64 prev_raw_count, new_raw_count, delta;
142
143 /*
144 * Careful: an NMI might modify the previous counter value.
145 *
146 * Our tactic to handle this is to first atomically read and
147 * exchange a new raw count - then add that new-prev delta
148 * count to the generic counter atomically:
149 */
150 again:
151 prev_raw_count = atomic64_read(&hwc->prev_count);
152 rdmsrl(hwc->counter_base + idx, new_raw_count);
153
154 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
155 new_raw_count) != prev_raw_count)
156 goto again;
157
158 /*
159 * Now we have the new raw value and have updated the prev
160 * timestamp already. We can now calculate the elapsed delta
161 * (counter-)time and add that to the generic counter.
162 *
163 * Careful, not all hw sign-extends above the physical width
164 * of the count, so we do that by clipping the delta to 32 bits:
165 */
166 delta = (u64)(u32)((s32)new_raw_count - (s32)prev_raw_count);
167
168 atomic64_add(delta, &counter->count);
169 atomic64_sub(delta, &hwc->period_left);
170
171 return new_raw_count;
172 }
173
174 static atomic_t active_counters;
175 static DEFINE_MUTEX(pmc_reserve_mutex);
176
177 static bool reserve_pmc_hardware(void)
178 {
179 int i;
180
181 if (nmi_watchdog == NMI_LOCAL_APIC)
182 disable_lapic_nmi_watchdog();
183
184 for (i = 0; i < x86_pmu.num_counters; i++) {
185 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
186 goto perfctr_fail;
187 }
188
189 for (i = 0; i < x86_pmu.num_counters; i++) {
190 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
191 goto eventsel_fail;
192 }
193
194 return true;
195
196 eventsel_fail:
197 for (i--; i >= 0; i--)
198 release_evntsel_nmi(x86_pmu.eventsel + i);
199
200 i = x86_pmu.num_counters;
201
202 perfctr_fail:
203 for (i--; i >= 0; i--)
204 release_perfctr_nmi(x86_pmu.perfctr + i);
205
206 if (nmi_watchdog == NMI_LOCAL_APIC)
207 enable_lapic_nmi_watchdog();
208
209 return false;
210 }
211
212 static void release_pmc_hardware(void)
213 {
214 int i;
215
216 for (i = 0; i < x86_pmu.num_counters; i++) {
217 release_perfctr_nmi(x86_pmu.perfctr + i);
218 release_evntsel_nmi(x86_pmu.eventsel + i);
219 }
220
221 if (nmi_watchdog == NMI_LOCAL_APIC)
222 enable_lapic_nmi_watchdog();
223 }
224
225 static void hw_perf_counter_destroy(struct perf_counter *counter)
226 {
227 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
228 release_pmc_hardware();
229 mutex_unlock(&pmc_reserve_mutex);
230 }
231 }
232
233 static inline int x86_pmu_initialized(void)
234 {
235 return x86_pmu.handle_irq != NULL;
236 }
237
238 /*
239 * Setup the hardware configuration for a given hw_event_type
240 */
241 static int __hw_perf_counter_init(struct perf_counter *counter)
242 {
243 struct perf_counter_hw_event *hw_event = &counter->hw_event;
244 struct hw_perf_counter *hwc = &counter->hw;
245 int err;
246
247 if (!x86_pmu_initialized())
248 return -ENODEV;
249
250 err = 0;
251 if (!atomic_inc_not_zero(&active_counters)) {
252 mutex_lock(&pmc_reserve_mutex);
253 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
254 err = -EBUSY;
255 else
256 atomic_inc(&active_counters);
257 mutex_unlock(&pmc_reserve_mutex);
258 }
259 if (err)
260 return err;
261
262 /*
263 * Generate PMC IRQs:
264 * (keep 'enabled' bit clear for now)
265 */
266 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
267
268 /*
269 * Count user and OS events unless requested not to.
270 */
271 if (!hw_event->exclude_user)
272 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
273 if (!hw_event->exclude_kernel)
274 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
275
276 /*
277 * If privileged enough, allow NMI events:
278 */
279 hwc->nmi = 0;
280 if (capable(CAP_SYS_ADMIN) && hw_event->nmi)
281 hwc->nmi = 1;
282
283 hwc->irq_period = hw_event->irq_period;
284 if ((s64)hwc->irq_period <= 0 || hwc->irq_period > x86_pmu.max_period)
285 hwc->irq_period = x86_pmu.max_period;
286
287 atomic64_set(&hwc->period_left, hwc->irq_period);
288
289 /*
290 * Raw event type provide the config in the event structure
291 */
292 if (perf_event_raw(hw_event)) {
293 hwc->config |= x86_pmu.raw_event(perf_event_config(hw_event));
294 } else {
295 if (perf_event_id(hw_event) >= x86_pmu.max_events)
296 return -EINVAL;
297 /*
298 * The generic map:
299 */
300 hwc->config |= x86_pmu.event_map(perf_event_id(hw_event));
301 }
302
303 counter->destroy = hw_perf_counter_destroy;
304
305 return 0;
306 }
307
308 static u64 intel_pmu_save_disable_all(void)
309 {
310 u64 ctrl;
311
312 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
314
315 return ctrl;
316 }
317
318 static u64 amd_pmu_save_disable_all(void)
319 {
320 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
321 int enabled, idx;
322
323 enabled = cpuc->enabled;
324 cpuc->enabled = 0;
325 /*
326 * ensure we write the disable before we start disabling the
327 * counters proper, so that amd_pmu_enable_counter() does the
328 * right thing.
329 */
330 barrier();
331
332 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
333 u64 val;
334
335 if (!test_bit(idx, cpuc->active_mask))
336 continue;
337 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
338 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
339 continue;
340 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
341 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
342 }
343
344 return enabled;
345 }
346
347 u64 hw_perf_save_disable(void)
348 {
349 if (!x86_pmu_initialized())
350 return 0;
351 return x86_pmu.save_disable_all();
352 }
353 /*
354 * Exported because of ACPI idle
355 */
356 EXPORT_SYMBOL_GPL(hw_perf_save_disable);
357
358 static void intel_pmu_restore_all(u64 ctrl)
359 {
360 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
361 }
362
363 static void amd_pmu_restore_all(u64 ctrl)
364 {
365 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
366 int idx;
367
368 cpuc->enabled = ctrl;
369 barrier();
370 if (!ctrl)
371 return;
372
373 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
374 u64 val;
375
376 if (!test_bit(idx, cpuc->active_mask))
377 continue;
378 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
379 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
380 continue;
381 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
382 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
383 }
384 }
385
386 void hw_perf_restore(u64 ctrl)
387 {
388 if (!x86_pmu_initialized())
389 return;
390 x86_pmu.restore_all(ctrl);
391 }
392 /*
393 * Exported because of ACPI idle
394 */
395 EXPORT_SYMBOL_GPL(hw_perf_restore);
396
397 static inline u64 intel_pmu_get_status(void)
398 {
399 u64 status;
400
401 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
402
403 return status;
404 }
405
406 static inline void intel_pmu_ack_status(u64 ack)
407 {
408 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
409 }
410
411 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
412 {
413 int err;
414 err = checking_wrmsrl(hwc->config_base + idx,
415 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
416 }
417
418 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
419 {
420 int err;
421 err = checking_wrmsrl(hwc->config_base + idx,
422 hwc->config);
423 }
424
425 static inline void
426 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
427 {
428 int idx = __idx - X86_PMC_IDX_FIXED;
429 u64 ctrl_val, mask;
430 int err;
431
432 mask = 0xfULL << (idx * 4);
433
434 rdmsrl(hwc->config_base, ctrl_val);
435 ctrl_val &= ~mask;
436 err = checking_wrmsrl(hwc->config_base, ctrl_val);
437 }
438
439 static inline void
440 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
441 {
442 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
443 intel_pmu_disable_fixed(hwc, idx);
444 return;
445 }
446
447 x86_pmu_disable_counter(hwc, idx);
448 }
449
450 static inline void
451 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
452 {
453 x86_pmu_disable_counter(hwc, idx);
454 }
455
456 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
457
458 /*
459 * Set the next IRQ period, based on the hwc->period_left value.
460 * To be called with the counter disabled in hw:
461 */
462 static void
463 x86_perf_counter_set_period(struct perf_counter *counter,
464 struct hw_perf_counter *hwc, int idx)
465 {
466 s64 left = atomic64_read(&hwc->period_left);
467 s64 period = hwc->irq_period;
468 int err;
469
470 /*
471 * If we are way outside a reasoable range then just skip forward:
472 */
473 if (unlikely(left <= -period)) {
474 left = period;
475 atomic64_set(&hwc->period_left, left);
476 }
477
478 if (unlikely(left <= 0)) {
479 left += period;
480 atomic64_set(&hwc->period_left, left);
481 }
482
483 per_cpu(prev_left[idx], smp_processor_id()) = left;
484
485 /*
486 * The hw counter starts counting from this counter offset,
487 * mark it to be able to extra future deltas:
488 */
489 atomic64_set(&hwc->prev_count, (u64)-left);
490
491 err = checking_wrmsrl(hwc->counter_base + idx,
492 (u64)(-left) & x86_pmu.counter_mask);
493 }
494
495 static inline void
496 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
497 {
498 int idx = __idx - X86_PMC_IDX_FIXED;
499 u64 ctrl_val, bits, mask;
500 int err;
501
502 /*
503 * Enable IRQ generation (0x8),
504 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
505 * if requested:
506 */
507 bits = 0x8ULL;
508 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
509 bits |= 0x2;
510 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
511 bits |= 0x1;
512 bits <<= (idx * 4);
513 mask = 0xfULL << (idx * 4);
514
515 rdmsrl(hwc->config_base, ctrl_val);
516 ctrl_val &= ~mask;
517 ctrl_val |= bits;
518 err = checking_wrmsrl(hwc->config_base, ctrl_val);
519 }
520
521 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
522 {
523 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
524 intel_pmu_enable_fixed(hwc, idx);
525 return;
526 }
527
528 x86_pmu_enable_counter(hwc, idx);
529 }
530
531 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
532 {
533 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
534
535 if (cpuc->enabled)
536 x86_pmu_enable_counter(hwc, idx);
537 else
538 x86_pmu_disable_counter(hwc, idx);
539 }
540
541 static int
542 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
543 {
544 unsigned int event;
545
546 if (!x86_pmu.num_counters_fixed)
547 return -1;
548
549 if (unlikely(hwc->nmi))
550 return -1;
551
552 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
553
554 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
555 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
556 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
557 return X86_PMC_IDX_FIXED_CPU_CYCLES;
558 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
559 return X86_PMC_IDX_FIXED_BUS_CYCLES;
560
561 return -1;
562 }
563
564 /*
565 * Find a PMC slot for the freshly enabled / scheduled in counter:
566 */
567 static int x86_pmu_enable(struct perf_counter *counter)
568 {
569 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
570 struct hw_perf_counter *hwc = &counter->hw;
571 int idx;
572
573 idx = fixed_mode_idx(counter, hwc);
574 if (idx >= 0) {
575 /*
576 * Try to get the fixed counter, if that is already taken
577 * then try to get a generic counter:
578 */
579 if (test_and_set_bit(idx, cpuc->used_mask))
580 goto try_generic;
581
582 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
583 /*
584 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
585 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
586 */
587 hwc->counter_base =
588 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
589 hwc->idx = idx;
590 } else {
591 idx = hwc->idx;
592 /* Try to get the previous generic counter again */
593 if (test_and_set_bit(idx, cpuc->used_mask)) {
594 try_generic:
595 idx = find_first_zero_bit(cpuc->used_mask,
596 x86_pmu.num_counters);
597 if (idx == x86_pmu.num_counters)
598 return -EAGAIN;
599
600 set_bit(idx, cpuc->used_mask);
601 hwc->idx = idx;
602 }
603 hwc->config_base = x86_pmu.eventsel;
604 hwc->counter_base = x86_pmu.perfctr;
605 }
606
607 perf_counters_lapic_init(hwc->nmi);
608
609 x86_pmu.disable(hwc, idx);
610
611 cpuc->counters[idx] = counter;
612 set_bit(idx, cpuc->active_mask);
613
614 x86_perf_counter_set_period(counter, hwc, idx);
615 x86_pmu.enable(hwc, idx);
616
617 return 0;
618 }
619
620 void perf_counter_print_debug(void)
621 {
622 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
623 struct cpu_hw_counters *cpuc;
624 int cpu, idx;
625
626 if (!x86_pmu.num_counters)
627 return;
628
629 local_irq_disable();
630
631 cpu = smp_processor_id();
632 cpuc = &per_cpu(cpu_hw_counters, cpu);
633
634 if (x86_pmu.version >= 2) {
635 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
636 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
637 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
638 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
639
640 pr_info("\n");
641 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
642 pr_info("CPU#%d: status: %016llx\n", cpu, status);
643 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
644 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
645 }
646 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
647
648 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
649 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
650 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
651
652 prev_left = per_cpu(prev_left[idx], cpu);
653
654 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
655 cpu, idx, pmc_ctrl);
656 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
657 cpu, idx, pmc_count);
658 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
659 cpu, idx, prev_left);
660 }
661 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
662 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
663
664 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
665 cpu, idx, pmc_count);
666 }
667 local_irq_enable();
668 }
669
670 static void x86_pmu_disable(struct perf_counter *counter)
671 {
672 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
673 struct hw_perf_counter *hwc = &counter->hw;
674 int idx = hwc->idx;
675
676 /*
677 * Must be done before we disable, otherwise the nmi handler
678 * could reenable again:
679 */
680 clear_bit(idx, cpuc->active_mask);
681 x86_pmu.disable(hwc, idx);
682
683 /*
684 * Make sure the cleared pointer becomes visible before we
685 * (potentially) free the counter:
686 */
687 barrier();
688
689 /*
690 * Drain the remaining delta count out of a counter
691 * that we are disabling:
692 */
693 x86_perf_counter_update(counter, hwc, idx);
694 cpuc->counters[idx] = NULL;
695 clear_bit(idx, cpuc->used_mask);
696 }
697
698 /*
699 * Save and restart an expired counter. Called by NMI contexts,
700 * so it has to be careful about preempting normal counter ops:
701 */
702 static void intel_pmu_save_and_restart(struct perf_counter *counter)
703 {
704 struct hw_perf_counter *hwc = &counter->hw;
705 int idx = hwc->idx;
706
707 x86_perf_counter_update(counter, hwc, idx);
708 x86_perf_counter_set_period(counter, hwc, idx);
709
710 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
711 intel_pmu_enable_counter(hwc, idx);
712 }
713
714 /*
715 * Maximum interrupt frequency of 100KHz per CPU
716 */
717 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
718
719 /*
720 * This handler is triggered by the local APIC, so the APIC IRQ handling
721 * rules apply:
722 */
723 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
724 {
725 int bit, cpu = smp_processor_id();
726 u64 ack, status;
727 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
728 int ret = 0;
729
730 cpuc->throttle_ctrl = intel_pmu_save_disable_all();
731
732 status = intel_pmu_get_status();
733 if (!status)
734 goto out;
735
736 ret = 1;
737 again:
738 inc_irq_stat(apic_perf_irqs);
739 ack = status;
740 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
741 struct perf_counter *counter = cpuc->counters[bit];
742
743 clear_bit(bit, (unsigned long *) &status);
744 if (!test_bit(bit, cpuc->active_mask))
745 continue;
746
747 intel_pmu_save_and_restart(counter);
748 if (perf_counter_overflow(counter, nmi, regs, 0))
749 intel_pmu_disable_counter(&counter->hw, bit);
750 }
751
752 intel_pmu_ack_status(ack);
753
754 /*
755 * Repeat if there is more work to be done:
756 */
757 status = intel_pmu_get_status();
758 if (status)
759 goto again;
760 out:
761 /*
762 * Restore - do not reenable when global enable is off or throttled:
763 */
764 if (++cpuc->interrupts < PERFMON_MAX_INTERRUPTS)
765 intel_pmu_restore_all(cpuc->throttle_ctrl);
766
767 return ret;
768 }
769
770 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
771 {
772 int cpu = smp_processor_id();
773 struct cpu_hw_counters *cpuc = &per_cpu(cpu_hw_counters, cpu);
774 u64 val;
775 int handled = 0;
776 struct perf_counter *counter;
777 struct hw_perf_counter *hwc;
778 int idx;
779
780 ++cpuc->interrupts;
781 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
782 if (!test_bit(idx, cpuc->active_mask))
783 continue;
784 counter = cpuc->counters[idx];
785 hwc = &counter->hw;
786 val = x86_perf_counter_update(counter, hwc, idx);
787 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
788 continue;
789 /* counter overflow */
790 x86_perf_counter_set_period(counter, hwc, idx);
791 handled = 1;
792 inc_irq_stat(apic_perf_irqs);
793 if (perf_counter_overflow(counter, nmi, regs, 0))
794 amd_pmu_disable_counter(hwc, idx);
795 else if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS)
796 /*
797 * do not reenable when throttled, but reload
798 * the register
799 */
800 amd_pmu_disable_counter(hwc, idx);
801 else if (counter->state == PERF_COUNTER_STATE_ACTIVE)
802 amd_pmu_enable_counter(hwc, idx);
803 }
804 return handled;
805 }
806
807 void perf_counter_unthrottle(void)
808 {
809 struct cpu_hw_counters *cpuc;
810
811 if (!x86_pmu_initialized())
812 return;
813
814 cpuc = &__get_cpu_var(cpu_hw_counters);
815 if (cpuc->interrupts >= PERFMON_MAX_INTERRUPTS) {
816 if (printk_ratelimit())
817 printk(KERN_WARNING "PERFMON: max interrupts exceeded!\n");
818 hw_perf_restore(cpuc->throttle_ctrl);
819 }
820 cpuc->interrupts = 0;
821 }
822
823 void smp_perf_counter_interrupt(struct pt_regs *regs)
824 {
825 irq_enter();
826 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
827 ack_APIC_irq();
828 x86_pmu.handle_irq(regs, 0);
829 irq_exit();
830 }
831
832 void smp_perf_pending_interrupt(struct pt_regs *regs)
833 {
834 irq_enter();
835 ack_APIC_irq();
836 inc_irq_stat(apic_pending_irqs);
837 perf_counter_do_pending();
838 irq_exit();
839 }
840
841 void set_perf_counter_pending(void)
842 {
843 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
844 }
845
846 void perf_counters_lapic_init(int nmi)
847 {
848 u32 apic_val;
849
850 if (!x86_pmu_initialized())
851 return;
852
853 /*
854 * Enable the performance counter vector in the APIC LVT:
855 */
856 apic_val = apic_read(APIC_LVTERR);
857
858 apic_write(APIC_LVTERR, apic_val | APIC_LVT_MASKED);
859 if (nmi)
860 apic_write(APIC_LVTPC, APIC_DM_NMI);
861 else
862 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
863 apic_write(APIC_LVTERR, apic_val);
864 }
865
866 static int __kprobes
867 perf_counter_nmi_handler(struct notifier_block *self,
868 unsigned long cmd, void *__args)
869 {
870 struct die_args *args = __args;
871 struct pt_regs *regs;
872 int ret;
873
874 if (!atomic_read(&active_counters))
875 return NOTIFY_DONE;
876
877 switch (cmd) {
878 case DIE_NMI:
879 case DIE_NMI_IPI:
880 break;
881
882 default:
883 return NOTIFY_DONE;
884 }
885
886 regs = args->regs;
887
888 apic_write(APIC_LVTPC, APIC_DM_NMI);
889 ret = x86_pmu.handle_irq(regs, 1);
890
891 return ret ? NOTIFY_STOP : NOTIFY_OK;
892 }
893
894 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
895 .notifier_call = perf_counter_nmi_handler,
896 .next = NULL,
897 .priority = 1
898 };
899
900 static struct x86_pmu intel_pmu = {
901 .name = "Intel",
902 .handle_irq = intel_pmu_handle_irq,
903 .save_disable_all = intel_pmu_save_disable_all,
904 .restore_all = intel_pmu_restore_all,
905 .enable = intel_pmu_enable_counter,
906 .disable = intel_pmu_disable_counter,
907 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
908 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
909 .event_map = intel_pmu_event_map,
910 .raw_event = intel_pmu_raw_event,
911 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
912 /*
913 * Intel PMCs cannot be accessed sanely above 32 bit width,
914 * so we install an artificial 1<<31 period regardless of
915 * the generic counter period:
916 */
917 .max_period = (1ULL << 31) - 1,
918 };
919
920 static struct x86_pmu amd_pmu = {
921 .name = "AMD",
922 .handle_irq = amd_pmu_handle_irq,
923 .save_disable_all = amd_pmu_save_disable_all,
924 .restore_all = amd_pmu_restore_all,
925 .enable = amd_pmu_enable_counter,
926 .disable = amd_pmu_disable_counter,
927 .eventsel = MSR_K7_EVNTSEL0,
928 .perfctr = MSR_K7_PERFCTR0,
929 .event_map = amd_pmu_event_map,
930 .raw_event = amd_pmu_raw_event,
931 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
932 .num_counters = 4,
933 .counter_bits = 48,
934 .counter_mask = (1ULL << 48) - 1,
935 /* use highest bit to detect overflow */
936 .max_period = (1ULL << 47) - 1,
937 };
938
939 static int intel_pmu_init(void)
940 {
941 union cpuid10_edx edx;
942 union cpuid10_eax eax;
943 unsigned int unused;
944 unsigned int ebx;
945 int version;
946
947 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
948 return -ENODEV;
949
950 /*
951 * Check whether the Architectural PerfMon supports
952 * Branch Misses Retired Event or not.
953 */
954 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
955 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
956 return -ENODEV;
957
958 version = eax.split.version_id;
959 if (version < 2)
960 return -ENODEV;
961
962 x86_pmu = intel_pmu;
963 x86_pmu.version = version;
964 x86_pmu.num_counters = eax.split.num_counters;
965 x86_pmu.num_counters_fixed = edx.split.num_counters_fixed;
966 x86_pmu.counter_bits = eax.split.bit_width;
967 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
968
969 return 0;
970 }
971
972 static int amd_pmu_init(void)
973 {
974 x86_pmu = amd_pmu;
975 return 0;
976 }
977
978 void __init init_hw_perf_counters(void)
979 {
980 int err;
981
982 switch (boot_cpu_data.x86_vendor) {
983 case X86_VENDOR_INTEL:
984 err = intel_pmu_init();
985 break;
986 case X86_VENDOR_AMD:
987 err = amd_pmu_init();
988 break;
989 default:
990 return;
991 }
992 if (err != 0)
993 return;
994
995 pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
996 pr_info("... version: %d\n", x86_pmu.version);
997 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
998
999 pr_info("... num counters: %d\n", x86_pmu.num_counters);
1000 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1001 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1002 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1003 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1004 }
1005 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1006 perf_max_counters = x86_pmu.num_counters;
1007
1008 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1009 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1010
1011 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1012 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1013 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1014 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1015 }
1016 pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed);
1017
1018 perf_counter_mask |=
1019 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1020
1021 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1022
1023 perf_counters_lapic_init(0);
1024 register_die_notifier(&perf_counter_nmi_notifier);
1025 }
1026
1027 static inline void x86_pmu_read(struct perf_counter *counter)
1028 {
1029 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1030 }
1031
1032 static const struct pmu pmu = {
1033 .enable = x86_pmu_enable,
1034 .disable = x86_pmu_disable,
1035 .read = x86_pmu_read,
1036 };
1037
1038 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1039 {
1040 int err;
1041
1042 err = __hw_perf_counter_init(counter);
1043 if (err)
1044 return ERR_PTR(err);
1045
1046 return &pmu;
1047 }
1048
1049 /*
1050 * callchain support
1051 */
1052
1053 static inline
1054 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1055 {
1056 if (entry->nr < MAX_STACK_DEPTH)
1057 entry->ip[entry->nr++] = ip;
1058 }
1059
1060 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1061 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1062
1063
1064 static void
1065 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1066 {
1067 /* Ignore warnings */
1068 }
1069
1070 static void backtrace_warning(void *data, char *msg)
1071 {
1072 /* Ignore warnings */
1073 }
1074
1075 static int backtrace_stack(void *data, char *name)
1076 {
1077 /* Don't bother with IRQ stacks for now */
1078 return -1;
1079 }
1080
1081 static void backtrace_address(void *data, unsigned long addr, int reliable)
1082 {
1083 struct perf_callchain_entry *entry = data;
1084
1085 if (reliable)
1086 callchain_store(entry, addr);
1087 }
1088
1089 static const struct stacktrace_ops backtrace_ops = {
1090 .warning = backtrace_warning,
1091 .warning_symbol = backtrace_warning_symbol,
1092 .stack = backtrace_stack,
1093 .address = backtrace_address,
1094 };
1095
1096 static void
1097 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1098 {
1099 unsigned long bp;
1100 char *stack;
1101 int nr = entry->nr;
1102
1103 callchain_store(entry, instruction_pointer(regs));
1104
1105 stack = ((char *)regs + sizeof(struct pt_regs));
1106 #ifdef CONFIG_FRAME_POINTER
1107 bp = frame_pointer(regs);
1108 #else
1109 bp = 0;
1110 #endif
1111
1112 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1113
1114 entry->kernel = entry->nr - nr;
1115 }
1116
1117
1118 struct stack_frame {
1119 const void __user *next_fp;
1120 unsigned long return_address;
1121 };
1122
1123 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1124 {
1125 int ret;
1126
1127 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1128 return 0;
1129
1130 ret = 1;
1131 pagefault_disable();
1132 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1133 ret = 0;
1134 pagefault_enable();
1135
1136 return ret;
1137 }
1138
1139 static void
1140 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1141 {
1142 struct stack_frame frame;
1143 const void __user *fp;
1144 int nr = entry->nr;
1145
1146 regs = (struct pt_regs *)current->thread.sp0 - 1;
1147 fp = (void __user *)regs->bp;
1148
1149 callchain_store(entry, regs->ip);
1150
1151 while (entry->nr < MAX_STACK_DEPTH) {
1152 frame.next_fp = NULL;
1153 frame.return_address = 0;
1154
1155 if (!copy_stack_frame(fp, &frame))
1156 break;
1157
1158 if ((unsigned long)fp < user_stack_pointer(regs))
1159 break;
1160
1161 callchain_store(entry, frame.return_address);
1162 fp = frame.next_fp;
1163 }
1164
1165 entry->user = entry->nr - nr;
1166 }
1167
1168 static void
1169 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1170 {
1171 int is_user;
1172
1173 if (!regs)
1174 return;
1175
1176 is_user = user_mode(regs);
1177
1178 if (!current || current->pid == 0)
1179 return;
1180
1181 if (is_user && current->state != TASK_RUNNING)
1182 return;
1183
1184 if (!is_user)
1185 perf_callchain_kernel(regs, entry);
1186
1187 if (current->mm)
1188 perf_callchain_user(regs, entry);
1189 }
1190
1191 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1192 {
1193 struct perf_callchain_entry *entry;
1194
1195 if (in_nmi())
1196 entry = &__get_cpu_var(nmi_entry);
1197 else
1198 entry = &__get_cpu_var(irq_entry);
1199
1200 entry->nr = 0;
1201 entry->hv = 0;
1202 entry->kernel = 0;
1203 entry->user = 0;
1204
1205 perf_do_callchain(regs, entry);
1206
1207 return entry;
1208 }
Linux kernel - Deliverables
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