2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly
;
44 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
48 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX
]
52 [PERF_COUNT_HW_CACHE_OP_MAX
]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64
x86_perf_event_update(struct perf_event
*event
)
66 struct hw_perf_event
*hwc
= &event
->hw
;
67 int shift
= 64 - x86_pmu
.cntval_bits
;
68 u64 prev_raw_count
, new_raw_count
;
72 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count
= local64_read(&hwc
->prev_count
);
84 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
86 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
87 new_raw_count
) != prev_raw_count
)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
101 local64_add(delta
, &event
->count
);
102 local64_sub(delta
, &hwc
->period_left
);
104 return new_raw_count
;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
112 struct hw_perf_event_extra
*reg
;
113 struct extra_reg
*er
;
115 reg
= &event
->hw
.extra_reg
;
117 if (!x86_pmu
.extra_regs
)
120 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
121 if (er
->event
!= (config
& er
->config_mask
))
123 if (event
->attr
.config1
& ~er
->valid_mask
)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er
->extra_msr_access
)
130 reg
->config
= event
->attr
.config1
;
137 static atomic_t active_events
;
138 static atomic_t pmc_refcount
;
139 static DEFINE_MUTEX(pmc_reserve_mutex
);
141 #ifdef CONFIG_X86_LOCAL_APIC
143 static bool reserve_pmc_hardware(void)
147 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
148 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
152 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
153 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
160 for (i
--; i
>= 0; i
--)
161 release_evntsel_nmi(x86_pmu_config_addr(i
));
163 i
= x86_pmu
.num_counters
;
166 for (i
--; i
>= 0; i
--)
167 release_perfctr_nmi(x86_pmu_event_addr(i
));
172 static void release_pmc_hardware(void)
176 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
177 release_perfctr_nmi(x86_pmu_event_addr(i
));
178 release_evntsel_nmi(x86_pmu_config_addr(i
));
184 static bool reserve_pmc_hardware(void) { return true; }
185 static void release_pmc_hardware(void) {}
189 static bool check_hw_exists(void)
191 u64 val
, val_fail
, val_new
= ~0;
192 int i
, reg
, reg_fail
, ret
= 0;
197 * Check to see if the BIOS enabled any of the counters, if so
200 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
201 reg
= x86_pmu_config_addr(i
);
202 ret
= rdmsrl_safe(reg
, &val
);
205 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
214 if (x86_pmu
.num_counters_fixed
) {
215 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
216 ret
= rdmsrl_safe(reg
, &val
);
219 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
220 if (val
& (0x03 << i
*4)) {
229 * If all the counters are enabled, the below test will always
230 * fail. The tools will also become useless in this scenario.
231 * Just fail and disable the hardware counters.
234 if (reg_safe
== -1) {
240 * Read the current value, change it and read it back to see if it
241 * matches, this is needed to detect certain hardware emulators
242 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
244 reg
= x86_pmu_event_addr(reg_safe
);
245 if (rdmsrl_safe(reg
, &val
))
248 ret
= wrmsrl_safe(reg
, val
);
249 ret
|= rdmsrl_safe(reg
, &val_new
);
250 if (ret
|| val
!= val_new
)
254 * We still allow the PMU driver to operate:
257 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
258 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail
, val_fail
);
264 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
265 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
266 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
272 static void hw_perf_event_destroy(struct perf_event
*event
)
274 x86_release_hardware();
275 atomic_dec(&active_events
);
278 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
280 hw_perf_event_destroy(event
);
282 /* undo the lbr/bts event accounting */
283 x86_del_exclusive(x86_lbr_exclusive_lbr
);
286 static inline int x86_pmu_initialized(void)
288 return x86_pmu
.handle_irq
!= NULL
;
292 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
294 struct perf_event_attr
*attr
= &event
->attr
;
295 unsigned int cache_type
, cache_op
, cache_result
;
298 config
= attr
->config
;
300 cache_type
= (config
>> 0) & 0xff;
301 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
304 cache_op
= (config
>> 8) & 0xff;
305 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
308 cache_result
= (config
>> 16) & 0xff;
309 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
312 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
321 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
322 return x86_pmu_extra_regs(val
, event
);
325 int x86_reserve_hardware(void)
329 if (!atomic_inc_not_zero(&pmc_refcount
)) {
330 mutex_lock(&pmc_reserve_mutex
);
331 if (atomic_read(&pmc_refcount
) == 0) {
332 if (!reserve_pmc_hardware())
335 reserve_ds_buffers();
338 atomic_inc(&pmc_refcount
);
339 mutex_unlock(&pmc_reserve_mutex
);
345 void x86_release_hardware(void)
347 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
348 release_pmc_hardware();
349 release_ds_buffers();
350 mutex_unlock(&pmc_reserve_mutex
);
355 * Check if we can create event of a certain type (that no conflicting events
358 int x86_add_exclusive(unsigned int what
)
362 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
363 mutex_lock(&pmc_reserve_mutex
);
364 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
365 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
368 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
369 mutex_unlock(&pmc_reserve_mutex
);
372 atomic_inc(&active_events
);
376 mutex_unlock(&pmc_reserve_mutex
);
380 void x86_del_exclusive(unsigned int what
)
382 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
383 atomic_dec(&active_events
);
386 int x86_setup_perfctr(struct perf_event
*event
)
388 struct perf_event_attr
*attr
= &event
->attr
;
389 struct hw_perf_event
*hwc
= &event
->hw
;
392 if (!is_sampling_event(event
)) {
393 hwc
->sample_period
= x86_pmu
.max_period
;
394 hwc
->last_period
= hwc
->sample_period
;
395 local64_set(&hwc
->period_left
, hwc
->sample_period
);
398 if (attr
->type
== PERF_TYPE_RAW
)
399 return x86_pmu_extra_regs(event
->attr
.config
, event
);
401 if (attr
->type
== PERF_TYPE_HW_CACHE
)
402 return set_ext_hw_attr(hwc
, event
);
404 if (attr
->config
>= x86_pmu
.max_events
)
410 config
= x86_pmu
.event_map(attr
->config
);
421 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
422 !attr
->freq
&& hwc
->sample_period
== 1) {
423 /* BTS is not supported by this architecture. */
424 if (!x86_pmu
.bts_active
)
427 /* BTS is currently only allowed for user-mode. */
428 if (!attr
->exclude_kernel
)
431 /* disallow bts if conflicting events are present */
432 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
435 event
->destroy
= hw_perf_lbr_event_destroy
;
438 hwc
->config
|= config
;
444 * check that branch_sample_type is compatible with
445 * settings needed for precise_ip > 1 which implies
446 * using the LBR to capture ALL taken branches at the
447 * priv levels of the measurement
449 static inline int precise_br_compat(struct perf_event
*event
)
451 u64 m
= event
->attr
.branch_sample_type
;
454 /* must capture all branches */
455 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
458 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
460 if (!event
->attr
.exclude_user
)
461 b
|= PERF_SAMPLE_BRANCH_USER
;
463 if (!event
->attr
.exclude_kernel
)
464 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
467 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
473 int x86_pmu_hw_config(struct perf_event
*event
)
475 if (event
->attr
.precise_ip
) {
478 /* Support for constant skid */
479 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
482 /* Support for IP fixup */
483 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
487 if (event
->attr
.precise_ip
> precise
)
491 * check that PEBS LBR correction does not conflict with
492 * whatever the user is asking with attr->branch_sample_type
494 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
495 u64
*br_type
= &event
->attr
.branch_sample_type
;
497 if (has_branch_stack(event
)) {
498 if (!precise_br_compat(event
))
501 /* branch_sample_type is compatible */
505 * user did not specify branch_sample_type
507 * For PEBS fixups, we capture all
508 * the branches at the priv level of the
511 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
513 if (!event
->attr
.exclude_user
)
514 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
516 if (!event
->attr
.exclude_kernel
)
517 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
521 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
522 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
526 * (keep 'enabled' bit clear for now)
528 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
531 * Count user and OS events unless requested not to
533 if (!event
->attr
.exclude_user
)
534 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
535 if (!event
->attr
.exclude_kernel
)
536 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
538 if (event
->attr
.type
== PERF_TYPE_RAW
)
539 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
541 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
542 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
543 event
->attr
.sample_period
)
547 return x86_setup_perfctr(event
);
551 * Setup the hardware configuration for a given attr_type
553 static int __x86_pmu_event_init(struct perf_event
*event
)
557 if (!x86_pmu_initialized())
560 err
= x86_reserve_hardware();
564 atomic_inc(&active_events
);
565 event
->destroy
= hw_perf_event_destroy
;
568 event
->hw
.last_cpu
= -1;
569 event
->hw
.last_tag
= ~0ULL;
572 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
573 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
575 return x86_pmu
.hw_config(event
);
578 void x86_pmu_disable_all(void)
580 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
583 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
586 if (!test_bit(idx
, cpuc
->active_mask
))
588 rdmsrl(x86_pmu_config_addr(idx
), val
);
589 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
591 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
592 wrmsrl(x86_pmu_config_addr(idx
), val
);
596 static void x86_pmu_disable(struct pmu
*pmu
)
598 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
600 if (!x86_pmu_initialized())
610 x86_pmu
.disable_all();
613 void x86_pmu_enable_all(int added
)
615 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
618 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
619 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
621 if (!test_bit(idx
, cpuc
->active_mask
))
624 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
628 static struct pmu pmu
;
630 static inline int is_x86_event(struct perf_event
*event
)
632 return event
->pmu
== &pmu
;
636 * Event scheduler state:
638 * Assign events iterating over all events and counters, beginning
639 * with events with least weights first. Keep the current iterator
640 * state in struct sched_state.
644 int event
; /* event index */
645 int counter
; /* counter index */
646 int unassigned
; /* number of events to be assigned left */
647 int nr_gp
; /* number of GP counters used */
648 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
651 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
652 #define SCHED_STATES_MAX 2
659 struct event_constraint
**constraints
;
660 struct sched_state state
;
661 struct sched_state saved
[SCHED_STATES_MAX
];
665 * Initialize interator that runs through all events and counters.
667 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
668 int num
, int wmin
, int wmax
, int gpmax
)
672 memset(sched
, 0, sizeof(*sched
));
673 sched
->max_events
= num
;
674 sched
->max_weight
= wmax
;
675 sched
->max_gp
= gpmax
;
676 sched
->constraints
= constraints
;
678 for (idx
= 0; idx
< num
; idx
++) {
679 if (constraints
[idx
]->weight
== wmin
)
683 sched
->state
.event
= idx
; /* start with min weight */
684 sched
->state
.weight
= wmin
;
685 sched
->state
.unassigned
= num
;
688 static void perf_sched_save_state(struct perf_sched
*sched
)
690 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
693 sched
->saved
[sched
->saved_states
] = sched
->state
;
694 sched
->saved_states
++;
697 static bool perf_sched_restore_state(struct perf_sched
*sched
)
699 if (!sched
->saved_states
)
702 sched
->saved_states
--;
703 sched
->state
= sched
->saved
[sched
->saved_states
];
705 /* continue with next counter: */
706 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
712 * Select a counter for the current event to schedule. Return true on
715 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
717 struct event_constraint
*c
;
720 if (!sched
->state
.unassigned
)
723 if (sched
->state
.event
>= sched
->max_events
)
726 c
= sched
->constraints
[sched
->state
.event
];
727 /* Prefer fixed purpose counters */
728 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
729 idx
= INTEL_PMC_IDX_FIXED
;
730 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
731 if (!__test_and_set_bit(idx
, sched
->state
.used
))
736 /* Grab the first unused counter starting with idx */
737 idx
= sched
->state
.counter
;
738 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
739 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
740 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
750 sched
->state
.counter
= idx
;
753 perf_sched_save_state(sched
);
758 static bool perf_sched_find_counter(struct perf_sched
*sched
)
760 while (!__perf_sched_find_counter(sched
)) {
761 if (!perf_sched_restore_state(sched
))
769 * Go through all unassigned events and find the next one to schedule.
770 * Take events with the least weight first. Return true on success.
772 static bool perf_sched_next_event(struct perf_sched
*sched
)
774 struct event_constraint
*c
;
776 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
781 sched
->state
.event
++;
782 if (sched
->state
.event
>= sched
->max_events
) {
784 sched
->state
.event
= 0;
785 sched
->state
.weight
++;
786 if (sched
->state
.weight
> sched
->max_weight
)
789 c
= sched
->constraints
[sched
->state
.event
];
790 } while (c
->weight
!= sched
->state
.weight
);
792 sched
->state
.counter
= 0; /* start with first counter */
798 * Assign a counter for each event.
800 int perf_assign_events(struct event_constraint
**constraints
, int n
,
801 int wmin
, int wmax
, int gpmax
, int *assign
)
803 struct perf_sched sched
;
805 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
808 if (!perf_sched_find_counter(&sched
))
811 assign
[sched
.state
.event
] = sched
.state
.counter
;
812 } while (perf_sched_next_event(&sched
));
814 return sched
.state
.unassigned
;
816 EXPORT_SYMBOL_GPL(perf_assign_events
);
818 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
820 struct event_constraint
*c
;
821 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
822 struct perf_event
*e
;
823 int i
, wmin
, wmax
, unsched
= 0;
824 struct hw_perf_event
*hwc
;
826 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
828 if (x86_pmu
.start_scheduling
)
829 x86_pmu
.start_scheduling(cpuc
);
831 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
832 cpuc
->event_constraint
[i
] = NULL
;
833 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
834 cpuc
->event_constraint
[i
] = c
;
836 wmin
= min(wmin
, c
->weight
);
837 wmax
= max(wmax
, c
->weight
);
841 * fastpath, try to reuse previous register
843 for (i
= 0; i
< n
; i
++) {
844 hwc
= &cpuc
->event_list
[i
]->hw
;
845 c
= cpuc
->event_constraint
[i
];
851 /* constraint still honored */
852 if (!test_bit(hwc
->idx
, c
->idxmsk
))
855 /* not already used */
856 if (test_bit(hwc
->idx
, used_mask
))
859 __set_bit(hwc
->idx
, used_mask
);
861 assign
[i
] = hwc
->idx
;
866 int gpmax
= x86_pmu
.num_counters
;
869 * Do not allow scheduling of more than half the available
872 * This helps avoid counter starvation of sibling thread by
873 * ensuring at most half the counters cannot be in exclusive
874 * mode. There is no designated counters for the limits. Any
875 * N/2 counters can be used. This helps with events with
876 * specific counter constraints.
878 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
879 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
882 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
883 wmax
, gpmax
, assign
);
887 * In case of success (unsched = 0), mark events as committed,
888 * so we do not put_constraint() in case new events are added
889 * and fail to be scheduled
891 * We invoke the lower level commit callback to lock the resource
893 * We do not need to do all of this in case we are called to
894 * validate an event group (assign == NULL)
896 if (!unsched
&& assign
) {
897 for (i
= 0; i
< n
; i
++) {
898 e
= cpuc
->event_list
[i
];
899 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
900 if (x86_pmu
.commit_scheduling
)
901 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
904 for (i
= 0; i
< n
; i
++) {
905 e
= cpuc
->event_list
[i
];
907 * do not put_constraint() on comitted events,
908 * because they are good to go
910 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
914 * release events that failed scheduling
916 if (x86_pmu
.put_event_constraints
)
917 x86_pmu
.put_event_constraints(cpuc
, e
);
921 if (x86_pmu
.stop_scheduling
)
922 x86_pmu
.stop_scheduling(cpuc
);
924 return unsched
? -EINVAL
: 0;
928 * dogrp: true if must collect siblings events (group)
929 * returns total number of events and error code
931 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
933 struct perf_event
*event
;
936 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
938 /* current number of events already accepted */
941 if (is_x86_event(leader
)) {
944 cpuc
->event_list
[n
] = leader
;
950 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
951 if (!is_x86_event(event
) ||
952 event
->state
<= PERF_EVENT_STATE_OFF
)
958 cpuc
->event_list
[n
] = event
;
964 static inline void x86_assign_hw_event(struct perf_event
*event
,
965 struct cpu_hw_events
*cpuc
, int i
)
967 struct hw_perf_event
*hwc
= &event
->hw
;
969 hwc
->idx
= cpuc
->assign
[i
];
970 hwc
->last_cpu
= smp_processor_id();
971 hwc
->last_tag
= ++cpuc
->tags
[i
];
973 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
974 hwc
->config_base
= 0;
976 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
977 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
978 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
979 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
981 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
982 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
983 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
987 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
988 struct cpu_hw_events
*cpuc
,
991 return hwc
->idx
== cpuc
->assign
[i
] &&
992 hwc
->last_cpu
== smp_processor_id() &&
993 hwc
->last_tag
== cpuc
->tags
[i
];
996 static void x86_pmu_start(struct perf_event
*event
, int flags
);
998 static void x86_pmu_enable(struct pmu
*pmu
)
1000 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1001 struct perf_event
*event
;
1002 struct hw_perf_event
*hwc
;
1003 int i
, added
= cpuc
->n_added
;
1005 if (!x86_pmu_initialized())
1011 if (cpuc
->n_added
) {
1012 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1014 * apply assignment obtained either from
1015 * hw_perf_group_sched_in() or x86_pmu_enable()
1017 * step1: save events moving to new counters
1019 for (i
= 0; i
< n_running
; i
++) {
1020 event
= cpuc
->event_list
[i
];
1024 * we can avoid reprogramming counter if:
1025 * - assigned same counter as last time
1026 * - running on same CPU as last time
1027 * - no other event has used the counter since
1029 if (hwc
->idx
== -1 ||
1030 match_prev_assignment(hwc
, cpuc
, i
))
1034 * Ensure we don't accidentally enable a stopped
1035 * counter simply because we rescheduled.
1037 if (hwc
->state
& PERF_HES_STOPPED
)
1038 hwc
->state
|= PERF_HES_ARCH
;
1040 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1044 * step2: reprogram moved events into new counters
1046 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1047 event
= cpuc
->event_list
[i
];
1050 if (!match_prev_assignment(hwc
, cpuc
, i
))
1051 x86_assign_hw_event(event
, cpuc
, i
);
1052 else if (i
< n_running
)
1055 if (hwc
->state
& PERF_HES_ARCH
)
1058 x86_pmu_start(event
, PERF_EF_RELOAD
);
1061 perf_events_lapic_init();
1067 x86_pmu
.enable_all(added
);
1070 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1073 * Set the next IRQ period, based on the hwc->period_left value.
1074 * To be called with the event disabled in hw:
1076 int x86_perf_event_set_period(struct perf_event
*event
)
1078 struct hw_perf_event
*hwc
= &event
->hw
;
1079 s64 left
= local64_read(&hwc
->period_left
);
1080 s64 period
= hwc
->sample_period
;
1081 int ret
= 0, idx
= hwc
->idx
;
1083 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1087 * If we are way outside a reasonable range then just skip forward:
1089 if (unlikely(left
<= -period
)) {
1091 local64_set(&hwc
->period_left
, left
);
1092 hwc
->last_period
= period
;
1096 if (unlikely(left
<= 0)) {
1098 local64_set(&hwc
->period_left
, left
);
1099 hwc
->last_period
= period
;
1103 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1105 if (unlikely(left
< 2))
1108 if (left
> x86_pmu
.max_period
)
1109 left
= x86_pmu
.max_period
;
1111 if (x86_pmu
.limit_period
)
1112 left
= x86_pmu
.limit_period(event
, left
);
1114 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1116 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1117 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1119 * The hw event starts counting from this event offset,
1120 * mark it to be able to extra future deltas:
1122 local64_set(&hwc
->prev_count
, (u64
)-left
);
1124 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1128 * Due to erratum on certan cpu we need
1129 * a second write to be sure the register
1130 * is updated properly
1132 if (x86_pmu
.perfctr_second_write
) {
1133 wrmsrl(hwc
->event_base
,
1134 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1137 perf_event_update_userpage(event
);
1142 void x86_pmu_enable_event(struct perf_event
*event
)
1144 if (__this_cpu_read(cpu_hw_events
.enabled
))
1145 __x86_pmu_enable_event(&event
->hw
,
1146 ARCH_PERFMON_EVENTSEL_ENABLE
);
1150 * Add a single event to the PMU.
1152 * The event is added to the group of enabled events
1153 * but only if it can be scehduled with existing events.
1155 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1157 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1158 struct hw_perf_event
*hwc
;
1159 int assign
[X86_PMC_IDX_MAX
];
1164 n0
= cpuc
->n_events
;
1165 ret
= n
= collect_events(cpuc
, event
, false);
1169 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1170 if (!(flags
& PERF_EF_START
))
1171 hwc
->state
|= PERF_HES_ARCH
;
1174 * If group events scheduling transaction was started,
1175 * skip the schedulability test here, it will be performed
1176 * at commit time (->commit_txn) as a whole.
1178 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1181 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1185 * copy new assignment, now we know it is possible
1186 * will be used by hw_perf_enable()
1188 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1192 * Commit the collect_events() state. See x86_pmu_del() and
1196 cpuc
->n_added
+= n
- n0
;
1197 cpuc
->n_txn
+= n
- n0
;
1204 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1206 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1207 int idx
= event
->hw
.idx
;
1209 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1212 if (WARN_ON_ONCE(idx
== -1))
1215 if (flags
& PERF_EF_RELOAD
) {
1216 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1217 x86_perf_event_set_period(event
);
1220 event
->hw
.state
= 0;
1222 cpuc
->events
[idx
] = event
;
1223 __set_bit(idx
, cpuc
->active_mask
);
1224 __set_bit(idx
, cpuc
->running
);
1225 x86_pmu
.enable(event
);
1226 perf_event_update_userpage(event
);
1229 void perf_event_print_debug(void)
1231 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1233 struct cpu_hw_events
*cpuc
;
1234 unsigned long flags
;
1237 if (!x86_pmu
.num_counters
)
1240 local_irq_save(flags
);
1242 cpu
= smp_processor_id();
1243 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1245 if (x86_pmu
.version
>= 2) {
1246 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1247 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1248 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1249 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1252 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1253 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1254 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1255 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1256 if (x86_pmu
.pebs_constraints
) {
1257 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1258 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1260 if (x86_pmu
.lbr_nr
) {
1261 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1262 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1265 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1267 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1268 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1269 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1271 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1273 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1274 cpu
, idx
, pmc_ctrl
);
1275 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1276 cpu
, idx
, pmc_count
);
1277 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1278 cpu
, idx
, prev_left
);
1280 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1281 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1283 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1284 cpu
, idx
, pmc_count
);
1286 local_irq_restore(flags
);
1289 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1291 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1292 struct hw_perf_event
*hwc
= &event
->hw
;
1294 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1295 x86_pmu
.disable(event
);
1296 cpuc
->events
[hwc
->idx
] = NULL
;
1297 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1298 hwc
->state
|= PERF_HES_STOPPED
;
1301 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1303 * Drain the remaining delta count out of a event
1304 * that we are disabling:
1306 x86_perf_event_update(event
);
1307 hwc
->state
|= PERF_HES_UPTODATE
;
1311 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1313 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1317 * event is descheduled
1319 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1322 * If we're called during a txn, we don't need to do anything.
1323 * The events never got scheduled and ->cancel_txn will truncate
1326 * XXX assumes any ->del() called during a TXN will only be on
1327 * an event added during that same TXN.
1329 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1333 * Not a TXN, therefore cleanup properly.
1335 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1337 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1338 if (event
== cpuc
->event_list
[i
])
1342 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1345 /* If we have a newly added event; make sure to decrease n_added. */
1346 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1349 if (x86_pmu
.put_event_constraints
)
1350 x86_pmu
.put_event_constraints(cpuc
, event
);
1352 /* Delete the array entry. */
1353 while (++i
< cpuc
->n_events
) {
1354 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1355 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1359 perf_event_update_userpage(event
);
1362 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1364 struct perf_sample_data data
;
1365 struct cpu_hw_events
*cpuc
;
1366 struct perf_event
*event
;
1367 int idx
, handled
= 0;
1370 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1373 * Some chipsets need to unmask the LVTPC in a particular spot
1374 * inside the nmi handler. As a result, the unmasking was pushed
1375 * into all the nmi handlers.
1377 * This generic handler doesn't seem to have any issues where the
1378 * unmasking occurs so it was left at the top.
1380 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1382 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1383 if (!test_bit(idx
, cpuc
->active_mask
)) {
1385 * Though we deactivated the counter some cpus
1386 * might still deliver spurious interrupts still
1387 * in flight. Catch them:
1389 if (__test_and_clear_bit(idx
, cpuc
->running
))
1394 event
= cpuc
->events
[idx
];
1396 val
= x86_perf_event_update(event
);
1397 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1404 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1406 if (!x86_perf_event_set_period(event
))
1409 if (perf_event_overflow(event
, &data
, regs
))
1410 x86_pmu_stop(event
, 0);
1414 inc_irq_stat(apic_perf_irqs
);
1419 void perf_events_lapic_init(void)
1421 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1425 * Always use NMI for PMU
1427 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1431 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1438 * All PMUs/events that share this PMI handler should make sure to
1439 * increment active_events for their events.
1441 if (!atomic_read(&active_events
))
1444 start_clock
= sched_clock();
1445 ret
= x86_pmu
.handle_irq(regs
);
1446 finish_clock
= sched_clock();
1448 perf_sample_event_took(finish_clock
- start_clock
);
1452 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1454 struct event_constraint emptyconstraint
;
1455 struct event_constraint unconstrained
;
1458 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1460 unsigned int cpu
= (long)hcpu
;
1461 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1462 int i
, ret
= NOTIFY_OK
;
1464 switch (action
& ~CPU_TASKS_FROZEN
) {
1465 case CPU_UP_PREPARE
:
1466 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1467 cpuc
->kfree_on_online
[i
] = NULL
;
1468 if (x86_pmu
.cpu_prepare
)
1469 ret
= x86_pmu
.cpu_prepare(cpu
);
1473 if (x86_pmu
.cpu_starting
)
1474 x86_pmu
.cpu_starting(cpu
);
1478 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1479 kfree(cpuc
->kfree_on_online
[i
]);
1480 cpuc
->kfree_on_online
[i
] = NULL
;
1485 if (x86_pmu
.cpu_dying
)
1486 x86_pmu
.cpu_dying(cpu
);
1489 case CPU_UP_CANCELED
:
1491 if (x86_pmu
.cpu_dead
)
1492 x86_pmu
.cpu_dead(cpu
);
1502 static void __init
pmu_check_apic(void)
1508 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1509 pr_info("no hardware sampling interrupt available.\n");
1512 * If we have a PMU initialized but no APIC
1513 * interrupts, we cannot sample hardware
1514 * events (user-space has to fall back and
1515 * sample via a hrtimer based software event):
1517 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1521 static struct attribute_group x86_pmu_format_group
= {
1527 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1528 * out of events_attr attributes.
1530 static void __init
filter_events(struct attribute
**attrs
)
1532 struct device_attribute
*d
;
1533 struct perf_pmu_events_attr
*pmu_attr
;
1536 for (i
= 0; attrs
[i
]; i
++) {
1537 d
= (struct device_attribute
*)attrs
[i
];
1538 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1540 if (pmu_attr
->event_str
)
1542 if (x86_pmu
.event_map(i
))
1545 for (j
= i
; attrs
[j
]; j
++)
1546 attrs
[j
] = attrs
[j
+ 1];
1548 /* Check the shifted attr. */
1553 /* Merge two pointer arrays */
1554 static __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1556 struct attribute
**new;
1559 for (j
= 0; a
[j
]; j
++)
1561 for (i
= 0; b
[i
]; i
++)
1565 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1570 for (i
= 0; a
[i
]; i
++)
1572 for (i
= 0; b
[i
]; i
++)
1579 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1582 struct perf_pmu_events_attr
*pmu_attr
= \
1583 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1584 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1586 /* string trumps id */
1587 if (pmu_attr
->event_str
)
1588 return sprintf(page
, "%s", pmu_attr
->event_str
);
1590 return x86_pmu
.events_sysfs_show(page
, config
);
1593 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1594 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1595 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1596 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1597 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1598 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1599 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1600 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1601 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1602 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1604 static struct attribute
*empty_attrs
;
1606 static struct attribute
*events_attr
[] = {
1607 EVENT_PTR(CPU_CYCLES
),
1608 EVENT_PTR(INSTRUCTIONS
),
1609 EVENT_PTR(CACHE_REFERENCES
),
1610 EVENT_PTR(CACHE_MISSES
),
1611 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1612 EVENT_PTR(BRANCH_MISSES
),
1613 EVENT_PTR(BUS_CYCLES
),
1614 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1615 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1616 EVENT_PTR(REF_CPU_CYCLES
),
1620 static struct attribute_group x86_pmu_events_group
= {
1622 .attrs
= events_attr
,
1625 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1627 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1628 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1629 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1630 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1631 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1632 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1636 * We have whole page size to spend and just little data
1637 * to write, so we can safely use sprintf.
1639 ret
= sprintf(page
, "event=0x%02llx", event
);
1642 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1645 ret
+= sprintf(page
+ ret
, ",edge");
1648 ret
+= sprintf(page
+ ret
, ",pc");
1651 ret
+= sprintf(page
+ ret
, ",any");
1654 ret
+= sprintf(page
+ ret
, ",inv");
1657 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1659 ret
+= sprintf(page
+ ret
, "\n");
1664 static int __init
init_hw_perf_events(void)
1666 struct x86_pmu_quirk
*quirk
;
1669 pr_info("Performance Events: ");
1671 switch (boot_cpu_data
.x86_vendor
) {
1672 case X86_VENDOR_INTEL
:
1673 err
= intel_pmu_init();
1675 case X86_VENDOR_AMD
:
1676 err
= amd_pmu_init();
1682 pr_cont("no PMU driver, software events only.\n");
1688 /* sanity check that the hardware exists or is emulated */
1689 if (!check_hw_exists())
1692 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1694 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1696 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1699 if (!x86_pmu
.intel_ctrl
)
1700 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1702 perf_events_lapic_init();
1703 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1705 unconstrained
= (struct event_constraint
)
1706 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1707 0, x86_pmu
.num_counters
, 0, 0);
1709 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1711 if (x86_pmu
.event_attrs
)
1712 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1714 if (!x86_pmu
.events_sysfs_show
)
1715 x86_pmu_events_group
.attrs
= &empty_attrs
;
1717 filter_events(x86_pmu_events_group
.attrs
);
1719 if (x86_pmu
.cpu_events
) {
1720 struct attribute
**tmp
;
1722 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1724 x86_pmu_events_group
.attrs
= tmp
;
1727 pr_info("... version: %d\n", x86_pmu
.version
);
1728 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1729 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1730 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1731 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1732 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1733 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1735 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1736 perf_cpu_notifier(x86_pmu_notifier
);
1740 early_initcall(init_hw_perf_events
);
1742 static inline void x86_pmu_read(struct perf_event
*event
)
1744 x86_perf_event_update(event
);
1748 * Start group events scheduling transaction
1749 * Set the flag to make pmu::enable() not perform the
1750 * schedulability test, it will be performed at commit time
1752 static void x86_pmu_start_txn(struct pmu
*pmu
)
1754 perf_pmu_disable(pmu
);
1755 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1756 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1760 * Stop group events scheduling transaction
1761 * Clear the flag and pmu::enable() will perform the
1762 * schedulability test.
1764 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1766 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1768 * Truncate collected array by the number of events added in this
1769 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1771 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1772 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1773 perf_pmu_enable(pmu
);
1777 * Commit group events scheduling transaction
1778 * Perform the group schedulability test as a whole
1779 * Return 0 if success
1781 * Does not cancel the transaction on failure; expects the caller to do this.
1783 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1785 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1786 int assign
[X86_PMC_IDX_MAX
];
1791 if (!x86_pmu_initialized())
1794 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1799 * copy new assignment, now we know it is possible
1800 * will be used by hw_perf_enable()
1802 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1804 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1805 perf_pmu_enable(pmu
);
1809 * a fake_cpuc is used to validate event groups. Due to
1810 * the extra reg logic, we need to also allocate a fake
1811 * per_core and per_cpu structure. Otherwise, group events
1812 * using extra reg may conflict without the kernel being
1813 * able to catch this when the last event gets added to
1816 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1818 kfree(cpuc
->shared_regs
);
1822 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1824 struct cpu_hw_events
*cpuc
;
1825 int cpu
= raw_smp_processor_id();
1827 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1829 return ERR_PTR(-ENOMEM
);
1831 /* only needed, if we have extra_regs */
1832 if (x86_pmu
.extra_regs
) {
1833 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1834 if (!cpuc
->shared_regs
)
1840 free_fake_cpuc(cpuc
);
1841 return ERR_PTR(-ENOMEM
);
1845 * validate that we can schedule this event
1847 static int validate_event(struct perf_event
*event
)
1849 struct cpu_hw_events
*fake_cpuc
;
1850 struct event_constraint
*c
;
1853 fake_cpuc
= allocate_fake_cpuc();
1854 if (IS_ERR(fake_cpuc
))
1855 return PTR_ERR(fake_cpuc
);
1857 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
1859 if (!c
|| !c
->weight
)
1862 if (x86_pmu
.put_event_constraints
)
1863 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1865 free_fake_cpuc(fake_cpuc
);
1871 * validate a single event group
1873 * validation include:
1874 * - check events are compatible which each other
1875 * - events do not compete for the same counter
1876 * - number of events <= number of counters
1878 * validation ensures the group can be loaded onto the
1879 * PMU if it was the only group available.
1881 static int validate_group(struct perf_event
*event
)
1883 struct perf_event
*leader
= event
->group_leader
;
1884 struct cpu_hw_events
*fake_cpuc
;
1885 int ret
= -EINVAL
, n
;
1887 fake_cpuc
= allocate_fake_cpuc();
1888 if (IS_ERR(fake_cpuc
))
1889 return PTR_ERR(fake_cpuc
);
1891 * the event is not yet connected with its
1892 * siblings therefore we must first collect
1893 * existing siblings, then add the new event
1894 * before we can simulate the scheduling
1896 n
= collect_events(fake_cpuc
, leader
, true);
1900 fake_cpuc
->n_events
= n
;
1901 n
= collect_events(fake_cpuc
, event
, false);
1905 fake_cpuc
->n_events
= n
;
1907 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1910 free_fake_cpuc(fake_cpuc
);
1914 static int x86_pmu_event_init(struct perf_event
*event
)
1919 switch (event
->attr
.type
) {
1921 case PERF_TYPE_HARDWARE
:
1922 case PERF_TYPE_HW_CACHE
:
1929 err
= __x86_pmu_event_init(event
);
1932 * we temporarily connect event to its pmu
1933 * such that validate_group() can classify
1934 * it as an x86 event using is_x86_event()
1939 if (event
->group_leader
!= event
)
1940 err
= validate_group(event
);
1942 err
= validate_event(event
);
1948 event
->destroy(event
);
1951 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
1952 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
1957 static void refresh_pce(void *ignored
)
1960 load_mm_cr4(current
->mm
);
1963 static void x86_pmu_event_mapped(struct perf_event
*event
)
1965 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1968 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
1969 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1972 static void x86_pmu_event_unmapped(struct perf_event
*event
)
1977 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1980 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
1981 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1984 static int x86_pmu_event_idx(struct perf_event
*event
)
1986 int idx
= event
->hw
.idx
;
1988 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1991 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
1992 idx
-= INTEL_PMC_IDX_FIXED
;
1999 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2000 struct device_attribute
*attr
,
2003 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2006 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2007 struct device_attribute
*attr
,
2008 const char *buf
, size_t count
)
2013 ret
= kstrtoul(buf
, 0, &val
);
2020 if (x86_pmu
.attr_rdpmc_broken
)
2023 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2025 * Changing into or out of always available, aka
2026 * perf-event-bypassing mode. This path is extremely slow,
2027 * but only root can trigger it, so it's okay.
2030 static_key_slow_inc(&rdpmc_always_available
);
2032 static_key_slow_dec(&rdpmc_always_available
);
2033 on_each_cpu(refresh_pce
, NULL
, 1);
2036 x86_pmu
.attr_rdpmc
= val
;
2041 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2043 static struct attribute
*x86_pmu_attrs
[] = {
2044 &dev_attr_rdpmc
.attr
,
2048 static struct attribute_group x86_pmu_attr_group
= {
2049 .attrs
= x86_pmu_attrs
,
2052 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2053 &x86_pmu_attr_group
,
2054 &x86_pmu_format_group
,
2055 &x86_pmu_events_group
,
2059 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2061 if (x86_pmu
.sched_task
)
2062 x86_pmu
.sched_task(ctx
, sched_in
);
2065 void perf_check_microcode(void)
2067 if (x86_pmu
.check_microcode
)
2068 x86_pmu
.check_microcode();
2070 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2072 static struct pmu pmu
= {
2073 .pmu_enable
= x86_pmu_enable
,
2074 .pmu_disable
= x86_pmu_disable
,
2076 .attr_groups
= x86_pmu_attr_groups
,
2078 .event_init
= x86_pmu_event_init
,
2080 .event_mapped
= x86_pmu_event_mapped
,
2081 .event_unmapped
= x86_pmu_event_unmapped
,
2085 .start
= x86_pmu_start
,
2086 .stop
= x86_pmu_stop
,
2087 .read
= x86_pmu_read
,
2089 .start_txn
= x86_pmu_start_txn
,
2090 .cancel_txn
= x86_pmu_cancel_txn
,
2091 .commit_txn
= x86_pmu_commit_txn
,
2093 .event_idx
= x86_pmu_event_idx
,
2094 .sched_task
= x86_pmu_sched_task
,
2095 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2098 void arch_perf_update_userpage(struct perf_event
*event
,
2099 struct perf_event_mmap_page
*userpg
, u64 now
)
2101 struct cyc2ns_data
*data
;
2103 userpg
->cap_user_time
= 0;
2104 userpg
->cap_user_time_zero
= 0;
2105 userpg
->cap_user_rdpmc
=
2106 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2107 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2109 if (!sched_clock_stable())
2112 data
= cyc2ns_read_begin();
2115 * Internal timekeeping for enabled/running/stopped times
2116 * is always in the local_clock domain.
2118 userpg
->cap_user_time
= 1;
2119 userpg
->time_mult
= data
->cyc2ns_mul
;
2120 userpg
->time_shift
= data
->cyc2ns_shift
;
2121 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2124 * cap_user_time_zero doesn't make sense when we're using a different
2125 * time base for the records.
2127 if (event
->clock
== &local_clock
) {
2128 userpg
->cap_user_time_zero
= 1;
2129 userpg
->time_zero
= data
->cyc2ns_offset
;
2132 cyc2ns_read_end(data
);
2139 static int backtrace_stack(void *data
, char *name
)
2144 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
2146 struct perf_callchain_entry
*entry
= data
;
2148 perf_callchain_store(entry
, addr
);
2151 static const struct stacktrace_ops backtrace_ops
= {
2152 .stack
= backtrace_stack
,
2153 .address
= backtrace_address
,
2154 .walk_stack
= print_context_stack_bp
,
2158 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2160 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2161 /* TODO: We don't support guest os callchain now */
2165 perf_callchain_store(entry
, regs
->ip
);
2167 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2171 valid_user_frame(const void __user
*fp
, unsigned long size
)
2173 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2176 static unsigned long get_segment_base(unsigned int segment
)
2178 struct desc_struct
*desc
;
2179 int idx
= segment
>> 3;
2181 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2182 struct ldt_struct
*ldt
;
2184 if (idx
> LDT_ENTRIES
)
2187 /* IRQs are off, so this synchronizes with smp_store_release */
2188 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2189 if (!ldt
|| idx
> ldt
->size
)
2192 desc
= &ldt
->entries
[idx
];
2194 if (idx
> GDT_ENTRIES
)
2197 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2200 return get_desc_base(desc
);
2203 #ifdef CONFIG_COMPAT
2205 #include <asm/compat.h>
2208 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2210 /* 32-bit process in 64-bit kernel. */
2211 unsigned long ss_base
, cs_base
;
2212 struct stack_frame_ia32 frame
;
2213 const void __user
*fp
;
2215 if (!test_thread_flag(TIF_IA32
))
2218 cs_base
= get_segment_base(regs
->cs
);
2219 ss_base
= get_segment_base(regs
->ss
);
2221 fp
= compat_ptr(ss_base
+ regs
->bp
);
2222 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2223 unsigned long bytes
;
2224 frame
.next_frame
= 0;
2225 frame
.return_address
= 0;
2227 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2231 if (!valid_user_frame(fp
, sizeof(frame
)))
2234 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2235 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2241 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2248 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2250 struct stack_frame frame
;
2251 const void __user
*fp
;
2253 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2254 /* TODO: We don't support guest os callchain now */
2259 * We don't know what to do with VM86 stacks.. ignore them for now.
2261 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2264 fp
= (void __user
*)regs
->bp
;
2266 perf_callchain_store(entry
, regs
->ip
);
2271 if (perf_callchain_user32(regs
, entry
))
2274 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2275 unsigned long bytes
;
2276 frame
.next_frame
= NULL
;
2277 frame
.return_address
= 0;
2279 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2283 if (!valid_user_frame(fp
, sizeof(frame
)))
2286 perf_callchain_store(entry
, frame
.return_address
);
2287 fp
= frame
.next_frame
;
2292 * Deal with code segment offsets for the various execution modes:
2294 * VM86 - the good olde 16 bit days, where the linear address is
2295 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2297 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2298 * to figure out what the 32bit base address is.
2300 * X32 - has TIF_X32 set, but is running in x86_64
2302 * X86_64 - CS,DS,SS,ES are all zero based.
2304 static unsigned long code_segment_base(struct pt_regs
*regs
)
2307 * For IA32 we look at the GDT/LDT segment base to convert the
2308 * effective IP to a linear address.
2311 #ifdef CONFIG_X86_32
2313 * If we are in VM86 mode, add the segment offset to convert to a
2316 if (regs
->flags
& X86_VM_MASK
)
2317 return 0x10 * regs
->cs
;
2319 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2320 return get_segment_base(regs
->cs
);
2322 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2323 regs
->cs
!= __USER32_CS
)
2324 return get_segment_base(regs
->cs
);
2329 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2331 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2332 return perf_guest_cbs
->get_guest_ip();
2334 return regs
->ip
+ code_segment_base(regs
);
2337 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2341 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2342 if (perf_guest_cbs
->is_user_mode())
2343 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2345 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2347 if (user_mode(regs
))
2348 misc
|= PERF_RECORD_MISC_USER
;
2350 misc
|= PERF_RECORD_MISC_KERNEL
;
2353 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2354 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2359 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2361 cap
->version
= x86_pmu
.version
;
2362 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2363 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2364 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2365 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2366 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2367 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2369 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);