2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 #define wrmsrl(msr, val) \
21 unsigned int _msr = (msr); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
44 EXTRA_REG_NONE
= -1, /* not used */
46 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
48 EXTRA_REG_LBR
= 2, /* lbr_select */
50 EXTRA_REG_MAX
/* number of entries needed */
53 struct event_constraint
{
55 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
65 int nb_id
; /* NorthBridge id */
66 int refcnt
; /* reference count */
67 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
68 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
71 /* The maximal number of PEBS events: */
72 #define MAX_PEBS_EVENTS 8
75 * A debug store configuration.
77 * We only support architectures that use 64bit fields.
82 u64 bts_absolute_maximum
;
83 u64 bts_interrupt_threshold
;
86 u64 pebs_absolute_maximum
;
87 u64 pebs_interrupt_threshold
;
88 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
95 raw_spinlock_t lock
; /* per-core: protect structure */
96 u64 config
; /* extra MSR config */
97 u64 reg
; /* extra MSR number */
98 atomic_t ref
; /* reference count */
104 * Used to coordinate shared registers between HT threads or
105 * among events on a single PMU.
107 struct intel_shared_regs
{
108 struct er_account regs
[EXTRA_REG_MAX
];
109 int refcnt
; /* per-core: #HT threads */
110 unsigned core_id
; /* per-core: core id */
113 #define MAX_LBR_ENTRIES 16
115 struct cpu_hw_events
{
117 * Generic x86 PMC bits
119 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
120 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
121 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
127 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
128 u64 tags
[X86_PMC_IDX_MAX
];
129 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
131 unsigned int group_flag
;
135 * Intel DebugStore bits
137 struct debug_store
*ds
;
145 struct perf_branch_stack lbr_stack
;
146 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
147 struct er_account
*lbr_sel
;
151 * Intel host/guest exclude bits
153 u64 intel_ctrl_guest_mask
;
154 u64 intel_ctrl_host_mask
;
155 struct perf_guest_switch_msr guest_switch_msrs
[X86_PMC_IDX_MAX
];
158 * manage shared (per-core, per-cpu) registers
159 * used on Intel NHM/WSM/SNB
161 struct intel_shared_regs
*shared_regs
;
166 struct amd_nb
*amd_nb
;
167 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
168 u64 perf_ctr_virt_mask
;
170 void *kfree_on_online
;
173 #define __EVENT_CONSTRAINT(c, n, m, w, o) {\
174 { .idxmsk64 = (n) }, \
181 #define EVENT_CONSTRAINT(c, n, m) \
182 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
185 * The overlap flag marks event constraints with overlapping counter
186 * masks. This is the case if the counter mask of such an event is not
187 * a subset of any other counter mask of a constraint with an equal or
188 * higher weight, e.g.:
190 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
191 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
192 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
194 * The event scheduler may not select the correct counter in the first
195 * cycle because it needs to know which subsequent events will be
196 * scheduled. It may fail to schedule the events then. So we set the
197 * overlap flag for such constraints to give the scheduler a hint which
198 * events to select for counter rescheduling.
200 * Care must be taken as the rescheduling algorithm is O(n!) which
201 * will increase scheduling cycles for an over-commited system
202 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
203 * and its counter masks must be kept at a minimum.
205 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
206 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
209 * Constraint on the Event code.
211 #define INTEL_EVENT_CONSTRAINT(c, n) \
212 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
215 * Constraint on the Event code + UMask + fixed-mask
217 * filter mask to validate fixed counter events.
218 * the following filters disqualify for fixed counters:
222 * The other filters are supported by fixed counters.
223 * The any-thread option is supported starting with v3.
225 #define FIXED_EVENT_CONSTRAINT(c, n) \
226 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
229 * Constraint on the Event code + UMask
231 #define INTEL_UEVENT_CONSTRAINT(c, n) \
232 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
234 #define EVENT_CONSTRAINT_END \
235 EVENT_CONSTRAINT(0, 0, 0)
237 #define for_each_event_constraint(e, c) \
238 for ((e) = (c); (e)->weight; (e)++)
241 * Extra registers for specific events.
243 * Some events need large masks and require external MSRs.
244 * Those extra MSRs end up being shared for all events on
245 * a PMU and sometimes between PMU of sibling HT threads.
246 * In either case, the kernel needs to handle conflicting
247 * accesses to those extra, shared, regs. The data structure
248 * to manage those registers is stored in cpu_hw_event.
255 int idx
; /* per_xxx->regs[] reg index */
258 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
261 .config_mask = (m), \
262 .valid_mask = (vm), \
263 .idx = EXTRA_REG_##i \
266 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
267 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
269 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
271 union perf_capabilities
{
282 struct x86_pmu_quirk
{
283 struct x86_pmu_quirk
*next
;
287 union x86_pmu_config
{
308 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
311 * struct x86_pmu - generic x86 pmu
315 * Generic x86 PMC bits
319 int (*handle_irq
)(struct pt_regs
*);
320 void (*disable_all
)(void);
321 void (*enable_all
)(int added
);
322 void (*enable
)(struct perf_event
*);
323 void (*disable
)(struct perf_event
*);
324 int (*hw_config
)(struct perf_event
*event
);
325 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
328 int (*addr_offset
)(int index
, bool eventsel
);
329 int (*rdpmc_index
)(int index
);
330 u64 (*event_map
)(int);
333 int num_counters_fixed
;
337 unsigned long events_maskl
;
338 unsigned long events_mask
[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT
)];
343 struct event_constraint
*
344 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
345 struct perf_event
*event
);
347 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
348 struct perf_event
*event
);
349 struct event_constraint
*event_constraints
;
350 struct x86_pmu_quirk
*quirks
;
351 int perfctr_second_write
;
357 struct attribute
**format_attrs
;
359 ssize_t (*events_sysfs_show
)(char *page
, u64 config
);
364 int (*cpu_prepare
)(int cpu
);
365 void (*cpu_starting
)(int cpu
);
366 void (*cpu_dying
)(int cpu
);
367 void (*cpu_dead
)(int cpu
);
369 void (*check_microcode
)(void);
370 void (*flush_branch_stack
)(void);
373 * Intel Arch Perfmon v2+
376 union perf_capabilities intel_cap
;
379 * Intel DebugStore bits
386 int pebs_record_size
;
387 void (*drain_pebs
)(struct pt_regs
*regs
);
388 struct event_constraint
*pebs_constraints
;
389 void (*pebs_aliases
)(struct perf_event
*event
);
395 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
396 int lbr_nr
; /* hardware stack size */
397 u64 lbr_sel_mask
; /* LBR_SELECT valid bits */
398 const int *lbr_sel_map
; /* lbr_select mappings */
401 * Extra registers for events
403 struct extra_reg
*extra_regs
;
404 unsigned int er_flags
;
407 * Intel host/guest support (KVM)
409 struct perf_guest_switch_msr
*(*guest_get_msrs
)(int *nr
);
412 #define x86_add_quirk(func_) \
414 static struct x86_pmu_quirk __quirk __initdata = { \
417 __quirk.next = x86_pmu.quirks; \
418 x86_pmu.quirks = &__quirk; \
421 #define ERF_NO_HT_SHARING 1
422 #define ERF_HAS_RSP_1 2
424 extern struct x86_pmu x86_pmu __read_mostly
;
426 DECLARE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
428 int x86_perf_event_set_period(struct perf_event
*event
);
431 * Generalized hw caching related hw_event table, filled
432 * in on a per model basis. A value of 0 means
433 * 'not supported', -1 means 'hw_event makes no sense on
434 * this CPU', any other value means the raw hw_event
438 #define C(x) PERF_COUNT_HW_CACHE_##x
440 extern u64 __read_mostly hw_cache_event_ids
441 [PERF_COUNT_HW_CACHE_MAX
]
442 [PERF_COUNT_HW_CACHE_OP_MAX
]
443 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
444 extern u64 __read_mostly hw_cache_extra_regs
445 [PERF_COUNT_HW_CACHE_MAX
]
446 [PERF_COUNT_HW_CACHE_OP_MAX
]
447 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
449 u64
x86_perf_event_update(struct perf_event
*event
);
451 static inline unsigned int x86_pmu_config_addr(int index
)
453 return x86_pmu
.eventsel
+ (x86_pmu
.addr_offset
?
454 x86_pmu
.addr_offset(index
, true) : index
);
457 static inline unsigned int x86_pmu_event_addr(int index
)
459 return x86_pmu
.perfctr
+ (x86_pmu
.addr_offset
?
460 x86_pmu
.addr_offset(index
, false) : index
);
463 static inline int x86_pmu_rdpmc_index(int index
)
465 return x86_pmu
.rdpmc_index
? x86_pmu
.rdpmc_index(index
) : index
;
468 int x86_setup_perfctr(struct perf_event
*event
);
470 int x86_pmu_hw_config(struct perf_event
*event
);
472 void x86_pmu_disable_all(void);
474 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
477 u64 disable_mask
= __this_cpu_read(cpu_hw_events
.perf_ctr_virt_mask
);
479 if (hwc
->extra_reg
.reg
)
480 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
481 wrmsrl(hwc
->config_base
, (hwc
->config
| enable_mask
) & ~disable_mask
);
484 void x86_pmu_enable_all(int added
);
486 int perf_assign_events(struct event_constraint
**constraints
, int n
,
487 int wmin
, int wmax
, int *assign
);
488 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
490 void x86_pmu_stop(struct perf_event
*event
, int flags
);
492 static inline void x86_pmu_disable_event(struct perf_event
*event
)
494 struct hw_perf_event
*hwc
= &event
->hw
;
496 wrmsrl(hwc
->config_base
, hwc
->config
);
499 void x86_pmu_enable_event(struct perf_event
*event
);
501 int x86_pmu_handle_irq(struct pt_regs
*regs
);
503 extern struct event_constraint emptyconstraint
;
505 extern struct event_constraint unconstrained
;
507 static inline bool kernel_ip(unsigned long ip
)
510 return ip
> PAGE_OFFSET
;
517 * Not all PMUs provide the right context information to place the reported IP
518 * into full context. Specifically segment registers are typically not
521 * Assuming the address is a linear address (it is for IBS), we fake the CS and
522 * vm86 mode using the known zero-based code segment and 'fix up' the registers
525 * Intel PEBS/LBR appear to typically provide the effective address, nothing
526 * much we can do about that but pray and treat it like a linear address.
528 static inline void set_linear_ip(struct pt_regs
*regs
, unsigned long ip
)
530 regs
->cs
= kernel_ip(ip
) ? __KERNEL_CS
: __USER_CS
;
531 if (regs
->flags
& X86_VM_MASK
)
532 regs
->flags
^= (PERF_EFLAGS_VM
| X86_VM_MASK
);
536 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
);
537 ssize_t
intel_event_sysfs_show(char *page
, u64 config
);
539 #ifdef CONFIG_CPU_SUP_AMD
541 int amd_pmu_init(void);
543 #else /* CONFIG_CPU_SUP_AMD */
545 static inline int amd_pmu_init(void)
550 #endif /* CONFIG_CPU_SUP_AMD */
552 #ifdef CONFIG_CPU_SUP_INTEL
554 int intel_pmu_save_and_restart(struct perf_event
*event
);
556 struct event_constraint
*
557 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
);
559 struct intel_shared_regs
*allocate_shared_regs(int cpu
);
561 int intel_pmu_init(void);
563 void init_debug_store_on_cpu(int cpu
);
565 void fini_debug_store_on_cpu(int cpu
);
567 void release_ds_buffers(void);
569 void reserve_ds_buffers(void);
571 extern struct event_constraint bts_constraint
;
573 void intel_pmu_enable_bts(u64 config
);
575 void intel_pmu_disable_bts(void);
577 int intel_pmu_drain_bts_buffer(void);
579 extern struct event_constraint intel_core2_pebs_event_constraints
[];
581 extern struct event_constraint intel_atom_pebs_event_constraints
[];
583 extern struct event_constraint intel_nehalem_pebs_event_constraints
[];
585 extern struct event_constraint intel_westmere_pebs_event_constraints
[];
587 extern struct event_constraint intel_snb_pebs_event_constraints
[];
589 extern struct event_constraint intel_ivb_pebs_event_constraints
[];
591 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
);
593 void intel_pmu_pebs_enable(struct perf_event
*event
);
595 void intel_pmu_pebs_disable(struct perf_event
*event
);
597 void intel_pmu_pebs_enable_all(void);
599 void intel_pmu_pebs_disable_all(void);
601 void intel_ds_init(void);
603 void intel_pmu_lbr_reset(void);
605 void intel_pmu_lbr_enable(struct perf_event
*event
);
607 void intel_pmu_lbr_disable(struct perf_event
*event
);
609 void intel_pmu_lbr_enable_all(void);
611 void intel_pmu_lbr_disable_all(void);
613 void intel_pmu_lbr_read(void);
615 void intel_pmu_lbr_init_core(void);
617 void intel_pmu_lbr_init_nhm(void);
619 void intel_pmu_lbr_init_atom(void);
621 void intel_pmu_lbr_init_snb(void);
623 int intel_pmu_setup_lbr_filter(struct perf_event
*event
);
625 int p4_pmu_init(void);
627 int p6_pmu_init(void);
629 int knc_pmu_init(void);
631 #else /* CONFIG_CPU_SUP_INTEL */
633 static inline void reserve_ds_buffers(void)
637 static inline void release_ds_buffers(void)
641 static inline int intel_pmu_init(void)
646 static inline struct intel_shared_regs
*allocate_shared_regs(int cpu
)
651 #endif /* CONFIG_CPU_SUP_INTEL */