arch/x86/kernel/cpu/perf_event.h

   1 /*
   2  * Performance events x86 architecture header
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16
  17 #if 0
  18 #undef wrmsrl
  19 #define wrmsrl(msr, val)                                                \
  20 do {                                                                    \
  21         unsigned int _msr = (msr);                                      \
  22         u64 _val = (val);                                               \
  23         trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr),         \
  24                         (unsigned long long)(_val));                    \
  25         native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32));       \
  26 } while (0)
  27 #endif
  28
  29 /*
  30  *          |   NHM/WSM    |      SNB     |
  31  * register -------------------------------
  32  *          |  HT  | no HT |  HT  | no HT |
  33  *-----------------------------------------
  34  * offcore  | core | core  | cpu  | core  |
  35  * lbr_sel  | core | core  | cpu  | core  |
  36  * ld_lat   | cpu  | core  | cpu  | core  |
  37  *-----------------------------------------
  38  *
  39  * Given that there is a small number of shared regs,
  40  * we can pre-allocate their slot in the per-cpu
  41  * per-core reg tables.
  42  */
  43 enum extra_reg_type {
  44         EXTRA_REG_NONE  = -1,   /* not used */
  45
  46         EXTRA_REG_RSP_0 = 0,    /* offcore_response_0 */
  47         EXTRA_REG_RSP_1 = 1,    /* offcore_response_1 */
  48         EXTRA_REG_LBR   = 2,    /* lbr_select */
  49         EXTRA_REG_LDLAT = 3,    /* ld_lat_threshold */
  50
  51         EXTRA_REG_MAX           /* number of entries needed */
  52 };
  53
  54 struct event_constraint {
  55         union {
  56                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  57                 u64             idxmsk64;
  58         };
  59         u64     code;
  60         u64     cmask;
  61         int     weight;
  62         int     overlap;
  63         int     flags;
  64 };
  65 /*
  66  * struct hw_perf_event.flags flags
  67  */
  68 #define PERF_X86_EVENT_PEBS_LDLAT       0x1 /* ld+ldlat data address sampling */
  69 #define PERF_X86_EVENT_PEBS_ST          0x2 /* st data address sampling */
  70 #define PERF_X86_EVENT_PEBS_ST_HSW      0x4 /* haswell style st data sampling */
  71 #define PERF_X86_EVENT_COMMITTED        0x8 /* event passed commit_txn */
  72
  73 struct amd_nb {
  74         int nb_id;  /* NorthBridge id */
  75         int refcnt; /* reference count */
  76         struct perf_event *owners[X86_PMC_IDX_MAX];
  77         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  78 };
  79
  80 /* The maximal number of PEBS events: */
  81 #define MAX_PEBS_EVENTS         8
  82
  83 /*
  84  * A debug store configuration.
  85  *
  86  * We only support architectures that use 64bit fields.
  87  */
  88 struct debug_store {
  89         u64     bts_buffer_base;
  90         u64     bts_index;
  91         u64     bts_absolute_maximum;
  92         u64     bts_interrupt_threshold;
  93         u64     pebs_buffer_base;
  94         u64     pebs_index;
  95         u64     pebs_absolute_maximum;
  96         u64     pebs_interrupt_threshold;
  97         u64     pebs_event_reset[MAX_PEBS_EVENTS];
  98 };
  99
 100 /*
 101  * Per register state.
 102  */
 103 struct er_account {
 104         raw_spinlock_t          lock;   /* per-core: protect structure */
 105         u64                 config;     /* extra MSR config */
 106         u64                 reg;        /* extra MSR number */
 107         atomic_t            ref;        /* reference count */
 108 };
 109
 110 /*
 111  * Per core/cpu state
 112  *
 113  * Used to coordinate shared registers between HT threads or
 114  * among events on a single PMU.
 115  */
 116 struct intel_shared_regs {
 117         struct er_account       regs[EXTRA_REG_MAX];
 118         int                     refcnt;         /* per-core: #HT threads */
 119         unsigned                core_id;        /* per-core: core id */
 120 };
 121
 122 #define MAX_LBR_ENTRIES         16
 123
 124 struct cpu_hw_events {
 125         /*
 126          * Generic x86 PMC bits
 127          */
 128         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 129         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 130         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 131         int                     enabled;
 132
 133         int                     n_events;
 134         int                     n_added;
 135         int                     n_txn;
 136         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 137         u64                     tags[X86_PMC_IDX_MAX];
 138         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 139
 140         unsigned int            group_flag;
 141         int                     is_fake;
 142
 143         /*
 144          * Intel DebugStore bits
 145          */
 146         struct debug_store      *ds;
 147         u64                     pebs_enabled;
 148
 149         /*
 150          * Intel LBR bits
 151          */
 152         int                             lbr_users;
 153         void                            *lbr_context;
 154         struct perf_branch_stack        lbr_stack;
 155         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 156         struct er_account               *lbr_sel;
 157         u64                             br_sel;
 158
 159         /*
 160          * Intel host/guest exclude bits
 161          */
 162         u64                             intel_ctrl_guest_mask;
 163         u64                             intel_ctrl_host_mask;
 164         struct perf_guest_switch_msr    guest_switch_msrs[X86_PMC_IDX_MAX];
 165
 166         /*
 167          * Intel checkpoint mask
 168          */
 169         u64                             intel_cp_status;
 170
 171         /*
 172          * manage shared (per-core, per-cpu) registers
 173          * used on Intel NHM/WSM/SNB
 174          */
 175         struct intel_shared_regs        *shared_regs;
 176
 177         /*
 178          * AMD specific bits
 179          */
 180         struct amd_nb                   *amd_nb;
 181         /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
 182         u64                             perf_ctr_virt_mask;
 183
 184         void                            *kfree_on_online;
 185 };
 186
 187 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
 188         { .idxmsk64 = (n) },            \
 189         .code = (c),                    \
 190         .cmask = (m),                   \
 191         .weight = (w),                  \
 192         .overlap = (o),                 \
 193         .flags = f,                     \
 194 }
 195
 196 #define EVENT_CONSTRAINT(c, n, m)       \
 197         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
 198
 199 /*
 200  * The overlap flag marks event constraints with overlapping counter
 201  * masks. This is the case if the counter mask of such an event is not
 202  * a subset of any other counter mask of a constraint with an equal or
 203  * higher weight, e.g.:
 204  *
 205  *  c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 206  *  c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
 207  *  c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
 208  *
 209  * The event scheduler may not select the correct counter in the first
 210  * cycle because it needs to know which subsequent events will be
 211  * scheduled. It may fail to schedule the events then. So we set the
 212  * overlap flag for such constraints to give the scheduler a hint which
 213  * events to select for counter rescheduling.
 214  *
 215  * Care must be taken as the rescheduling algorithm is O(n!) which
 216  * will increase scheduling cycles for an over-commited system
 217  * dramatically.  The number of such EVENT_CONSTRAINT_OVERLAP() macros
 218  * and its counter masks must be kept at a minimum.
 219  */
 220 #define EVENT_CONSTRAINT_OVERLAP(c, n, m)       \
 221         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
 222
 223 /*
 224  * Constraint on the Event code.
 225  */
 226 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 227         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 228
 229 /*
 230  * Constraint on the Event code + UMask + fixed-mask
 231  *
 232  * filter mask to validate fixed counter events.
 233  * the following filters disqualify for fixed counters:
 234  *  - inv
 235  *  - edge
 236  *  - cnt-mask
 237  *  - in_tx
 238  *  - in_tx_checkpointed
 239  *  The other filters are supported by fixed counters.
 240  *  The any-thread option is supported starting with v3.
 241  */
 242 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
 243 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 244         EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
 245
 246 /*
 247  * Constraint on the Event code + UMask
 248  */
 249 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 250         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 251
 252 #define INTEL_PLD_CONSTRAINT(c, n)      \
 253         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 254                            HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
 255
 256 #define INTEL_PST_CONSTRAINT(c, n)      \
 257         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 258                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 259
 260 /* DataLA version of store sampling without extra enable bit. */
 261 #define INTEL_PST_HSW_CONSTRAINT(c, n)  \
 262         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
 263                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
 264
 265 /*
 266  * We define the end marker as having a weight of -1
 267  * to enable blacklisting of events using a counter bitmask
 268  * of zero and thus a weight of zero.
 269  * The end marker has a weight that cannot possibly be
 270  * obtained from counting the bits in the bitmask.
 271  */
 272 #define EVENT_CONSTRAINT_END { .weight = -1 }
 273
 274 /*
 275  * Check for end marker with weight == -1
 276  */
 277 #define for_each_event_constraint(e, c) \
 278         for ((e) = (c); (e)->weight != -1; (e)++)
 279
 280 /*
 281  * Extra registers for specific events.
 282  *
 283  * Some events need large masks and require external MSRs.
 284  * Those extra MSRs end up being shared for all events on
 285  * a PMU and sometimes between PMU of sibling HT threads.
 286  * In either case, the kernel needs to handle conflicting
 287  * accesses to those extra, shared, regs. The data structure
 288  * to manage those registers is stored in cpu_hw_event.
 289  */
 290 struct extra_reg {
 291         unsigned int            event;
 292         unsigned int            msr;
 293         u64                     config_mask;
 294         u64                     valid_mask;
 295         int                     idx;  /* per_xxx->regs[] reg index */
 296 };
 297
 298 #define EVENT_EXTRA_REG(e, ms, m, vm, i) {      \
 299         .event = (e),           \
 300         .msr = (ms),            \
 301         .config_mask = (m),     \
 302         .valid_mask = (vm),     \
 303         .idx = EXTRA_REG_##i,   \
 304         }
 305
 306 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)      \
 307         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
 308
 309 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
 310         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
 311                         ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
 312
 313 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
 314         INTEL_UEVENT_EXTRA_REG(c, \
 315                                MSR_PEBS_LD_LAT_THRESHOLD, \
 316                                0xffff, \
 317                                LDLAT)
 318
 319 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
 320
 321 union perf_capabilities {
 322         struct {
 323                 u64     lbr_format:6;
 324                 u64     pebs_trap:1;
 325                 u64     pebs_arch_reg:1;
 326                 u64     pebs_format:4;
 327                 u64     smm_freeze:1;
 328                 /*
 329                  * PMU supports separate counter range for writing
 330                  * values > 32bit.
 331                  */
 332                 u64     full_width_write:1;
 333         };
 334         u64     capabilities;
 335 };
 336
 337 struct x86_pmu_quirk {
 338         struct x86_pmu_quirk *next;
 339         void (*func)(void);
 340 };
 341
 342 union x86_pmu_config {
 343         struct {
 344                 u64 event:8,
 345                     umask:8,
 346                     usr:1,
 347                     os:1,
 348                     edge:1,
 349                     pc:1,
 350                     interrupt:1,
 351                     __reserved1:1,
 352                     en:1,
 353                     inv:1,
 354                     cmask:8,
 355                     event2:4,
 356                     __reserved2:4,
 357                     go:1,
 358                     ho:1;
 359         } bits;
 360         u64 value;
 361 };
 362
 363 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
 364
 365 /*
 366  * struct x86_pmu - generic x86 pmu
 367  */
 368 struct x86_pmu {
 369         /*
 370          * Generic x86 PMC bits
 371          */
 372         const char      *name;
 373         int             version;
 374         int             (*handle_irq)(struct pt_regs *);
 375         void            (*disable_all)(void);
 376         void            (*enable_all)(int added);
 377         void            (*enable)(struct perf_event *);
 378         void            (*disable)(struct perf_event *);
 379         int             (*hw_config)(struct perf_event *event);
 380         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 381         unsigned        eventsel;
 382         unsigned        perfctr;
 383         int             (*addr_offset)(int index, bool eventsel);
 384         int             (*rdpmc_index)(int index);
 385         u64             (*event_map)(int);
 386         int             max_events;
 387         int             num_counters;
 388         int             num_counters_fixed;
 389         int             cntval_bits;
 390         u64             cntval_mask;
 391         union {
 392                         unsigned long events_maskl;
 393                         unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
 394         };
 395         int             events_mask_len;
 396         int             apic;
 397         u64             max_period;
 398         struct event_constraint *
 399                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 400                                                  struct perf_event *event);
 401
 402         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 403                                                  struct perf_event *event);
 404         struct event_constraint *event_constraints;
 405         struct x86_pmu_quirk *quirks;
 406         int             perfctr_second_write;
 407         bool            late_ack;
 408
 409         /*
 410          * sysfs attrs
 411          */
 412         int             attr_rdpmc;
 413         struct attribute **format_attrs;
 414         struct attribute **event_attrs;
 415
 416         ssize_t         (*events_sysfs_show)(char *page, u64 config);
 417         struct attribute **cpu_events;
 418
 419         /*
 420          * CPU Hotplug hooks
 421          */
 422         int             (*cpu_prepare)(int cpu);
 423         void            (*cpu_starting)(int cpu);
 424         void            (*cpu_dying)(int cpu);
 425         void            (*cpu_dead)(int cpu);
 426
 427         void            (*check_microcode)(void);
 428         void            (*flush_branch_stack)(void);
 429
 430         /*
 431          * Intel Arch Perfmon v2+
 432          */
 433         u64                     intel_ctrl;
 434         union perf_capabilities intel_cap;
 435
 436         /*
 437          * Intel DebugStore bits
 438          */
 439         unsigned int    bts             :1,
 440                         bts_active      :1,
 441                         pebs            :1,
 442                         pebs_active     :1,
 443                         pebs_broken     :1;
 444         int             pebs_record_size;
 445         void            (*drain_pebs)(struct pt_regs *regs);
 446         struct event_constraint *pebs_constraints;
 447         void            (*pebs_aliases)(struct perf_event *event);
 448         int             max_pebs_events;
 449
 450         /*
 451          * Intel LBR
 452          */
 453         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 454         int             lbr_nr;                    /* hardware stack size */
 455         u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
 456         const int       *lbr_sel_map;              /* lbr_select mappings */
 457         bool            lbr_double_abort;          /* duplicated lbr aborts */
 458
 459         /*
 460          * Extra registers for events
 461          */
 462         struct extra_reg *extra_regs;
 463         unsigned int er_flags;
 464
 465         /*
 466          * Intel host/guest support (KVM)
 467          */
 468         struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
 469 };
 470
 471 #define x86_add_quirk(func_)                                            \
 472 do {                                                                    \
 473         static struct x86_pmu_quirk __quirk __initdata = {              \
 474                 .func = func_,                                          \
 475         };                                                              \
 476         __quirk.next = x86_pmu.quirks;                                  \
 477         x86_pmu.quirks = &__quirk;                                      \
 478 } while (0)
 479
 480 #define ERF_NO_HT_SHARING       1
 481 #define ERF_HAS_RSP_1           2
 482
 483 #define EVENT_VAR(_id)  event_attr_##_id
 484 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
 485
 486 #define EVENT_ATTR(_name, _id)                                          \
 487 static struct perf_pmu_events_attr EVENT_VAR(_id) = {                   \
 488         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 489         .id             = PERF_COUNT_HW_##_id,                          \
 490         .event_str      = NULL,                                         \
 491 };
 492
 493 #define EVENT_ATTR_STR(_name, v, str)                                   \
 494 static struct perf_pmu_events_attr event_attr_##v = {                   \
 495         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 496         .id             = 0,                                            \
 497         .event_str      = str,                                          \
 498 };
 499
 500 extern struct x86_pmu x86_pmu __read_mostly;
 501
 502 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 503
 504 int x86_perf_event_set_period(struct perf_event *event);
 505
 506 /*
 507  * Generalized hw caching related hw_event table, filled
 508  * in on a per model basis. A value of 0 means
 509  * 'not supported', -1 means 'hw_event makes no sense on
 510  * this CPU', any other value means the raw hw_event
 511  * ID.
 512  */
 513
 514 #define C(x) PERF_COUNT_HW_CACHE_##x
 515
 516 extern u64 __read_mostly hw_cache_event_ids
 517                                 [PERF_COUNT_HW_CACHE_MAX]
 518                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 519                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 520 extern u64 __read_mostly hw_cache_extra_regs
 521                                 [PERF_COUNT_HW_CACHE_MAX]
 522                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 523                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 524
 525 u64 x86_perf_event_update(struct perf_event *event);
 526
 527 static inline unsigned int x86_pmu_config_addr(int index)
 528 {
 529         return x86_pmu.eventsel + (x86_pmu.addr_offset ?
 530                                    x86_pmu.addr_offset(index, true) : index);
 531 }
 532
 533 static inline unsigned int x86_pmu_event_addr(int index)
 534 {
 535         return x86_pmu.perfctr + (x86_pmu.addr_offset ?
 536                                   x86_pmu.addr_offset(index, false) : index);
 537 }
 538
 539 static inline int x86_pmu_rdpmc_index(int index)
 540 {
 541         return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
 542 }
 543
 544 int x86_setup_perfctr(struct perf_event *event);
 545
 546 int x86_pmu_hw_config(struct perf_event *event);
 547
 548 void x86_pmu_disable_all(void);
 549
 550 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 551                                           u64 enable_mask)
 552 {
 553         u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
 554
 555         if (hwc->extra_reg.reg)
 556                 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
 557         wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
 558 }
 559
 560 void x86_pmu_enable_all(int added);
 561
 562 int perf_assign_events(struct perf_event **events, int n,
 563                         int wmin, int wmax, int *assign);
 564 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
 565
 566 void x86_pmu_stop(struct perf_event *event, int flags);
 567
 568 static inline void x86_pmu_disable_event(struct perf_event *event)
 569 {
 570         struct hw_perf_event *hwc = &event->hw;
 571
 572         wrmsrl(hwc->config_base, hwc->config);
 573 }
 574
 575 void x86_pmu_enable_event(struct perf_event *event);
 576
 577 int x86_pmu_handle_irq(struct pt_regs *regs);
 578
 579 extern struct event_constraint emptyconstraint;
 580
 581 extern struct event_constraint unconstrained;
 582
 583 static inline bool kernel_ip(unsigned long ip)
 584 {
 585 #ifdef CONFIG_X86_32
 586         return ip > PAGE_OFFSET;
 587 #else
 588         return (long)ip < 0;
 589 #endif
 590 }
 591
 592 /*
 593  * Not all PMUs provide the right context information to place the reported IP
 594  * into full context. Specifically segment registers are typically not
 595  * supplied.
 596  *
 597  * Assuming the address is a linear address (it is for IBS), we fake the CS and
 598  * vm86 mode using the known zero-based code segment and 'fix up' the registers
 599  * to reflect this.
 600  *
 601  * Intel PEBS/LBR appear to typically provide the effective address, nothing
 602  * much we can do about that but pray and treat it like a linear address.
 603  */
 604 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
 605 {
 606         regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
 607         if (regs->flags & X86_VM_MASK)
 608                 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
 609         regs->ip = ip;
 610 }
 611
 612 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
 613 ssize_t intel_event_sysfs_show(char *page, u64 config);
 614
 615 #ifdef CONFIG_CPU_SUP_AMD
 616
 617 int amd_pmu_init(void);
 618
 619 #else /* CONFIG_CPU_SUP_AMD */
 620
 621 static inline int amd_pmu_init(void)
 622 {
 623         return 0;
 624 }
 625
 626 #endif /* CONFIG_CPU_SUP_AMD */
 627
 628 #ifdef CONFIG_CPU_SUP_INTEL
 629
 630 int intel_pmu_save_and_restart(struct perf_event *event);
 631
 632 struct event_constraint *
 633 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
 634
 635 struct intel_shared_regs *allocate_shared_regs(int cpu);
 636
 637 int intel_pmu_init(void);
 638
 639 void init_debug_store_on_cpu(int cpu);
 640
 641 void fini_debug_store_on_cpu(int cpu);
 642
 643 void release_ds_buffers(void);
 644
 645 void reserve_ds_buffers(void);
 646
 647 extern struct event_constraint bts_constraint;
 648
 649 void intel_pmu_enable_bts(u64 config);
 650
 651 void intel_pmu_disable_bts(void);
 652
 653 int intel_pmu_drain_bts_buffer(void);
 654
 655 extern struct event_constraint intel_core2_pebs_event_constraints[];
 656
 657 extern struct event_constraint intel_atom_pebs_event_constraints[];
 658
 659 extern struct event_constraint intel_slm_pebs_event_constraints[];
 660
 661 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
 662
 663 extern struct event_constraint intel_westmere_pebs_event_constraints[];
 664
 665 extern struct event_constraint intel_snb_pebs_event_constraints[];
 666
 667 extern struct event_constraint intel_ivb_pebs_event_constraints[];
 668
 669 extern struct event_constraint intel_hsw_pebs_event_constraints[];
 670
 671 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
 672
 673 void intel_pmu_pebs_enable(struct perf_event *event);
 674
 675 void intel_pmu_pebs_disable(struct perf_event *event);
 676
 677 void intel_pmu_pebs_enable_all(void);
 678
 679 void intel_pmu_pebs_disable_all(void);
 680
 681 void intel_ds_init(void);
 682
 683 void intel_pmu_lbr_reset(void);
 684
 685 void intel_pmu_lbr_enable(struct perf_event *event);
 686
 687 void intel_pmu_lbr_disable(struct perf_event *event);
 688
 689 void intel_pmu_lbr_enable_all(void);
 690
 691 void intel_pmu_lbr_disable_all(void);
 692
 693 void intel_pmu_lbr_read(void);
 694
 695 void intel_pmu_lbr_init_core(void);
 696
 697 void intel_pmu_lbr_init_nhm(void);
 698
 699 void intel_pmu_lbr_init_atom(void);
 700
 701 void intel_pmu_lbr_init_snb(void);
 702
 703 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 704
 705 int p4_pmu_init(void);
 706
 707 int p6_pmu_init(void);
 708
 709 int knc_pmu_init(void);
 710
 711 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
 712                           char *page);
 713
 714 #else /* CONFIG_CPU_SUP_INTEL */
 715
 716 static inline void reserve_ds_buffers(void)
 717 {
 718 }
 719
 720 static inline void release_ds_buffers(void)
 721 {
 722 }
 723
 724 static inline int intel_pmu_init(void)
 725 {
 726         return 0;
 727 }
 728
 729 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
 730 {
 731         return NULL;
 732 }
 733
 734 #endif /* CONFIG_CPU_SUP_INTEL */