x86, apic: remove genapic.h
[deliverable/linux.git] / arch / x86 / kernel / genapic_flat_64.c
1 /*
2 * Copyright 2004 James Cleverdon, IBM.
3 * Subject to the GNU Public License, v.2
4 *
5 * Flat APIC subarch code.
6 *
7 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
8 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
9 * James Cleverdon.
10 */
11 #include <linux/errno.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/hardirq.h>
19 #include <asm/smp.h>
20 #include <asm/apic.h>
21 #include <asm/ipi.h>
22
23 #ifdef CONFIG_ACPI
24 #include <acpi/acpi_bus.h>
25 #endif
26
27 static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
28 {
29 return 1;
30 }
31
32 static const struct cpumask *flat_target_cpus(void)
33 {
34 return cpu_online_mask;
35 }
36
37 static void flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
38 {
39 /* Careful. Some cpus do not strictly honor the set of cpus
40 * specified in the interrupt destination when using lowest
41 * priority interrupt delivery mode.
42 *
43 * In particular there was a hyperthreading cpu observed to
44 * deliver interrupts to the wrong hyperthread when only one
45 * hyperthread was specified in the interrupt desitination.
46 */
47 cpumask_clear(retmask);
48 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
49 }
50
51 /*
52 * Set up the logical destination ID.
53 *
54 * Intel recommends to set DFR, LDR and TPR before enabling
55 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
56 * document number 292116). So here it goes...
57 */
58 static void flat_init_apic_ldr(void)
59 {
60 unsigned long val;
61 unsigned long num, id;
62
63 num = smp_processor_id();
64 id = 1UL << num;
65 apic_write(APIC_DFR, APIC_DFR_FLAT);
66 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
67 val |= SET_APIC_LOGICAL_ID(id);
68 apic_write(APIC_LDR, val);
69 }
70
71 static inline void _flat_send_IPI_mask(unsigned long mask, int vector)
72 {
73 unsigned long flags;
74
75 local_irq_save(flags);
76 __default_send_IPI_dest_field(mask, vector, apic->dest_logical);
77 local_irq_restore(flags);
78 }
79
80 static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector)
81 {
82 unsigned long mask = cpumask_bits(cpumask)[0];
83
84 _flat_send_IPI_mask(mask, vector);
85 }
86
87 static void
88 flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector)
89 {
90 unsigned long mask = cpumask_bits(cpumask)[0];
91 int cpu = smp_processor_id();
92
93 if (cpu < BITS_PER_LONG)
94 clear_bit(cpu, &mask);
95
96 _flat_send_IPI_mask(mask, vector);
97 }
98
99 static void flat_send_IPI_allbutself(int vector)
100 {
101 int cpu = smp_processor_id();
102 #ifdef CONFIG_HOTPLUG_CPU
103 int hotplug = 1;
104 #else
105 int hotplug = 0;
106 #endif
107 if (hotplug || vector == NMI_VECTOR) {
108 if (!cpumask_equal(cpu_online_mask, cpumask_of(cpu))) {
109 unsigned long mask = cpumask_bits(cpu_online_mask)[0];
110
111 if (cpu < BITS_PER_LONG)
112 clear_bit(cpu, &mask);
113
114 _flat_send_IPI_mask(mask, vector);
115 }
116 } else if (num_online_cpus() > 1) {
117 __default_send_IPI_shortcut(APIC_DEST_ALLBUT,
118 vector, apic->dest_logical);
119 }
120 }
121
122 static void flat_send_IPI_all(int vector)
123 {
124 if (vector == NMI_VECTOR) {
125 flat_send_IPI_mask(cpu_online_mask, vector);
126 } else {
127 __default_send_IPI_shortcut(APIC_DEST_ALLINC,
128 vector, apic->dest_logical);
129 }
130 }
131
132 static unsigned int flat_get_apic_id(unsigned long x)
133 {
134 unsigned int id;
135
136 id = (((x)>>24) & 0xFFu);
137
138 return id;
139 }
140
141 static unsigned long set_apic_id(unsigned int id)
142 {
143 unsigned long x;
144
145 x = ((id & 0xFFu)<<24);
146 return x;
147 }
148
149 static unsigned int read_xapic_id(void)
150 {
151 unsigned int id;
152
153 id = flat_get_apic_id(apic_read(APIC_ID));
154 return id;
155 }
156
157 static int flat_apic_id_registered(void)
158 {
159 return physid_isset(read_xapic_id(), phys_cpu_present_map);
160 }
161
162 static unsigned int flat_cpu_mask_to_apicid(const struct cpumask *cpumask)
163 {
164 return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
165 }
166
167 static unsigned int flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
168 const struct cpumask *andmask)
169 {
170 unsigned long mask1 = cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
171 unsigned long mask2 = cpumask_bits(andmask)[0] & APIC_ALL_CPUS;
172
173 return mask1 & mask2;
174 }
175
176 static int flat_phys_pkg_id(int initial_apic_id, int index_msb)
177 {
178 return hard_smp_processor_id() >> index_msb;
179 }
180
181 struct genapic apic_flat = {
182 .name = "flat",
183 .probe = NULL,
184 .acpi_madt_oem_check = flat_acpi_madt_oem_check,
185 .apic_id_registered = flat_apic_id_registered,
186
187 .irq_delivery_mode = dest_LowestPrio,
188 .irq_dest_mode = 1, /* logical */
189
190 .target_cpus = flat_target_cpus,
191 .disable_esr = 0,
192 .dest_logical = APIC_DEST_LOGICAL,
193 .check_apicid_used = NULL,
194 .check_apicid_present = NULL,
195
196 .vector_allocation_domain = flat_vector_allocation_domain,
197 .init_apic_ldr = flat_init_apic_ldr,
198
199 .ioapic_phys_id_map = NULL,
200 .setup_apic_routing = NULL,
201 .multi_timer_check = NULL,
202 .apicid_to_node = NULL,
203 .cpu_to_logical_apicid = NULL,
204 .cpu_present_to_apicid = default_cpu_present_to_apicid,
205 .apicid_to_cpu_present = NULL,
206 .setup_portio_remap = NULL,
207 .check_phys_apicid_present = default_check_phys_apicid_present,
208 .enable_apic_mode = NULL,
209 .phys_pkg_id = flat_phys_pkg_id,
210 .mps_oem_check = NULL,
211
212 .get_apic_id = flat_get_apic_id,
213 .set_apic_id = set_apic_id,
214 .apic_id_mask = 0xFFu << 24,
215
216 .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
217 .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and,
218
219 .send_IPI_mask = flat_send_IPI_mask,
220 .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself,
221 .send_IPI_allbutself = flat_send_IPI_allbutself,
222 .send_IPI_all = flat_send_IPI_all,
223 .send_IPI_self = apic_send_IPI_self,
224
225 .wakeup_cpu = NULL,
226 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
227 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
228 .wait_for_init_deassert = NULL,
229 .smp_callin_clear_local_apic = NULL,
230 .store_NMI_vector = NULL,
231 .inquire_remote_apic = NULL,
232
233 .read = native_apic_mem_read,
234 .write = native_apic_mem_write,
235 .icr_read = native_apic_icr_read,
236 .icr_write = native_apic_icr_write,
237 .wait_icr_idle = native_apic_wait_icr_idle,
238 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
239 };
240
241 /*
242 * Physflat mode is used when there are more than 8 CPUs on a AMD system.
243 * We cannot use logical delivery in this case because the mask
244 * overflows, so use physical mode.
245 */
246 static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
247 {
248 #ifdef CONFIG_ACPI
249 /*
250 * Quirk: some x86_64 machines can only use physical APIC mode
251 * regardless of how many processors are present (x86_64 ES7000
252 * is an example).
253 */
254 if (acpi_gbl_FADT.header.revision > FADT2_REVISION_ID &&
255 (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) {
256 printk(KERN_DEBUG "system APIC only can use physical flat");
257 return 1;
258 }
259 #endif
260
261 return 0;
262 }
263
264 static const struct cpumask *physflat_target_cpus(void)
265 {
266 return cpu_online_mask;
267 }
268
269 static void physflat_vector_allocation_domain(int cpu, struct cpumask *retmask)
270 {
271 cpumask_clear(retmask);
272 cpumask_set_cpu(cpu, retmask);
273 }
274
275 static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector)
276 {
277 default_send_IPI_mask_sequence_phys(cpumask, vector);
278 }
279
280 static void physflat_send_IPI_mask_allbutself(const struct cpumask *cpumask,
281 int vector)
282 {
283 default_send_IPI_mask_allbutself_phys(cpumask, vector);
284 }
285
286 static void physflat_send_IPI_allbutself(int vector)
287 {
288 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
289 }
290
291 static void physflat_send_IPI_all(int vector)
292 {
293 physflat_send_IPI_mask(cpu_online_mask, vector);
294 }
295
296 static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask)
297 {
298 int cpu;
299
300 /*
301 * We're using fixed IRQ delivery, can only return one phys APIC ID.
302 * May as well be the first.
303 */
304 cpu = cpumask_first(cpumask);
305 if ((unsigned)cpu < nr_cpu_ids)
306 return per_cpu(x86_cpu_to_apicid, cpu);
307 else
308 return BAD_APICID;
309 }
310
311 static unsigned int
312 physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
313 const struct cpumask *andmask)
314 {
315 int cpu;
316
317 /*
318 * We're using fixed IRQ delivery, can only return one phys APIC ID.
319 * May as well be the first.
320 */
321 for_each_cpu_and(cpu, cpumask, andmask) {
322 if (cpumask_test_cpu(cpu, cpu_online_mask))
323 break;
324 }
325 if (cpu < nr_cpu_ids)
326 return per_cpu(x86_cpu_to_apicid, cpu);
327
328 return BAD_APICID;
329 }
330
331 struct genapic apic_physflat = {
332
333 .name = "physical flat",
334 .probe = NULL,
335 .acpi_madt_oem_check = physflat_acpi_madt_oem_check,
336 .apic_id_registered = flat_apic_id_registered,
337
338 .irq_delivery_mode = dest_Fixed,
339 .irq_dest_mode = 0, /* physical */
340
341 .target_cpus = physflat_target_cpus,
342 .disable_esr = 0,
343 .dest_logical = 0,
344 .check_apicid_used = NULL,
345 .check_apicid_present = NULL,
346
347 .vector_allocation_domain = physflat_vector_allocation_domain,
348 /* not needed, but shouldn't hurt: */
349 .init_apic_ldr = flat_init_apic_ldr,
350
351 .ioapic_phys_id_map = NULL,
352 .setup_apic_routing = NULL,
353 .multi_timer_check = NULL,
354 .apicid_to_node = NULL,
355 .cpu_to_logical_apicid = NULL,
356 .cpu_present_to_apicid = default_cpu_present_to_apicid,
357 .apicid_to_cpu_present = NULL,
358 .setup_portio_remap = NULL,
359 .check_phys_apicid_present = default_check_phys_apicid_present,
360 .enable_apic_mode = NULL,
361 .phys_pkg_id = flat_phys_pkg_id,
362 .mps_oem_check = NULL,
363
364 .get_apic_id = flat_get_apic_id,
365 .set_apic_id = set_apic_id,
366 .apic_id_mask = 0xFFu << 24,
367
368 .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
369 .cpu_mask_to_apicid_and = physflat_cpu_mask_to_apicid_and,
370
371 .send_IPI_mask = physflat_send_IPI_mask,
372 .send_IPI_mask_allbutself = physflat_send_IPI_mask_allbutself,
373 .send_IPI_allbutself = physflat_send_IPI_allbutself,
374 .send_IPI_all = physflat_send_IPI_all,
375 .send_IPI_self = apic_send_IPI_self,
376
377 .wakeup_cpu = NULL,
378 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
379 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
380 .wait_for_init_deassert = NULL,
381 .smp_callin_clear_local_apic = NULL,
382 .store_NMI_vector = NULL,
383 .inquire_remote_apic = NULL,
384
385 .read = native_apic_mem_read,
386 .write = native_apic_mem_write,
387 .icr_read = native_apic_icr_read,
388 .icr_write = native_apic_icr_write,
389 .wait_icr_idle = native_apic_wait_icr_idle,
390 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
391 };
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