2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/init.h>
17 #include <linux/sched.h>
18 #include <linux/bootmem.h>
19 #include <linux/module.h>
20 #include <linux/hardirq.h>
23 #include <asm/genapic.h>
24 #include <asm/pgtable.h>
25 #include <asm/uv/uv_mmrs.h>
26 #include <asm/uv/uv_hub.h>
27 #include <asm/uv/bios.h>
29 DEFINE_PER_CPU(int, x2apic_extra_bits
);
31 static enum uv_system_type uv_system_type
;
33 static int __init
uv_acpi_madt_oem_check(char *oem_id
, char *oem_table_id
)
35 if (!strcmp(oem_id
, "SGI")) {
36 if (!strcmp(oem_table_id
, "UVL"))
37 uv_system_type
= UV_LEGACY_APIC
;
38 else if (!strcmp(oem_table_id
, "UVX"))
39 uv_system_type
= UV_X2APIC
;
40 else if (!strcmp(oem_table_id
, "UVH")) {
41 uv_system_type
= UV_NON_UNIQUE_APIC
;
48 enum uv_system_type
get_uv_system_type(void)
50 return uv_system_type
;
53 int is_uv_system(void)
55 return uv_system_type
!= UV_NONE
;
58 DEFINE_PER_CPU(struct uv_hub_info_s
, __uv_hub_info
);
59 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info
);
61 struct uv_blade_info
*uv_blade_info
;
62 EXPORT_SYMBOL_GPL(uv_blade_info
);
64 short *uv_node_to_blade
;
65 EXPORT_SYMBOL_GPL(uv_node_to_blade
);
67 short *uv_cpu_to_blade
;
68 EXPORT_SYMBOL_GPL(uv_cpu_to_blade
);
70 short uv_possible_blades
;
71 EXPORT_SYMBOL_GPL(uv_possible_blades
);
73 unsigned long sn_rtc_cycles_per_second
;
74 EXPORT_SYMBOL(sn_rtc_cycles_per_second
);
76 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
78 static cpumask_t
uv_target_cpus(void)
80 return cpumask_of_cpu(0);
83 static cpumask_t
uv_vector_allocation_domain(int cpu
)
85 cpumask_t domain
= CPU_MASK_NONE
;
90 int uv_wakeup_secondary(int phys_apicid
, unsigned int start_rip
)
95 pnode
= uv_apicid_to_pnode(phys_apicid
);
96 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
97 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
98 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
100 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
103 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
104 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
105 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
107 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
111 static void uv_send_IPI_one(int cpu
, int vector
)
113 unsigned long val
, apicid
, lapicid
;
116 apicid
= per_cpu(x86_cpu_to_apicid
, cpu
); /* ZZZ - cache node-local ? */
117 lapicid
= apicid
& 0x3f; /* ZZZ macro needed */
118 pnode
= uv_apicid_to_pnode(apicid
);
120 (1UL << UVH_IPI_INT_SEND_SHFT
) | (lapicid
<<
121 UVH_IPI_INT_APIC_ID_SHFT
) |
122 (vector
<< UVH_IPI_INT_VECTOR_SHFT
);
123 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
126 static void uv_send_IPI_mask(cpumask_t mask
, int vector
)
130 for_each_possible_cpu(cpu
)
131 if (cpu_isset(cpu
, mask
))
132 uv_send_IPI_one(cpu
, vector
);
135 static void uv_send_IPI_allbutself(int vector
)
137 cpumask_t mask
= cpu_online_map
;
139 cpu_clear(smp_processor_id(), mask
);
141 if (!cpus_empty(mask
))
142 uv_send_IPI_mask(mask
, vector
);
145 static void uv_send_IPI_all(int vector
)
147 uv_send_IPI_mask(cpu_online_map
, vector
);
150 static int uv_apic_id_registered(void)
155 static void uv_init_apic_ldr(void)
159 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask
)
164 * We're using fixed IRQ delivery, can only return one phys APIC ID.
165 * May as well be the first.
167 cpu
= first_cpu(cpumask
);
168 if ((unsigned)cpu
< nr_cpu_ids
)
169 return per_cpu(x86_cpu_to_apicid
, cpu
);
174 static unsigned int get_apic_id(unsigned long x
)
178 WARN_ON(preemptible() && num_online_cpus() > 1);
179 id
= x
| __get_cpu_var(x2apic_extra_bits
);
184 static unsigned long set_apic_id(unsigned int id
)
188 /* maskout x2apic_extra_bits ? */
193 static unsigned int uv_read_apic_id(void)
196 return get_apic_id(apic_read(APIC_ID
));
199 static unsigned int phys_pkg_id(int index_msb
)
201 return uv_read_apic_id() >> index_msb
;
204 #ifdef ZZZ /* Needs x2apic patch */
205 static void uv_send_IPI_self(int vector
)
207 apic_write(APIC_SELF_IPI
, vector
);
211 struct genapic apic_x2apic_uv_x
= {
212 .name
= "UV large system",
213 .acpi_madt_oem_check
= uv_acpi_madt_oem_check
,
214 .int_delivery_mode
= dest_Fixed
,
215 .int_dest_mode
= (APIC_DEST_PHYSICAL
!= 0),
216 .target_cpus
= uv_target_cpus
,
217 .vector_allocation_domain
= uv_vector_allocation_domain
,/* Fixme ZZZ */
218 .apic_id_registered
= uv_apic_id_registered
,
219 .init_apic_ldr
= uv_init_apic_ldr
,
220 .send_IPI_all
= uv_send_IPI_all
,
221 .send_IPI_allbutself
= uv_send_IPI_allbutself
,
222 .send_IPI_mask
= uv_send_IPI_mask
,
223 /* ZZZ.send_IPI_self = uv_send_IPI_self, */
224 .cpu_mask_to_apicid
= uv_cpu_mask_to_apicid
,
225 .phys_pkg_id
= phys_pkg_id
, /* Fixme ZZZ */
226 .get_apic_id
= get_apic_id
,
227 .set_apic_id
= set_apic_id
,
228 .apic_id_mask
= (0xFFFFFFFFu
),
231 static __cpuinit
void set_x2apic_extra_bits(int pnode
)
233 __get_cpu_var(x2apic_extra_bits
) = (pnode
<< 6);
237 * Called on boot cpu.
239 static __init
int boot_pnode_to_blade(int pnode
)
243 for (blade
= 0; blade
< uv_num_possible_blades(); blade
++)
244 if (pnode
== uv_blade_info
[blade
].pnode
)
250 unsigned long redirect
;
254 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
256 static __initdata
struct redir_addr redir_addrs
[] = {
257 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
, UVH_SI_ALIAS0_OVERLAY_CONFIG
},
258 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
, UVH_SI_ALIAS1_OVERLAY_CONFIG
},
259 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
, UVH_SI_ALIAS2_OVERLAY_CONFIG
},
262 static __init
void get_lowmem_redirect(unsigned long *base
, unsigned long *size
)
264 union uvh_si_alias0_overlay_config_u alias
;
265 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect
;
268 for (i
= 0; i
< ARRAY_SIZE(redir_addrs
); i
++) {
269 alias
.v
= uv_read_local_mmr(redir_addrs
[i
].alias
);
270 if (alias
.s
.base
== 0) {
271 *size
= (1UL << alias
.s
.m_alias
);
272 redirect
.v
= uv_read_local_mmr(redir_addrs
[i
].redirect
);
273 *base
= (unsigned long)redirect
.s
.dest_base
<< DEST_SHIFT
;
280 static __init
void map_low_mmrs(void)
282 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE
, UV_GLOBAL_MMR32_SIZE
);
283 init_extra_mapping_uc(UV_LOCAL_MMR_BASE
, UV_LOCAL_MMR_SIZE
);
286 enum map_type
{map_wb
, map_uc
};
288 static __init
void map_high(char *id
, unsigned long base
, int shift
, enum map_type map_type
)
290 unsigned long bytes
, paddr
;
292 paddr
= base
<< shift
;
293 bytes
= (1UL << shift
);
294 printk(KERN_INFO
"UV: Map %s_HI 0x%lx - 0x%lx\n", id
, paddr
,
296 if (map_type
== map_uc
)
297 init_extra_mapping_uc(paddr
, bytes
);
299 init_extra_mapping_wb(paddr
, bytes
);
302 static __init
void map_gru_high(int max_pnode
)
304 union uvh_rh_gam_gru_overlay_config_mmr_u gru
;
305 int shift
= UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
;
307 gru
.v
= uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR
);
309 map_high("GRU", gru
.s
.base
, shift
, map_wb
);
312 static __init
void map_config_high(int max_pnode
)
314 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg
;
315 int shift
= UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT
;
317 cfg
.v
= uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR
);
319 map_high("CONFIG", cfg
.s
.base
, shift
, map_uc
);
322 static __init
void map_mmr_high(int max_pnode
)
324 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr
;
325 int shift
= UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
;
327 mmr
.v
= uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
);
329 map_high("MMR", mmr
.s
.base
, shift
, map_uc
);
332 static __init
void map_mmioh_high(int max_pnode
)
334 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh
;
335 int shift
= UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT
;
337 mmioh
.v
= uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
);
339 map_high("MMIOH", mmioh
.s
.base
, shift
, map_uc
);
342 static __init
void uv_rtc_init(void)
344 long status
, ticks_per_sec
, drift
;
347 x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK
, &ticks_per_sec
,
349 if (status
!= 0 || ticks_per_sec
< 100000) {
351 "unable to determine platform RTC clock frequency, "
353 /* BIOS gives wrong value for clock freq. so guess */
354 sn_rtc_cycles_per_second
= 1000000000000UL / 30000UL;
356 sn_rtc_cycles_per_second
= ticks_per_sec
;
359 static bool uv_system_inited
;
361 void __init
uv_system_init(void)
363 union uvh_si_addr_map_config_u m_n_config
;
364 union uvh_node_id_u node_id
;
365 unsigned long gnode_upper
, lowmem_redir_base
, lowmem_redir_size
;
366 int bytes
, nid
, cpu
, lcpu
, pnode
, blade
, i
, j
, m_val
, n_val
;
368 unsigned long mmr_base
, present
;
372 m_n_config
.v
= uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG
);
373 m_val
= m_n_config
.s
.m_skt
;
374 n_val
= m_n_config
.s
.n_skt
;
376 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
) &
378 printk(KERN_DEBUG
"UV: global MMR base 0x%lx\n", mmr_base
);
380 for(i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++)
381 uv_possible_blades
+=
382 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE
+ i
* 8));
383 printk(KERN_DEBUG
"UV: Found %d blades\n", uv_num_possible_blades());
385 bytes
= sizeof(struct uv_blade_info
) * uv_num_possible_blades();
386 uv_blade_info
= alloc_bootmem_pages(bytes
);
388 get_lowmem_redirect(&lowmem_redir_base
, &lowmem_redir_size
);
390 bytes
= sizeof(uv_node_to_blade
[0]) * num_possible_nodes();
391 uv_node_to_blade
= alloc_bootmem_pages(bytes
);
392 memset(uv_node_to_blade
, 255, bytes
);
394 bytes
= sizeof(uv_cpu_to_blade
[0]) * num_possible_cpus();
395 uv_cpu_to_blade
= alloc_bootmem_pages(bytes
);
396 memset(uv_cpu_to_blade
, 255, bytes
);
399 for (i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++) {
400 present
= uv_read_local_mmr(UVH_NODE_PRESENT_TABLE
+ i
* 8);
401 for (j
= 0; j
< 64; j
++) {
402 if (!test_bit(j
, &present
))
404 uv_blade_info
[blade
].pnode
= (i
* 64 + j
);
405 uv_blade_info
[blade
].nr_possible_cpus
= 0;
406 uv_blade_info
[blade
].nr_online_cpus
= 0;
411 node_id
.v
= uv_read_local_mmr(UVH_NODE_ID
);
412 gnode_upper
= (((unsigned long)node_id
.s
.node_id
) &
413 ~((1 << n_val
) - 1)) << m_val
;
417 for_each_present_cpu(cpu
) {
418 nid
= cpu_to_node(cpu
);
419 pnode
= uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid
, cpu
));
420 blade
= boot_pnode_to_blade(pnode
);
421 lcpu
= uv_blade_info
[blade
].nr_possible_cpus
;
422 uv_blade_info
[blade
].nr_possible_cpus
++;
424 uv_cpu_hub_info(cpu
)->lowmem_remap_base
= lowmem_redir_base
;
425 uv_cpu_hub_info(cpu
)->lowmem_remap_top
=
426 lowmem_redir_base
+ lowmem_redir_size
;
427 uv_cpu_hub_info(cpu
)->m_val
= m_val
;
428 uv_cpu_hub_info(cpu
)->n_val
= m_val
;
429 uv_cpu_hub_info(cpu
)->numa_blade_id
= blade
;
430 uv_cpu_hub_info(cpu
)->blade_processor_id
= lcpu
;
431 uv_cpu_hub_info(cpu
)->pnode
= pnode
;
432 uv_cpu_hub_info(cpu
)->pnode_mask
= (1 << n_val
) - 1;
433 uv_cpu_hub_info(cpu
)->gpa_mask
= (1 << (m_val
+ n_val
)) - 1;
434 uv_cpu_hub_info(cpu
)->gnode_upper
= gnode_upper
;
435 uv_cpu_hub_info(cpu
)->global_mmr_base
= mmr_base
;
436 uv_cpu_hub_info(cpu
)->coherency_domain_number
= 0;/* ZZZ */
437 uv_node_to_blade
[nid
] = blade
;
438 uv_cpu_to_blade
[cpu
] = blade
;
439 max_pnode
= max(pnode
, max_pnode
);
441 printk(KERN_DEBUG
"UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
442 "lcpu %d, blade %d\n",
443 cpu
, per_cpu(x86_cpu_to_apicid
, cpu
), pnode
, nid
,
447 map_gru_high(max_pnode
);
448 map_mmr_high(max_pnode
);
449 map_config_high(max_pnode
);
450 map_mmioh_high(max_pnode
);
451 uv_system_inited
= true;
455 * Called on each cpu to initialize the per_cpu UV data area.
456 * ZZZ hotplug not supported yet
458 void __cpuinit
uv_cpu_init(void)
460 BUG_ON(!uv_system_inited
);
462 uv_blade_info
[uv_numa_blade_id()].nr_online_cpus
++;
464 if (get_uv_system_type() == UV_NON_UNIQUE_APIC
)
465 set_x2apic_extra_bits(uv_hub_info
->pnode
);