arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/delay.h>
   4 #include <linux/errno.h>
   5 #include <linux/hpet.h>
   6 #include <linux/init.h>
   7 #include <linux/sysdev.h>
   8 #include <linux/pm.h>
   9 #include <linux/delay.h>
  10
  11 #include <asm/fixmap.h>
  12 #include <asm/hpet.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15
  16 #define HPET_MASK       CLOCKSOURCE_MASK(32)
  17 #define HPET_SHIFT      22
  18
  19 /* FSEC = 10^-15
  20    NSEC = 10^-9 */
  21 #define FSEC_PER_NSEC   1000000
  22
  23 /*
  24  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  25  */
  26 unsigned long hpet_address;
  27 static void __iomem *hpet_virt_address;
  28
  29 unsigned long hpet_readl(unsigned long a)
  30 {
  31         return readl(hpet_virt_address + a);
  32 }
  33
  34 static inline void hpet_writel(unsigned long d, unsigned long a)
  35 {
  36         writel(d, hpet_virt_address + a);
  37 }
  38
  39 #ifdef CONFIG_X86_64
  40
  41 #include <asm/pgtable.h>
  42
  43 static inline void hpet_set_mapping(void)
  44 {
  45         set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
  46         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  47         hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
  48 }
  49
  50 static inline void hpet_clear_mapping(void)
  51 {
  52         hpet_virt_address = NULL;
  53 }
  54
  55 #else
  56
  57 static inline void hpet_set_mapping(void)
  58 {
  59         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  60 }
  61
  62 static inline void hpet_clear_mapping(void)
  63 {
  64         iounmap(hpet_virt_address);
  65         hpet_virt_address = NULL;
  66 }
  67 #endif
  68
  69 /*
  70  * HPET command line enable / disable
  71  */
  72 static int boot_hpet_disable;
  73 int hpet_force_user;
  74
  75 static int __init hpet_setup(char* str)
  76 {
  77         if (str) {
  78                 if (!strncmp("disable", str, 7))
  79                         boot_hpet_disable = 1;
  80                 if (!strncmp("force", str, 5))
  81                         hpet_force_user = 1;
  82         }
  83         return 1;
  84 }
  85 __setup("hpet=", hpet_setup);
  86
  87 static int __init disable_hpet(char *str)
  88 {
  89         boot_hpet_disable = 1;
  90         return 1;
  91 }
  92 __setup("nohpet", disable_hpet);
  93
  94 static inline int is_hpet_capable(void)
  95 {
  96         return (!boot_hpet_disable && hpet_address);
  97 }
  98
  99 /*
 100  * HPET timer interrupt enable / disable
 101  */
 102 static int hpet_legacy_int_enabled;
 103
 104 /**
 105  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 106  */
 107 int is_hpet_enabled(void)
 108 {
 109         return is_hpet_capable() && hpet_legacy_int_enabled;
 110 }
 111
 112 /*
 113  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 114  * timer 0 and timer 1 in case of RTC emulation.
 115  */
 116 #ifdef CONFIG_HPET
 117 static void hpet_reserve_platform_timers(unsigned long id)
 118 {
 119         struct hpet __iomem *hpet = hpet_virt_address;
 120         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 121         unsigned int nrtimers, i;
 122         struct hpet_data hd;
 123
 124         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 125
 126         memset(&hd, 0, sizeof (hd));
 127         hd.hd_phys_address = hpet_address;
 128         hd.hd_address = hpet;
 129         hd.hd_nirqs = nrtimers;
 130         hd.hd_flags = HPET_DATA_PLATFORM;
 131         hpet_reserve_timer(&hd, 0);
 132
 133 #ifdef CONFIG_HPET_EMULATE_RTC
 134         hpet_reserve_timer(&hd, 1);
 135 #endif
 136         hd.hd_irq[0] = HPET_LEGACY_8254;
 137         hd.hd_irq[1] = HPET_LEGACY_RTC;
 138
 139        for (i = 2; i < nrtimers; timer++, i++)
 140                hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
 141                        Tn_INT_ROUTE_CNF_SHIFT;
 142         hpet_alloc(&hd);
 143 }
 144 #else
 145 static void hpet_reserve_platform_timers(unsigned long id) { }
 146 #endif
 147
 148 /*
 149  * Common hpet info
 150  */
 151 static unsigned long hpet_period;
 152
 153 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 154                           struct clock_event_device *evt);
 155 static int hpet_legacy_next_event(unsigned long delta,
 156                            struct clock_event_device *evt);
 157
 158 /*
 159  * The hpet clock event device
 160  */
 161 static struct clock_event_device hpet_clockevent = {
 162         .name           = "hpet",
 163         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 164         .set_mode       = hpet_legacy_set_mode,
 165         .set_next_event = hpet_legacy_next_event,
 166         .shift          = 32,
 167         .irq            = 0,
 168         .rating         = 50,
 169 };
 170
 171 static void hpet_start_counter(void)
 172 {
 173         unsigned long cfg = hpet_readl(HPET_CFG);
 174
 175         cfg &= ~HPET_CFG_ENABLE;
 176         hpet_writel(cfg, HPET_CFG);
 177         hpet_writel(0, HPET_COUNTER);
 178         hpet_writel(0, HPET_COUNTER + 4);
 179         cfg |= HPET_CFG_ENABLE;
 180         hpet_writel(cfg, HPET_CFG);
 181 }
 182
 183 static void hpet_resume_device(void)
 184 {
 185         force_hpet_resume();
 186 }
 187
 188 static void hpet_restart_counter(void)
 189 {
 190         hpet_resume_device();
 191         hpet_start_counter();
 192 }
 193
 194 static void hpet_enable_legacy_int(void)
 195 {
 196         unsigned long cfg = hpet_readl(HPET_CFG);
 197
 198         cfg |= HPET_CFG_LEGACY;
 199         hpet_writel(cfg, HPET_CFG);
 200         hpet_legacy_int_enabled = 1;
 201 }
 202
 203 static void hpet_legacy_clockevent_register(void)
 204 {
 205         uint64_t hpet_freq;
 206
 207         /* Start HPET legacy interrupts */
 208         hpet_enable_legacy_int();
 209
 210         /*
 211          * The period is a femto seconds value. We need to calculate the
 212          * scaled math multiplication factor for nanosecond to hpet tick
 213          * conversion.
 214          */
 215         hpet_freq = 1000000000000000ULL;
 216         do_div(hpet_freq, hpet_period);
 217         hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
 218                                       NSEC_PER_SEC, 32);
 219         /* Calculate the min / max delta */
 220         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 221                                                            &hpet_clockevent);
 222         hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
 223                                                            &hpet_clockevent);
 224
 225         /*
 226          * Start hpet with the boot cpu mask and make it
 227          * global after the IO_APIC has been initialized.
 228          */
 229         hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
 230         clockevents_register_device(&hpet_clockevent);
 231         global_clock_event = &hpet_clockevent;
 232         printk(KERN_DEBUG "hpet clockevent registered\n");
 233 }
 234
 235 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 236                           struct clock_event_device *evt)
 237 {
 238         unsigned long cfg, cmp, now;
 239         uint64_t delta;
 240
 241         switch(mode) {
 242         case CLOCK_EVT_MODE_PERIODIC:
 243                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
 244                 delta >>= hpet_clockevent.shift;
 245                 now = hpet_readl(HPET_COUNTER);
 246                 cmp = now + (unsigned long) delta;
 247                 cfg = hpet_readl(HPET_T0_CFG);
 248                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 249                        HPET_TN_SETVAL | HPET_TN_32BIT;
 250                 hpet_writel(cfg, HPET_T0_CFG);
 251                 /*
 252                  * The first write after writing TN_SETVAL to the
 253                  * config register sets the counter value, the second
 254                  * write sets the period.
 255                  */
 256                 hpet_writel(cmp, HPET_T0_CMP);
 257                 udelay(1);
 258                 hpet_writel((unsigned long) delta, HPET_T0_CMP);
 259                 break;
 260
 261         case CLOCK_EVT_MODE_ONESHOT:
 262                 cfg = hpet_readl(HPET_T0_CFG);
 263                 cfg &= ~HPET_TN_PERIODIC;
 264                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 265                 hpet_writel(cfg, HPET_T0_CFG);
 266                 break;
 267
 268         case CLOCK_EVT_MODE_UNUSED:
 269         case CLOCK_EVT_MODE_SHUTDOWN:
 270                 cfg = hpet_readl(HPET_T0_CFG);
 271                 cfg &= ~HPET_TN_ENABLE;
 272                 hpet_writel(cfg, HPET_T0_CFG);
 273                 break;
 274
 275         case CLOCK_EVT_MODE_RESUME:
 276                 hpet_enable_legacy_int();
 277                 break;
 278         }
 279 }
 280
 281 static int hpet_legacy_next_event(unsigned long delta,
 282                            struct clock_event_device *evt)
 283 {
 284         unsigned long cnt;
 285
 286         cnt = hpet_readl(HPET_COUNTER);
 287         cnt += delta;
 288         hpet_writel(cnt, HPET_T0_CMP);
 289
 290         return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
 291 }
 292
 293 /*
 294  * Clock source related code
 295  */
 296 static cycle_t read_hpet(void)
 297 {
 298         return (cycle_t)hpet_readl(HPET_COUNTER);
 299 }
 300
 301 #ifdef CONFIG_X86_64
 302 static cycle_t __vsyscall_fn vread_hpet(void)
 303 {
 304         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 305 }
 306 #endif
 307
 308 static struct clocksource clocksource_hpet = {
 309         .name           = "hpet",
 310         .rating         = 250,
 311         .read           = read_hpet,
 312         .mask           = HPET_MASK,
 313         .shift          = HPET_SHIFT,
 314         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 315         .resume         = hpet_restart_counter,
 316 #ifdef CONFIG_X86_64
 317         .vread          = vread_hpet,
 318 #endif
 319 };
 320
 321 static int hpet_clocksource_register(void)
 322 {
 323         u64 tmp, start, now;
 324         cycle_t t1;
 325
 326         /* Start the counter */
 327         hpet_start_counter();
 328
 329         /* Verify whether hpet counter works */
 330         t1 = read_hpet();
 331         rdtscll(start);
 332
 333         /*
 334          * We don't know the TSC frequency yet, but waiting for
 335          * 200000 TSC cycles is safe:
 336          * 4 GHz == 50us
 337          * 1 GHz == 200us
 338          */
 339         do {
 340                 rep_nop();
 341                 rdtscll(now);
 342         } while ((now - start) < 200000UL);
 343
 344         if (t1 == read_hpet()) {
 345                 printk(KERN_WARNING
 346                        "HPET counter not counting. HPET disabled\n");
 347                 return -ENODEV;
 348         }
 349
 350         /* Initialize and register HPET clocksource
 351          *
 352          * hpet period is in femto seconds per cycle
 353          * so we need to convert this to ns/cyc units
 354          * approximated by mult/2^shift
 355          *
 356          *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
 357          *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
 358          *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
 359          *  (fsec/cyc << shift)/1000000 = mult
 360          *  (hpet_period << shift)/FSEC_PER_NSEC = mult
 361          */
 362         tmp = (u64)hpet_period << HPET_SHIFT;
 363         do_div(tmp, FSEC_PER_NSEC);
 364         clocksource_hpet.mult = (u32)tmp;
 365
 366         clocksource_register(&clocksource_hpet);
 367
 368         return 0;
 369 }
 370
 371 /*
 372  * Try to setup the HPET timer
 373  */
 374 int __init hpet_enable(void)
 375 {
 376         unsigned long id;
 377
 378         if (!is_hpet_capable())
 379                 return 0;
 380
 381         hpet_set_mapping();
 382
 383         /*
 384          * Read the period and check for a sane value:
 385          */
 386         hpet_period = hpet_readl(HPET_PERIOD);
 387         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 388                 goto out_nohpet;
 389
 390         /*
 391          * Read the HPET ID register to retrieve the IRQ routing
 392          * information and the number of channels
 393          */
 394         id = hpet_readl(HPET_ID);
 395
 396 #ifdef CONFIG_HPET_EMULATE_RTC
 397         /*
 398          * The legacy routing mode needs at least two channels, tick timer
 399          * and the rtc emulation channel.
 400          */
 401         if (!(id & HPET_ID_NUMBER))
 402                 goto out_nohpet;
 403 #endif
 404
 405         if (hpet_clocksource_register())
 406                 goto out_nohpet;
 407
 408         if (id & HPET_ID_LEGSUP) {
 409                 hpet_legacy_clockevent_register();
 410                 return 1;
 411         }
 412         return 0;
 413
 414 out_nohpet:
 415         hpet_clear_mapping();
 416         boot_hpet_disable = 1;
 417         return 0;
 418 }
 419
 420 /*
 421  * Needs to be late, as the reserve_timer code calls kalloc !
 422  *
 423  * Not a problem on i386 as hpet_enable is called from late_time_init,
 424  * but on x86_64 it is necessary !
 425  */
 426 static __init int hpet_late_init(void)
 427 {
 428         if (boot_hpet_disable)
 429                 return -ENODEV;
 430
 431         if (!hpet_address) {
 432                 if (!force_hpet_address)
 433                         return -ENODEV;
 434
 435                 hpet_address = force_hpet_address;
 436                 hpet_enable();
 437                 if (!hpet_virt_address)
 438                         return -ENODEV;
 439         }
 440
 441         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 442
 443         return 0;
 444 }
 445 fs_initcall(hpet_late_init);
 446
 447 void hpet_disable(void)
 448 {
 449         if (is_hpet_capable()) {
 450                 unsigned long cfg = hpet_readl(HPET_CFG);
 451
 452                 if (hpet_legacy_int_enabled) {
 453                         cfg &= ~HPET_CFG_LEGACY;
 454                         hpet_legacy_int_enabled = 0;
 455                 }
 456                 cfg &= ~HPET_CFG_ENABLE;
 457                 hpet_writel(cfg, HPET_CFG);
 458         }
 459 }
 460
 461 #ifdef CONFIG_HPET_EMULATE_RTC
 462
 463 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 464  * is enabled, we support RTC interrupt functionality in software.
 465  * RTC has 3 kinds of interrupts:
 466  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 467  *    is updated
 468  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 469  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 470  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 471  * (1) and (2) above are implemented using polling at a frequency of
 472  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 473  * overhead. (DEFAULT_RTC_INT_FREQ)
 474  * For (3), we use interrupts at 64Hz or user specified periodic
 475  * frequency, whichever is higher.
 476  */
 477 #include <linux/mc146818rtc.h>
 478 #include <linux/rtc.h>
 479
 480 #define DEFAULT_RTC_INT_FREQ    64
 481 #define DEFAULT_RTC_SHIFT       6
 482 #define RTC_NUM_INTS            1
 483
 484 static unsigned long hpet_rtc_flags;
 485 static unsigned long hpet_prev_update_sec;
 486 static struct rtc_time hpet_alarm_time;
 487 static unsigned long hpet_pie_count;
 488 static unsigned long hpet_t1_cmp;
 489 static unsigned long hpet_default_delta;
 490 static unsigned long hpet_pie_delta;
 491 static unsigned long hpet_pie_limit;
 492
 493 /*
 494  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 495  * is not supported by all HPET implementations for timer 1.
 496  *
 497  * hpet_rtc_timer_init() is called when the rtc is initialized.
 498  */
 499 int hpet_rtc_timer_init(void)
 500 {
 501         unsigned long cfg, cnt, delta, flags;
 502
 503         if (!is_hpet_enabled())
 504                 return 0;
 505
 506         if (!hpet_default_delta) {
 507                 uint64_t clc;
 508
 509                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 510                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
 511                 hpet_default_delta = (unsigned long) clc;
 512         }
 513
 514         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 515                 delta = hpet_default_delta;
 516         else
 517                 delta = hpet_pie_delta;
 518
 519         local_irq_save(flags);
 520
 521         cnt = delta + hpet_readl(HPET_COUNTER);
 522         hpet_writel(cnt, HPET_T1_CMP);
 523         hpet_t1_cmp = cnt;
 524
 525         cfg = hpet_readl(HPET_T1_CFG);
 526         cfg &= ~HPET_TN_PERIODIC;
 527         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 528         hpet_writel(cfg, HPET_T1_CFG);
 529
 530         local_irq_restore(flags);
 531
 532         return 1;
 533 }
 534
 535 /*
 536  * The functions below are called from rtc driver.
 537  * Return 0 if HPET is not being used.
 538  * Otherwise do the necessary changes and return 1.
 539  */
 540 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
 541 {
 542         if (!is_hpet_enabled())
 543                 return 0;
 544
 545         hpet_rtc_flags &= ~bit_mask;
 546         return 1;
 547 }
 548
 549 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
 550 {
 551         unsigned long oldbits = hpet_rtc_flags;
 552
 553         if (!is_hpet_enabled())
 554                 return 0;
 555
 556         hpet_rtc_flags |= bit_mask;
 557
 558         if (!oldbits)
 559                 hpet_rtc_timer_init();
 560
 561         return 1;
 562 }
 563
 564 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
 565                         unsigned char sec)
 566 {
 567         if (!is_hpet_enabled())
 568                 return 0;
 569
 570         hpet_alarm_time.tm_hour = hrs;
 571         hpet_alarm_time.tm_min = min;
 572         hpet_alarm_time.tm_sec = sec;
 573
 574         return 1;
 575 }
 576
 577 int hpet_set_periodic_freq(unsigned long freq)
 578 {
 579         uint64_t clc;
 580
 581         if (!is_hpet_enabled())
 582                 return 0;
 583
 584         if (freq <= DEFAULT_RTC_INT_FREQ)
 585                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
 586         else {
 587                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 588                 do_div(clc, freq);
 589                 clc >>= hpet_clockevent.shift;
 590                 hpet_pie_delta = (unsigned long) clc;
 591         }
 592         return 1;
 593 }
 594
 595 int hpet_rtc_dropped_irq(void)
 596 {
 597         return is_hpet_enabled();
 598 }
 599
 600 static void hpet_rtc_timer_reinit(void)
 601 {
 602         unsigned long cfg, delta;
 603         int lost_ints = -1;
 604
 605         if (unlikely(!hpet_rtc_flags)) {
 606                 cfg = hpet_readl(HPET_T1_CFG);
 607                 cfg &= ~HPET_TN_ENABLE;
 608                 hpet_writel(cfg, HPET_T1_CFG);
 609                 return;
 610         }
 611
 612         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 613                 delta = hpet_default_delta;
 614         else
 615                 delta = hpet_pie_delta;
 616
 617         /*
 618          * Increment the comparator value until we are ahead of the
 619          * current count.
 620          */
 621         do {
 622                 hpet_t1_cmp += delta;
 623                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
 624                 lost_ints++;
 625         } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
 626
 627         if (lost_ints) {
 628                 if (hpet_rtc_flags & RTC_PIE)
 629                         hpet_pie_count += lost_ints;
 630                 if (printk_ratelimit())
 631                         printk(KERN_WARNING "rtc: lost %d interrupts\n",
 632                                 lost_ints);
 633         }
 634 }
 635
 636 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
 637 {
 638         struct rtc_time curr_time;
 639         unsigned long rtc_int_flag = 0;
 640
 641         hpet_rtc_timer_reinit();
 642
 643         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
 644                 rtc_get_rtc_time(&curr_time);
 645
 646         if (hpet_rtc_flags & RTC_UIE &&
 647             curr_time.tm_sec != hpet_prev_update_sec) {
 648                 rtc_int_flag = RTC_UF;
 649                 hpet_prev_update_sec = curr_time.tm_sec;
 650         }
 651
 652         if (hpet_rtc_flags & RTC_PIE &&
 653             ++hpet_pie_count >= hpet_pie_limit) {
 654                 rtc_int_flag |= RTC_PF;
 655                 hpet_pie_count = 0;
 656         }
 657
 658         if (hpet_rtc_flags & RTC_AIE &&
 659             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
 660             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
 661             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
 662                         rtc_int_flag |= RTC_AF;
 663
 664         if (rtc_int_flag) {
 665                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
 666                 rtc_interrupt(rtc_int_flag, dev_id);
 667         }
 668         return IRQ_HANDLED;
 669 }
 670 #endif