arch/x86/kernel/i8253.c

   1 /*
   2  * 8253/PIT functions
   3  *
   4  */
   5 #include <linux/clockchips.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/jiffies.h>
   9 #include <linux/module.h>
  10 #include <linux/timex.h>
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/i8253.h>
  16 #include <asm/hpet.h>
  17 #include <asm/smp.h>
  18
  19 DEFINE_RAW_SPINLOCK(i8253_lock);
  20 EXPORT_SYMBOL(i8253_lock);
  21
  22 /*
  23  * HPET replaces the PIT, when enabled. So we need to know, which of
  24  * the two timers is used
  25  */
  26 struct clock_event_device *global_clock_event;
  27
  28 /*
  29  * Initialize the PIT timer.
  30  *
  31  * This is also called after resume to bring the PIT into operation again.
  32  */
  33 static void init_pit_timer(enum clock_event_mode mode,
  34                            struct clock_event_device *evt)
  35 {
  36         raw_spin_lock(&i8253_lock);
  37
  38         switch (mode) {
  39         case CLOCK_EVT_MODE_PERIODIC:
  40                 /* binary, mode 2, LSB/MSB, ch 0 */
  41                 outb_pit(0x34, PIT_MODE);
  42                 outb_pit(LATCH & 0xff , PIT_CH0);       /* LSB */
  43                 outb_pit(LATCH >> 8 , PIT_CH0);         /* MSB */
  44                 break;
  45
  46         case CLOCK_EVT_MODE_SHUTDOWN:
  47         case CLOCK_EVT_MODE_UNUSED:
  48                 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
  49                     evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  50                         outb_pit(0x30, PIT_MODE);
  51                         outb_pit(0, PIT_CH0);
  52                         outb_pit(0, PIT_CH0);
  53                 }
  54                 break;
  55
  56         case CLOCK_EVT_MODE_ONESHOT:
  57                 /* One shot setup */
  58                 outb_pit(0x38, PIT_MODE);
  59                 break;
  60
  61         case CLOCK_EVT_MODE_RESUME:
  62                 /* Nothing to do here */
  63                 break;
  64         }
  65         raw_spin_unlock(&i8253_lock);
  66 }
  67
  68 /*
  69  * Program the next event in oneshot mode
  70  *
  71  * Delta is given in PIT ticks
  72  */
  73 static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
  74 {
  75         raw_spin_lock(&i8253_lock);
  76         outb_pit(delta & 0xff , PIT_CH0);       /* LSB */
  77         outb_pit(delta >> 8 , PIT_CH0);         /* MSB */
  78         raw_spin_unlock(&i8253_lock);
  79
  80         return 0;
  81 }
  82
  83 /*
  84  * On UP the PIT can serve all of the possible timer functions. On SMP systems
  85  * it can be solely used for the global tick.
  86  *
  87  * The profiling and update capabilities are switched off once the local apic is
  88  * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
  89  * !using_apic_timer decisions in do_timer_interrupt_hook()
  90  */
  91 static struct clock_event_device pit_ce = {
  92         .name           = "pit",
  93         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  94         .set_mode       = init_pit_timer,
  95         .set_next_event = pit_next_event,
  96         .shift          = 32,
  97         .irq            = 0,
  98 };
  99
 100 /*
 101  * Initialize the conversion factor and the min/max deltas of the clock event
 102  * structure and register the clock event source with the framework.
 103  */
 104 void __init setup_pit_timer(void)
 105 {
 106         /*
 107          * Start pit with the boot cpu mask and make it global after the
 108          * IO_APIC has been initialized.
 109          */
 110         pit_ce.cpumask = cpumask_of(smp_processor_id());
 111         pit_ce.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, pit_ce.shift);
 112         pit_ce.max_delta_ns = clockevent_delta2ns(0x7FFF, &pit_ce);
 113         pit_ce.min_delta_ns = clockevent_delta2ns(0xF, &pit_ce);
 114
 115         clockevents_register_device(&pit_ce);
 116         global_clock_event = &pit_ce;
 117 }
 118
 119 #ifndef CONFIG_X86_64
 120 /*
 121  * Since the PIT overflows every tick, its not very useful
 122  * to just read by itself. So use jiffies to emulate a free
 123  * running counter:
 124  */
 125 static cycle_t pit_read(struct clocksource *cs)
 126 {
 127         static int old_count;
 128         static u32 old_jifs;
 129         unsigned long flags;
 130         int count;
 131         u32 jifs;
 132
 133         raw_spin_lock_irqsave(&i8253_lock, flags);
 134         /*
 135          * Although our caller may have the read side of xtime_lock,
 136          * this is now a seqlock, and we are cheating in this routine
 137          * by having side effects on state that we cannot undo if
 138          * there is a collision on the seqlock and our caller has to
 139          * retry.  (Namely, old_jifs and old_count.)  So we must treat
 140          * jiffies as volatile despite the lock.  We read jiffies
 141          * before latching the timer count to guarantee that although
 142          * the jiffies value might be older than the count (that is,
 143          * the counter may underflow between the last point where
 144          * jiffies was incremented and the point where we latch the
 145          * count), it cannot be newer.
 146          */
 147         jifs = jiffies;
 148         outb_pit(0x00, PIT_MODE);       /* latch the count ASAP */
 149         count = inb_pit(PIT_CH0);       /* read the latched count */
 150         count |= inb_pit(PIT_CH0) << 8;
 151
 152         /* VIA686a test code... reset the latch if count > max + 1 */
 153         if (count > LATCH) {
 154                 outb_pit(0x34, PIT_MODE);
 155                 outb_pit(LATCH & 0xff, PIT_CH0);
 156                 outb_pit(LATCH >> 8, PIT_CH0);
 157                 count = LATCH - 1;
 158         }
 159
 160         /*
 161          * It's possible for count to appear to go the wrong way for a
 162          * couple of reasons:
 163          *
 164          *  1. The timer counter underflows, but we haven't handled the
 165          *     resulting interrupt and incremented jiffies yet.
 166          *  2. Hardware problem with the timer, not giving us continuous time,
 167          *     the counter does small "jumps" upwards on some Pentium systems,
 168          *     (see c't 95/10 page 335 for Neptun bug.)
 169          *
 170          * Previous attempts to handle these cases intelligently were
 171          * buggy, so we just do the simple thing now.
 172          */
 173         if (count > old_count && jifs == old_jifs)
 174                 count = old_count;
 175
 176         old_count = count;
 177         old_jifs = jifs;
 178
 179         raw_spin_unlock_irqrestore(&i8253_lock, flags);
 180
 181         count = (LATCH - 1) - count;
 182
 183         return (cycle_t)(jifs * LATCH) + count;
 184 }
 185
 186 static struct clocksource pit_cs = {
 187         .name           = "pit",
 188         .rating         = 110,
 189         .read           = pit_read,
 190         .mask           = CLOCKSOURCE_MASK(32),
 191         .mult           = 0,
 192         .shift          = 20,
 193 };
 194
 195 static int __init init_pit_clocksource(void)
 196 {
 197          /*
 198           * Several reasons not to register PIT as a clocksource:
 199           *
 200           * - On SMP PIT does not scale due to i8253_lock
 201           * - when HPET is enabled
 202           * - when local APIC timer is active (PIT is switched off)
 203           */
 204         if (num_possible_cpus() > 1 || is_hpet_enabled() ||
 205             pit_ce.mode != CLOCK_EVT_MODE_PERIODIC)
 206                 return 0;
 207
 208         pit_cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, pit_cs.shift);
 209
 210         return clocksource_register(&pit_cs);
 211 }
 212 arch_initcall(init_pit_clocksource);
 213
 214 #endif /* !CONFIG_X86_64 */