2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 static int __init
parse_noapic(char *str
)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic
);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list
{
121 struct irq_pin_list
*next
;
124 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
126 struct irq_pin_list
*pin
;
129 node
= cpu_to_node(cpu
);
131 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
132 printk(KERN_DEBUG
" alloc irq_2_pin on cpu %d node %d\n", cpu
, node
);
138 struct irq_pin_list
*irq_2_pin
;
139 cpumask_var_t domain
;
140 cpumask_var_t old_domain
;
141 unsigned move_cleanup_count
;
143 u8 move_in_progress
: 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending
: 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx
[] = {
153 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
155 [0] = { .vector
= IRQ0_VECTOR
, },
156 [1] = { .vector
= IRQ1_VECTOR
, },
157 [2] = { .vector
= IRQ2_VECTOR
, },
158 [3] = { .vector
= IRQ3_VECTOR
, },
159 [4] = { .vector
= IRQ4_VECTOR
, },
160 [5] = { .vector
= IRQ5_VECTOR
, },
161 [6] = { .vector
= IRQ6_VECTOR
, },
162 [7] = { .vector
= IRQ7_VECTOR
, },
163 [8] = { .vector
= IRQ8_VECTOR
, },
164 [9] = { .vector
= IRQ9_VECTOR
, },
165 [10] = { .vector
= IRQ10_VECTOR
, },
166 [11] = { .vector
= IRQ11_VECTOR
, },
167 [12] = { .vector
= IRQ12_VECTOR
, },
168 [13] = { .vector
= IRQ13_VECTOR
, },
169 [14] = { .vector
= IRQ14_VECTOR
, },
170 [15] = { .vector
= IRQ15_VECTOR
, },
173 void __init
arch_early_irq_init(void)
176 struct irq_desc
*desc
;
181 count
= ARRAY_SIZE(irq_cfgx
);
183 for (i
= 0; i
< count
; i
++) {
184 desc
= irq_to_desc(i
);
185 desc
->chip_data
= &cfg
[i
];
186 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
187 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
188 if (i
< NR_IRQS_LEGACY
)
189 cpumask_setall(cfg
[i
].domain
);
193 #ifdef CONFIG_SPARSE_IRQ
194 static struct irq_cfg
*irq_cfg(unsigned int irq
)
196 struct irq_cfg
*cfg
= NULL
;
197 struct irq_desc
*desc
;
199 desc
= irq_to_desc(irq
);
201 cfg
= desc
->chip_data
;
206 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
211 node
= cpu_to_node(cpu
);
213 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
215 /* FIXME: needs alloc_cpumask_var_node() */
216 if (!alloc_cpumask_var(&cfg
->domain
, GFP_ATOMIC
)) {
219 } else if (!alloc_cpumask_var(&cfg
->old_domain
, GFP_ATOMIC
)) {
220 free_cpumask_var(cfg
->domain
);
224 cpumask_clear(cfg
->domain
);
225 cpumask_clear(cfg
->old_domain
);
228 printk(KERN_DEBUG
" alloc irq_cfg on cpu %d node %d\n", cpu
, node
);
233 void arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
237 cfg
= desc
->chip_data
;
239 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
240 if (!desc
->chip_data
) {
241 printk(KERN_ERR
"can not alloc irq_cfg\n");
247 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
250 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
252 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
254 cfg
->irq_2_pin
= NULL
;
255 old_entry
= old_cfg
->irq_2_pin
;
259 entry
= get_one_free_irq_2_pin(cpu
);
263 entry
->apic
= old_entry
->apic
;
264 entry
->pin
= old_entry
->pin
;
267 old_entry
= old_entry
->next
;
269 entry
= get_one_free_irq_2_pin(cpu
);
277 /* still use the old one */
280 entry
->apic
= old_entry
->apic
;
281 entry
->pin
= old_entry
->pin
;
284 old_entry
= old_entry
->next
;
288 cfg
->irq_2_pin
= head
;
291 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
293 struct irq_pin_list
*entry
, *next
;
295 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
298 entry
= old_cfg
->irq_2_pin
;
305 old_cfg
->irq_2_pin
= NULL
;
308 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
309 struct irq_desc
*desc
, int cpu
)
312 struct irq_cfg
*old_cfg
;
314 cfg
= get_one_free_irq_cfg(cpu
);
319 desc
->chip_data
= cfg
;
321 old_cfg
= old_desc
->chip_data
;
323 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
325 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
328 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
333 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
335 struct irq_cfg
*old_cfg
, *cfg
;
337 old_cfg
= old_desc
->chip_data
;
338 cfg
= desc
->chip_data
;
344 free_irq_2_pin(old_cfg
, cfg
);
345 free_irq_cfg(old_cfg
);
346 old_desc
->chip_data
= NULL
;
351 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
353 struct irq_cfg
*cfg
= desc
->chip_data
;
355 if (!cfg
->move_in_progress
) {
356 /* it means that domain is not changed */
357 if (!cpumask_intersects(&desc
->affinity
, mask
))
358 cfg
->move_desc_pending
= 1;
364 static struct irq_cfg
*irq_cfg(unsigned int irq
)
366 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
371 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
373 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
380 unsigned int unused
[3];
384 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
386 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
387 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
390 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
392 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
393 writel(reg
, &io_apic
->index
);
394 return readl(&io_apic
->data
);
397 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
399 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
400 writel(reg
, &io_apic
->index
);
401 writel(value
, &io_apic
->data
);
405 * Re-write a value: to be used for read-modify-write
406 * cycles where the read already set up the index register.
408 * Older SiS APIC requires we rewrite the index register
410 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
412 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
415 writel(reg
, &io_apic
->index
);
416 writel(value
, &io_apic
->data
);
419 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
421 struct irq_pin_list
*entry
;
424 spin_lock_irqsave(&ioapic_lock
, flags
);
425 entry
= cfg
->irq_2_pin
;
433 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
434 /* Is the remote IRR bit set? */
435 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
436 spin_unlock_irqrestore(&ioapic_lock
, flags
);
443 spin_unlock_irqrestore(&ioapic_lock
, flags
);
449 struct { u32 w1
, w2
; };
450 struct IO_APIC_route_entry entry
;
453 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
455 union entry_union eu
;
457 spin_lock_irqsave(&ioapic_lock
, flags
);
458 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
459 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
460 spin_unlock_irqrestore(&ioapic_lock
, flags
);
465 * When we write a new IO APIC routing entry, we need to write the high
466 * word first! If the mask bit in the low word is clear, we will enable
467 * the interrupt, and we need to make sure the entry is fully populated
468 * before that happens.
471 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
473 union entry_union eu
;
475 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
476 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
479 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
482 spin_lock_irqsave(&ioapic_lock
, flags
);
483 __ioapic_write_entry(apic
, pin
, e
);
484 spin_unlock_irqrestore(&ioapic_lock
, flags
);
488 * When we mask an IO APIC routing entry, we need to write the low
489 * word first, in order to set the mask bit before we change the
492 static void ioapic_mask_entry(int apic
, int pin
)
495 union entry_union eu
= { .entry
.mask
= 1 };
497 spin_lock_irqsave(&ioapic_lock
, flags
);
498 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
499 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
500 spin_unlock_irqrestore(&ioapic_lock
, flags
);
504 static void send_cleanup_vector(struct irq_cfg
*cfg
)
506 cpumask_var_t cleanup_mask
;
508 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
510 cfg
->move_cleanup_count
= 0;
511 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
512 cfg
->move_cleanup_count
++;
513 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
514 send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
516 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
517 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
518 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
519 free_cpumask_var(cleanup_mask
);
521 cfg
->move_in_progress
= 0;
524 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
527 struct irq_pin_list
*entry
;
528 u8 vector
= cfg
->vector
;
530 entry
= cfg
->irq_2_pin
;
539 #ifdef CONFIG_INTR_REMAP
541 * With interrupt-remapping, destination information comes
542 * from interrupt-remapping table entry.
544 if (!irq_remapped(irq
))
545 io_apic_write(apic
, 0x11 + pin
*2, dest
);
547 io_apic_write(apic
, 0x11 + pin
*2, dest
);
549 reg
= io_apic_read(apic
, 0x10 + pin
*2);
550 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
552 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
560 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
563 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
564 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
567 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
572 if (!cpumask_intersects(mask
, cpu_online_mask
))
576 cfg
= desc
->chip_data
;
577 if (assign_irq_vector(irq
, cfg
, mask
))
580 cpumask_and(&desc
->affinity
, cfg
->domain
, mask
);
581 set_extra_move_desc(desc
, mask
);
582 return cpu_mask_to_apicid_and(&desc
->affinity
, cpu_online_mask
);
586 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
594 cfg
= desc
->chip_data
;
596 spin_lock_irqsave(&ioapic_lock
, flags
);
597 dest
= set_desc_affinity(desc
, mask
);
598 if (dest
!= BAD_APICID
) {
599 /* Only the high 8 bits are valid. */
600 dest
= SET_APIC_LOGICAL_ID(dest
);
601 __target_IO_APIC_irq(irq
, dest
, cfg
);
603 spin_unlock_irqrestore(&ioapic_lock
, flags
);
607 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
609 struct irq_desc
*desc
;
611 desc
= irq_to_desc(irq
);
613 set_ioapic_affinity_irq_desc(desc
, mask
);
615 #endif /* CONFIG_SMP */
618 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
619 * shared ISA-space IRQs, so we have to support them. We are super
620 * fast in the common case, and fast for shared ISA-space IRQs.
622 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
624 struct irq_pin_list
*entry
;
626 entry
= cfg
->irq_2_pin
;
628 entry
= get_one_free_irq_2_pin(cpu
);
630 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
634 cfg
->irq_2_pin
= entry
;
640 while (entry
->next
) {
641 /* not again, please */
642 if (entry
->apic
== apic
&& entry
->pin
== pin
)
648 entry
->next
= get_one_free_irq_2_pin(cpu
);
655 * Reroute an IRQ to a different pin.
657 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
658 int oldapic
, int oldpin
,
659 int newapic
, int newpin
)
661 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
665 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
666 entry
->apic
= newapic
;
669 /* every one is different, right? */
675 /* why? call replace before add? */
677 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
680 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
681 int mask_and
, int mask_or
,
682 void (*final
)(struct irq_pin_list
*entry
))
685 struct irq_pin_list
*entry
;
687 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
690 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
693 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
699 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
701 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
705 void io_apic_sync(struct irq_pin_list
*entry
)
708 * Synchronize the IO-APIC and the CPU by doing
709 * a dummy read from the IO-APIC
711 struct io_apic __iomem
*io_apic
;
712 io_apic
= io_apic_base(entry
->apic
);
713 readl(&io_apic
->data
);
716 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
718 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
720 #else /* CONFIG_X86_32 */
721 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
723 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
726 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
728 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
729 IO_APIC_REDIR_MASKED
, NULL
);
732 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
734 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
735 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
737 #endif /* CONFIG_X86_32 */
739 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
741 struct irq_cfg
*cfg
= desc
->chip_data
;
746 spin_lock_irqsave(&ioapic_lock
, flags
);
747 __mask_IO_APIC_irq(cfg
);
748 spin_unlock_irqrestore(&ioapic_lock
, flags
);
751 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
753 struct irq_cfg
*cfg
= desc
->chip_data
;
756 spin_lock_irqsave(&ioapic_lock
, flags
);
757 __unmask_IO_APIC_irq(cfg
);
758 spin_unlock_irqrestore(&ioapic_lock
, flags
);
761 static void mask_IO_APIC_irq(unsigned int irq
)
763 struct irq_desc
*desc
= irq_to_desc(irq
);
765 mask_IO_APIC_irq_desc(desc
);
767 static void unmask_IO_APIC_irq(unsigned int irq
)
769 struct irq_desc
*desc
= irq_to_desc(irq
);
771 unmask_IO_APIC_irq_desc(desc
);
774 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
776 struct IO_APIC_route_entry entry
;
778 /* Check delivery_mode to be sure we're not clearing an SMI pin */
779 entry
= ioapic_read_entry(apic
, pin
);
780 if (entry
.delivery_mode
== dest_SMI
)
783 * Disable it in the IO-APIC irq-routing table:
785 ioapic_mask_entry(apic
, pin
);
788 static void clear_IO_APIC (void)
792 for (apic
= 0; apic
< nr_ioapics
; apic
++)
793 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
794 clear_IO_APIC_pin(apic
, pin
);
797 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
798 void send_IPI_self(int vector
)
805 apic_wait_icr_idle();
806 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
808 * Send the IPI. The write to APIC_ICR fires this off.
810 apic_write(APIC_ICR
, cfg
);
812 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
816 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
817 * specific CPU-side IRQs.
821 static int pirq_entries
[MAX_PIRQS
];
822 static int pirqs_enabled
;
824 static int __init
ioapic_pirq_setup(char *str
)
827 int ints
[MAX_PIRQS
+1];
829 get_options(str
, ARRAY_SIZE(ints
), ints
);
831 for (i
= 0; i
< MAX_PIRQS
; i
++)
832 pirq_entries
[i
] = -1;
835 apic_printk(APIC_VERBOSE
, KERN_INFO
836 "PIRQ redirection, working around broken MP-BIOS.\n");
838 if (ints
[0] < MAX_PIRQS
)
841 for (i
= 0; i
< max
; i
++) {
842 apic_printk(APIC_VERBOSE
, KERN_DEBUG
843 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
845 * PIRQs are mapped upside down, usually.
847 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
852 __setup("pirq=", ioapic_pirq_setup
);
853 #endif /* CONFIG_X86_32 */
855 #ifdef CONFIG_INTR_REMAP
856 /* I/O APIC RTE contents at the OS boot up */
857 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
860 * Saves and masks all the unmasked IO-APIC RTE's
862 int save_mask_IO_APIC_setup(void)
864 union IO_APIC_reg_01 reg_01
;
869 * The number of IO-APIC IRQ registers (== #pins):
871 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
872 spin_lock_irqsave(&ioapic_lock
, flags
);
873 reg_01
.raw
= io_apic_read(apic
, 1);
874 spin_unlock_irqrestore(&ioapic_lock
, flags
);
875 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
878 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
879 early_ioapic_entries
[apic
] =
880 kzalloc(sizeof(struct IO_APIC_route_entry
) *
881 nr_ioapic_registers
[apic
], GFP_KERNEL
);
882 if (!early_ioapic_entries
[apic
])
886 for (apic
= 0; apic
< nr_ioapics
; apic
++)
887 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
888 struct IO_APIC_route_entry entry
;
890 entry
= early_ioapic_entries
[apic
][pin
] =
891 ioapic_read_entry(apic
, pin
);
894 ioapic_write_entry(apic
, pin
, entry
);
902 kfree(early_ioapic_entries
[apic
--]);
903 memset(early_ioapic_entries
, 0,
904 ARRAY_SIZE(early_ioapic_entries
));
909 void restore_IO_APIC_setup(void)
913 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
914 if (!early_ioapic_entries
[apic
])
916 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
917 ioapic_write_entry(apic
, pin
,
918 early_ioapic_entries
[apic
][pin
]);
919 kfree(early_ioapic_entries
[apic
]);
920 early_ioapic_entries
[apic
] = NULL
;
924 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
927 * for now plain restore of previous settings.
928 * TBD: In the case of OS enabling interrupt-remapping,
929 * IO-APIC RTE's need to be setup to point to interrupt-remapping
930 * table entries. for now, do a plain restore, and wait for
931 * the setup_IO_APIC_irqs() to do proper initialization.
933 restore_IO_APIC_setup();
938 * Find the IRQ entry number of a certain pin.
940 static int find_irq_entry(int apic
, int pin
, int type
)
944 for (i
= 0; i
< mp_irq_entries
; i
++)
945 if (mp_irqs
[i
].mp_irqtype
== type
&&
946 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
947 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
948 mp_irqs
[i
].mp_dstirq
== pin
)
955 * Find the pin to which IRQ[irq] (ISA) is connected
957 static int __init
find_isa_irq_pin(int irq
, int type
)
961 for (i
= 0; i
< mp_irq_entries
; i
++) {
962 int lbus
= mp_irqs
[i
].mp_srcbus
;
964 if (test_bit(lbus
, mp_bus_not_pci
) &&
965 (mp_irqs
[i
].mp_irqtype
== type
) &&
966 (mp_irqs
[i
].mp_srcbusirq
== irq
))
968 return mp_irqs
[i
].mp_dstirq
;
973 static int __init
find_isa_irq_apic(int irq
, int type
)
977 for (i
= 0; i
< mp_irq_entries
; i
++) {
978 int lbus
= mp_irqs
[i
].mp_srcbus
;
980 if (test_bit(lbus
, mp_bus_not_pci
) &&
981 (mp_irqs
[i
].mp_irqtype
== type
) &&
982 (mp_irqs
[i
].mp_srcbusirq
== irq
))
985 if (i
< mp_irq_entries
) {
987 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
988 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
997 * Find a specific PCI IRQ entry.
998 * Not an __init, possibly needed by modules
1000 static int pin_2_irq(int idx
, int apic
, int pin
);
1002 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1004 int apic
, i
, best_guess
= -1;
1006 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1008 if (test_bit(bus
, mp_bus_not_pci
)) {
1009 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1012 for (i
= 0; i
< mp_irq_entries
; i
++) {
1013 int lbus
= mp_irqs
[i
].mp_srcbus
;
1015 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1016 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
1017 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
1020 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1021 !mp_irqs
[i
].mp_irqtype
&&
1023 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
1024 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
1026 if (!(apic
|| IO_APIC_IRQ(irq
)))
1029 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
1032 * Use the first all-but-pin matching entry as a
1033 * best-guess fuzzy result for broken mptables.
1042 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1044 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1046 * EISA Edge/Level control register, ELCR
1048 static int EISA_ELCR(unsigned int irq
)
1050 if (irq
< NR_IRQS_LEGACY
) {
1051 unsigned int port
= 0x4d0 + (irq
>> 3);
1052 return (inb(port
) >> (irq
& 7)) & 1;
1054 apic_printk(APIC_VERBOSE
, KERN_INFO
1055 "Broken MPtable reports ISA irq %d\n", irq
);
1061 /* ISA interrupts are always polarity zero edge triggered,
1062 * when listed as conforming in the MP table. */
1064 #define default_ISA_trigger(idx) (0)
1065 #define default_ISA_polarity(idx) (0)
1067 /* EISA interrupts are always polarity zero and can be edge or level
1068 * trigger depending on the ELCR value. If an interrupt is listed as
1069 * EISA conforming in the MP table, that means its trigger type must
1070 * be read in from the ELCR */
1072 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1073 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1075 /* PCI interrupts are always polarity one level triggered,
1076 * when listed as conforming in the MP table. */
1078 #define default_PCI_trigger(idx) (1)
1079 #define default_PCI_polarity(idx) (1)
1081 /* MCA interrupts are always polarity zero level triggered,
1082 * when listed as conforming in the MP table. */
1084 #define default_MCA_trigger(idx) (1)
1085 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1087 static int MPBIOS_polarity(int idx
)
1089 int bus
= mp_irqs
[idx
].mp_srcbus
;
1093 * Determine IRQ line polarity (high active or low active):
1095 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1097 case 0: /* conforms, ie. bus-type dependent polarity */
1098 if (test_bit(bus
, mp_bus_not_pci
))
1099 polarity
= default_ISA_polarity(idx
);
1101 polarity
= default_PCI_polarity(idx
);
1103 case 1: /* high active */
1108 case 2: /* reserved */
1110 printk(KERN_WARNING
"broken BIOS!!\n");
1114 case 3: /* low active */
1119 default: /* invalid */
1121 printk(KERN_WARNING
"broken BIOS!!\n");
1129 static int MPBIOS_trigger(int idx
)
1131 int bus
= mp_irqs
[idx
].mp_srcbus
;
1135 * Determine IRQ trigger mode (edge or level sensitive):
1137 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1139 case 0: /* conforms, ie. bus-type dependent */
1140 if (test_bit(bus
, mp_bus_not_pci
))
1141 trigger
= default_ISA_trigger(idx
);
1143 trigger
= default_PCI_trigger(idx
);
1144 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1145 switch (mp_bus_id_to_type
[bus
]) {
1146 case MP_BUS_ISA
: /* ISA pin */
1148 /* set before the switch */
1151 case MP_BUS_EISA
: /* EISA pin */
1153 trigger
= default_EISA_trigger(idx
);
1156 case MP_BUS_PCI
: /* PCI pin */
1158 /* set before the switch */
1161 case MP_BUS_MCA
: /* MCA pin */
1163 trigger
= default_MCA_trigger(idx
);
1168 printk(KERN_WARNING
"broken BIOS!!\n");
1180 case 2: /* reserved */
1182 printk(KERN_WARNING
"broken BIOS!!\n");
1191 default: /* invalid */
1193 printk(KERN_WARNING
"broken BIOS!!\n");
1201 static inline int irq_polarity(int idx
)
1203 return MPBIOS_polarity(idx
);
1206 static inline int irq_trigger(int idx
)
1208 return MPBIOS_trigger(idx
);
1211 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1212 static int pin_2_irq(int idx
, int apic
, int pin
)
1215 int bus
= mp_irqs
[idx
].mp_srcbus
;
1218 * Debugging check, we are in big trouble if this message pops up!
1220 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1221 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1223 if (test_bit(bus
, mp_bus_not_pci
)) {
1224 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1227 * PCI IRQs are mapped in order
1231 irq
+= nr_ioapic_registers
[i
++];
1234 * For MPS mode, so far only needed by ES7000 platform
1236 if (ioapic_renumber_irq
)
1237 irq
= ioapic_renumber_irq(apic
, irq
);
1240 #ifdef CONFIG_X86_32
1242 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1244 if ((pin
>= 16) && (pin
<= 23)) {
1245 if (pirq_entries
[pin
-16] != -1) {
1246 if (!pirq_entries
[pin
-16]) {
1247 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1248 "disabling PIRQ%d\n", pin
-16);
1250 irq
= pirq_entries
[pin
-16];
1251 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1252 "using PIRQ%d -> IRQ %d\n",
1262 void lock_vector_lock(void)
1264 /* Used to the online set of cpus does not change
1265 * during assign_irq_vector.
1267 spin_lock(&vector_lock
);
1270 void unlock_vector_lock(void)
1272 spin_unlock(&vector_lock
);
1276 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1279 * NOTE! The local APIC isn't very good at handling
1280 * multiple interrupts at the same interrupt level.
1281 * As the interrupt level is determined by taking the
1282 * vector number and shifting that right by 4, we
1283 * want to spread these out a bit so that they don't
1284 * all fall in the same interrupt level.
1286 * Also, we've got to be careful not to trash gate
1287 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1289 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1290 unsigned int old_vector
;
1292 cpumask_var_t tmp_mask
;
1294 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1297 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1300 old_vector
= cfg
->vector
;
1302 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1303 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1304 if (!cpumask_empty(tmp_mask
)) {
1305 free_cpumask_var(tmp_mask
);
1310 /* Only try and allocate irqs on cpus that are present */
1312 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1316 vector_allocation_domain(cpu
, tmp_mask
);
1318 vector
= current_vector
;
1319 offset
= current_offset
;
1322 if (vector
>= first_system_vector
) {
1323 /* If out of vectors on large boxen, must share them. */
1324 offset
= (offset
+ 1) % 8;
1325 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1327 if (unlikely(current_vector
== vector
))
1330 if (test_bit(vector
, used_vectors
))
1333 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1334 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1337 current_vector
= vector
;
1338 current_offset
= offset
;
1340 cfg
->move_in_progress
= 1;
1341 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1343 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1344 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1345 cfg
->vector
= vector
;
1346 cpumask_copy(cfg
->domain
, tmp_mask
);
1350 free_cpumask_var(tmp_mask
);
1355 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1358 unsigned long flags
;
1360 spin_lock_irqsave(&vector_lock
, flags
);
1361 err
= __assign_irq_vector(irq
, cfg
, mask
);
1362 spin_unlock_irqrestore(&vector_lock
, flags
);
1366 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1370 BUG_ON(!cfg
->vector
);
1372 vector
= cfg
->vector
;
1373 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1374 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1377 cpumask_clear(cfg
->domain
);
1379 if (likely(!cfg
->move_in_progress
))
1381 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1382 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1384 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1386 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1390 cfg
->move_in_progress
= 0;
1393 void __setup_vector_irq(int cpu
)
1395 /* Initialize vector_irq on a new cpu */
1396 /* This function must be called with vector_lock held */
1398 struct irq_cfg
*cfg
;
1399 struct irq_desc
*desc
;
1401 /* Mark the inuse vectors */
1402 for_each_irq_desc(irq
, desc
) {
1405 cfg
= desc
->chip_data
;
1406 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1408 vector
= cfg
->vector
;
1409 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1411 /* Mark the free vectors */
1412 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1413 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1418 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1419 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1423 static struct irq_chip ioapic_chip
;
1424 #ifdef CONFIG_INTR_REMAP
1425 static struct irq_chip ir_ioapic_chip
;
1428 #define IOAPIC_AUTO -1
1429 #define IOAPIC_EDGE 0
1430 #define IOAPIC_LEVEL 1
1432 #ifdef CONFIG_X86_32
1433 static inline int IO_APIC_irq_trigger(int irq
)
1437 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1438 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1439 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1440 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1441 return irq_trigger(idx
);
1445 * nonexistent IRQs are edge default
1450 static inline int IO_APIC_irq_trigger(int irq
)
1456 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1459 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1460 trigger
== IOAPIC_LEVEL
)
1461 desc
->status
|= IRQ_LEVEL
;
1463 desc
->status
&= ~IRQ_LEVEL
;
1465 #ifdef CONFIG_INTR_REMAP
1466 if (irq_remapped(irq
)) {
1467 desc
->status
|= IRQ_MOVE_PCNTXT
;
1469 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1473 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1474 handle_edge_irq
, "edge");
1478 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1479 trigger
== IOAPIC_LEVEL
)
1480 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1484 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1485 handle_edge_irq
, "edge");
1488 static int setup_ioapic_entry(int apic
, int irq
,
1489 struct IO_APIC_route_entry
*entry
,
1490 unsigned int destination
, int trigger
,
1491 int polarity
, int vector
)
1494 * add it to the IO-APIC irq-routing table:
1496 memset(entry
,0,sizeof(*entry
));
1498 #ifdef CONFIG_INTR_REMAP
1499 if (intr_remapping_enabled
) {
1500 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1502 struct IR_IO_APIC_route_entry
*ir_entry
=
1503 (struct IR_IO_APIC_route_entry
*) entry
;
1507 panic("No mapping iommu for ioapic %d\n", apic
);
1509 index
= alloc_irte(iommu
, irq
, 1);
1511 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1513 memset(&irte
, 0, sizeof(irte
));
1516 irte
.dst_mode
= INT_DEST_MODE
;
1517 irte
.trigger_mode
= trigger
;
1518 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1519 irte
.vector
= vector
;
1520 irte
.dest_id
= IRTE_DEST(destination
);
1522 modify_irte(irq
, &irte
);
1524 ir_entry
->index2
= (index
>> 15) & 0x1;
1526 ir_entry
->format
= 1;
1527 ir_entry
->index
= (index
& 0x7fff);
1531 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1532 entry
->dest_mode
= INT_DEST_MODE
;
1533 entry
->dest
= destination
;
1536 entry
->mask
= 0; /* enable IRQ */
1537 entry
->trigger
= trigger
;
1538 entry
->polarity
= polarity
;
1539 entry
->vector
= vector
;
1541 /* Mask level triggered irqs.
1542 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1549 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1550 int trigger
, int polarity
)
1552 struct irq_cfg
*cfg
;
1553 struct IO_APIC_route_entry entry
;
1556 if (!IO_APIC_IRQ(irq
))
1559 cfg
= desc
->chip_data
;
1561 if (assign_irq_vector(irq
, cfg
, TARGET_CPUS
))
1564 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
1566 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1567 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1568 "IRQ %d Mode:%i Active:%i)\n",
1569 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1570 irq
, trigger
, polarity
);
1573 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1574 dest
, trigger
, polarity
, cfg
->vector
)) {
1575 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1576 mp_ioapics
[apic
].mp_apicid
, pin
);
1577 __clear_irq_vector(irq
, cfg
);
1581 ioapic_register_intr(irq
, desc
, trigger
);
1582 if (irq
< NR_IRQS_LEGACY
)
1583 disable_8259A_irq(irq
);
1585 ioapic_write_entry(apic
, pin
, entry
);
1588 static void __init
setup_IO_APIC_irqs(void)
1590 int apic
, pin
, idx
, irq
;
1592 struct irq_desc
*desc
;
1593 struct irq_cfg
*cfg
;
1594 int cpu
= boot_cpu_id
;
1596 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1598 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1599 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1601 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1605 apic_printk(APIC_VERBOSE
,
1606 KERN_DEBUG
" %d-%d",
1607 mp_ioapics
[apic
].mp_apicid
,
1610 apic_printk(APIC_VERBOSE
, " %d-%d",
1611 mp_ioapics
[apic
].mp_apicid
,
1616 apic_printk(APIC_VERBOSE
,
1617 " (apicid-pin) not connected\n");
1621 irq
= pin_2_irq(idx
, apic
, pin
);
1622 #ifdef CONFIG_X86_32
1623 if (multi_timer_check(apic
, irq
))
1626 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1628 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1631 cfg
= desc
->chip_data
;
1632 add_pin_to_irq_cpu(cfg
, cpu
, apic
, pin
);
1634 setup_IO_APIC_irq(apic
, pin
, irq
, desc
,
1635 irq_trigger(idx
), irq_polarity(idx
));
1640 apic_printk(APIC_VERBOSE
,
1641 " (apicid-pin) not connected\n");
1645 * Set up the timer pin, possibly with the 8259A-master behind.
1647 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1650 struct IO_APIC_route_entry entry
;
1652 #ifdef CONFIG_INTR_REMAP
1653 if (intr_remapping_enabled
)
1657 memset(&entry
, 0, sizeof(entry
));
1660 * We use logical delivery to get the timer IRQ
1663 entry
.dest_mode
= INT_DEST_MODE
;
1664 entry
.mask
= 1; /* mask IRQ now */
1665 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1666 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1669 entry
.vector
= vector
;
1672 * The timer IRQ doesn't have to know that behind the
1673 * scene we may have a 8259A-master in AEOI mode ...
1675 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1678 * Add it to the IO-APIC irq-routing table:
1680 ioapic_write_entry(apic
, pin
, entry
);
1684 __apicdebuginit(void) print_IO_APIC(void)
1687 union IO_APIC_reg_00 reg_00
;
1688 union IO_APIC_reg_01 reg_01
;
1689 union IO_APIC_reg_02 reg_02
;
1690 union IO_APIC_reg_03 reg_03
;
1691 unsigned long flags
;
1692 struct irq_cfg
*cfg
;
1693 struct irq_desc
*desc
;
1696 if (apic_verbosity
== APIC_QUIET
)
1699 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1700 for (i
= 0; i
< nr_ioapics
; i
++)
1701 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1702 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1705 * We are a bit conservative about what we expect. We have to
1706 * know about every hardware change ASAP.
1708 printk(KERN_INFO
"testing the IO APIC.......................\n");
1710 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1712 spin_lock_irqsave(&ioapic_lock
, flags
);
1713 reg_00
.raw
= io_apic_read(apic
, 0);
1714 reg_01
.raw
= io_apic_read(apic
, 1);
1715 if (reg_01
.bits
.version
>= 0x10)
1716 reg_02
.raw
= io_apic_read(apic
, 2);
1717 if (reg_01
.bits
.version
>= 0x20)
1718 reg_03
.raw
= io_apic_read(apic
, 3);
1719 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1722 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1723 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1724 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1725 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1726 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1728 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1729 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1731 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1732 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1735 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1736 * but the value of reg_02 is read as the previous read register
1737 * value, so ignore it if reg_02 == reg_01.
1739 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1740 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1741 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1745 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1746 * or reg_03, but the value of reg_0[23] is read as the previous read
1747 * register value, so ignore it if reg_03 == reg_0[12].
1749 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1750 reg_03
.raw
!= reg_01
.raw
) {
1751 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1752 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1755 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1757 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1758 " Stat Dmod Deli Vect: \n");
1760 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1761 struct IO_APIC_route_entry entry
;
1763 entry
= ioapic_read_entry(apic
, i
);
1765 printk(KERN_DEBUG
" %02x %03X ",
1770 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1775 entry
.delivery_status
,
1777 entry
.delivery_mode
,
1782 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1783 for_each_irq_desc(irq
, desc
) {
1784 struct irq_pin_list
*entry
;
1788 cfg
= desc
->chip_data
;
1789 entry
= cfg
->irq_2_pin
;
1792 printk(KERN_DEBUG
"IRQ%d ", irq
);
1794 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1797 entry
= entry
->next
;
1802 printk(KERN_INFO
".................................... done.\n");
1807 __apicdebuginit(void) print_APIC_bitfield(int base
)
1812 if (apic_verbosity
== APIC_QUIET
)
1815 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1816 for (i
= 0; i
< 8; i
++) {
1817 v
= apic_read(base
+ i
*0x10);
1818 for (j
= 0; j
< 32; j
++) {
1828 __apicdebuginit(void) print_local_APIC(void *dummy
)
1830 unsigned int v
, ver
, maxlvt
;
1833 if (apic_verbosity
== APIC_QUIET
)
1836 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1837 smp_processor_id(), hard_smp_processor_id());
1838 v
= apic_read(APIC_ID
);
1839 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1840 v
= apic_read(APIC_LVR
);
1841 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1842 ver
= GET_APIC_VERSION(v
);
1843 maxlvt
= lapic_get_maxlvt();
1845 v
= apic_read(APIC_TASKPRI
);
1846 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1848 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1849 if (!APIC_XAPIC(ver
)) {
1850 v
= apic_read(APIC_ARBPRI
);
1851 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1852 v
& APIC_ARBPRI_MASK
);
1854 v
= apic_read(APIC_PROCPRI
);
1855 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1859 * Remote read supported only in the 82489DX and local APIC for
1860 * Pentium processors.
1862 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1863 v
= apic_read(APIC_RRR
);
1864 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1867 v
= apic_read(APIC_LDR
);
1868 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1869 if (!x2apic_enabled()) {
1870 v
= apic_read(APIC_DFR
);
1871 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1873 v
= apic_read(APIC_SPIV
);
1874 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1876 printk(KERN_DEBUG
"... APIC ISR field:\n");
1877 print_APIC_bitfield(APIC_ISR
);
1878 printk(KERN_DEBUG
"... APIC TMR field:\n");
1879 print_APIC_bitfield(APIC_TMR
);
1880 printk(KERN_DEBUG
"... APIC IRR field:\n");
1881 print_APIC_bitfield(APIC_IRR
);
1883 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1884 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1885 apic_write(APIC_ESR
, 0);
1887 v
= apic_read(APIC_ESR
);
1888 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1891 icr
= apic_icr_read();
1892 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1893 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1895 v
= apic_read(APIC_LVTT
);
1896 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1898 if (maxlvt
> 3) { /* PC is LVT#4. */
1899 v
= apic_read(APIC_LVTPC
);
1900 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1902 v
= apic_read(APIC_LVT0
);
1903 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1904 v
= apic_read(APIC_LVT1
);
1905 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1907 if (maxlvt
> 2) { /* ERR is LVT#3. */
1908 v
= apic_read(APIC_LVTERR
);
1909 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1912 v
= apic_read(APIC_TMICT
);
1913 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1914 v
= apic_read(APIC_TMCCT
);
1915 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1916 v
= apic_read(APIC_TDCR
);
1917 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1921 __apicdebuginit(void) print_all_local_APICs(void)
1926 for_each_online_cpu(cpu
)
1927 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1931 __apicdebuginit(void) print_PIC(void)
1934 unsigned long flags
;
1936 if (apic_verbosity
== APIC_QUIET
)
1939 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1941 spin_lock_irqsave(&i8259A_lock
, flags
);
1943 v
= inb(0xa1) << 8 | inb(0x21);
1944 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1946 v
= inb(0xa0) << 8 | inb(0x20);
1947 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1951 v
= inb(0xa0) << 8 | inb(0x20);
1955 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1957 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1959 v
= inb(0x4d1) << 8 | inb(0x4d0);
1960 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1963 __apicdebuginit(int) print_all_ICs(void)
1966 print_all_local_APICs();
1972 fs_initcall(print_all_ICs
);
1975 /* Where if anywhere is the i8259 connect in external int mode */
1976 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1978 void __init
enable_IO_APIC(void)
1980 union IO_APIC_reg_01 reg_01
;
1981 int i8259_apic
, i8259_pin
;
1983 unsigned long flags
;
1985 #ifdef CONFIG_X86_32
1988 for (i
= 0; i
< MAX_PIRQS
; i
++)
1989 pirq_entries
[i
] = -1;
1993 * The number of IO-APIC IRQ registers (== #pins):
1995 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1996 spin_lock_irqsave(&ioapic_lock
, flags
);
1997 reg_01
.raw
= io_apic_read(apic
, 1);
1998 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1999 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2001 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2003 /* See if any of the pins is in ExtINT mode */
2004 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2005 struct IO_APIC_route_entry entry
;
2006 entry
= ioapic_read_entry(apic
, pin
);
2008 /* If the interrupt line is enabled and in ExtInt mode
2009 * I have found the pin where the i8259 is connected.
2011 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2012 ioapic_i8259
.apic
= apic
;
2013 ioapic_i8259
.pin
= pin
;
2019 /* Look to see what if the MP table has reported the ExtINT */
2020 /* If we could not find the appropriate pin by looking at the ioapic
2021 * the i8259 probably is not connected the ioapic but give the
2022 * mptable a chance anyway.
2024 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2025 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2026 /* Trust the MP table if nothing is setup in the hardware */
2027 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2028 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2029 ioapic_i8259
.pin
= i8259_pin
;
2030 ioapic_i8259
.apic
= i8259_apic
;
2032 /* Complain if the MP table and the hardware disagree */
2033 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2034 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2036 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2040 * Do not trust the IO-APIC being empty at bootup
2046 * Not an __init, needed by the reboot code
2048 void disable_IO_APIC(void)
2051 * Clear the IO-APIC before rebooting:
2056 * If the i8259 is routed through an IOAPIC
2057 * Put that IOAPIC in virtual wire mode
2058 * so legacy interrupts can be delivered.
2060 if (ioapic_i8259
.pin
!= -1) {
2061 struct IO_APIC_route_entry entry
;
2063 memset(&entry
, 0, sizeof(entry
));
2064 entry
.mask
= 0; /* Enabled */
2065 entry
.trigger
= 0; /* Edge */
2067 entry
.polarity
= 0; /* High */
2068 entry
.delivery_status
= 0;
2069 entry
.dest_mode
= 0; /* Physical */
2070 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2072 entry
.dest
= read_apic_id();
2075 * Add it to the IO-APIC irq-routing table:
2077 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2080 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2083 #ifdef CONFIG_X86_32
2085 * function to set the IO-APIC physical IDs based on the
2086 * values stored in the MPC table.
2088 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2091 static void __init
setup_ioapic_ids_from_mpc(void)
2093 union IO_APIC_reg_00 reg_00
;
2094 physid_mask_t phys_id_present_map
;
2097 unsigned char old_id
;
2098 unsigned long flags
;
2100 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2104 * Don't check I/O APIC IDs for xAPIC systems. They have
2105 * no meaning without the serial APIC bus.
2107 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2108 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2111 * This is broken; anything with a real cpu count has to
2112 * circumvent this idiocy regardless.
2114 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2117 * Set the IOAPIC ID to the value stored in the MPC table.
2119 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2121 /* Read the register 0 value */
2122 spin_lock_irqsave(&ioapic_lock
, flags
);
2123 reg_00
.raw
= io_apic_read(apic
, 0);
2124 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2126 old_id
= mp_ioapics
[apic
].mp_apicid
;
2128 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2129 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2130 apic
, mp_ioapics
[apic
].mp_apicid
);
2131 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2133 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2137 * Sanity check, is the ID really free? Every APIC in a
2138 * system must have a unique ID or we get lots of nice
2139 * 'stuck on smp_invalidate_needed IPI wait' messages.
2141 if (check_apicid_used(phys_id_present_map
,
2142 mp_ioapics
[apic
].mp_apicid
)) {
2143 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2144 apic
, mp_ioapics
[apic
].mp_apicid
);
2145 for (i
= 0; i
< get_physical_broadcast(); i
++)
2146 if (!physid_isset(i
, phys_id_present_map
))
2148 if (i
>= get_physical_broadcast())
2149 panic("Max APIC ID exceeded!\n");
2150 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2152 physid_set(i
, phys_id_present_map
);
2153 mp_ioapics
[apic
].mp_apicid
= i
;
2156 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2157 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2158 "phys_id_present_map\n",
2159 mp_ioapics
[apic
].mp_apicid
);
2160 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2165 * We need to adjust the IRQ routing table
2166 * if the ID changed.
2168 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2169 for (i
= 0; i
< mp_irq_entries
; i
++)
2170 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2171 mp_irqs
[i
].mp_dstapic
2172 = mp_ioapics
[apic
].mp_apicid
;
2175 * Read the right value from the MPC table and
2176 * write it into the ID register.
2178 apic_printk(APIC_VERBOSE
, KERN_INFO
2179 "...changing IO-APIC physical APIC ID to %d ...",
2180 mp_ioapics
[apic
].mp_apicid
);
2182 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2183 spin_lock_irqsave(&ioapic_lock
, flags
);
2184 io_apic_write(apic
, 0, reg_00
.raw
);
2185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2190 spin_lock_irqsave(&ioapic_lock
, flags
);
2191 reg_00
.raw
= io_apic_read(apic
, 0);
2192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2193 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2194 printk("could not set ID!\n");
2196 apic_printk(APIC_VERBOSE
, " ok.\n");
2201 int no_timer_check __initdata
;
2203 static int __init
notimercheck(char *s
)
2208 __setup("no_timer_check", notimercheck
);
2211 * There is a nasty bug in some older SMP boards, their mptable lies
2212 * about the timer IRQ. We do the following to work around the situation:
2214 * - timer IRQ defaults to IO-APIC IRQ
2215 * - if this function detects that timer IRQs are defunct, then we fall
2216 * back to ISA timer IRQs
2218 static int __init
timer_irq_works(void)
2220 unsigned long t1
= jiffies
;
2221 unsigned long flags
;
2226 local_save_flags(flags
);
2228 /* Let ten ticks pass... */
2229 mdelay((10 * 1000) / HZ
);
2230 local_irq_restore(flags
);
2233 * Expect a few ticks at least, to be sure some possible
2234 * glue logic does not lock up after one or two first
2235 * ticks in a non-ExtINT mode. Also the local APIC
2236 * might have cached one ExtINT interrupt. Finally, at
2237 * least one tick may be lost due to delays.
2241 if (time_after(jiffies
, t1
+ 4))
2247 * In the SMP+IOAPIC case it might happen that there are an unspecified
2248 * number of pending IRQ events unhandled. These cases are very rare,
2249 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2250 * better to do it this way as thus we do not have to be aware of
2251 * 'pending' interrupts in the IRQ path, except at this point.
2254 * Edge triggered needs to resend any interrupt
2255 * that was delayed but this is now handled in the device
2260 * Starting up a edge-triggered IO-APIC interrupt is
2261 * nasty - we need to make sure that we get the edge.
2262 * If it is already asserted for some reason, we need
2263 * return 1 to indicate that is was pending.
2265 * This is not complete - we should be able to fake
2266 * an edge even if it isn't on the 8259A...
2269 static unsigned int startup_ioapic_irq(unsigned int irq
)
2271 int was_pending
= 0;
2272 unsigned long flags
;
2273 struct irq_cfg
*cfg
;
2275 spin_lock_irqsave(&ioapic_lock
, flags
);
2276 if (irq
< NR_IRQS_LEGACY
) {
2277 disable_8259A_irq(irq
);
2278 if (i8259A_irq_pending(irq
))
2282 __unmask_IO_APIC_irq(cfg
);
2283 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2288 #ifdef CONFIG_X86_64
2289 static int ioapic_retrigger_irq(unsigned int irq
)
2292 struct irq_cfg
*cfg
= irq_cfg(irq
);
2293 unsigned long flags
;
2295 spin_lock_irqsave(&vector_lock
, flags
);
2296 send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2297 spin_unlock_irqrestore(&vector_lock
, flags
);
2302 static int ioapic_retrigger_irq(unsigned int irq
)
2304 send_IPI_self(irq_cfg(irq
)->vector
);
2311 * Level and edge triggered IO-APIC interrupts need different handling,
2312 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2313 * handled with the level-triggered descriptor, but that one has slightly
2314 * more overhead. Level-triggered interrupts cannot be handled with the
2315 * edge-triggered handler, without risking IRQ storms and other ugly
2321 #ifdef CONFIG_INTR_REMAP
2322 static void ir_irq_migration(struct work_struct
*work
);
2324 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2327 * Migrate the IO-APIC irq in the presence of intr-remapping.
2329 * For edge triggered, irq migration is a simple atomic update(of vector
2330 * and cpu destination) of IRTE and flush the hardware cache.
2332 * For level triggered, we need to modify the io-apic RTE aswell with the update
2333 * vector information, along with modifying IRTE with vector and destination.
2334 * So irq migration for level triggered is little bit more complex compared to
2335 * edge triggered migration. But the good news is, we use the same algorithm
2336 * for level triggered migration as we have today, only difference being,
2337 * we now initiate the irq migration from process context instead of the
2338 * interrupt context.
2340 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2341 * suppression) to the IO-APIC, level triggered irq migration will also be
2342 * as simple as edge triggered migration and we can do the irq migration
2343 * with a simple atomic update to IO-APIC RTE.
2346 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2348 struct irq_cfg
*cfg
;
2350 int modify_ioapic_rte
;
2352 unsigned long flags
;
2355 if (!cpumask_intersects(mask
, cpu_online_mask
))
2359 if (get_irte(irq
, &irte
))
2362 cfg
= desc
->chip_data
;
2363 if (assign_irq_vector(irq
, cfg
, mask
))
2366 set_extra_move_desc(desc
, mask
);
2368 dest
= cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2370 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2371 if (modify_ioapic_rte
) {
2372 spin_lock_irqsave(&ioapic_lock
, flags
);
2373 __target_IO_APIC_irq(irq
, dest
, cfg
);
2374 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2377 irte
.vector
= cfg
->vector
;
2378 irte
.dest_id
= IRTE_DEST(dest
);
2381 * Modified the IRTE and flushes the Interrupt entry cache.
2383 modify_irte(irq
, &irte
);
2385 if (cfg
->move_in_progress
)
2386 send_cleanup_vector(cfg
);
2388 cpumask_copy(&desc
->affinity
, mask
);
2391 static int migrate_irq_remapped_level_desc(struct irq_desc
*desc
)
2394 struct irq_cfg
*cfg
= desc
->chip_data
;
2396 mask_IO_APIC_irq_desc(desc
);
2398 if (io_apic_level_ack_pending(cfg
)) {
2400 * Interrupt in progress. Migrating irq now will change the
2401 * vector information in the IO-APIC RTE and that will confuse
2402 * the EOI broadcast performed by cpu.
2403 * So, delay the irq migration to the next instance.
2405 schedule_delayed_work(&ir_migration_work
, 1);
2409 /* everthing is clear. we have right of way */
2410 migrate_ioapic_irq_desc(desc
, &desc
->pending_mask
);
2413 desc
->status
&= ~IRQ_MOVE_PENDING
;
2414 cpumask_clear(&desc
->pending_mask
);
2417 unmask_IO_APIC_irq_desc(desc
);
2422 static void ir_irq_migration(struct work_struct
*work
)
2425 struct irq_desc
*desc
;
2427 for_each_irq_desc(irq
, desc
) {
2431 if (desc
->status
& IRQ_MOVE_PENDING
) {
2432 unsigned long flags
;
2434 spin_lock_irqsave(&desc
->lock
, flags
);
2435 if (!desc
->chip
->set_affinity
||
2436 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2437 desc
->status
&= ~IRQ_MOVE_PENDING
;
2438 spin_unlock_irqrestore(&desc
->lock
, flags
);
2442 desc
->chip
->set_affinity(irq
, &desc
->pending_mask
);
2443 spin_unlock_irqrestore(&desc
->lock
, flags
);
2449 * Migrates the IRQ destination in the process context.
2451 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2452 const struct cpumask
*mask
)
2454 if (desc
->status
& IRQ_LEVEL
) {
2455 desc
->status
|= IRQ_MOVE_PENDING
;
2456 cpumask_copy(&desc
->pending_mask
, mask
);
2457 migrate_irq_remapped_level_desc(desc
);
2461 migrate_ioapic_irq_desc(desc
, mask
);
2463 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2464 const struct cpumask
*mask
)
2466 struct irq_desc
*desc
= irq_to_desc(irq
);
2468 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2472 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2474 unsigned vector
, me
;
2480 me
= smp_processor_id();
2481 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2483 struct irq_desc
*desc
;
2484 struct irq_cfg
*cfg
;
2485 irq
= __get_cpu_var(vector_irq
)[vector
];
2490 desc
= irq_to_desc(irq
);
2495 spin_lock(&desc
->lock
);
2496 if (!cfg
->move_cleanup_count
)
2499 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2502 __get_cpu_var(vector_irq
)[vector
] = -1;
2503 cfg
->move_cleanup_count
--;
2505 spin_unlock(&desc
->lock
);
2511 static void irq_complete_move(struct irq_desc
**descp
)
2513 struct irq_desc
*desc
= *descp
;
2514 struct irq_cfg
*cfg
= desc
->chip_data
;
2515 unsigned vector
, me
;
2517 if (likely(!cfg
->move_in_progress
)) {
2518 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2519 if (likely(!cfg
->move_desc_pending
))
2522 /* domain has not changed, but affinity did */
2523 me
= smp_processor_id();
2524 if (cpu_isset(me
, desc
->affinity
)) {
2525 *descp
= desc
= move_irq_desc(desc
, me
);
2526 /* get the new one */
2527 cfg
= desc
->chip_data
;
2528 cfg
->move_desc_pending
= 0;
2534 vector
= ~get_irq_regs()->orig_ax
;
2535 me
= smp_processor_id();
2536 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2537 *descp
= desc
= move_irq_desc(desc
, me
);
2538 /* get the new one */
2539 cfg
= desc
->chip_data
;
2542 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2543 send_cleanup_vector(cfg
);
2546 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2549 #ifdef CONFIG_INTR_REMAP
2550 static void ack_x2apic_level(unsigned int irq
)
2555 static void ack_x2apic_edge(unsigned int irq
)
2562 static void ack_apic_edge(unsigned int irq
)
2564 struct irq_desc
*desc
= irq_to_desc(irq
);
2566 irq_complete_move(&desc
);
2567 move_native_irq(irq
);
2571 atomic_t irq_mis_count
;
2573 static void ack_apic_level(unsigned int irq
)
2575 struct irq_desc
*desc
= irq_to_desc(irq
);
2577 #ifdef CONFIG_X86_32
2581 struct irq_cfg
*cfg
;
2582 int do_unmask_irq
= 0;
2584 irq_complete_move(&desc
);
2585 #ifdef CONFIG_GENERIC_PENDING_IRQ
2586 /* If we are moving the irq we need to mask it */
2587 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2589 mask_IO_APIC_irq_desc(desc
);
2593 #ifdef CONFIG_X86_32
2595 * It appears there is an erratum which affects at least version 0x11
2596 * of I/O APIC (that's the 82093AA and cores integrated into various
2597 * chipsets). Under certain conditions a level-triggered interrupt is
2598 * erroneously delivered as edge-triggered one but the respective IRR
2599 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2600 * message but it will never arrive and further interrupts are blocked
2601 * from the source. The exact reason is so far unknown, but the
2602 * phenomenon was observed when two consecutive interrupt requests
2603 * from a given source get delivered to the same CPU and the source is
2604 * temporarily disabled in between.
2606 * A workaround is to simulate an EOI message manually. We achieve it
2607 * by setting the trigger mode to edge and then to level when the edge
2608 * trigger mode gets detected in the TMR of a local APIC for a
2609 * level-triggered interrupt. We mask the source for the time of the
2610 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2611 * The idea is from Manfred Spraul. --macro
2613 cfg
= desc
->chip_data
;
2616 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2620 * We must acknowledge the irq before we move it or the acknowledge will
2621 * not propagate properly.
2625 /* Now we can move and renable the irq */
2626 if (unlikely(do_unmask_irq
)) {
2627 /* Only migrate the irq if the ack has been received.
2629 * On rare occasions the broadcast level triggered ack gets
2630 * delayed going to ioapics, and if we reprogram the
2631 * vector while Remote IRR is still set the irq will never
2634 * To prevent this scenario we read the Remote IRR bit
2635 * of the ioapic. This has two effects.
2636 * - On any sane system the read of the ioapic will
2637 * flush writes (and acks) going to the ioapic from
2639 * - We get to see if the ACK has actually been delivered.
2641 * Based on failed experiments of reprogramming the
2642 * ioapic entry from outside of irq context starting
2643 * with masking the ioapic entry and then polling until
2644 * Remote IRR was clear before reprogramming the
2645 * ioapic I don't trust the Remote IRR bit to be
2646 * completey accurate.
2648 * However there appears to be no other way to plug
2649 * this race, so if the Remote IRR bit is not
2650 * accurate and is causing problems then it is a hardware bug
2651 * and you can go talk to the chipset vendor about it.
2653 cfg
= desc
->chip_data
;
2654 if (!io_apic_level_ack_pending(cfg
))
2655 move_masked_irq(irq
);
2656 unmask_IO_APIC_irq_desc(desc
);
2659 #ifdef CONFIG_X86_32
2660 if (!(v
& (1 << (i
& 0x1f)))) {
2661 atomic_inc(&irq_mis_count
);
2662 spin_lock(&ioapic_lock
);
2663 __mask_and_edge_IO_APIC_irq(cfg
);
2664 __unmask_and_level_IO_APIC_irq(cfg
);
2665 spin_unlock(&ioapic_lock
);
2670 static struct irq_chip ioapic_chip __read_mostly
= {
2672 .startup
= startup_ioapic_irq
,
2673 .mask
= mask_IO_APIC_irq
,
2674 .unmask
= unmask_IO_APIC_irq
,
2675 .ack
= ack_apic_edge
,
2676 .eoi
= ack_apic_level
,
2678 .set_affinity
= set_ioapic_affinity_irq
,
2680 .retrigger
= ioapic_retrigger_irq
,
2683 #ifdef CONFIG_INTR_REMAP
2684 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2685 .name
= "IR-IO-APIC",
2686 .startup
= startup_ioapic_irq
,
2687 .mask
= mask_IO_APIC_irq
,
2688 .unmask
= unmask_IO_APIC_irq
,
2689 .ack
= ack_x2apic_edge
,
2690 .eoi
= ack_x2apic_level
,
2692 .set_affinity
= set_ir_ioapic_affinity_irq
,
2694 .retrigger
= ioapic_retrigger_irq
,
2698 static inline void init_IO_APIC_traps(void)
2701 struct irq_desc
*desc
;
2702 struct irq_cfg
*cfg
;
2705 * NOTE! The local APIC isn't very good at handling
2706 * multiple interrupts at the same interrupt level.
2707 * As the interrupt level is determined by taking the
2708 * vector number and shifting that right by 4, we
2709 * want to spread these out a bit so that they don't
2710 * all fall in the same interrupt level.
2712 * Also, we've got to be careful not to trash gate
2713 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2715 for_each_irq_desc(irq
, desc
) {
2719 cfg
= desc
->chip_data
;
2720 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2722 * Hmm.. We don't have an entry for this,
2723 * so default to an old-fashioned 8259
2724 * interrupt if we can..
2726 if (irq
< NR_IRQS_LEGACY
)
2727 make_8259A_irq(irq
);
2729 /* Strange. Oh, well.. */
2730 desc
->chip
= &no_irq_chip
;
2736 * The local APIC irq-chip implementation:
2739 static void mask_lapic_irq(unsigned int irq
)
2743 v
= apic_read(APIC_LVT0
);
2744 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2747 static void unmask_lapic_irq(unsigned int irq
)
2751 v
= apic_read(APIC_LVT0
);
2752 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2755 static void ack_lapic_irq(unsigned int irq
)
2760 static struct irq_chip lapic_chip __read_mostly
= {
2761 .name
= "local-APIC",
2762 .mask
= mask_lapic_irq
,
2763 .unmask
= unmask_lapic_irq
,
2764 .ack
= ack_lapic_irq
,
2767 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2769 desc
->status
&= ~IRQ_LEVEL
;
2770 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2774 static void __init
setup_nmi(void)
2777 * Dirty trick to enable the NMI watchdog ...
2778 * We put the 8259A master into AEOI mode and
2779 * unmask on all local APICs LVT0 as NMI.
2781 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2782 * is from Maciej W. Rozycki - so we do not have to EOI from
2783 * the NMI handler or the timer interrupt.
2785 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2787 enable_NMI_through_LVT0();
2789 apic_printk(APIC_VERBOSE
, " done.\n");
2793 * This looks a bit hackish but it's about the only one way of sending
2794 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2795 * not support the ExtINT mode, unfortunately. We need to send these
2796 * cycles as some i82489DX-based boards have glue logic that keeps the
2797 * 8259A interrupt line asserted until INTA. --macro
2799 static inline void __init
unlock_ExtINT_logic(void)
2802 struct IO_APIC_route_entry entry0
, entry1
;
2803 unsigned char save_control
, save_freq_select
;
2805 pin
= find_isa_irq_pin(8, mp_INT
);
2810 apic
= find_isa_irq_apic(8, mp_INT
);
2816 entry0
= ioapic_read_entry(apic
, pin
);
2817 clear_IO_APIC_pin(apic
, pin
);
2819 memset(&entry1
, 0, sizeof(entry1
));
2821 entry1
.dest_mode
= 0; /* physical delivery */
2822 entry1
.mask
= 0; /* unmask IRQ now */
2823 entry1
.dest
= hard_smp_processor_id();
2824 entry1
.delivery_mode
= dest_ExtINT
;
2825 entry1
.polarity
= entry0
.polarity
;
2829 ioapic_write_entry(apic
, pin
, entry1
);
2831 save_control
= CMOS_READ(RTC_CONTROL
);
2832 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2833 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2835 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2840 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2844 CMOS_WRITE(save_control
, RTC_CONTROL
);
2845 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2846 clear_IO_APIC_pin(apic
, pin
);
2848 ioapic_write_entry(apic
, pin
, entry0
);
2851 static int disable_timer_pin_1 __initdata
;
2852 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2853 static int __init
disable_timer_pin_setup(char *arg
)
2855 disable_timer_pin_1
= 1;
2858 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2860 int timer_through_8259 __initdata
;
2863 * This code may look a bit paranoid, but it's supposed to cooperate with
2864 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2865 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2866 * fanatically on his truly buggy board.
2868 * FIXME: really need to revamp this for all platforms.
2870 static inline void __init
check_timer(void)
2872 struct irq_desc
*desc
= irq_to_desc(0);
2873 struct irq_cfg
*cfg
= desc
->chip_data
;
2874 int cpu
= boot_cpu_id
;
2875 int apic1
, pin1
, apic2
, pin2
;
2876 unsigned long flags
;
2880 local_irq_save(flags
);
2882 ver
= apic_read(APIC_LVR
);
2883 ver
= GET_APIC_VERSION(ver
);
2886 * get/set the timer IRQ vector:
2888 disable_8259A_irq(0);
2889 assign_irq_vector(0, cfg
, TARGET_CPUS
);
2892 * As IRQ0 is to be enabled in the 8259A, the virtual
2893 * wire has to be disabled in the local APIC. Also
2894 * timer interrupts need to be acknowledged manually in
2895 * the 8259A for the i82489DX when using the NMI
2896 * watchdog as that APIC treats NMIs as level-triggered.
2897 * The AEOI mode will finish them in the 8259A
2900 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2902 #ifdef CONFIG_X86_32
2903 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2906 pin1
= find_isa_irq_pin(0, mp_INT
);
2907 apic1
= find_isa_irq_apic(0, mp_INT
);
2908 pin2
= ioapic_i8259
.pin
;
2909 apic2
= ioapic_i8259
.apic
;
2911 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2912 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2913 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2916 * Some BIOS writers are clueless and report the ExtINTA
2917 * I/O APIC input from the cascaded 8259A as the timer
2918 * interrupt input. So just in case, if only one pin
2919 * was found above, try it both directly and through the
2923 #ifdef CONFIG_INTR_REMAP
2924 if (intr_remapping_enabled
)
2925 panic("BIOS bug: timer not connected to IO-APIC");
2930 } else if (pin2
== -1) {
2937 * Ok, does IRQ0 through the IOAPIC work?
2940 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2941 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2943 unmask_IO_APIC_irq_desc(desc
);
2944 if (timer_irq_works()) {
2945 if (nmi_watchdog
== NMI_IO_APIC
) {
2947 enable_8259A_irq(0);
2949 if (disable_timer_pin_1
> 0)
2950 clear_IO_APIC_pin(0, pin1
);
2953 #ifdef CONFIG_INTR_REMAP
2954 if (intr_remapping_enabled
)
2955 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2957 clear_IO_APIC_pin(apic1
, pin1
);
2959 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2960 "8254 timer not connected to IO-APIC\n");
2962 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2963 "(IRQ0) through the 8259A ...\n");
2964 apic_printk(APIC_QUIET
, KERN_INFO
2965 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2967 * legacy devices should be connected to IO APIC #0
2969 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2970 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2971 unmask_IO_APIC_irq_desc(desc
);
2972 enable_8259A_irq(0);
2973 if (timer_irq_works()) {
2974 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2975 timer_through_8259
= 1;
2976 if (nmi_watchdog
== NMI_IO_APIC
) {
2977 disable_8259A_irq(0);
2979 enable_8259A_irq(0);
2984 * Cleanup, just in case ...
2986 disable_8259A_irq(0);
2987 clear_IO_APIC_pin(apic2
, pin2
);
2988 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2991 if (nmi_watchdog
== NMI_IO_APIC
) {
2992 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2993 "through the IO-APIC - disabling NMI Watchdog!\n");
2994 nmi_watchdog
= NMI_NONE
;
2996 #ifdef CONFIG_X86_32
3000 apic_printk(APIC_QUIET
, KERN_INFO
3001 "...trying to set up timer as Virtual Wire IRQ...\n");
3003 lapic_register_intr(0, desc
);
3004 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3005 enable_8259A_irq(0);
3007 if (timer_irq_works()) {
3008 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3011 disable_8259A_irq(0);
3012 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3013 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3015 apic_printk(APIC_QUIET
, KERN_INFO
3016 "...trying to set up timer as ExtINT IRQ...\n");
3020 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3022 unlock_ExtINT_logic();
3024 if (timer_irq_works()) {
3025 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3028 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3029 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3030 "report. Then try booting with the 'noapic' option.\n");
3032 local_irq_restore(flags
);
3036 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3037 * to devices. However there may be an I/O APIC pin available for
3038 * this interrupt regardless. The pin may be left unconnected, but
3039 * typically it will be reused as an ExtINT cascade interrupt for
3040 * the master 8259A. In the MPS case such a pin will normally be
3041 * reported as an ExtINT interrupt in the MP table. With ACPI
3042 * there is no provision for ExtINT interrupts, and in the absence
3043 * of an override it would be treated as an ordinary ISA I/O APIC
3044 * interrupt, that is edge-triggered and unmasked by default. We
3045 * used to do this, but it caused problems on some systems because
3046 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3047 * the same ExtINT cascade interrupt to drive the local APIC of the
3048 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3049 * the I/O APIC in all cases now. No actual device should request
3050 * it anyway. --macro
3052 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3054 void __init
setup_IO_APIC(void)
3057 #ifdef CONFIG_X86_32
3061 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3065 io_apic_irqs
= ~PIC_IRQS
;
3067 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3069 * Set up IO-APIC IRQ routing.
3071 #ifdef CONFIG_X86_32
3073 setup_ioapic_ids_from_mpc();
3076 setup_IO_APIC_irqs();
3077 init_IO_APIC_traps();
3082 * Called after all the initialization is done. If we didnt find any
3083 * APIC bugs then we can allow the modify fast path
3086 static int __init
io_apic_bug_finalize(void)
3088 if (sis_apic_bug
== -1)
3093 late_initcall(io_apic_bug_finalize
);
3095 struct sysfs_ioapic_data
{
3096 struct sys_device dev
;
3097 struct IO_APIC_route_entry entry
[0];
3099 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3101 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3103 struct IO_APIC_route_entry
*entry
;
3104 struct sysfs_ioapic_data
*data
;
3107 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3108 entry
= data
->entry
;
3109 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3110 *entry
= ioapic_read_entry(dev
->id
, i
);
3115 static int ioapic_resume(struct sys_device
*dev
)
3117 struct IO_APIC_route_entry
*entry
;
3118 struct sysfs_ioapic_data
*data
;
3119 unsigned long flags
;
3120 union IO_APIC_reg_00 reg_00
;
3123 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3124 entry
= data
->entry
;
3126 spin_lock_irqsave(&ioapic_lock
, flags
);
3127 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3128 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3129 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3130 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3132 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3133 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3134 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3139 static struct sysdev_class ioapic_sysdev_class
= {
3141 .suspend
= ioapic_suspend
,
3142 .resume
= ioapic_resume
,
3145 static int __init
ioapic_init_sysfs(void)
3147 struct sys_device
* dev
;
3150 error
= sysdev_class_register(&ioapic_sysdev_class
);
3154 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3155 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3156 * sizeof(struct IO_APIC_route_entry
);
3157 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3158 if (!mp_ioapic_data
[i
]) {
3159 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3162 dev
= &mp_ioapic_data
[i
]->dev
;
3164 dev
->cls
= &ioapic_sysdev_class
;
3165 error
= sysdev_register(dev
);
3167 kfree(mp_ioapic_data
[i
]);
3168 mp_ioapic_data
[i
] = NULL
;
3169 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3177 device_initcall(ioapic_init_sysfs
);
3180 * Dynamic irq allocate and deallocation
3182 unsigned int create_irq_nr(unsigned int irq_want
)
3184 /* Allocate an unused irq */
3187 unsigned long flags
;
3188 struct irq_cfg
*cfg_new
= NULL
;
3189 int cpu
= boot_cpu_id
;
3190 struct irq_desc
*desc_new
= NULL
;
3193 spin_lock_irqsave(&vector_lock
, flags
);
3194 for (new = irq_want
; new < NR_IRQS
; new++) {
3195 if (platform_legacy_irq(new))
3198 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3200 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3203 cfg_new
= desc_new
->chip_data
;
3205 if (cfg_new
->vector
!= 0)
3207 if (__assign_irq_vector(new, cfg_new
, TARGET_CPUS
) == 0)
3211 spin_unlock_irqrestore(&vector_lock
, flags
);
3214 dynamic_irq_init(irq
);
3215 /* restore it, in case dynamic_irq_init clear it */
3217 desc_new
->chip_data
= cfg_new
;
3222 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3223 int create_irq(void)
3225 unsigned int irq_want
;
3228 irq_want
= nr_irqs_gsi
;
3229 irq
= create_irq_nr(irq_want
);
3237 void destroy_irq(unsigned int irq
)
3239 unsigned long flags
;
3240 struct irq_cfg
*cfg
;
3241 struct irq_desc
*desc
;
3243 /* store it, in case dynamic_irq_cleanup clear it */
3244 desc
= irq_to_desc(irq
);
3245 cfg
= desc
->chip_data
;
3246 dynamic_irq_cleanup(irq
);
3247 /* connect back irq_cfg */
3249 desc
->chip_data
= cfg
;
3251 #ifdef CONFIG_INTR_REMAP
3254 spin_lock_irqsave(&vector_lock
, flags
);
3255 __clear_irq_vector(irq
, cfg
);
3256 spin_unlock_irqrestore(&vector_lock
, flags
);
3260 * MSI message composition
3262 #ifdef CONFIG_PCI_MSI
3263 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3265 struct irq_cfg
*cfg
;
3270 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3274 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3276 #ifdef CONFIG_INTR_REMAP
3277 if (irq_remapped(irq
)) {
3282 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3283 BUG_ON(ir_index
== -1);
3285 memset (&irte
, 0, sizeof(irte
));
3288 irte
.dst_mode
= INT_DEST_MODE
;
3289 irte
.trigger_mode
= 0; /* edge */
3290 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3291 irte
.vector
= cfg
->vector
;
3292 irte
.dest_id
= IRTE_DEST(dest
);
3294 modify_irte(irq
, &irte
);
3296 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3297 msg
->data
= sub_handle
;
3298 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3300 MSI_ADDR_IR_INDEX1(ir_index
) |
3301 MSI_ADDR_IR_INDEX2(ir_index
);
3305 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3308 ((INT_DEST_MODE
== 0) ?
3309 MSI_ADDR_DEST_MODE_PHYSICAL
:
3310 MSI_ADDR_DEST_MODE_LOGICAL
) |
3311 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3312 MSI_ADDR_REDIRECTION_CPU
:
3313 MSI_ADDR_REDIRECTION_LOWPRI
) |
3314 MSI_ADDR_DEST_ID(dest
);
3317 MSI_DATA_TRIGGER_EDGE
|
3318 MSI_DATA_LEVEL_ASSERT
|
3319 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3320 MSI_DATA_DELIVERY_FIXED
:
3321 MSI_DATA_DELIVERY_LOWPRI
) |
3322 MSI_DATA_VECTOR(cfg
->vector
);
3328 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3330 struct irq_desc
*desc
= irq_to_desc(irq
);
3331 struct irq_cfg
*cfg
;
3335 dest
= set_desc_affinity(desc
, mask
);
3336 if (dest
== BAD_APICID
)
3339 cfg
= desc
->chip_data
;
3341 read_msi_msg_desc(desc
, &msg
);
3343 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3344 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3345 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3346 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3348 write_msi_msg_desc(desc
, &msg
);
3350 #ifdef CONFIG_INTR_REMAP
3352 * Migrate the MSI irq to another cpumask. This migration is
3353 * done in the process context using interrupt-remapping hardware.
3356 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3358 struct irq_desc
*desc
= irq_to_desc(irq
);
3359 struct irq_cfg
*cfg
= desc
->chip_data
;
3363 if (get_irte(irq
, &irte
))
3366 dest
= set_desc_affinity(desc
, mask
);
3367 if (dest
== BAD_APICID
)
3370 irte
.vector
= cfg
->vector
;
3371 irte
.dest_id
= IRTE_DEST(dest
);
3374 * atomically update the IRTE with the new destination and vector.
3376 modify_irte(irq
, &irte
);
3379 * After this point, all the interrupts will start arriving
3380 * at the new destination. So, time to cleanup the previous
3381 * vector allocation.
3383 if (cfg
->move_in_progress
)
3384 send_cleanup_vector(cfg
);
3388 #endif /* CONFIG_SMP */
3391 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3392 * which implement the MSI or MSI-X Capability Structure.
3394 static struct irq_chip msi_chip
= {
3396 .unmask
= unmask_msi_irq
,
3397 .mask
= mask_msi_irq
,
3398 .ack
= ack_apic_edge
,
3400 .set_affinity
= set_msi_irq_affinity
,
3402 .retrigger
= ioapic_retrigger_irq
,
3405 #ifdef CONFIG_INTR_REMAP
3406 static struct irq_chip msi_ir_chip
= {
3407 .name
= "IR-PCI-MSI",
3408 .unmask
= unmask_msi_irq
,
3409 .mask
= mask_msi_irq
,
3410 .ack
= ack_x2apic_edge
,
3412 .set_affinity
= ir_set_msi_irq_affinity
,
3414 .retrigger
= ioapic_retrigger_irq
,
3418 * Map the PCI dev to the corresponding remapping hardware unit
3419 * and allocate 'nvec' consecutive interrupt-remapping table entries
3422 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3424 struct intel_iommu
*iommu
;
3427 iommu
= map_dev_to_ir(dev
);
3430 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3434 index
= alloc_irte(iommu
, irq
, nvec
);
3437 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3445 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3450 ret
= msi_compose_msg(dev
, irq
, &msg
);
3454 set_irq_msi(irq
, msidesc
);
3455 write_msi_msg(irq
, &msg
);
3457 #ifdef CONFIG_INTR_REMAP
3458 if (irq_remapped(irq
)) {
3459 struct irq_desc
*desc
= irq_to_desc(irq
);
3461 * irq migration in process context
3463 desc
->status
|= IRQ_MOVE_PCNTXT
;
3464 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3467 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3469 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3474 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
)
3478 unsigned int irq_want
;
3480 irq_want
= nr_irqs_gsi
;
3481 irq
= create_irq_nr(irq_want
);
3485 #ifdef CONFIG_INTR_REMAP
3486 if (!intr_remapping_enabled
)
3489 ret
= msi_alloc_irte(dev
, irq
, 1);
3494 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3501 #ifdef CONFIG_INTR_REMAP
3508 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3511 int ret
, sub_handle
;
3512 struct msi_desc
*msidesc
;
3513 unsigned int irq_want
;
3515 #ifdef CONFIG_INTR_REMAP
3516 struct intel_iommu
*iommu
= 0;
3520 irq_want
= nr_irqs_gsi
;
3522 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3523 irq
= create_irq_nr(irq_want
);
3527 #ifdef CONFIG_INTR_REMAP
3528 if (!intr_remapping_enabled
)
3533 * allocate the consecutive block of IRTE's
3536 index
= msi_alloc_irte(dev
, irq
, nvec
);
3542 iommu
= map_dev_to_ir(dev
);
3548 * setup the mapping between the irq and the IRTE
3549 * base index, the sub_handle pointing to the
3550 * appropriate interrupt remap table entry.
3552 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3556 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3568 void arch_teardown_msi_irq(unsigned int irq
)
3575 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3577 struct irq_desc
*desc
= irq_to_desc(irq
);
3578 struct irq_cfg
*cfg
;
3582 dest
= set_desc_affinity(desc
, mask
);
3583 if (dest
== BAD_APICID
)
3586 cfg
= desc
->chip_data
;
3588 dmar_msi_read(irq
, &msg
);
3590 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3591 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3592 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3593 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3595 dmar_msi_write(irq
, &msg
);
3598 #endif /* CONFIG_SMP */
3600 struct irq_chip dmar_msi_type
= {
3602 .unmask
= dmar_msi_unmask
,
3603 .mask
= dmar_msi_mask
,
3604 .ack
= ack_apic_edge
,
3606 .set_affinity
= dmar_msi_set_affinity
,
3608 .retrigger
= ioapic_retrigger_irq
,
3611 int arch_setup_dmar_msi(unsigned int irq
)
3616 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3619 dmar_msi_write(irq
, &msg
);
3620 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3626 #ifdef CONFIG_HPET_TIMER
3629 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3631 struct irq_desc
*desc
= irq_to_desc(irq
);
3632 struct irq_cfg
*cfg
;
3636 dest
= set_desc_affinity(desc
, mask
);
3637 if (dest
== BAD_APICID
)
3640 cfg
= desc
->chip_data
;
3642 hpet_msi_read(irq
, &msg
);
3644 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3645 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3646 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3647 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3649 hpet_msi_write(irq
, &msg
);
3652 #endif /* CONFIG_SMP */
3654 struct irq_chip hpet_msi_type
= {
3656 .unmask
= hpet_msi_unmask
,
3657 .mask
= hpet_msi_mask
,
3658 .ack
= ack_apic_edge
,
3660 .set_affinity
= hpet_msi_set_affinity
,
3662 .retrigger
= ioapic_retrigger_irq
,
3665 int arch_setup_hpet_msi(unsigned int irq
)
3670 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3674 hpet_msi_write(irq
, &msg
);
3675 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3682 #endif /* CONFIG_PCI_MSI */
3684 * Hypertransport interrupt support
3686 #ifdef CONFIG_HT_IRQ
3690 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3692 struct ht_irq_msg msg
;
3693 fetch_ht_irq_msg(irq
, &msg
);
3695 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3696 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3698 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3699 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3701 write_ht_irq_msg(irq
, &msg
);
3704 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3706 struct irq_desc
*desc
= irq_to_desc(irq
);
3707 struct irq_cfg
*cfg
;
3710 dest
= set_desc_affinity(desc
, mask
);
3711 if (dest
== BAD_APICID
)
3714 cfg
= desc
->chip_data
;
3716 target_ht_irq(irq
, dest
, cfg
->vector
);
3721 static struct irq_chip ht_irq_chip
= {
3723 .mask
= mask_ht_irq
,
3724 .unmask
= unmask_ht_irq
,
3725 .ack
= ack_apic_edge
,
3727 .set_affinity
= set_ht_irq_affinity
,
3729 .retrigger
= ioapic_retrigger_irq
,
3732 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3734 struct irq_cfg
*cfg
;
3738 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3740 struct ht_irq_msg msg
;
3743 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3745 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3749 HT_IRQ_LOW_DEST_ID(dest
) |
3750 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3751 ((INT_DEST_MODE
== 0) ?
3752 HT_IRQ_LOW_DM_PHYSICAL
:
3753 HT_IRQ_LOW_DM_LOGICAL
) |
3754 HT_IRQ_LOW_RQEOI_EDGE
|
3755 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3756 HT_IRQ_LOW_MT_FIXED
:
3757 HT_IRQ_LOW_MT_ARBITRATED
) |
3758 HT_IRQ_LOW_IRQ_MASKED
;
3760 write_ht_irq_msg(irq
, &msg
);
3762 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3763 handle_edge_irq
, "edge");
3765 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3769 #endif /* CONFIG_HT_IRQ */
3771 #ifdef CONFIG_X86_64
3773 * Re-target the irq to the specified CPU and enable the specified MMR located
3774 * on the specified blade to allow the sending of MSIs to the specified CPU.
3776 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3777 unsigned long mmr_offset
)
3779 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3780 struct irq_cfg
*cfg
;
3782 unsigned long mmr_value
;
3783 struct uv_IO_APIC_route_entry
*entry
;
3784 unsigned long flags
;
3789 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3793 spin_lock_irqsave(&vector_lock
, flags
);
3794 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3796 spin_unlock_irqrestore(&vector_lock
, flags
);
3799 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3800 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3802 entry
->vector
= cfg
->vector
;
3803 entry
->delivery_mode
= INT_DELIVERY_MODE
;
3804 entry
->dest_mode
= INT_DEST_MODE
;
3805 entry
->polarity
= 0;
3808 entry
->dest
= cpu_mask_to_apicid(eligible_cpu
);
3810 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3811 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3817 * Disable the specified MMR located on the specified blade so that MSIs are
3818 * longer allowed to be sent.
3820 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3822 unsigned long mmr_value
;
3823 struct uv_IO_APIC_route_entry
*entry
;
3827 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3828 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3832 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3833 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3835 #endif /* CONFIG_X86_64 */
3837 int __init
io_apic_get_redir_entries (int ioapic
)
3839 union IO_APIC_reg_01 reg_01
;
3840 unsigned long flags
;
3842 spin_lock_irqsave(&ioapic_lock
, flags
);
3843 reg_01
.raw
= io_apic_read(ioapic
, 1);
3844 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3846 return reg_01
.bits
.entries
;
3849 void __init
probe_nr_irqs_gsi(void)
3854 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3855 nr
+= io_apic_get_redir_entries(idx
) + 1;
3857 if (nr
> nr_irqs_gsi
)
3861 /* --------------------------------------------------------------------------
3862 ACPI-based IOAPIC Configuration
3863 -------------------------------------------------------------------------- */
3867 #ifdef CONFIG_X86_32
3868 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3870 union IO_APIC_reg_00 reg_00
;
3871 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3873 unsigned long flags
;
3877 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3878 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3879 * supports up to 16 on one shared APIC bus.
3881 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3882 * advantage of new APIC bus architecture.
3885 if (physids_empty(apic_id_map
))
3886 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3888 spin_lock_irqsave(&ioapic_lock
, flags
);
3889 reg_00
.raw
= io_apic_read(ioapic
, 0);
3890 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3892 if (apic_id
>= get_physical_broadcast()) {
3893 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3894 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3895 apic_id
= reg_00
.bits
.ID
;
3899 * Every APIC in a system must have a unique ID or we get lots of nice
3900 * 'stuck on smp_invalidate_needed IPI wait' messages.
3902 if (check_apicid_used(apic_id_map
, apic_id
)) {
3904 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3905 if (!check_apicid_used(apic_id_map
, i
))
3909 if (i
== get_physical_broadcast())
3910 panic("Max apic_id exceeded!\n");
3912 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3913 "trying %d\n", ioapic
, apic_id
, i
);
3918 tmp
= apicid_to_cpu_present(apic_id
);
3919 physids_or(apic_id_map
, apic_id_map
, tmp
);
3921 if (reg_00
.bits
.ID
!= apic_id
) {
3922 reg_00
.bits
.ID
= apic_id
;
3924 spin_lock_irqsave(&ioapic_lock
, flags
);
3925 io_apic_write(ioapic
, 0, reg_00
.raw
);
3926 reg_00
.raw
= io_apic_read(ioapic
, 0);
3927 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3930 if (reg_00
.bits
.ID
!= apic_id
) {
3931 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3936 apic_printk(APIC_VERBOSE
, KERN_INFO
3937 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3942 int __init
io_apic_get_version(int ioapic
)
3944 union IO_APIC_reg_01 reg_01
;
3945 unsigned long flags
;
3947 spin_lock_irqsave(&ioapic_lock
, flags
);
3948 reg_01
.raw
= io_apic_read(ioapic
, 1);
3949 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3951 return reg_01
.bits
.version
;
3955 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3957 struct irq_desc
*desc
;
3958 struct irq_cfg
*cfg
;
3959 int cpu
= boot_cpu_id
;
3961 if (!IO_APIC_IRQ(irq
)) {
3962 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3967 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3969 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3974 * IRQs < 16 are already in the irq_2_pin[] map
3976 if (irq
>= NR_IRQS_LEGACY
) {
3977 cfg
= desc
->chip_data
;
3978 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3981 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3987 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3991 if (skip_ioapic_setup
)
3994 for (i
= 0; i
< mp_irq_entries
; i
++)
3995 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3996 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3998 if (i
>= mp_irq_entries
)
4001 *trigger
= irq_trigger(i
);
4002 *polarity
= irq_polarity(i
);
4006 #endif /* CONFIG_ACPI */
4009 * This function currently is only a helper for the i386 smp boot process where
4010 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4011 * so mask in all cases should simply be TARGET_CPUS
4014 void __init
setup_ioapic_dest(void)
4016 int pin
, ioapic
, irq
, irq_entry
;
4017 struct irq_desc
*desc
;
4018 struct irq_cfg
*cfg
;
4019 const struct cpumask
*mask
;
4021 if (skip_ioapic_setup
== 1)
4024 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4025 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4026 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4027 if (irq_entry
== -1)
4029 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4031 /* setup_IO_APIC_irqs could fail to get vector for some device
4032 * when you have too many devices, because at that time only boot
4035 desc
= irq_to_desc(irq
);
4036 cfg
= desc
->chip_data
;
4038 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4039 irq_trigger(irq_entry
),
4040 irq_polarity(irq_entry
));
4046 * Honour affinities which have been set in early boot
4049 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4050 mask
= &desc
->affinity
;
4054 #ifdef CONFIG_INTR_REMAP
4055 if (intr_remapping_enabled
)
4056 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4059 set_ioapic_affinity_irq_desc(desc
, mask
);
4066 #define IOAPIC_RESOURCE_NAME_SIZE 11
4068 static struct resource
*ioapic_resources
;
4070 static struct resource
* __init
ioapic_setup_resources(void)
4073 struct resource
*res
;
4077 if (nr_ioapics
<= 0)
4080 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4083 mem
= alloc_bootmem(n
);
4087 mem
+= sizeof(struct resource
) * nr_ioapics
;
4089 for (i
= 0; i
< nr_ioapics
; i
++) {
4091 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4092 sprintf(mem
, "IOAPIC %u", i
);
4093 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4097 ioapic_resources
= res
;
4102 void __init
ioapic_init_mappings(void)
4104 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4105 struct resource
*ioapic_res
;
4108 ioapic_res
= ioapic_setup_resources();
4109 for (i
= 0; i
< nr_ioapics
; i
++) {
4110 if (smp_found_config
) {
4111 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
4112 #ifdef CONFIG_X86_32
4115 "WARNING: bogus zero IO-APIC "
4116 "address found in MPTABLE, "
4117 "disabling IO/APIC support!\n");
4118 smp_found_config
= 0;
4119 skip_ioapic_setup
= 1;
4120 goto fake_ioapic_page
;
4124 #ifdef CONFIG_X86_32
4127 ioapic_phys
= (unsigned long)
4128 alloc_bootmem_pages(PAGE_SIZE
);
4129 ioapic_phys
= __pa(ioapic_phys
);
4131 set_fixmap_nocache(idx
, ioapic_phys
);
4132 apic_printk(APIC_VERBOSE
,
4133 "mapped IOAPIC to %08lx (%08lx)\n",
4134 __fix_to_virt(idx
), ioapic_phys
);
4137 if (ioapic_res
!= NULL
) {
4138 ioapic_res
->start
= ioapic_phys
;
4139 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4145 static int __init
ioapic_insert_resources(void)
4148 struct resource
*r
= ioapic_resources
;
4152 "IO APIC resources could be not be allocated.\n");
4156 for (i
= 0; i
< nr_ioapics
; i
++) {
4157 insert_resource(&iomem_resource
, r
);
4164 /* Insert the IO APIC resources after PCI initialization has occured to handle
4165 * IO APICS that are mapped in on a BAR in PCI space. */
4166 late_initcall(ioapic_insert_resources
);