140950fb9902df81cb72a683d233f34aa8464833
[deliverable/linux.git] / arch / x86 / kernel / irq.c
1 /*
2 * Common interrupt code for 32 and 64 bit
3 */
4 #include <linux/cpu.h>
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
7 #include <linux/of.h>
8 #include <linux/seq_file.h>
9 #include <linux/smp.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13
14 #include <asm/apic.h>
15 #include <asm/io_apic.h>
16 #include <asm/irq.h>
17 #include <asm/idle.h>
18 #include <asm/mce.h>
19 #include <asm/hw_irq.h>
20 #include <asm/desc.h>
21
22 #define CREATE_TRACE_POINTS
23 #include <asm/trace/irq_vectors.h>
24
25 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
26 EXPORT_PER_CPU_SYMBOL(irq_stat);
27
28 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
29 EXPORT_PER_CPU_SYMBOL(irq_regs);
30
31 atomic_t irq_err_count;
32
33 /* Function pointer for generic interrupt vector handling */
34 void (*x86_platform_ipi_callback)(void) = NULL;
35
36 /*
37 * 'what should we do if we get a hw irq event on an illegal vector'.
38 * each architecture has to answer this themselves.
39 */
40 void ack_bad_irq(unsigned int irq)
41 {
42 if (printk_ratelimit())
43 pr_err("unexpected IRQ trap at vector %02x\n", irq);
44
45 /*
46 * Currently unexpected vectors happen only on SMP and APIC.
47 * We _must_ ack these because every local APIC has only N
48 * irq slots per priority level, and a 'hanging, unacked' IRQ
49 * holds up an irq slot - in excessive cases (when multiple
50 * unexpected vectors occur) that might lock up the APIC
51 * completely.
52 * But only ack when the APIC is enabled -AK
53 */
54 ack_APIC_irq();
55 }
56
57 #define irq_stats(x) (&per_cpu(irq_stat, x))
58 /*
59 * /proc/interrupts printing for arch specific interrupts
60 */
61 int arch_show_interrupts(struct seq_file *p, int prec)
62 {
63 int j;
64
65 seq_printf(p, "%*s: ", prec, "NMI");
66 for_each_online_cpu(j)
67 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
68 seq_puts(p, " Non-maskable interrupts\n");
69 #ifdef CONFIG_X86_LOCAL_APIC
70 seq_printf(p, "%*s: ", prec, "LOC");
71 for_each_online_cpu(j)
72 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
73 seq_puts(p, " Local timer interrupts\n");
74
75 seq_printf(p, "%*s: ", prec, "SPU");
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
78 seq_puts(p, " Spurious interrupts\n");
79 seq_printf(p, "%*s: ", prec, "PMI");
80 for_each_online_cpu(j)
81 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
82 seq_puts(p, " Performance monitoring interrupts\n");
83 seq_printf(p, "%*s: ", prec, "IWI");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
86 seq_puts(p, " IRQ work interrupts\n");
87 seq_printf(p, "%*s: ", prec, "RTR");
88 for_each_online_cpu(j)
89 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
90 seq_puts(p, " APIC ICR read retries\n");
91 #endif
92 if (x86_platform_ipi_callback) {
93 seq_printf(p, "%*s: ", prec, "PLT");
94 for_each_online_cpu(j)
95 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
96 seq_puts(p, " Platform interrupts\n");
97 }
98 #ifdef CONFIG_SMP
99 seq_printf(p, "%*s: ", prec, "RES");
100 for_each_online_cpu(j)
101 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
102 seq_puts(p, " Rescheduling interrupts\n");
103 seq_printf(p, "%*s: ", prec, "CAL");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
106 irq_stats(j)->irq_tlb_count);
107 seq_puts(p, " Function call interrupts\n");
108 seq_printf(p, "%*s: ", prec, "TLB");
109 for_each_online_cpu(j)
110 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
111 seq_puts(p, " TLB shootdowns\n");
112 #endif
113 #ifdef CONFIG_X86_THERMAL_VECTOR
114 seq_printf(p, "%*s: ", prec, "TRM");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
117 seq_puts(p, " Thermal event interrupts\n");
118 #endif
119 #ifdef CONFIG_X86_MCE_THRESHOLD
120 seq_printf(p, "%*s: ", prec, "THR");
121 for_each_online_cpu(j)
122 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
123 seq_puts(p, " Threshold APIC interrupts\n");
124 #endif
125 #ifdef CONFIG_X86_MCE_AMD
126 seq_printf(p, "%*s: ", prec, "DFR");
127 for_each_online_cpu(j)
128 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
129 seq_puts(p, " Deferred Error APIC interrupts\n");
130 #endif
131 #ifdef CONFIG_X86_MCE
132 seq_printf(p, "%*s: ", prec, "MCE");
133 for_each_online_cpu(j)
134 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
135 seq_puts(p, " Machine check exceptions\n");
136 seq_printf(p, "%*s: ", prec, "MCP");
137 for_each_online_cpu(j)
138 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
139 seq_puts(p, " Machine check polls\n");
140 #endif
141 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
142 seq_printf(p, "%*s: ", prec, "HYP");
143 for_each_online_cpu(j)
144 seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
145 seq_puts(p, " Hypervisor callback interrupts\n");
146 #endif
147 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
148 #if defined(CONFIG_X86_IO_APIC)
149 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
150 #endif
151 #ifdef CONFIG_HAVE_KVM
152 seq_printf(p, "%*s: ", prec, "PIN");
153 for_each_online_cpu(j)
154 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
155 seq_puts(p, " Posted-interrupt notification event\n");
156
157 seq_printf(p, "%*s: ", prec, "PIW");
158 for_each_online_cpu(j)
159 seq_printf(p, "%10u ",
160 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
161 seq_puts(p, " Posted-interrupt wakeup event\n");
162 #endif
163 return 0;
164 }
165
166 /*
167 * /proc/stat helpers
168 */
169 u64 arch_irq_stat_cpu(unsigned int cpu)
170 {
171 u64 sum = irq_stats(cpu)->__nmi_count;
172
173 #ifdef CONFIG_X86_LOCAL_APIC
174 sum += irq_stats(cpu)->apic_timer_irqs;
175 sum += irq_stats(cpu)->irq_spurious_count;
176 sum += irq_stats(cpu)->apic_perf_irqs;
177 sum += irq_stats(cpu)->apic_irq_work_irqs;
178 sum += irq_stats(cpu)->icr_read_retry_count;
179 #endif
180 if (x86_platform_ipi_callback)
181 sum += irq_stats(cpu)->x86_platform_ipis;
182 #ifdef CONFIG_SMP
183 sum += irq_stats(cpu)->irq_resched_count;
184 sum += irq_stats(cpu)->irq_call_count;
185 #endif
186 #ifdef CONFIG_X86_THERMAL_VECTOR
187 sum += irq_stats(cpu)->irq_thermal_count;
188 #endif
189 #ifdef CONFIG_X86_MCE_THRESHOLD
190 sum += irq_stats(cpu)->irq_threshold_count;
191 #endif
192 #ifdef CONFIG_X86_MCE
193 sum += per_cpu(mce_exception_count, cpu);
194 sum += per_cpu(mce_poll_count, cpu);
195 #endif
196 return sum;
197 }
198
199 u64 arch_irq_stat(void)
200 {
201 u64 sum = atomic_read(&irq_err_count);
202 return sum;
203 }
204
205
206 /*
207 * do_IRQ handles all normal device IRQ's (the special
208 * SMP cross-CPU interrupts have their own specific
209 * handlers).
210 */
211 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
212 {
213 struct pt_regs *old_regs = set_irq_regs(regs);
214
215 /* high bit used in ret_from_ code */
216 unsigned vector = ~regs->orig_ax;
217 unsigned irq;
218
219 entering_irq();
220
221 irq = __this_cpu_read(vector_irq[vector]);
222
223 if (!handle_irq(irq, regs)) {
224 ack_APIC_irq();
225
226 if (irq != VECTOR_RETRIGGERED) {
227 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
228 __func__, smp_processor_id(),
229 vector, irq);
230 } else {
231 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
232 }
233 }
234
235 exiting_irq();
236
237 set_irq_regs(old_regs);
238 return 1;
239 }
240
241 /*
242 * Handler for X86_PLATFORM_IPI_VECTOR.
243 */
244 void __smp_x86_platform_ipi(void)
245 {
246 inc_irq_stat(x86_platform_ipis);
247
248 if (x86_platform_ipi_callback)
249 x86_platform_ipi_callback();
250 }
251
252 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
253 {
254 struct pt_regs *old_regs = set_irq_regs(regs);
255
256 entering_ack_irq();
257 __smp_x86_platform_ipi();
258 exiting_irq();
259 set_irq_regs(old_regs);
260 }
261
262 #ifdef CONFIG_HAVE_KVM
263 static void dummy_handler(void) {}
264 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
265
266 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
267 {
268 if (handler)
269 kvm_posted_intr_wakeup_handler = handler;
270 else
271 kvm_posted_intr_wakeup_handler = dummy_handler;
272 }
273 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
274
275 /*
276 * Handler for POSTED_INTERRUPT_VECTOR.
277 */
278 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
279 {
280 struct pt_regs *old_regs = set_irq_regs(regs);
281
282 entering_ack_irq();
283 inc_irq_stat(kvm_posted_intr_ipis);
284 exiting_irq();
285 set_irq_regs(old_regs);
286 }
287
288 /*
289 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
290 */
291 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
292 {
293 struct pt_regs *old_regs = set_irq_regs(regs);
294
295 entering_ack_irq();
296 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
297 kvm_posted_intr_wakeup_handler();
298 exiting_irq();
299 set_irq_regs(old_regs);
300 }
301 #endif
302
303 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
304 {
305 struct pt_regs *old_regs = set_irq_regs(regs);
306
307 entering_ack_irq();
308 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
309 __smp_x86_platform_ipi();
310 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
311 exiting_irq();
312 set_irq_regs(old_regs);
313 }
314
315 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
316
317 #ifdef CONFIG_HOTPLUG_CPU
318
319 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
320 * below, which is protected by stop_machine(). Putting them on the stack
321 * results in a stack frame overflow. Dynamically allocating could result in a
322 * failure so declare these two cpumasks as global.
323 */
324 static struct cpumask affinity_new, online_new;
325
326 /*
327 * This cpu is going to be removed and its vectors migrated to the remaining
328 * online cpus. Check to see if there are enough vectors in the remaining cpus.
329 * This function is protected by stop_machine().
330 */
331 int check_irq_vectors_for_cpu_disable(void)
332 {
333 int irq, cpu;
334 unsigned int this_cpu, vector, this_count, count;
335 struct irq_desc *desc;
336 struct irq_data *data;
337
338 this_cpu = smp_processor_id();
339 cpumask_copy(&online_new, cpu_online_mask);
340 cpumask_clear_cpu(this_cpu, &online_new);
341
342 this_count = 0;
343 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
344 irq = __this_cpu_read(vector_irq[vector]);
345 if (irq < 0)
346 continue;
347 desc = irq_to_desc(irq);
348 if (!desc)
349 continue;
350
351 /*
352 * Protect against concurrent action removal, affinity
353 * changes etc.
354 */
355 raw_spin_lock(&desc->lock);
356 data = irq_desc_get_irq_data(desc);
357 cpumask_copy(&affinity_new, irq_data_get_affinity_mask(data));
358 cpumask_clear_cpu(this_cpu, &affinity_new);
359
360 /* Do not count inactive or per-cpu irqs. */
361 if (!irq_has_action(irq) || irqd_is_per_cpu(data)) {
362 raw_spin_unlock(&desc->lock);
363 continue;
364 }
365
366 raw_spin_unlock(&desc->lock);
367 /*
368 * A single irq may be mapped to multiple cpu's
369 * vector_irq[] (for example IOAPIC cluster mode). In
370 * this case we have two possibilities:
371 *
372 * 1) the resulting affinity mask is empty; that is
373 * this the down'd cpu is the last cpu in the irq's
374 * affinity mask, or
375 *
376 * 2) the resulting affinity mask is no longer a
377 * subset of the online cpus but the affinity mask is
378 * not zero; that is the down'd cpu is the last online
379 * cpu in a user set affinity mask.
380 */
381 if (cpumask_empty(&affinity_new) ||
382 !cpumask_subset(&affinity_new, &online_new))
383 this_count++;
384 }
385
386 count = 0;
387 for_each_online_cpu(cpu) {
388 if (cpu == this_cpu)
389 continue;
390 /*
391 * We scan from FIRST_EXTERNAL_VECTOR to first system
392 * vector. If the vector is marked in the used vectors
393 * bitmap or an irq is assigned to it, we don't count
394 * it as available.
395 *
396 * As this is an inaccurate snapshot anyway, we can do
397 * this w/o holding vector_lock.
398 */
399 for (vector = FIRST_EXTERNAL_VECTOR;
400 vector < first_system_vector; vector++) {
401 if (!test_bit(vector, used_vectors) &&
402 per_cpu(vector_irq, cpu)[vector] <= VECTOR_UNUSED)
403 count++;
404 }
405 }
406
407 if (count < this_count) {
408 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
409 this_cpu, this_count, count);
410 return -ERANGE;
411 }
412 return 0;
413 }
414
415 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
416 void fixup_irqs(void)
417 {
418 unsigned int irq, vector;
419 static int warned;
420 struct irq_desc *desc;
421 struct irq_data *data;
422 struct irq_chip *chip;
423 int ret;
424
425 for_each_irq_desc(irq, desc) {
426 int break_affinity = 0;
427 int set_affinity = 1;
428 const struct cpumask *affinity;
429
430 if (!desc)
431 continue;
432 if (irq == 2)
433 continue;
434
435 /* interrupt's are disabled at this point */
436 raw_spin_lock(&desc->lock);
437
438 data = irq_desc_get_irq_data(desc);
439 affinity = irq_data_get_affinity_mask(data);
440 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
441 cpumask_subset(affinity, cpu_online_mask)) {
442 raw_spin_unlock(&desc->lock);
443 continue;
444 }
445
446 /*
447 * Complete the irq move. This cpu is going down and for
448 * non intr-remapping case, we can't wait till this interrupt
449 * arrives at this cpu before completing the irq move.
450 */
451 irq_force_complete_move(irq);
452
453 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
454 break_affinity = 1;
455 affinity = cpu_online_mask;
456 }
457
458 chip = irq_data_get_irq_chip(data);
459 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
460 chip->irq_mask(data);
461
462 if (chip->irq_set_affinity) {
463 ret = chip->irq_set_affinity(data, affinity, true);
464 if (ret == -ENOSPC)
465 pr_crit("IRQ %d set affinity failed because there are no available vectors. The device assigned to this IRQ is unstable.\n", irq);
466 } else {
467 if (!(warned++))
468 set_affinity = 0;
469 }
470
471 /*
472 * We unmask if the irq was not marked masked by the
473 * core code. That respects the lazy irq disable
474 * behaviour.
475 */
476 if (!irqd_can_move_in_process_context(data) &&
477 !irqd_irq_masked(data) && chip->irq_unmask)
478 chip->irq_unmask(data);
479
480 raw_spin_unlock(&desc->lock);
481
482 if (break_affinity && set_affinity)
483 pr_notice("Broke affinity for irq %i\n", irq);
484 else if (!set_affinity)
485 pr_notice("Cannot set affinity for irq %i\n", irq);
486 }
487
488 /*
489 * We can remove mdelay() and then send spuriuous interrupts to
490 * new cpu targets for all the irqs that were handled previously by
491 * this cpu. While it works, I have seen spurious interrupt messages
492 * (nothing wrong but still...).
493 *
494 * So for now, retain mdelay(1) and check the IRR and then send those
495 * interrupts to new targets as this cpu is already offlined...
496 */
497 mdelay(1);
498
499 /*
500 * We can walk the vector array of this cpu without holding
501 * vector_lock because the cpu is already marked !online, so
502 * nothing else will touch it.
503 */
504 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
505 unsigned int irr;
506
507 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNUSED)
508 continue;
509
510 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
511 if (irr & (1 << (vector % 32))) {
512 irq = __this_cpu_read(vector_irq[vector]);
513
514 desc = irq_to_desc(irq);
515 raw_spin_lock(&desc->lock);
516 data = irq_desc_get_irq_data(desc);
517 chip = irq_data_get_irq_chip(data);
518 if (chip->irq_retrigger) {
519 chip->irq_retrigger(data);
520 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
521 }
522 raw_spin_unlock(&desc->lock);
523 }
524 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
525 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
526 }
527 }
528 #endif
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