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052043ed64991b14e9b7f9297d8f241dc60b99bd
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38
39 /*
40 * Various Linux-internal data structures created from the
41 * MP-table.
42 */
43 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
44 int mp_bus_id_to_type [MAX_MP_BUSSES];
45 #endif
46 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
47 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
48 static int mp_current_pci_id;
49
50 int pic_mode;
51
52 /*
53 * Intel MP BIOS table parsing routines:
54 */
55
56
57 /*
58 * Checksum an MP configuration block.
59 */
60
61 static int __init mpf_checksum(unsigned char *mp, int len)
62 {
63 int sum = 0;
64
65 while (len--)
66 sum += *mp++;
67
68 return sum & 0xFF;
69 }
70
71 #ifdef CONFIG_X86_NUMAQ
72 /*
73 * Have to match translation table entries to main table entries by counter
74 * hence the mpc_record variable .... can't see a less disgusting way of
75 * doing this ....
76 */
77
78 static int mpc_record;
79 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
80 #endif
81
82 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
83 {
84 int apicid;
85
86 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
87 disabled_cpus++;
88 return;
89 }
90
91 #ifdef CONFIG_X86_NUMAQ
92 apicid = mpc_apic_id(m, translation_table[mpc_record]);
93 #else
94 Dprintk("Processor #%d %u:%u APIC version %d\n",
95 m->mpc_apicid,
96 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
97 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
98 m->mpc_apicver);
99 apicid = m->mpc_apicid;
100 #endif
101
102 if (m->mpc_featureflag&(1<<0))
103 Dprintk(" Floating point unit present.\n");
104 if (m->mpc_featureflag&(1<<7))
105 Dprintk(" Machine Exception supported.\n");
106 if (m->mpc_featureflag&(1<<8))
107 Dprintk(" 64 bit compare & exchange supported.\n");
108 if (m->mpc_featureflag&(1<<9))
109 Dprintk(" Internal APIC present.\n");
110 if (m->mpc_featureflag&(1<<11))
111 Dprintk(" SEP present.\n");
112 if (m->mpc_featureflag&(1<<12))
113 Dprintk(" MTRR present.\n");
114 if (m->mpc_featureflag&(1<<13))
115 Dprintk(" PGE present.\n");
116 if (m->mpc_featureflag&(1<<14))
117 Dprintk(" MCA present.\n");
118 if (m->mpc_featureflag&(1<<15))
119 Dprintk(" CMOV present.\n");
120 if (m->mpc_featureflag&(1<<16))
121 Dprintk(" PAT present.\n");
122 if (m->mpc_featureflag&(1<<17))
123 Dprintk(" PSE present.\n");
124 if (m->mpc_featureflag&(1<<18))
125 Dprintk(" PSN present.\n");
126 if (m->mpc_featureflag&(1<<19))
127 Dprintk(" Cache Line Flush Instruction present.\n");
128 /* 20 Reserved */
129 if (m->mpc_featureflag&(1<<21))
130 Dprintk(" Debug Trace and EMON Store present.\n");
131 if (m->mpc_featureflag&(1<<22))
132 Dprintk(" ACPI Thermal Throttle Registers present.\n");
133 if (m->mpc_featureflag&(1<<23))
134 Dprintk(" MMX present.\n");
135 if (m->mpc_featureflag&(1<<24))
136 Dprintk(" FXSR present.\n");
137 if (m->mpc_featureflag&(1<<25))
138 Dprintk(" XMM present.\n");
139 if (m->mpc_featureflag&(1<<26))
140 Dprintk(" Willamette New Instructions present.\n");
141 if (m->mpc_featureflag&(1<<27))
142 Dprintk(" Self Snoop present.\n");
143 if (m->mpc_featureflag&(1<<28))
144 Dprintk(" HT present.\n");
145 if (m->mpc_featureflag&(1<<29))
146 Dprintk(" Thermal Monitor present.\n");
147 /* 30, 31 Reserved */
148
149
150 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
151 Dprintk(" Bootup CPU\n");
152 boot_cpu_physical_apicid = m->mpc_apicid;
153 }
154
155 generic_processor_info(apicid, m->mpc_apicver);
156 }
157
158 static void __init MP_bus_info (struct mpc_config_bus *m)
159 {
160 char str[7];
161
162 memcpy(str, m->mpc_bustype, 6);
163 str[6] = 0;
164
165 #ifdef CONFIG_X86_NUMAQ
166 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
167 #else
168 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
169 #endif
170
171 #if MAX_MP_BUSSES < 256
172 if (m->mpc_busid >= MAX_MP_BUSSES) {
173 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
174 " is too large, max. supported is %d\n",
175 m->mpc_busid, str, MAX_MP_BUSSES - 1);
176 return;
177 }
178 #endif
179
180 set_bit(m->mpc_busid, mp_bus_not_pci);
181 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
182 #ifdef CONFIG_X86_NUMAQ
183 mpc_oem_pci_bus(m, translation_table[mpc_record]);
184 #endif
185 clear_bit(m->mpc_busid, mp_bus_not_pci);
186 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
187 mp_current_pci_id++;
188 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
189 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
190 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
191 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
192 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
193 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
194 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
195 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
196 } else {
197 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
198 #endif
199 }
200 }
201
202 #ifdef CONFIG_X86_IO_APIC
203
204 static int bad_ioapic(unsigned long address)
205 {
206 if (nr_ioapics >= MAX_IO_APICS) {
207 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
208 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
209 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
210 }
211 if (!address) {
212 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
213 " found in table, skipping!\n");
214 return 1;
215 }
216 return 0;
217 }
218
219 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
220 {
221 if (!(m->mpc_flags & MPC_APIC_USABLE))
222 return;
223
224 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
225 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
226
227 if (bad_ioapic(m->mpc_apicaddr))
228 return;
229
230 mp_ioapics[nr_ioapics] = *m;
231 nr_ioapics++;
232 }
233
234 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
235 {
236 mp_irqs [mp_irq_entries] = *m;
237 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
238 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
239 m->mpc_irqtype, m->mpc_irqflag & 3,
240 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
241 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
242 if (++mp_irq_entries == MAX_IRQ_SOURCES)
243 panic("Max # of irq sources exceeded!!\n");
244 }
245
246 #endif
247
248 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
249 {
250 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
251 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
252 m->mpc_irqtype, m->mpc_irqflag & 3,
253 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
254 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
255 }
256
257 #ifdef CONFIG_X86_NUMAQ
258 static void __init MP_translation_info (struct mpc_config_translation *m)
259 {
260 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
261
262 if (mpc_record >= MAX_MPC_ENTRY)
263 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
264 else
265 translation_table[mpc_record] = m; /* stash this for later */
266 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
267 node_set_online(m->trans_quad);
268 }
269
270 /*
271 * Read/parse the MPC oem tables
272 */
273
274 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
275 unsigned short oemsize)
276 {
277 int count = sizeof (*oemtable); /* the header size */
278 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
279
280 mpc_record = 0;
281 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
282 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
283 {
284 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
285 oemtable->oem_signature[0],
286 oemtable->oem_signature[1],
287 oemtable->oem_signature[2],
288 oemtable->oem_signature[3]);
289 return;
290 }
291 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
292 {
293 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
294 return;
295 }
296 while (count < oemtable->oem_length) {
297 switch (*oemptr) {
298 case MP_TRANSLATION:
299 {
300 struct mpc_config_translation *m=
301 (struct mpc_config_translation *)oemptr;
302 MP_translation_info(m);
303 oemptr += sizeof(*m);
304 count += sizeof(*m);
305 ++mpc_record;
306 break;
307 }
308 default:
309 {
310 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
311 return;
312 }
313 }
314 }
315 }
316
317 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
318 char *productid)
319 {
320 if (strncmp(oem, "IBM NUMA", 8))
321 printk("Warning! May not be a NUMA-Q system!\n");
322 if (mpc->mpc_oemptr)
323 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
324 mpc->mpc_oemsize);
325 }
326 #endif /* CONFIG_X86_NUMAQ */
327
328 /*
329 * Read/parse the MPC
330 */
331
332 static int __init smp_read_mpc(struct mp_config_table *mpc)
333 {
334 char str[16];
335 char oem[10];
336 int count=sizeof(*mpc);
337 unsigned char *mpt=((unsigned char *)mpc)+count;
338
339 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
340 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
341 *(u32 *)mpc->mpc_signature);
342 return 0;
343 }
344 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
345 printk(KERN_ERR "SMP mptable: checksum error!\n");
346 return 0;
347 }
348 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
349 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
350 mpc->mpc_spec);
351 return 0;
352 }
353 if (!mpc->mpc_lapic) {
354 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
355 return 0;
356 }
357 memcpy(oem,mpc->mpc_oem,8);
358 oem[8]=0;
359 printk(KERN_INFO "OEM ID: %s ",oem);
360
361 memcpy(str,mpc->mpc_productid,12);
362 str[12]=0;
363 printk("Product ID: %s ",str);
364
365 mps_oem_check(mpc, oem, str);
366
367 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
368
369 /*
370 * Save the local APIC address (it might be non-default) -- but only
371 * if we're not using ACPI.
372 */
373 if (!acpi_lapic)
374 mp_lapic_addr = mpc->mpc_lapic;
375
376 /*
377 * Now process the configuration blocks.
378 */
379 #ifdef CONFIG_X86_NUMAQ
380 mpc_record = 0;
381 #endif
382 while (count < mpc->mpc_length) {
383 switch(*mpt) {
384 case MP_PROCESSOR:
385 {
386 struct mpc_config_processor *m=
387 (struct mpc_config_processor *)mpt;
388 /* ACPI may have already provided this data */
389 if (!acpi_lapic)
390 MP_processor_info(m);
391 mpt += sizeof(*m);
392 count += sizeof(*m);
393 break;
394 }
395 case MP_BUS:
396 {
397 struct mpc_config_bus *m=
398 (struct mpc_config_bus *)mpt;
399 MP_bus_info(m);
400 mpt += sizeof(*m);
401 count += sizeof(*m);
402 break;
403 }
404 case MP_IOAPIC:
405 {
406 #ifdef CONFIG_X86_IO_APIC
407 struct mpc_config_ioapic *m=
408 (struct mpc_config_ioapic *)mpt;
409 MP_ioapic_info(m);
410 #endif
411 mpt+=sizeof(struct mpc_config_ioapic);
412 count+=sizeof(struct mpc_config_ioapic);
413 break;
414 }
415 case MP_INTSRC:
416 {
417 #ifdef CONFIG_X86_IO_APIC
418 struct mpc_config_intsrc *m=
419 (struct mpc_config_intsrc *)mpt;
420
421 MP_intsrc_info(m);
422 #endif
423 mpt+=sizeof(struct mpc_config_intsrc);
424 count+=sizeof(struct mpc_config_intsrc);
425 break;
426 }
427 case MP_LINTSRC:
428 {
429 struct mpc_config_lintsrc *m=
430 (struct mpc_config_lintsrc *)mpt;
431 MP_lintsrc_info(m);
432 mpt+=sizeof(*m);
433 count+=sizeof(*m);
434 break;
435 }
436 default:
437 {
438 count = mpc->mpc_length;
439 break;
440 }
441 }
442 #ifdef CONFIG_X86_NUMAQ
443 ++mpc_record;
444 #endif
445 }
446 setup_apic_routing();
447 if (!num_processors)
448 printk(KERN_ERR "SMP mptable: no processors registered!\n");
449 return num_processors;
450 }
451
452 #ifdef CONFIG_X86_IO_APIC
453
454 static int __init ELCR_trigger(unsigned int irq)
455 {
456 unsigned int port;
457
458 port = 0x4d0 + (irq >> 3);
459 return (inb(port) >> (irq & 7)) & 1;
460 }
461
462 static void __init construct_default_ioirq_mptable(int mpc_default_type)
463 {
464 struct mpc_config_intsrc intsrc;
465 int i;
466 int ELCR_fallback = 0;
467
468 intsrc.mpc_type = MP_INTSRC;
469 intsrc.mpc_irqflag = 0; /* conforming */
470 intsrc.mpc_srcbus = 0;
471 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
472
473 intsrc.mpc_irqtype = mp_INT;
474
475 /*
476 * If true, we have an ISA/PCI system with no IRQ entries
477 * in the MP table. To prevent the PCI interrupts from being set up
478 * incorrectly, we try to use the ELCR. The sanity check to see if
479 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
480 * never be level sensitive, so we simply see if the ELCR agrees.
481 * If it does, we assume it's valid.
482 */
483 if (mpc_default_type == 5) {
484 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
485
486 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
487 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
488 else {
489 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
490 ELCR_fallback = 1;
491 }
492 }
493
494 for (i = 0; i < 16; i++) {
495 switch (mpc_default_type) {
496 case 2:
497 if (i == 0 || i == 13)
498 continue; /* IRQ0 & IRQ13 not connected */
499 /* fall through */
500 default:
501 if (i == 2)
502 continue; /* IRQ2 is never connected */
503 }
504
505 if (ELCR_fallback) {
506 /*
507 * If the ELCR indicates a level-sensitive interrupt, we
508 * copy that information over to the MP table in the
509 * irqflag field (level sensitive, active high polarity).
510 */
511 if (ELCR_trigger(i))
512 intsrc.mpc_irqflag = 13;
513 else
514 intsrc.mpc_irqflag = 0;
515 }
516
517 intsrc.mpc_srcbusirq = i;
518 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
519 MP_intsrc_info(&intsrc);
520 }
521
522 intsrc.mpc_irqtype = mp_ExtINT;
523 intsrc.mpc_srcbusirq = 0;
524 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
525 MP_intsrc_info(&intsrc);
526 }
527
528 #endif
529
530 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
531 {
532 struct mpc_config_processor processor;
533 struct mpc_config_bus bus;
534 #ifdef CONFIG_X86_IO_APIC
535 struct mpc_config_ioapic ioapic;
536 #endif
537 struct mpc_config_lintsrc lintsrc;
538 int linttypes[2] = { mp_ExtINT, mp_NMI };
539 int i;
540
541 /*
542 * local APIC has default address
543 */
544 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
545
546 /*
547 * 2 CPUs, numbered 0 & 1.
548 */
549 processor.mpc_type = MP_PROCESSOR;
550 /* Either an integrated APIC or a discrete 82489DX. */
551 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
552 processor.mpc_cpuflag = CPU_ENABLED;
553 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
554 (boot_cpu_data.x86_model << 4) |
555 boot_cpu_data.x86_mask;
556 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
557 processor.mpc_reserved[0] = 0;
558 processor.mpc_reserved[1] = 0;
559 for (i = 0; i < 2; i++) {
560 processor.mpc_apicid = i;
561 MP_processor_info(&processor);
562 }
563
564 bus.mpc_type = MP_BUS;
565 bus.mpc_busid = 0;
566 switch (mpc_default_type) {
567 default:
568 printk("???\n");
569 printk(KERN_ERR "Unknown standard configuration %d\n",
570 mpc_default_type);
571 /* fall through */
572 case 1:
573 case 5:
574 memcpy(bus.mpc_bustype, "ISA ", 6);
575 break;
576 case 2:
577 case 6:
578 case 3:
579 memcpy(bus.mpc_bustype, "EISA ", 6);
580 break;
581 case 4:
582 case 7:
583 memcpy(bus.mpc_bustype, "MCA ", 6);
584 }
585 MP_bus_info(&bus);
586 if (mpc_default_type > 4) {
587 bus.mpc_busid = 1;
588 memcpy(bus.mpc_bustype, "PCI ", 6);
589 MP_bus_info(&bus);
590 }
591
592 #ifdef CONFIG_X86_IO_APIC
593 ioapic.mpc_type = MP_IOAPIC;
594 ioapic.mpc_apicid = 2;
595 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
596 ioapic.mpc_flags = MPC_APIC_USABLE;
597 ioapic.mpc_apicaddr = 0xFEC00000;
598 MP_ioapic_info(&ioapic);
599
600 /*
601 * We set up most of the low 16 IO-APIC pins according to MPS rules.
602 */
603 construct_default_ioirq_mptable(mpc_default_type);
604 #endif
605 lintsrc.mpc_type = MP_LINTSRC;
606 lintsrc.mpc_irqflag = 0; /* conforming */
607 lintsrc.mpc_srcbusid = 0;
608 lintsrc.mpc_srcbusirq = 0;
609 lintsrc.mpc_destapic = MP_APIC_ALL;
610 for (i = 0; i < 2; i++) {
611 lintsrc.mpc_irqtype = linttypes[i];
612 lintsrc.mpc_destapiclint = i;
613 MP_lintsrc_info(&lintsrc);
614 }
615 }
616
617 static struct intel_mp_floating *mpf_found;
618
619 /*
620 * Scan the memory blocks for an SMP configuration block.
621 */
622 void __init get_smp_config (void)
623 {
624 struct intel_mp_floating *mpf = mpf_found;
625
626 /*
627 * ACPI supports both logical (e.g. Hyper-Threading) and physical
628 * processors, where MPS only supports physical.
629 */
630 if (acpi_lapic && acpi_ioapic) {
631 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
632 return;
633 }
634 else if (acpi_lapic)
635 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
636
637 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
638 if (mpf->mpf_feature2 & (1<<7)) {
639 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
640 pic_mode = 1;
641 } else {
642 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
643 pic_mode = 0;
644 }
645
646 /*
647 * Now see if we need to read further.
648 */
649 if (mpf->mpf_feature1 != 0) {
650
651 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
652 construct_default_ISA_mptable(mpf->mpf_feature1);
653
654 } else if (mpf->mpf_physptr) {
655
656 /*
657 * Read the physical hardware table. Anything here will
658 * override the defaults.
659 */
660 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
661 smp_found_config = 0;
662 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
663 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
664 return;
665 }
666
667 #ifdef CONFIG_X86_IO_APIC
668 /*
669 * If there are no explicit MP IRQ entries, then we are
670 * broken. We set up most of the low 16 IO-APIC pins to
671 * ISA defaults and hope it will work.
672 */
673 if (!mp_irq_entries) {
674 struct mpc_config_bus bus;
675
676 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
677
678 bus.mpc_type = MP_BUS;
679 bus.mpc_busid = 0;
680 memcpy(bus.mpc_bustype, "ISA ", 6);
681 MP_bus_info(&bus);
682
683 construct_default_ioirq_mptable(0);
684 }
685 #endif
686 } else
687 BUG();
688
689 printk(KERN_INFO "Processors: %d\n", num_processors);
690 /*
691 * Only use the first configuration found.
692 */
693 }
694
695 static int __init smp_scan_config (unsigned long base, unsigned long length)
696 {
697 unsigned long *bp = phys_to_virt(base);
698 struct intel_mp_floating *mpf;
699
700 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
701 if (sizeof(*mpf) != 16)
702 printk("Error: MPF size\n");
703
704 while (length > 0) {
705 mpf = (struct intel_mp_floating *)bp;
706 if ((*bp == SMP_MAGIC_IDENT) &&
707 (mpf->mpf_length == 1) &&
708 !mpf_checksum((unsigned char *)bp, 16) &&
709 ((mpf->mpf_specification == 1)
710 || (mpf->mpf_specification == 4)) ) {
711
712 smp_found_config = 1;
713 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
714 mpf, virt_to_phys(mpf));
715 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
716 BOOTMEM_DEFAULT);
717 if (mpf->mpf_physptr) {
718 /*
719 * We cannot access to MPC table to compute
720 * table size yet, as only few megabytes from
721 * the bottom is mapped now.
722 * PC-9800's MPC table places on the very last
723 * of physical memory; so that simply reserving
724 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
725 * in reserve_bootmem.
726 */
727 unsigned long size = PAGE_SIZE;
728 unsigned long end = max_low_pfn * PAGE_SIZE;
729 if (mpf->mpf_physptr + size > end)
730 size = end - mpf->mpf_physptr;
731 reserve_bootmem(mpf->mpf_physptr, size,
732 BOOTMEM_DEFAULT);
733 }
734
735 mpf_found = mpf;
736 return 1;
737 }
738 bp += 4;
739 length -= 16;
740 }
741 return 0;
742 }
743
744 void __init find_smp_config (void)
745 {
746 unsigned int address;
747
748 /*
749 * FIXME: Linux assumes you have 640K of base ram..
750 * this continues the error...
751 *
752 * 1) Scan the bottom 1K for a signature
753 * 2) Scan the top 1K of base RAM
754 * 3) Scan the 64K of bios
755 */
756 if (smp_scan_config(0x0,0x400) ||
757 smp_scan_config(639*0x400,0x400) ||
758 smp_scan_config(0xF0000,0x10000))
759 return;
760 /*
761 * If it is an SMP machine we should know now, unless the
762 * configuration is in an EISA/MCA bus machine with an
763 * extended bios data area.
764 *
765 * there is a real-mode segmented pointer pointing to the
766 * 4K EBDA area at 0x40E, calculate and scan it here.
767 *
768 * NOTE! There are Linux loaders that will corrupt the EBDA
769 * area, and as such this kind of SMP config may be less
770 * trustworthy, simply because the SMP table may have been
771 * stomped on during early boot. These loaders are buggy and
772 * should be fixed.
773 *
774 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
775 */
776
777 address = get_bios_ebda();
778 if (address)
779 smp_scan_config(address, 0x400);
780 }
781
782 /* --------------------------------------------------------------------------
783 ACPI-based MP Configuration
784 -------------------------------------------------------------------------- */
785
786 #ifdef CONFIG_ACPI
787
788 #ifdef CONFIG_X86_IO_APIC
789
790 #define MP_ISA_BUS 0
791 #define MP_MAX_IOAPIC_PIN 127
792
793 extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
794
795 static int mp_find_ioapic (int gsi)
796 {
797 int i = 0;
798
799 /* Find the IOAPIC that manages this GSI. */
800 for (i = 0; i < nr_ioapics; i++) {
801 if ((gsi >= mp_ioapic_routing[i].gsi_base)
802 && (gsi <= mp_ioapic_routing[i].gsi_end))
803 return i;
804 }
805
806 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
807
808 return -1;
809 }
810
811 static u8 uniq_ioapic_id(u8 id)
812 {
813 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
814 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
815 return io_apic_get_unique_id(nr_ioapics, id);
816 else
817 return id;
818 }
819
820 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
821 {
822 int idx = 0;
823
824 if (bad_ioapic(address))
825 return;
826
827 idx = nr_ioapics;
828
829 mp_ioapics[idx].mpc_type = MP_IOAPIC;
830 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
831 mp_ioapics[idx].mpc_apicaddr = address;
832
833 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
834 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
835 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
836
837 /*
838 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
839 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
840 */
841 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
842 mp_ioapic_routing[idx].gsi_base = gsi_base;
843 mp_ioapic_routing[idx].gsi_end = gsi_base +
844 io_apic_get_redir_entries(idx);
845
846 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
847 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
848 mp_ioapics[idx].mpc_apicver,
849 mp_ioapics[idx].mpc_apicaddr,
850 mp_ioapic_routing[idx].gsi_base,
851 mp_ioapic_routing[idx].gsi_end);
852
853 nr_ioapics++;
854 }
855
856 void __init
857 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
858 {
859 struct mpc_config_intsrc intsrc;
860 int ioapic = -1;
861 int pin = -1;
862
863 /*
864 * Convert 'gsi' to 'ioapic.pin'.
865 */
866 ioapic = mp_find_ioapic(gsi);
867 if (ioapic < 0)
868 return;
869 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
870
871 /*
872 * TBD: This check is for faulty timer entries, where the override
873 * erroneously sets the trigger to level, resulting in a HUGE
874 * increase of timer interrupts!
875 */
876 if ((bus_irq == 0) && (trigger == 3))
877 trigger = 1;
878
879 intsrc.mpc_type = MP_INTSRC;
880 intsrc.mpc_irqtype = mp_INT;
881 intsrc.mpc_irqflag = (trigger << 2) | polarity;
882 intsrc.mpc_srcbus = MP_ISA_BUS;
883 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
884 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
885 intsrc.mpc_dstirq = pin; /* INTIN# */
886
887 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
888 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
889 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
890 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
891
892 mp_irqs[mp_irq_entries] = intsrc;
893 if (++mp_irq_entries == MAX_IRQ_SOURCES)
894 panic("Max # of irq sources exceeded!\n");
895 }
896
897 int es7000_plat;
898
899 void __init mp_config_acpi_legacy_irqs (void)
900 {
901 struct mpc_config_intsrc intsrc;
902 int i = 0;
903 int ioapic = -1;
904
905 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
906 /*
907 * Fabricate the legacy ISA bus (bus #31).
908 */
909 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
910 #endif
911 set_bit(MP_ISA_BUS, mp_bus_not_pci);
912 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
913
914 /*
915 * Older generations of ES7000 have no legacy identity mappings
916 */
917 if (es7000_plat == 1)
918 return;
919
920 /*
921 * Locate the IOAPIC that manages the ISA IRQs (0-15).
922 */
923 ioapic = mp_find_ioapic(0);
924 if (ioapic < 0)
925 return;
926
927 intsrc.mpc_type = MP_INTSRC;
928 intsrc.mpc_irqflag = 0; /* Conforming */
929 intsrc.mpc_srcbus = MP_ISA_BUS;
930 #ifdef CONFIG_X86_IO_APIC
931 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
932 #endif
933 /*
934 * Use the default configuration for the IRQs 0-15. Unless
935 * overridden by (MADT) interrupt source override entries.
936 */
937 for (i = 0; i < 16; i++) {
938 int idx;
939
940 for (idx = 0; idx < mp_irq_entries; idx++) {
941 struct mpc_config_intsrc *irq = mp_irqs + idx;
942
943 /* Do we already have a mapping for this ISA IRQ? */
944 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
945 break;
946
947 /* Do we already have a mapping for this IOAPIC pin */
948 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
949 (irq->mpc_dstirq == i))
950 break;
951 }
952
953 if (idx != mp_irq_entries) {
954 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
955 continue; /* IRQ already used */
956 }
957
958 intsrc.mpc_irqtype = mp_INT;
959 intsrc.mpc_srcbusirq = i; /* Identity mapped */
960 intsrc.mpc_dstirq = i;
961
962 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
963 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
964 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
965 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
966 intsrc.mpc_dstirq);
967
968 mp_irqs[mp_irq_entries] = intsrc;
969 if (++mp_irq_entries == MAX_IRQ_SOURCES)
970 panic("Max # of irq sources exceeded!\n");
971 }
972 }
973
974 #define MAX_GSI_NUM 4096
975 #define IRQ_COMPRESSION_START 64
976
977 int mp_register_gsi(u32 gsi, int triggering, int polarity)
978 {
979 int ioapic = -1;
980 int ioapic_pin = 0;
981 int idx, bit = 0;
982 static int pci_irq = IRQ_COMPRESSION_START;
983 /*
984 * Mapping between Global System Interrupts, which
985 * represent all possible interrupts, and IRQs
986 * assigned to actual devices.
987 */
988 static int gsi_to_irq[MAX_GSI_NUM];
989
990 /* Don't set up the ACPI SCI because it's already set up */
991 if (acpi_gbl_FADT.sci_interrupt == gsi)
992 return gsi;
993
994 ioapic = mp_find_ioapic(gsi);
995 if (ioapic < 0) {
996 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
997 return gsi;
998 }
999
1000 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1001
1002 if (ioapic_renumber_irq)
1003 gsi = ioapic_renumber_irq(ioapic, gsi);
1004
1005 /*
1006 * Avoid pin reprogramming. PRTs typically include entries
1007 * with redundant pin->gsi mappings (but unique PCI devices);
1008 * we only program the IOAPIC on the first.
1009 */
1010 bit = ioapic_pin % 32;
1011 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1012 if (idx > 3) {
1013 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1014 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1015 ioapic_pin);
1016 return gsi;
1017 }
1018 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1019 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1020 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1021 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1022 }
1023
1024 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1025
1026 /*
1027 * For GSI >= 64, use IRQ compression
1028 */
1029 if ((gsi >= IRQ_COMPRESSION_START)
1030 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1031 /*
1032 * For PCI devices assign IRQs in order, avoiding gaps
1033 * due to unused I/O APIC pins.
1034 */
1035 int irq = gsi;
1036 if (gsi < MAX_GSI_NUM) {
1037 /*
1038 * Retain the VIA chipset work-around (gsi > 15), but
1039 * avoid a problem where the 8254 timer (IRQ0) is setup
1040 * via an override (so it's not on pin 0 of the ioapic),
1041 * and at the same time, the pin 0 interrupt is a PCI
1042 * type. The gsi > 15 test could cause these two pins
1043 * to be shared as IRQ0, and they are not shareable.
1044 * So test for this condition, and if necessary, avoid
1045 * the pin collision.
1046 */
1047 gsi = pci_irq++;
1048 /*
1049 * Don't assign IRQ used by ACPI SCI
1050 */
1051 if (gsi == acpi_gbl_FADT.sci_interrupt)
1052 gsi = pci_irq++;
1053 gsi_to_irq[irq] = gsi;
1054 } else {
1055 printk(KERN_ERR "GSI %u is too high\n", gsi);
1056 return gsi;
1057 }
1058 }
1059
1060 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1061 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1062 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1063 return gsi;
1064 }
1065
1066 #endif /* CONFIG_X86_IO_APIC */
1067 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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