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[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30
31 #include <mach_apic.h>
32 #include <mach_apicdef.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 #endif
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
51
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57
58 /* MP IRQ source entries */
59 int mp_irq_entries;
60
61 int nr_ioapics;
62
63 int pic_mode;
64 unsigned long mp_lapic_addr;
65
66 unsigned int def_to_bigsmp = 0;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
72
73 unsigned disabled_cpus __cpuinitdata;
74
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
77
78 #ifndef CONFIG_SMP
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
80 #endif
81
82 /*
83 * Intel MP BIOS table parsing routines:
84 */
85
86
87 /*
88 * Checksum an MP configuration block.
89 */
90
91 static int __init mpf_checksum(unsigned char *mp, int len)
92 {
93 int sum = 0;
94
95 while (len--)
96 sum += *mp++;
97
98 return sum & 0xFF;
99 }
100
101 /*
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
104 * doing this ....
105 */
106
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
109
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
111 {
112 int ver, apicid, cpu;
113 cpumask_t tmp_map;
114 physid_mask_t phys_cpu;
115
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
117 disabled_cpus++;
118 return;
119 }
120
121 apicid = mpc_apic_id(m, translation_table[mpc_record]);
122
123 if (m->mpc_featureflag&(1<<0))
124 Dprintk(" Floating point unit present.\n");
125 if (m->mpc_featureflag&(1<<7))
126 Dprintk(" Machine Exception supported.\n");
127 if (m->mpc_featureflag&(1<<8))
128 Dprintk(" 64 bit compare & exchange supported.\n");
129 if (m->mpc_featureflag&(1<<9))
130 Dprintk(" Internal APIC present.\n");
131 if (m->mpc_featureflag&(1<<11))
132 Dprintk(" SEP present.\n");
133 if (m->mpc_featureflag&(1<<12))
134 Dprintk(" MTRR present.\n");
135 if (m->mpc_featureflag&(1<<13))
136 Dprintk(" PGE present.\n");
137 if (m->mpc_featureflag&(1<<14))
138 Dprintk(" MCA present.\n");
139 if (m->mpc_featureflag&(1<<15))
140 Dprintk(" CMOV present.\n");
141 if (m->mpc_featureflag&(1<<16))
142 Dprintk(" PAT present.\n");
143 if (m->mpc_featureflag&(1<<17))
144 Dprintk(" PSE present.\n");
145 if (m->mpc_featureflag&(1<<18))
146 Dprintk(" PSN present.\n");
147 if (m->mpc_featureflag&(1<<19))
148 Dprintk(" Cache Line Flush Instruction present.\n");
149 /* 20 Reserved */
150 if (m->mpc_featureflag&(1<<21))
151 Dprintk(" Debug Trace and EMON Store present.\n");
152 if (m->mpc_featureflag&(1<<22))
153 Dprintk(" ACPI Thermal Throttle Registers present.\n");
154 if (m->mpc_featureflag&(1<<23))
155 Dprintk(" MMX present.\n");
156 if (m->mpc_featureflag&(1<<24))
157 Dprintk(" FXSR present.\n");
158 if (m->mpc_featureflag&(1<<25))
159 Dprintk(" XMM present.\n");
160 if (m->mpc_featureflag&(1<<26))
161 Dprintk(" Willamette New Instructions present.\n");
162 if (m->mpc_featureflag&(1<<27))
163 Dprintk(" Self Snoop present.\n");
164 if (m->mpc_featureflag&(1<<28))
165 Dprintk(" HT present.\n");
166 if (m->mpc_featureflag&(1<<29))
167 Dprintk(" Thermal Monitor present.\n");
168 /* 30, 31 Reserved */
169
170
171 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
172 Dprintk(" Bootup CPU\n");
173 boot_cpu_physical_apicid = m->mpc_apicid;
174 }
175
176 ver = m->mpc_apicver;
177
178 /*
179 * Validate version
180 */
181 if (ver == 0x0) {
182 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
183 "fixing up to 0x10. (tell your hw vendor)\n",
184 m->mpc_apicid);
185 ver = 0x10;
186 }
187 apic_version[m->mpc_apicid] = ver;
188
189 phys_cpu = apicid_to_cpu_present(apicid);
190 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
191
192 if (num_processors >= NR_CPUS) {
193 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
194 " Processor ignored.\n", NR_CPUS);
195 return;
196 }
197
198 if (num_processors >= maxcpus) {
199 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
200 " Processor ignored.\n", maxcpus);
201 return;
202 }
203
204 cpu_set(num_processors, cpu_possible_map);
205 num_processors++;
206 cpus_complement(tmp_map, cpu_present_map);
207 cpu = first_cpu(tmp_map);
208
209 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
210 /*
211 * x86_bios_cpu_apicid is required to have processors listed
212 * in same order as logical cpu numbers. Hence the first
213 * entry is BSP, and so on.
214 */
215 cpu = 0;
216
217 /*
218 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
219 * but we need to work other dependencies like SMP_SUSPEND etc
220 * before this can be done without some confusion.
221 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
222 * - Ashok Raj <ashok.raj@intel.com>
223 */
224 if (num_processors > 8) {
225 switch (boot_cpu_data.x86_vendor) {
226 case X86_VENDOR_INTEL:
227 if (!APIC_XAPIC(ver)) {
228 def_to_bigsmp = 0;
229 break;
230 }
231 /* If P4 and above fall through */
232 case X86_VENDOR_AMD:
233 def_to_bigsmp = 1;
234 }
235 }
236 #ifdef CONFIG_SMP
237 /* are we being called early in kernel startup? */
238 if (x86_cpu_to_apicid_early_ptr) {
239 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
240 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
241
242 cpu_to_apicid[cpu] = m->mpc_apicid;
243 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
244 } else {
245 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
246 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
247 }
248 #endif
249 cpu_set(cpu, cpu_present_map);
250 }
251
252 static void __init MP_bus_info (struct mpc_config_bus *m)
253 {
254 char str[7];
255
256 memcpy(str, m->mpc_bustype, 6);
257 str[6] = 0;
258
259 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
260
261 #if MAX_MP_BUSSES < 256
262 if (m->mpc_busid >= MAX_MP_BUSSES) {
263 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
264 " is too large, max. supported is %d\n",
265 m->mpc_busid, str, MAX_MP_BUSSES - 1);
266 return;
267 }
268 #endif
269
270 set_bit(m->mpc_busid, mp_bus_not_pci);
271 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
272 mpc_oem_pci_bus(m, translation_table[mpc_record]);
273 clear_bit(m->mpc_busid, mp_bus_not_pci);
274 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
275 mp_current_pci_id++;
276 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
277 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
278 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
279 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
280 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
281 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
282 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
283 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
284 } else {
285 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
286 #endif
287 }
288 }
289
290 static int bad_ioapic(unsigned long address)
291 {
292 if (nr_ioapics >= MAX_IO_APICS) {
293 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
294 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
295 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
296 }
297 if (!address) {
298 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
299 " found in table, skipping!\n");
300 return 1;
301 }
302 return 0;
303 }
304
305 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
306 {
307 if (!(m->mpc_flags & MPC_APIC_USABLE))
308 return;
309
310 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
311 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
312
313 if (bad_ioapic(m->mpc_apicaddr))
314 return;
315
316 mp_ioapics[nr_ioapics] = *m;
317 nr_ioapics++;
318 }
319
320 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
321 {
322 mp_irqs [mp_irq_entries] = *m;
323 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
324 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
325 m->mpc_irqtype, m->mpc_irqflag & 3,
326 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
327 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
328 if (++mp_irq_entries == MAX_IRQ_SOURCES)
329 panic("Max # of irq sources exceeded!!\n");
330 }
331
332 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
333 {
334 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
335 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
336 m->mpc_irqtype, m->mpc_irqflag & 3,
337 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
338 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
339 }
340
341 #ifdef CONFIG_X86_NUMAQ
342 static void __init MP_translation_info (struct mpc_config_translation *m)
343 {
344 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
345
346 if (mpc_record >= MAX_MPC_ENTRY)
347 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
348 else
349 translation_table[mpc_record] = m; /* stash this for later */
350 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
351 node_set_online(m->trans_quad);
352 }
353
354 /*
355 * Read/parse the MPC oem tables
356 */
357
358 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
359 unsigned short oemsize)
360 {
361 int count = sizeof (*oemtable); /* the header size */
362 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
363
364 mpc_record = 0;
365 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
366 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
367 {
368 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
369 oemtable->oem_signature[0],
370 oemtable->oem_signature[1],
371 oemtable->oem_signature[2],
372 oemtable->oem_signature[3]);
373 return;
374 }
375 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
376 {
377 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
378 return;
379 }
380 while (count < oemtable->oem_length) {
381 switch (*oemptr) {
382 case MP_TRANSLATION:
383 {
384 struct mpc_config_translation *m=
385 (struct mpc_config_translation *)oemptr;
386 MP_translation_info(m);
387 oemptr += sizeof(*m);
388 count += sizeof(*m);
389 ++mpc_record;
390 break;
391 }
392 default:
393 {
394 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
395 return;
396 }
397 }
398 }
399 }
400
401 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
402 char *productid)
403 {
404 if (strncmp(oem, "IBM NUMA", 8))
405 printk("Warning! May not be a NUMA-Q system!\n");
406 if (mpc->mpc_oemptr)
407 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
408 mpc->mpc_oemsize);
409 }
410 #endif /* CONFIG_X86_NUMAQ */
411
412 /*
413 * Read/parse the MPC
414 */
415
416 static int __init smp_read_mpc(struct mp_config_table *mpc)
417 {
418 char str[16];
419 char oem[10];
420 int count=sizeof(*mpc);
421 unsigned char *mpt=((unsigned char *)mpc)+count;
422
423 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
424 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
425 *(u32 *)mpc->mpc_signature);
426 return 0;
427 }
428 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
429 printk(KERN_ERR "SMP mptable: checksum error!\n");
430 return 0;
431 }
432 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
433 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
434 mpc->mpc_spec);
435 return 0;
436 }
437 if (!mpc->mpc_lapic) {
438 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
439 return 0;
440 }
441 memcpy(oem,mpc->mpc_oem,8);
442 oem[8]=0;
443 printk(KERN_INFO "OEM ID: %s ",oem);
444
445 memcpy(str,mpc->mpc_productid,12);
446 str[12]=0;
447 printk("Product ID: %s ",str);
448
449 mps_oem_check(mpc, oem, str);
450
451 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
452
453 /*
454 * Save the local APIC address (it might be non-default) -- but only
455 * if we're not using ACPI.
456 */
457 if (!acpi_lapic)
458 mp_lapic_addr = mpc->mpc_lapic;
459
460 /*
461 * Now process the configuration blocks.
462 */
463 mpc_record = 0;
464 while (count < mpc->mpc_length) {
465 switch(*mpt) {
466 case MP_PROCESSOR:
467 {
468 struct mpc_config_processor *m=
469 (struct mpc_config_processor *)mpt;
470 /* ACPI may have already provided this data */
471 if (!acpi_lapic)
472 MP_processor_info(m);
473 mpt += sizeof(*m);
474 count += sizeof(*m);
475 break;
476 }
477 case MP_BUS:
478 {
479 struct mpc_config_bus *m=
480 (struct mpc_config_bus *)mpt;
481 MP_bus_info(m);
482 mpt += sizeof(*m);
483 count += sizeof(*m);
484 break;
485 }
486 case MP_IOAPIC:
487 {
488 struct mpc_config_ioapic *m=
489 (struct mpc_config_ioapic *)mpt;
490 MP_ioapic_info(m);
491 mpt+=sizeof(*m);
492 count+=sizeof(*m);
493 break;
494 }
495 case MP_INTSRC:
496 {
497 struct mpc_config_intsrc *m=
498 (struct mpc_config_intsrc *)mpt;
499
500 MP_intsrc_info(m);
501 mpt+=sizeof(*m);
502 count+=sizeof(*m);
503 break;
504 }
505 case MP_LINTSRC:
506 {
507 struct mpc_config_lintsrc *m=
508 (struct mpc_config_lintsrc *)mpt;
509 MP_lintsrc_info(m);
510 mpt+=sizeof(*m);
511 count+=sizeof(*m);
512 break;
513 }
514 default:
515 {
516 count = mpc->mpc_length;
517 break;
518 }
519 }
520 ++mpc_record;
521 }
522 setup_apic_routing();
523 if (!num_processors)
524 printk(KERN_ERR "SMP mptable: no processors registered!\n");
525 return num_processors;
526 }
527
528 static int __init ELCR_trigger(unsigned int irq)
529 {
530 unsigned int port;
531
532 port = 0x4d0 + (irq >> 3);
533 return (inb(port) >> (irq & 7)) & 1;
534 }
535
536 static void __init construct_default_ioirq_mptable(int mpc_default_type)
537 {
538 struct mpc_config_intsrc intsrc;
539 int i;
540 int ELCR_fallback = 0;
541
542 intsrc.mpc_type = MP_INTSRC;
543 intsrc.mpc_irqflag = 0; /* conforming */
544 intsrc.mpc_srcbus = 0;
545 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
546
547 intsrc.mpc_irqtype = mp_INT;
548
549 /*
550 * If true, we have an ISA/PCI system with no IRQ entries
551 * in the MP table. To prevent the PCI interrupts from being set up
552 * incorrectly, we try to use the ELCR. The sanity check to see if
553 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
554 * never be level sensitive, so we simply see if the ELCR agrees.
555 * If it does, we assume it's valid.
556 */
557 if (mpc_default_type == 5) {
558 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
559
560 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
561 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
562 else {
563 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
564 ELCR_fallback = 1;
565 }
566 }
567
568 for (i = 0; i < 16; i++) {
569 switch (mpc_default_type) {
570 case 2:
571 if (i == 0 || i == 13)
572 continue; /* IRQ0 & IRQ13 not connected */
573 /* fall through */
574 default:
575 if (i == 2)
576 continue; /* IRQ2 is never connected */
577 }
578
579 if (ELCR_fallback) {
580 /*
581 * If the ELCR indicates a level-sensitive interrupt, we
582 * copy that information over to the MP table in the
583 * irqflag field (level sensitive, active high polarity).
584 */
585 if (ELCR_trigger(i))
586 intsrc.mpc_irqflag = 13;
587 else
588 intsrc.mpc_irqflag = 0;
589 }
590
591 intsrc.mpc_srcbusirq = i;
592 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
593 MP_intsrc_info(&intsrc);
594 }
595
596 intsrc.mpc_irqtype = mp_ExtINT;
597 intsrc.mpc_srcbusirq = 0;
598 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
599 MP_intsrc_info(&intsrc);
600 }
601
602 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
603 {
604 struct mpc_config_processor processor;
605 struct mpc_config_bus bus;
606 struct mpc_config_ioapic ioapic;
607 struct mpc_config_lintsrc lintsrc;
608 int linttypes[2] = { mp_ExtINT, mp_NMI };
609 int i;
610
611 /*
612 * local APIC has default address
613 */
614 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
615
616 /*
617 * 2 CPUs, numbered 0 & 1.
618 */
619 processor.mpc_type = MP_PROCESSOR;
620 /* Either an integrated APIC or a discrete 82489DX. */
621 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
622 processor.mpc_cpuflag = CPU_ENABLED;
623 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
624 (boot_cpu_data.x86_model << 4) |
625 boot_cpu_data.x86_mask;
626 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
627 processor.mpc_reserved[0] = 0;
628 processor.mpc_reserved[1] = 0;
629 for (i = 0; i < 2; i++) {
630 processor.mpc_apicid = i;
631 MP_processor_info(&processor);
632 }
633
634 bus.mpc_type = MP_BUS;
635 bus.mpc_busid = 0;
636 switch (mpc_default_type) {
637 default:
638 printk("???\n");
639 printk(KERN_ERR "Unknown standard configuration %d\n",
640 mpc_default_type);
641 /* fall through */
642 case 1:
643 case 5:
644 memcpy(bus.mpc_bustype, "ISA ", 6);
645 break;
646 case 2:
647 case 6:
648 case 3:
649 memcpy(bus.mpc_bustype, "EISA ", 6);
650 break;
651 case 4:
652 case 7:
653 memcpy(bus.mpc_bustype, "MCA ", 6);
654 }
655 MP_bus_info(&bus);
656 if (mpc_default_type > 4) {
657 bus.mpc_busid = 1;
658 memcpy(bus.mpc_bustype, "PCI ", 6);
659 MP_bus_info(&bus);
660 }
661
662 ioapic.mpc_type = MP_IOAPIC;
663 ioapic.mpc_apicid = 2;
664 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
665 ioapic.mpc_flags = MPC_APIC_USABLE;
666 ioapic.mpc_apicaddr = 0xFEC00000;
667 MP_ioapic_info(&ioapic);
668
669 /*
670 * We set up most of the low 16 IO-APIC pins according to MPS rules.
671 */
672 construct_default_ioirq_mptable(mpc_default_type);
673
674 lintsrc.mpc_type = MP_LINTSRC;
675 lintsrc.mpc_irqflag = 0; /* conforming */
676 lintsrc.mpc_srcbusid = 0;
677 lintsrc.mpc_srcbusirq = 0;
678 lintsrc.mpc_destapic = MP_APIC_ALL;
679 for (i = 0; i < 2; i++) {
680 lintsrc.mpc_irqtype = linttypes[i];
681 lintsrc.mpc_destapiclint = i;
682 MP_lintsrc_info(&lintsrc);
683 }
684 }
685
686 static struct intel_mp_floating *mpf_found;
687
688 /*
689 * Scan the memory blocks for an SMP configuration block.
690 */
691 void __init get_smp_config (void)
692 {
693 struct intel_mp_floating *mpf = mpf_found;
694
695 /*
696 * ACPI supports both logical (e.g. Hyper-Threading) and physical
697 * processors, where MPS only supports physical.
698 */
699 if (acpi_lapic && acpi_ioapic) {
700 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
701 return;
702 }
703 else if (acpi_lapic)
704 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
705
706 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
707 if (mpf->mpf_feature2 & (1<<7)) {
708 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
709 pic_mode = 1;
710 } else {
711 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
712 pic_mode = 0;
713 }
714
715 /*
716 * Now see if we need to read further.
717 */
718 if (mpf->mpf_feature1 != 0) {
719
720 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
721 construct_default_ISA_mptable(mpf->mpf_feature1);
722
723 } else if (mpf->mpf_physptr) {
724
725 /*
726 * Read the physical hardware table. Anything here will
727 * override the defaults.
728 */
729 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
730 smp_found_config = 0;
731 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
732 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
733 return;
734 }
735 /*
736 * If there are no explicit MP IRQ entries, then we are
737 * broken. We set up most of the low 16 IO-APIC pins to
738 * ISA defaults and hope it will work.
739 */
740 if (!mp_irq_entries) {
741 struct mpc_config_bus bus;
742
743 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
744
745 bus.mpc_type = MP_BUS;
746 bus.mpc_busid = 0;
747 memcpy(bus.mpc_bustype, "ISA ", 6);
748 MP_bus_info(&bus);
749
750 construct_default_ioirq_mptable(0);
751 }
752
753 } else
754 BUG();
755
756 printk(KERN_INFO "Processors: %d\n", num_processors);
757 /*
758 * Only use the first configuration found.
759 */
760 }
761
762 static int __init smp_scan_config (unsigned long base, unsigned long length)
763 {
764 unsigned long *bp = phys_to_virt(base);
765 struct intel_mp_floating *mpf;
766
767 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
768 if (sizeof(*mpf) != 16)
769 printk("Error: MPF size\n");
770
771 while (length > 0) {
772 mpf = (struct intel_mp_floating *)bp;
773 if ((*bp == SMP_MAGIC_IDENT) &&
774 (mpf->mpf_length == 1) &&
775 !mpf_checksum((unsigned char *)bp, 16) &&
776 ((mpf->mpf_specification == 1)
777 || (mpf->mpf_specification == 4)) ) {
778
779 smp_found_config = 1;
780 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
781 mpf, virt_to_phys(mpf));
782 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
783 BOOTMEM_DEFAULT);
784 if (mpf->mpf_physptr) {
785 /*
786 * We cannot access to MPC table to compute
787 * table size yet, as only few megabytes from
788 * the bottom is mapped now.
789 * PC-9800's MPC table places on the very last
790 * of physical memory; so that simply reserving
791 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
792 * in reserve_bootmem.
793 */
794 unsigned long size = PAGE_SIZE;
795 unsigned long end = max_low_pfn * PAGE_SIZE;
796 if (mpf->mpf_physptr + size > end)
797 size = end - mpf->mpf_physptr;
798 reserve_bootmem(mpf->mpf_physptr, size,
799 BOOTMEM_DEFAULT);
800 }
801
802 mpf_found = mpf;
803 return 1;
804 }
805 bp += 4;
806 length -= 16;
807 }
808 return 0;
809 }
810
811 void __init find_smp_config (void)
812 {
813 unsigned int address;
814
815 /*
816 * FIXME: Linux assumes you have 640K of base ram..
817 * this continues the error...
818 *
819 * 1) Scan the bottom 1K for a signature
820 * 2) Scan the top 1K of base RAM
821 * 3) Scan the 64K of bios
822 */
823 if (smp_scan_config(0x0,0x400) ||
824 smp_scan_config(639*0x400,0x400) ||
825 smp_scan_config(0xF0000,0x10000))
826 return;
827 /*
828 * If it is an SMP machine we should know now, unless the
829 * configuration is in an EISA/MCA bus machine with an
830 * extended bios data area.
831 *
832 * there is a real-mode segmented pointer pointing to the
833 * 4K EBDA area at 0x40E, calculate and scan it here.
834 *
835 * NOTE! There are Linux loaders that will corrupt the EBDA
836 * area, and as such this kind of SMP config may be less
837 * trustworthy, simply because the SMP table may have been
838 * stomped on during early boot. These loaders are buggy and
839 * should be fixed.
840 *
841 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
842 */
843
844 address = get_bios_ebda();
845 if (address)
846 smp_scan_config(address, 0x400);
847 }
848
849 int es7000_plat;
850
851 /* --------------------------------------------------------------------------
852 ACPI-based MP Configuration
853 -------------------------------------------------------------------------- */
854
855 #ifdef CONFIG_ACPI
856
857 void __init mp_register_lapic_address(u64 address)
858 {
859 mp_lapic_addr = (unsigned long) address;
860
861 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
862
863 if (boot_cpu_physical_apicid == -1U)
864 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
865
866 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
867 }
868
869 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
870 {
871 struct mpc_config_processor processor;
872 int boot_cpu = 0;
873
874 if (MAX_APICS - id <= 0) {
875 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
876 id, MAX_APICS);
877 return;
878 }
879
880 if (id == boot_cpu_physical_apicid)
881 boot_cpu = 1;
882
883 processor.mpc_type = MP_PROCESSOR;
884 processor.mpc_apicid = id;
885 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
886 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
887 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
888 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
889 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
890 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
891 processor.mpc_reserved[0] = 0;
892 processor.mpc_reserved[1] = 0;
893
894 MP_processor_info(&processor);
895 }
896
897 #ifdef CONFIG_X86_IO_APIC
898
899 #define MP_ISA_BUS 0
900 #define MP_MAX_IOAPIC_PIN 127
901
902 static struct mp_ioapic_routing {
903 int apic_id;
904 int gsi_base;
905 int gsi_end;
906 u32 pin_programmed[4];
907 } mp_ioapic_routing[MAX_IO_APICS];
908
909 static int mp_find_ioapic (int gsi)
910 {
911 int i = 0;
912
913 /* Find the IOAPIC that manages this GSI. */
914 for (i = 0; i < nr_ioapics; i++) {
915 if ((gsi >= mp_ioapic_routing[i].gsi_base)
916 && (gsi <= mp_ioapic_routing[i].gsi_end))
917 return i;
918 }
919
920 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
921
922 return -1;
923 }
924
925 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
926 {
927 int idx = 0;
928 int tmpid;
929
930 if (bad_ioapic(address))
931 return;
932
933 idx = nr_ioapics++;
934
935 mp_ioapics[idx].mpc_type = MP_IOAPIC;
936 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
937 mp_ioapics[idx].mpc_apicaddr = address;
938
939 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
940 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
941 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
942 tmpid = io_apic_get_unique_id(idx, id);
943 else
944 tmpid = id;
945 if (tmpid == -1) {
946 nr_ioapics--;
947 return;
948 }
949 mp_ioapics[idx].mpc_apicid = tmpid;
950 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
951
952 /*
953 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
954 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
955 */
956 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
957 mp_ioapic_routing[idx].gsi_base = gsi_base;
958 mp_ioapic_routing[idx].gsi_end = gsi_base +
959 io_apic_get_redir_entries(idx);
960
961 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
962 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
963 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
964 mp_ioapic_routing[idx].gsi_base,
965 mp_ioapic_routing[idx].gsi_end);
966 }
967
968 void __init
969 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
970 {
971 struct mpc_config_intsrc intsrc;
972 int ioapic = -1;
973 int pin = -1;
974
975 /*
976 * Convert 'gsi' to 'ioapic.pin'.
977 */
978 ioapic = mp_find_ioapic(gsi);
979 if (ioapic < 0)
980 return;
981 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
982
983 /*
984 * TBD: This check is for faulty timer entries, where the override
985 * erroneously sets the trigger to level, resulting in a HUGE
986 * increase of timer interrupts!
987 */
988 if ((bus_irq == 0) && (trigger == 3))
989 trigger = 1;
990
991 intsrc.mpc_type = MP_INTSRC;
992 intsrc.mpc_irqtype = mp_INT;
993 intsrc.mpc_irqflag = (trigger << 2) | polarity;
994 intsrc.mpc_srcbus = MP_ISA_BUS;
995 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
996 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
997 intsrc.mpc_dstirq = pin; /* INTIN# */
998
999 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1000 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1001 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1002 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1003
1004 mp_irqs[mp_irq_entries] = intsrc;
1005 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1006 panic("Max # of irq sources exceeded!\n");
1007 }
1008
1009 void __init mp_config_acpi_legacy_irqs (void)
1010 {
1011 struct mpc_config_intsrc intsrc;
1012 int i = 0;
1013 int ioapic = -1;
1014
1015 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1016 /*
1017 * Fabricate the legacy ISA bus (bus #31).
1018 */
1019 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1020 #endif
1021 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1022 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1023
1024 /*
1025 * Older generations of ES7000 have no legacy identity mappings
1026 */
1027 if (es7000_plat == 1)
1028 return;
1029
1030 /*
1031 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1032 */
1033 ioapic = mp_find_ioapic(0);
1034 if (ioapic < 0)
1035 return;
1036
1037 intsrc.mpc_type = MP_INTSRC;
1038 intsrc.mpc_irqflag = 0; /* Conforming */
1039 intsrc.mpc_srcbus = MP_ISA_BUS;
1040 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1041
1042 /*
1043 * Use the default configuration for the IRQs 0-15. Unless
1044 * overridden by (MADT) interrupt source override entries.
1045 */
1046 for (i = 0; i < 16; i++) {
1047 int idx;
1048
1049 for (idx = 0; idx < mp_irq_entries; idx++) {
1050 struct mpc_config_intsrc *irq = mp_irqs + idx;
1051
1052 /* Do we already have a mapping for this ISA IRQ? */
1053 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1054 break;
1055
1056 /* Do we already have a mapping for this IOAPIC pin */
1057 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1058 (irq->mpc_dstirq == i))
1059 break;
1060 }
1061
1062 if (idx != mp_irq_entries) {
1063 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1064 continue; /* IRQ already used */
1065 }
1066
1067 intsrc.mpc_irqtype = mp_INT;
1068 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1069 intsrc.mpc_dstirq = i;
1070
1071 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1072 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1073 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1074 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1075 intsrc.mpc_dstirq);
1076
1077 mp_irqs[mp_irq_entries] = intsrc;
1078 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1079 panic("Max # of irq sources exceeded!\n");
1080 }
1081 }
1082
1083 #define MAX_GSI_NUM 4096
1084 #define IRQ_COMPRESSION_START 64
1085
1086 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1087 {
1088 int ioapic = -1;
1089 int ioapic_pin = 0;
1090 int idx, bit = 0;
1091 static int pci_irq = IRQ_COMPRESSION_START;
1092 /*
1093 * Mapping between Global System Interrupts, which
1094 * represent all possible interrupts, and IRQs
1095 * assigned to actual devices.
1096 */
1097 static int gsi_to_irq[MAX_GSI_NUM];
1098
1099 /* Don't set up the ACPI SCI because it's already set up */
1100 if (acpi_gbl_FADT.sci_interrupt == gsi)
1101 return gsi;
1102
1103 ioapic = mp_find_ioapic(gsi);
1104 if (ioapic < 0) {
1105 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1106 return gsi;
1107 }
1108
1109 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1110
1111 if (ioapic_renumber_irq)
1112 gsi = ioapic_renumber_irq(ioapic, gsi);
1113
1114 /*
1115 * Avoid pin reprogramming. PRTs typically include entries
1116 * with redundant pin->gsi mappings (but unique PCI devices);
1117 * we only program the IOAPIC on the first.
1118 */
1119 bit = ioapic_pin % 32;
1120 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1121 if (idx > 3) {
1122 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1123 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1124 ioapic_pin);
1125 return gsi;
1126 }
1127 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1128 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1129 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1130 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1131 }
1132
1133 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1134
1135 /*
1136 * For GSI >= 64, use IRQ compression
1137 */
1138 if ((gsi >= IRQ_COMPRESSION_START)
1139 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1140 /*
1141 * For PCI devices assign IRQs in order, avoiding gaps
1142 * due to unused I/O APIC pins.
1143 */
1144 int irq = gsi;
1145 if (gsi < MAX_GSI_NUM) {
1146 /*
1147 * Retain the VIA chipset work-around (gsi > 15), but
1148 * avoid a problem where the 8254 timer (IRQ0) is setup
1149 * via an override (so it's not on pin 0 of the ioapic),
1150 * and at the same time, the pin 0 interrupt is a PCI
1151 * type. The gsi > 15 test could cause these two pins
1152 * to be shared as IRQ0, and they are not shareable.
1153 * So test for this condition, and if necessary, avoid
1154 * the pin collision.
1155 */
1156 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1157 gsi = pci_irq++;
1158 /*
1159 * Don't assign IRQ used by ACPI SCI
1160 */
1161 if (gsi == acpi_gbl_FADT.sci_interrupt)
1162 gsi = pci_irq++;
1163 gsi_to_irq[irq] = gsi;
1164 } else {
1165 printk(KERN_ERR "GSI %u is too high\n", gsi);
1166 return gsi;
1167 }
1168 }
1169
1170 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1171 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1172 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1173 return gsi;
1174 }
1175
1176 #endif /* CONFIG_X86_IO_APIC */
1177 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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