projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
x86: mpparse, move disabled cpus to smpboot.c, fix
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 #endif
47 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 static int mp_current_pci_id;
50
51 /* I/O APIC entries */
52 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53
54 /* # of MP IRQ source entries */
55 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56
57 /* MP IRQ source entries */
58 int mp_irq_entries;
59
60 int nr_ioapics;
61
62 int pic_mode;
63
64 unsigned int def_to_bigsmp = 0;
65
66 /* Processor that is doing the boot up */
67 unsigned int boot_cpu_physical_apicid = -1U;
68
69 /* Make it easy to share the UP and SMP code: */
70 #ifndef CONFIG_X86_SMP
71 unsigned int num_processors;
72 unsigned disabled_cpus __cpuinitdata;
73 #endif
74
75 /* Make it easy to share the UP and SMP code: */
76 #ifndef CONFIG_X86_SMP
77 physid_mask_t phys_cpu_present_map;
78 #endif
79
80 #ifndef CONFIG_SMP
81 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
82 #endif
83
84 /*
85 * Intel MP BIOS table parsing routines:
86 */
87
88
89 /*
90 * Checksum an MP configuration block.
91 */
92
93 static int __init mpf_checksum(unsigned char *mp, int len)
94 {
95 int sum = 0;
96
97 while (len--)
98 sum += *mp++;
99
100 return sum & 0xFF;
101 }
102
103 #ifdef CONFIG_X86_NUMAQ
104 /*
105 * Have to match translation table entries to main table entries by counter
106 * hence the mpc_record variable .... can't see a less disgusting way of
107 * doing this ....
108 */
109
110 static int mpc_record;
111 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
112 #endif
113
114 static void __cpuinit generic_processor_info(int apicid, int version)
115 {
116 int cpu;
117 cpumask_t tmp_map;
118 physid_mask_t phys_cpu;
119
120 /*
121 * Validate version
122 */
123 if (version == 0x0) {
124 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
125 "fixing up to 0x10. (tell your hw vendor)\n",
126 version);
127 version = 0x10;
128 }
129 apic_version[apicid] = version;
130
131 phys_cpu = apicid_to_cpu_present(apicid);
132 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
133
134 if (num_processors >= NR_CPUS) {
135 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
136 " Processor ignored.\n", NR_CPUS);
137 return;
138 }
139
140 if (num_processors >= maxcpus) {
141 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
142 " Processor ignored.\n", maxcpus);
143 return;
144 }
145
146 num_processors++;
147 cpus_complement(tmp_map, cpu_present_map);
148 cpu = first_cpu(tmp_map);
149
150 if (apicid == boot_cpu_physical_apicid)
151 /*
152 * x86_bios_cpu_apicid is required to have processors listed
153 * in same order as logical cpu numbers. Hence the first
154 * entry is BSP, and so on.
155 */
156 cpu = 0;
157
158 /*
159 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
160 * but we need to work other dependencies like SMP_SUSPEND etc
161 * before this can be done without some confusion.
162 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
163 * - Ashok Raj <ashok.raj@intel.com>
164 */
165 if (num_processors > 8) {
166 switch (boot_cpu_data.x86_vendor) {
167 case X86_VENDOR_INTEL:
168 if (!APIC_XAPIC(version)) {
169 def_to_bigsmp = 0;
170 break;
171 }
172 /* If P4 and above fall through */
173 case X86_VENDOR_AMD:
174 def_to_bigsmp = 1;
175 }
176 }
177 #ifdef CONFIG_SMP
178 /* are we being called early in kernel startup? */
179 if (x86_cpu_to_apicid_early_ptr) {
180 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
181 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
182
183 cpu_to_apicid[cpu] = apicid;
184 bios_cpu_apicid[cpu] = apicid;
185 } else {
186 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
187 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
188 }
189 #endif
190 cpu_set(cpu, cpu_possible_map);
191 cpu_set(cpu, cpu_present_map);
192 }
193
194 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
195 {
196 int apicid;
197
198 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
199 #ifdef CONFIG_X86_SMP
200 disabled_cpus++;
201 #endif
202 return;
203 }
204
205 #ifdef CONFIG_X86_NUMAQ
206 apicid = mpc_apic_id(m, translation_table[mpc_record]);
207 #else
208 Dprintk("Processor #%d %u:%u APIC version %d\n",
209 m->mpc_apicid,
210 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
211 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
212 m->mpc_apicver);
213 apicid = m->mpc_apicid;
214 #endif
215
216 if (m->mpc_featureflag&(1<<0))
217 Dprintk(" Floating point unit present.\n");
218 if (m->mpc_featureflag&(1<<7))
219 Dprintk(" Machine Exception supported.\n");
220 if (m->mpc_featureflag&(1<<8))
221 Dprintk(" 64 bit compare & exchange supported.\n");
222 if (m->mpc_featureflag&(1<<9))
223 Dprintk(" Internal APIC present.\n");
224 if (m->mpc_featureflag&(1<<11))
225 Dprintk(" SEP present.\n");
226 if (m->mpc_featureflag&(1<<12))
227 Dprintk(" MTRR present.\n");
228 if (m->mpc_featureflag&(1<<13))
229 Dprintk(" PGE present.\n");
230 if (m->mpc_featureflag&(1<<14))
231 Dprintk(" MCA present.\n");
232 if (m->mpc_featureflag&(1<<15))
233 Dprintk(" CMOV present.\n");
234 if (m->mpc_featureflag&(1<<16))
235 Dprintk(" PAT present.\n");
236 if (m->mpc_featureflag&(1<<17))
237 Dprintk(" PSE present.\n");
238 if (m->mpc_featureflag&(1<<18))
239 Dprintk(" PSN present.\n");
240 if (m->mpc_featureflag&(1<<19))
241 Dprintk(" Cache Line Flush Instruction present.\n");
242 /* 20 Reserved */
243 if (m->mpc_featureflag&(1<<21))
244 Dprintk(" Debug Trace and EMON Store present.\n");
245 if (m->mpc_featureflag&(1<<22))
246 Dprintk(" ACPI Thermal Throttle Registers present.\n");
247 if (m->mpc_featureflag&(1<<23))
248 Dprintk(" MMX present.\n");
249 if (m->mpc_featureflag&(1<<24))
250 Dprintk(" FXSR present.\n");
251 if (m->mpc_featureflag&(1<<25))
252 Dprintk(" XMM present.\n");
253 if (m->mpc_featureflag&(1<<26))
254 Dprintk(" Willamette New Instructions present.\n");
255 if (m->mpc_featureflag&(1<<27))
256 Dprintk(" Self Snoop present.\n");
257 if (m->mpc_featureflag&(1<<28))
258 Dprintk(" HT present.\n");
259 if (m->mpc_featureflag&(1<<29))
260 Dprintk(" Thermal Monitor present.\n");
261 /* 30, 31 Reserved */
262
263
264 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
265 Dprintk(" Bootup CPU\n");
266 boot_cpu_physical_apicid = m->mpc_apicid;
267 }
268
269 generic_processor_info(apicid, m->mpc_apicver);
270 }
271
272 static void __init MP_bus_info (struct mpc_config_bus *m)
273 {
274 char str[7];
275
276 memcpy(str, m->mpc_bustype, 6);
277 str[6] = 0;
278
279 #ifdef CONFIG_X86_NUMAQ
280 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
281 #else
282 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
283 #endif
284
285 #if MAX_MP_BUSSES < 256
286 if (m->mpc_busid >= MAX_MP_BUSSES) {
287 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
288 " is too large, max. supported is %d\n",
289 m->mpc_busid, str, MAX_MP_BUSSES - 1);
290 return;
291 }
292 #endif
293
294 set_bit(m->mpc_busid, mp_bus_not_pci);
295 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
296 #ifdef CONFIG_X86_NUMAQ
297 mpc_oem_pci_bus(m, translation_table[mpc_record]);
298 #endif
299 clear_bit(m->mpc_busid, mp_bus_not_pci);
300 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
301 mp_current_pci_id++;
302 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
303 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
304 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
305 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
306 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
307 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
308 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
309 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
310 } else {
311 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
312 #endif
313 }
314 }
315
316 static int bad_ioapic(unsigned long address)
317 {
318 if (nr_ioapics >= MAX_IO_APICS) {
319 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
320 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
321 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
322 }
323 if (!address) {
324 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
325 " found in table, skipping!\n");
326 return 1;
327 }
328 return 0;
329 }
330
331 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
332 {
333 if (!(m->mpc_flags & MPC_APIC_USABLE))
334 return;
335
336 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
337 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
338
339 if (bad_ioapic(m->mpc_apicaddr))
340 return;
341
342 mp_ioapics[nr_ioapics] = *m;
343 nr_ioapics++;
344 }
345
346 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
347 {
348 mp_irqs [mp_irq_entries] = *m;
349 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
350 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
351 m->mpc_irqtype, m->mpc_irqflag & 3,
352 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
353 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
354 if (++mp_irq_entries == MAX_IRQ_SOURCES)
355 panic("Max # of irq sources exceeded!!\n");
356 }
357
358 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
359 {
360 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
361 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
362 m->mpc_irqtype, m->mpc_irqflag & 3,
363 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
364 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
365 }
366
367 #ifdef CONFIG_X86_NUMAQ
368 static void __init MP_translation_info (struct mpc_config_translation *m)
369 {
370 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
371
372 if (mpc_record >= MAX_MPC_ENTRY)
373 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
374 else
375 translation_table[mpc_record] = m; /* stash this for later */
376 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
377 node_set_online(m->trans_quad);
378 }
379
380 /*
381 * Read/parse the MPC oem tables
382 */
383
384 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
385 unsigned short oemsize)
386 {
387 int count = sizeof (*oemtable); /* the header size */
388 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
389
390 mpc_record = 0;
391 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
392 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
393 {
394 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
395 oemtable->oem_signature[0],
396 oemtable->oem_signature[1],
397 oemtable->oem_signature[2],
398 oemtable->oem_signature[3]);
399 return;
400 }
401 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
402 {
403 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
404 return;
405 }
406 while (count < oemtable->oem_length) {
407 switch (*oemptr) {
408 case MP_TRANSLATION:
409 {
410 struct mpc_config_translation *m=
411 (struct mpc_config_translation *)oemptr;
412 MP_translation_info(m);
413 oemptr += sizeof(*m);
414 count += sizeof(*m);
415 ++mpc_record;
416 break;
417 }
418 default:
419 {
420 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
421 return;
422 }
423 }
424 }
425 }
426
427 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
428 char *productid)
429 {
430 if (strncmp(oem, "IBM NUMA", 8))
431 printk("Warning! May not be a NUMA-Q system!\n");
432 if (mpc->mpc_oemptr)
433 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
434 mpc->mpc_oemsize);
435 }
436 #endif /* CONFIG_X86_NUMAQ */
437
438 /*
439 * Read/parse the MPC
440 */
441
442 static int __init smp_read_mpc(struct mp_config_table *mpc)
443 {
444 char str[16];
445 char oem[10];
446 int count=sizeof(*mpc);
447 unsigned char *mpt=((unsigned char *)mpc)+count;
448
449 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
450 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
451 *(u32 *)mpc->mpc_signature);
452 return 0;
453 }
454 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
455 printk(KERN_ERR "SMP mptable: checksum error!\n");
456 return 0;
457 }
458 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
459 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
460 mpc->mpc_spec);
461 return 0;
462 }
463 if (!mpc->mpc_lapic) {
464 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
465 return 0;
466 }
467 memcpy(oem,mpc->mpc_oem,8);
468 oem[8]=0;
469 printk(KERN_INFO "OEM ID: %s ",oem);
470
471 memcpy(str,mpc->mpc_productid,12);
472 str[12]=0;
473 printk("Product ID: %s ",str);
474
475 mps_oem_check(mpc, oem, str);
476
477 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
478
479 /*
480 * Save the local APIC address (it might be non-default) -- but only
481 * if we're not using ACPI.
482 */
483 if (!acpi_lapic)
484 mp_lapic_addr = mpc->mpc_lapic;
485
486 /*
487 * Now process the configuration blocks.
488 */
489 #ifdef CONFIG_X86_NUMAQ
490 mpc_record = 0;
491 #endif
492 while (count < mpc->mpc_length) {
493 switch(*mpt) {
494 case MP_PROCESSOR:
495 {
496 struct mpc_config_processor *m=
497 (struct mpc_config_processor *)mpt;
498 /* ACPI may have already provided this data */
499 if (!acpi_lapic)
500 MP_processor_info(m);
501 mpt += sizeof(*m);
502 count += sizeof(*m);
503 break;
504 }
505 case MP_BUS:
506 {
507 struct mpc_config_bus *m=
508 (struct mpc_config_bus *)mpt;
509 MP_bus_info(m);
510 mpt += sizeof(*m);
511 count += sizeof(*m);
512 break;
513 }
514 case MP_IOAPIC:
515 {
516 struct mpc_config_ioapic *m=
517 (struct mpc_config_ioapic *)mpt;
518 MP_ioapic_info(m);
519 mpt+=sizeof(*m);
520 count+=sizeof(*m);
521 break;
522 }
523 case MP_INTSRC:
524 {
525 struct mpc_config_intsrc *m=
526 (struct mpc_config_intsrc *)mpt;
527
528 MP_intsrc_info(m);
529 mpt+=sizeof(*m);
530 count+=sizeof(*m);
531 break;
532 }
533 case MP_LINTSRC:
534 {
535 struct mpc_config_lintsrc *m=
536 (struct mpc_config_lintsrc *)mpt;
537 MP_lintsrc_info(m);
538 mpt+=sizeof(*m);
539 count+=sizeof(*m);
540 break;
541 }
542 default:
543 {
544 count = mpc->mpc_length;
545 break;
546 }
547 }
548 #ifdef CONFIG_X86_NUMAQ
549 ++mpc_record;
550 #endif
551 }
552 setup_apic_routing();
553 if (!num_processors)
554 printk(KERN_ERR "SMP mptable: no processors registered!\n");
555 return num_processors;
556 }
557
558 static int __init ELCR_trigger(unsigned int irq)
559 {
560 unsigned int port;
561
562 port = 0x4d0 + (irq >> 3);
563 return (inb(port) >> (irq & 7)) & 1;
564 }
565
566 static void __init construct_default_ioirq_mptable(int mpc_default_type)
567 {
568 struct mpc_config_intsrc intsrc;
569 int i;
570 int ELCR_fallback = 0;
571
572 intsrc.mpc_type = MP_INTSRC;
573 intsrc.mpc_irqflag = 0; /* conforming */
574 intsrc.mpc_srcbus = 0;
575 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
576
577 intsrc.mpc_irqtype = mp_INT;
578
579 /*
580 * If true, we have an ISA/PCI system with no IRQ entries
581 * in the MP table. To prevent the PCI interrupts from being set up
582 * incorrectly, we try to use the ELCR. The sanity check to see if
583 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
584 * never be level sensitive, so we simply see if the ELCR agrees.
585 * If it does, we assume it's valid.
586 */
587 if (mpc_default_type == 5) {
588 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
589
590 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
591 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
592 else {
593 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
594 ELCR_fallback = 1;
595 }
596 }
597
598 for (i = 0; i < 16; i++) {
599 switch (mpc_default_type) {
600 case 2:
601 if (i == 0 || i == 13)
602 continue; /* IRQ0 & IRQ13 not connected */
603 /* fall through */
604 default:
605 if (i == 2)
606 continue; /* IRQ2 is never connected */
607 }
608
609 if (ELCR_fallback) {
610 /*
611 * If the ELCR indicates a level-sensitive interrupt, we
612 * copy that information over to the MP table in the
613 * irqflag field (level sensitive, active high polarity).
614 */
615 if (ELCR_trigger(i))
616 intsrc.mpc_irqflag = 13;
617 else
618 intsrc.mpc_irqflag = 0;
619 }
620
621 intsrc.mpc_srcbusirq = i;
622 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
623 MP_intsrc_info(&intsrc);
624 }
625
626 intsrc.mpc_irqtype = mp_ExtINT;
627 intsrc.mpc_srcbusirq = 0;
628 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
629 MP_intsrc_info(&intsrc);
630 }
631
632 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
633 {
634 struct mpc_config_processor processor;
635 struct mpc_config_bus bus;
636 struct mpc_config_ioapic ioapic;
637 struct mpc_config_lintsrc lintsrc;
638 int linttypes[2] = { mp_ExtINT, mp_NMI };
639 int i;
640
641 /*
642 * local APIC has default address
643 */
644 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
645
646 /*
647 * 2 CPUs, numbered 0 & 1.
648 */
649 processor.mpc_type = MP_PROCESSOR;
650 /* Either an integrated APIC or a discrete 82489DX. */
651 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
652 processor.mpc_cpuflag = CPU_ENABLED;
653 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
654 (boot_cpu_data.x86_model << 4) |
655 boot_cpu_data.x86_mask;
656 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
657 processor.mpc_reserved[0] = 0;
658 processor.mpc_reserved[1] = 0;
659 for (i = 0; i < 2; i++) {
660 processor.mpc_apicid = i;
661 MP_processor_info(&processor);
662 }
663
664 bus.mpc_type = MP_BUS;
665 bus.mpc_busid = 0;
666 switch (mpc_default_type) {
667 default:
668 printk("???\n");
669 printk(KERN_ERR "Unknown standard configuration %d\n",
670 mpc_default_type);
671 /* fall through */
672 case 1:
673 case 5:
674 memcpy(bus.mpc_bustype, "ISA ", 6);
675 break;
676 case 2:
677 case 6:
678 case 3:
679 memcpy(bus.mpc_bustype, "EISA ", 6);
680 break;
681 case 4:
682 case 7:
683 memcpy(bus.mpc_bustype, "MCA ", 6);
684 }
685 MP_bus_info(&bus);
686 if (mpc_default_type > 4) {
687 bus.mpc_busid = 1;
688 memcpy(bus.mpc_bustype, "PCI ", 6);
689 MP_bus_info(&bus);
690 }
691
692 ioapic.mpc_type = MP_IOAPIC;
693 ioapic.mpc_apicid = 2;
694 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
695 ioapic.mpc_flags = MPC_APIC_USABLE;
696 ioapic.mpc_apicaddr = 0xFEC00000;
697 MP_ioapic_info(&ioapic);
698
699 /*
700 * We set up most of the low 16 IO-APIC pins according to MPS rules.
701 */
702 construct_default_ioirq_mptable(mpc_default_type);
703
704 lintsrc.mpc_type = MP_LINTSRC;
705 lintsrc.mpc_irqflag = 0; /* conforming */
706 lintsrc.mpc_srcbusid = 0;
707 lintsrc.mpc_srcbusirq = 0;
708 lintsrc.mpc_destapic = MP_APIC_ALL;
709 for (i = 0; i < 2; i++) {
710 lintsrc.mpc_irqtype = linttypes[i];
711 lintsrc.mpc_destapiclint = i;
712 MP_lintsrc_info(&lintsrc);
713 }
714 }
715
716 static struct intel_mp_floating *mpf_found;
717
718 /*
719 * Scan the memory blocks for an SMP configuration block.
720 */
721 void __init get_smp_config (void)
722 {
723 struct intel_mp_floating *mpf = mpf_found;
724
725 /*
726 * ACPI supports both logical (e.g. Hyper-Threading) and physical
727 * processors, where MPS only supports physical.
728 */
729 if (acpi_lapic && acpi_ioapic) {
730 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
731 return;
732 }
733 else if (acpi_lapic)
734 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
735
736 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
737 if (mpf->mpf_feature2 & (1<<7)) {
738 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
739 pic_mode = 1;
740 } else {
741 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
742 pic_mode = 0;
743 }
744
745 /*
746 * Now see if we need to read further.
747 */
748 if (mpf->mpf_feature1 != 0) {
749
750 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
751 construct_default_ISA_mptable(mpf->mpf_feature1);
752
753 } else if (mpf->mpf_physptr) {
754
755 /*
756 * Read the physical hardware table. Anything here will
757 * override the defaults.
758 */
759 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
760 smp_found_config = 0;
761 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
762 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
763 return;
764 }
765 /*
766 * If there are no explicit MP IRQ entries, then we are
767 * broken. We set up most of the low 16 IO-APIC pins to
768 * ISA defaults and hope it will work.
769 */
770 if (!mp_irq_entries) {
771 struct mpc_config_bus bus;
772
773 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
774
775 bus.mpc_type = MP_BUS;
776 bus.mpc_busid = 0;
777 memcpy(bus.mpc_bustype, "ISA ", 6);
778 MP_bus_info(&bus);
779
780 construct_default_ioirq_mptable(0);
781 }
782
783 } else
784 BUG();
785
786 printk(KERN_INFO "Processors: %d\n", num_processors);
787 /*
788 * Only use the first configuration found.
789 */
790 }
791
792 static int __init smp_scan_config (unsigned long base, unsigned long length)
793 {
794 unsigned long *bp = phys_to_virt(base);
795 struct intel_mp_floating *mpf;
796
797 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
798 if (sizeof(*mpf) != 16)
799 printk("Error: MPF size\n");
800
801 while (length > 0) {
802 mpf = (struct intel_mp_floating *)bp;
803 if ((*bp == SMP_MAGIC_IDENT) &&
804 (mpf->mpf_length == 1) &&
805 !mpf_checksum((unsigned char *)bp, 16) &&
806 ((mpf->mpf_specification == 1)
807 || (mpf->mpf_specification == 4)) ) {
808
809 smp_found_config = 1;
810 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
811 mpf, virt_to_phys(mpf));
812 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
813 BOOTMEM_DEFAULT);
814 if (mpf->mpf_physptr) {
815 /*
816 * We cannot access to MPC table to compute
817 * table size yet, as only few megabytes from
818 * the bottom is mapped now.
819 * PC-9800's MPC table places on the very last
820 * of physical memory; so that simply reserving
821 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
822 * in reserve_bootmem.
823 */
824 unsigned long size = PAGE_SIZE;
825 unsigned long end = max_low_pfn * PAGE_SIZE;
826 if (mpf->mpf_physptr + size > end)
827 size = end - mpf->mpf_physptr;
828 reserve_bootmem(mpf->mpf_physptr, size,
829 BOOTMEM_DEFAULT);
830 }
831
832 mpf_found = mpf;
833 return 1;
834 }
835 bp += 4;
836 length -= 16;
837 }
838 return 0;
839 }
840
841 void __init find_smp_config (void)
842 {
843 unsigned int address;
844
845 /*
846 * FIXME: Linux assumes you have 640K of base ram..
847 * this continues the error...
848 *
849 * 1) Scan the bottom 1K for a signature
850 * 2) Scan the top 1K of base RAM
851 * 3) Scan the 64K of bios
852 */
853 if (smp_scan_config(0x0,0x400) ||
854 smp_scan_config(639*0x400,0x400) ||
855 smp_scan_config(0xF0000,0x10000))
856 return;
857 /*
858 * If it is an SMP machine we should know now, unless the
859 * configuration is in an EISA/MCA bus machine with an
860 * extended bios data area.
861 *
862 * there is a real-mode segmented pointer pointing to the
863 * 4K EBDA area at 0x40E, calculate and scan it here.
864 *
865 * NOTE! There are Linux loaders that will corrupt the EBDA
866 * area, and as such this kind of SMP config may be less
867 * trustworthy, simply because the SMP table may have been
868 * stomped on during early boot. These loaders are buggy and
869 * should be fixed.
870 *
871 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
872 */
873
874 address = get_bios_ebda();
875 if (address)
876 smp_scan_config(address, 0x400);
877 }
878
879 /* --------------------------------------------------------------------------
880 ACPI-based MP Configuration
881 -------------------------------------------------------------------------- */
882
883 #ifdef CONFIG_ACPI
884
885 void __init mp_register_lapic_address(u64 address)
886 {
887 mp_lapic_addr = (unsigned long) address;
888
889 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
890
891 if (boot_cpu_physical_apicid == -1U)
892 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
893
894 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
895 }
896
897 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
898 {
899 if (MAX_APICS - id <= 0) {
900 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
901 id, MAX_APICS);
902 return;
903 }
904
905 if (!enabled) {
906 #ifdef CONFIG_X86_SMP
907 ++disabled_cpus;
908 #endif
909 return;
910 }
911
912 generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR)));
913 }
914
915 #ifdef CONFIG_X86_IO_APIC
916
917 #define MP_ISA_BUS 0
918 #define MP_MAX_IOAPIC_PIN 127
919
920 static struct mp_ioapic_routing {
921 int apic_id;
922 int gsi_base;
923 int gsi_end;
924 u32 pin_programmed[4];
925 } mp_ioapic_routing[MAX_IO_APICS];
926
927 static int mp_find_ioapic (int gsi)
928 {
929 int i = 0;
930
931 /* Find the IOAPIC that manages this GSI. */
932 for (i = 0; i < nr_ioapics; i++) {
933 if ((gsi >= mp_ioapic_routing[i].gsi_base)
934 && (gsi <= mp_ioapic_routing[i].gsi_end))
935 return i;
936 }
937
938 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
939
940 return -1;
941 }
942
943 static u8 uniq_ioapic_id(u8 id)
944 {
945 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
946 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
947 return io_apic_get_unique_id(nr_ioapics, id);
948 else
949 return id;
950 }
951
952 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
953 {
954 int idx = 0;
955
956 if (bad_ioapic(address))
957 return;
958
959 idx = nr_ioapics;
960
961 mp_ioapics[idx].mpc_type = MP_IOAPIC;
962 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
963 mp_ioapics[idx].mpc_apicaddr = address;
964
965 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
966 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
967 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
968
969 /*
970 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
971 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
972 */
973 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
974 mp_ioapic_routing[idx].gsi_base = gsi_base;
975 mp_ioapic_routing[idx].gsi_end = gsi_base +
976 io_apic_get_redir_entries(idx);
977
978 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
979 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
980 mp_ioapics[idx].mpc_apicver,
981 mp_ioapics[idx].mpc_apicaddr,
982 mp_ioapic_routing[idx].gsi_base,
983 mp_ioapic_routing[idx].gsi_end);
984
985 nr_ioapics++;
986 }
987
988 void __init
989 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
990 {
991 struct mpc_config_intsrc intsrc;
992 int ioapic = -1;
993 int pin = -1;
994
995 /*
996 * Convert 'gsi' to 'ioapic.pin'.
997 */
998 ioapic = mp_find_ioapic(gsi);
999 if (ioapic < 0)
1000 return;
1001 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1002
1003 /*
1004 * TBD: This check is for faulty timer entries, where the override
1005 * erroneously sets the trigger to level, resulting in a HUGE
1006 * increase of timer interrupts!
1007 */
1008 if ((bus_irq == 0) && (trigger == 3))
1009 trigger = 1;
1010
1011 intsrc.mpc_type = MP_INTSRC;
1012 intsrc.mpc_irqtype = mp_INT;
1013 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1014 intsrc.mpc_srcbus = MP_ISA_BUS;
1015 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1016 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1017 intsrc.mpc_dstirq = pin; /* INTIN# */
1018
1019 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1020 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1021 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1022 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1023
1024 mp_irqs[mp_irq_entries] = intsrc;
1025 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1026 panic("Max # of irq sources exceeded!\n");
1027 }
1028
1029 int es7000_plat;
1030
1031 void __init mp_config_acpi_legacy_irqs (void)
1032 {
1033 struct mpc_config_intsrc intsrc;
1034 int i = 0;
1035 int ioapic = -1;
1036
1037 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1038 /*
1039 * Fabricate the legacy ISA bus (bus #31).
1040 */
1041 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1042 #endif
1043 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1044 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1045
1046 /*
1047 * Older generations of ES7000 have no legacy identity mappings
1048 */
1049 if (es7000_plat == 1)
1050 return;
1051
1052 /*
1053 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1054 */
1055 ioapic = mp_find_ioapic(0);
1056 if (ioapic < 0)
1057 return;
1058
1059 intsrc.mpc_type = MP_INTSRC;
1060 intsrc.mpc_irqflag = 0; /* Conforming */
1061 intsrc.mpc_srcbus = MP_ISA_BUS;
1062 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1063
1064 /*
1065 * Use the default configuration for the IRQs 0-15. Unless
1066 * overridden by (MADT) interrupt source override entries.
1067 */
1068 for (i = 0; i < 16; i++) {
1069 int idx;
1070
1071 for (idx = 0; idx < mp_irq_entries; idx++) {
1072 struct mpc_config_intsrc *irq = mp_irqs + idx;
1073
1074 /* Do we already have a mapping for this ISA IRQ? */
1075 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1076 break;
1077
1078 /* Do we already have a mapping for this IOAPIC pin */
1079 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1080 (irq->mpc_dstirq == i))
1081 break;
1082 }
1083
1084 if (idx != mp_irq_entries) {
1085 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1086 continue; /* IRQ already used */
1087 }
1088
1089 intsrc.mpc_irqtype = mp_INT;
1090 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1091 intsrc.mpc_dstirq = i;
1092
1093 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1094 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1095 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1096 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1097 intsrc.mpc_dstirq);
1098
1099 mp_irqs[mp_irq_entries] = intsrc;
1100 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1101 panic("Max # of irq sources exceeded!\n");
1102 }
1103 }
1104
1105 #define MAX_GSI_NUM 4096
1106 #define IRQ_COMPRESSION_START 64
1107
1108 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1109 {
1110 int ioapic = -1;
1111 int ioapic_pin = 0;
1112 int idx, bit = 0;
1113 static int pci_irq = IRQ_COMPRESSION_START;
1114 /*
1115 * Mapping between Global System Interrupts, which
1116 * represent all possible interrupts, and IRQs
1117 * assigned to actual devices.
1118 */
1119 static int gsi_to_irq[MAX_GSI_NUM];
1120
1121 /* Don't set up the ACPI SCI because it's already set up */
1122 if (acpi_gbl_FADT.sci_interrupt == gsi)
1123 return gsi;
1124
1125 ioapic = mp_find_ioapic(gsi);
1126 if (ioapic < 0) {
1127 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1128 return gsi;
1129 }
1130
1131 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1132
1133 if (ioapic_renumber_irq)
1134 gsi = ioapic_renumber_irq(ioapic, gsi);
1135
1136 /*
1137 * Avoid pin reprogramming. PRTs typically include entries
1138 * with redundant pin->gsi mappings (but unique PCI devices);
1139 * we only program the IOAPIC on the first.
1140 */
1141 bit = ioapic_pin % 32;
1142 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1143 if (idx > 3) {
1144 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1145 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1146 ioapic_pin);
1147 return gsi;
1148 }
1149 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1150 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1151 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1152 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1153 }
1154
1155 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1156
1157 /*
1158 * For GSI >= 64, use IRQ compression
1159 */
1160 if ((gsi >= IRQ_COMPRESSION_START)
1161 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1162 /*
1163 * For PCI devices assign IRQs in order, avoiding gaps
1164 * due to unused I/O APIC pins.
1165 */
1166 int irq = gsi;
1167 if (gsi < MAX_GSI_NUM) {
1168 /*
1169 * Retain the VIA chipset work-around (gsi > 15), but
1170 * avoid a problem where the 8254 timer (IRQ0) is setup
1171 * via an override (so it's not on pin 0 of the ioapic),
1172 * and at the same time, the pin 0 interrupt is a PCI
1173 * type. The gsi > 15 test could cause these two pins
1174 * to be shared as IRQ0, and they are not shareable.
1175 * So test for this condition, and if necessary, avoid
1176 * the pin collision.
1177 */
1178 gsi = pci_irq++;
1179 /*
1180 * Don't assign IRQ used by ACPI SCI
1181 */
1182 if (gsi == acpi_gbl_FADT.sci_interrupt)
1183 gsi = pci_irq++;
1184 gsi_to_irq[irq] = gsi;
1185 } else {
1186 printk(KERN_ERR "GSI %u is too high\n", gsi);
1187 return gsi;
1188 }
1189 }
1190
1191 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1192 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1193 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1194 return gsi;
1195 }
1196
1197 #endif /* CONFIG_X86_IO_APIC */
1198 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
This page took 0.056282 seconds and 6 git commands to generate.