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x86: fill cpu to apicid and present map in mpparse, fix
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30
31 #include <mach_apic.h>
32 #include <mach_apicdef.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 #endif
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
51
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57
58 /* MP IRQ source entries */
59 int mp_irq_entries;
60
61 int nr_ioapics;
62
63 int pic_mode;
64 unsigned long mp_lapic_addr;
65
66 unsigned int def_to_bigsmp = 0;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
72
73 unsigned disabled_cpus __cpuinitdata;
74
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
77
78 #ifndef CONFIG_SMP
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
80 #endif
81
82 /*
83 * Intel MP BIOS table parsing routines:
84 */
85
86
87 /*
88 * Checksum an MP configuration block.
89 */
90
91 static int __init mpf_checksum(unsigned char *mp, int len)
92 {
93 int sum = 0;
94
95 while (len--)
96 sum += *mp++;
97
98 return sum & 0xFF;
99 }
100
101 /*
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
104 * doing this ....
105 */
106
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
109
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
111 {
112 int ver, apicid, cpu;
113 cpumask_t tmp_map;
114 physid_mask_t phys_cpu;
115
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
117 disabled_cpus++;
118 return;
119 }
120
121 apicid = mpc_apic_id(m, translation_table[mpc_record]);
122
123 if (m->mpc_featureflag&(1<<0))
124 Dprintk(" Floating point unit present.\n");
125 if (m->mpc_featureflag&(1<<7))
126 Dprintk(" Machine Exception supported.\n");
127 if (m->mpc_featureflag&(1<<8))
128 Dprintk(" 64 bit compare & exchange supported.\n");
129 if (m->mpc_featureflag&(1<<9))
130 Dprintk(" Internal APIC present.\n");
131 if (m->mpc_featureflag&(1<<11))
132 Dprintk(" SEP present.\n");
133 if (m->mpc_featureflag&(1<<12))
134 Dprintk(" MTRR present.\n");
135 if (m->mpc_featureflag&(1<<13))
136 Dprintk(" PGE present.\n");
137 if (m->mpc_featureflag&(1<<14))
138 Dprintk(" MCA present.\n");
139 if (m->mpc_featureflag&(1<<15))
140 Dprintk(" CMOV present.\n");
141 if (m->mpc_featureflag&(1<<16))
142 Dprintk(" PAT present.\n");
143 if (m->mpc_featureflag&(1<<17))
144 Dprintk(" PSE present.\n");
145 if (m->mpc_featureflag&(1<<18))
146 Dprintk(" PSN present.\n");
147 if (m->mpc_featureflag&(1<<19))
148 Dprintk(" Cache Line Flush Instruction present.\n");
149 /* 20 Reserved */
150 if (m->mpc_featureflag&(1<<21))
151 Dprintk(" Debug Trace and EMON Store present.\n");
152 if (m->mpc_featureflag&(1<<22))
153 Dprintk(" ACPI Thermal Throttle Registers present.\n");
154 if (m->mpc_featureflag&(1<<23))
155 Dprintk(" MMX present.\n");
156 if (m->mpc_featureflag&(1<<24))
157 Dprintk(" FXSR present.\n");
158 if (m->mpc_featureflag&(1<<25))
159 Dprintk(" XMM present.\n");
160 if (m->mpc_featureflag&(1<<26))
161 Dprintk(" Willamette New Instructions present.\n");
162 if (m->mpc_featureflag&(1<<27))
163 Dprintk(" Self Snoop present.\n");
164 if (m->mpc_featureflag&(1<<28))
165 Dprintk(" HT present.\n");
166 if (m->mpc_featureflag&(1<<29))
167 Dprintk(" Thermal Monitor present.\n");
168 /* 30, 31 Reserved */
169
170
171 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
172 Dprintk(" Bootup CPU\n");
173 boot_cpu_physical_apicid = m->mpc_apicid;
174 }
175
176 ver = m->mpc_apicver;
177
178 /*
179 * Validate version
180 */
181 if (ver == 0x0) {
182 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
183 "fixing up to 0x10. (tell your hw vendor)\n",
184 m->mpc_apicid);
185 ver = 0x10;
186 }
187 apic_version[m->mpc_apicid] = ver;
188
189 phys_cpu = apicid_to_cpu_present(apicid);
190 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
191
192 if (num_processors >= NR_CPUS) {
193 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
194 " Processor ignored.\n", NR_CPUS);
195 return;
196 }
197
198 if (num_processors >= maxcpus) {
199 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
200 " Processor ignored.\n", maxcpus);
201 return;
202 }
203
204 cpu_set(num_processors, cpu_possible_map);
205 num_processors++;
206 cpus_complement(tmp_map, cpu_present_map);
207 cpu = first_cpu(tmp_map);
208
209 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
210 /*
211 * x86_bios_cpu_apicid is required to have processors listed
212 * in same order as logical cpu numbers. Hence the first
213 * entry is BSP, and so on.
214 */
215 cpu = 0;
216
217 /*
218 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
219 * but we need to work other dependencies like SMP_SUSPEND etc
220 * before this can be done without some confusion.
221 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
222 * - Ashok Raj <ashok.raj@intel.com>
223 */
224 if (num_processors > 8) {
225 switch (boot_cpu_data.x86_vendor) {
226 case X86_VENDOR_INTEL:
227 if (!APIC_XAPIC(ver)) {
228 def_to_bigsmp = 0;
229 break;
230 }
231 /* If P4 and above fall through */
232 case X86_VENDOR_AMD:
233 def_to_bigsmp = 1;
234 }
235 }
236 #ifdef CONFIG_SMP
237 /* are we being called early in kernel startup? */
238 if (x86_cpu_to_apicid_early_ptr) {
239 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
240 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
241
242 cpu_to_apicid[cpu] = m->mpc_apicid;
243 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
244 } else {
245 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
246 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
247 }
248 #endif
249 cpu_set(cpu, cpu_present_map);
250 }
251
252 static void __init MP_bus_info (struct mpc_config_bus *m)
253 {
254 char str[7];
255
256 memcpy(str, m->mpc_bustype, 6);
257 str[6] = 0;
258
259 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
260
261 #if MAX_MP_BUSSES < 256
262 if (m->mpc_busid >= MAX_MP_BUSSES) {
263 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
264 " is too large, max. supported is %d\n",
265 m->mpc_busid, str, MAX_MP_BUSSES - 1);
266 return;
267 }
268 #endif
269
270 set_bit(m->mpc_busid, mp_bus_not_pci);
271 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
272 mpc_oem_pci_bus(m, translation_table[mpc_record]);
273 clear_bit(m->mpc_busid, mp_bus_not_pci);
274 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
275 mp_current_pci_id++;
276 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
277 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
278 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
279 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
280 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
281 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
282 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
283 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
284 } else {
285 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
286 #endif
287 }
288 }
289
290 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
291 {
292 if (!(m->mpc_flags & MPC_APIC_USABLE))
293 return;
294
295 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
296 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
297 if (nr_ioapics >= MAX_IO_APICS) {
298 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
299 MAX_IO_APICS, nr_ioapics);
300 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
301 }
302 if (!m->mpc_apicaddr) {
303 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
304 " found in MP table, skipping!\n");
305 return;
306 }
307 mp_ioapics[nr_ioapics] = *m;
308 nr_ioapics++;
309 }
310
311 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
312 {
313 mp_irqs [mp_irq_entries] = *m;
314 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
315 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
316 m->mpc_irqtype, m->mpc_irqflag & 3,
317 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
318 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
319 if (++mp_irq_entries == MAX_IRQ_SOURCES)
320 panic("Max # of irq sources exceeded!!\n");
321 }
322
323 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
324 {
325 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
326 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
327 m->mpc_irqtype, m->mpc_irqflag & 3,
328 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
329 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
330 }
331
332 #ifdef CONFIG_X86_NUMAQ
333 static void __init MP_translation_info (struct mpc_config_translation *m)
334 {
335 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
336
337 if (mpc_record >= MAX_MPC_ENTRY)
338 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
339 else
340 translation_table[mpc_record] = m; /* stash this for later */
341 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
342 node_set_online(m->trans_quad);
343 }
344
345 /*
346 * Read/parse the MPC oem tables
347 */
348
349 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
350 unsigned short oemsize)
351 {
352 int count = sizeof (*oemtable); /* the header size */
353 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
354
355 mpc_record = 0;
356 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
357 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
358 {
359 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
360 oemtable->oem_signature[0],
361 oemtable->oem_signature[1],
362 oemtable->oem_signature[2],
363 oemtable->oem_signature[3]);
364 return;
365 }
366 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
367 {
368 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
369 return;
370 }
371 while (count < oemtable->oem_length) {
372 switch (*oemptr) {
373 case MP_TRANSLATION:
374 {
375 struct mpc_config_translation *m=
376 (struct mpc_config_translation *)oemptr;
377 MP_translation_info(m);
378 oemptr += sizeof(*m);
379 count += sizeof(*m);
380 ++mpc_record;
381 break;
382 }
383 default:
384 {
385 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
386 return;
387 }
388 }
389 }
390 }
391
392 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
393 char *productid)
394 {
395 if (strncmp(oem, "IBM NUMA", 8))
396 printk("Warning! May not be a NUMA-Q system!\n");
397 if (mpc->mpc_oemptr)
398 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
399 mpc->mpc_oemsize);
400 }
401 #endif /* CONFIG_X86_NUMAQ */
402
403 /*
404 * Read/parse the MPC
405 */
406
407 static int __init smp_read_mpc(struct mp_config_table *mpc)
408 {
409 char str[16];
410 char oem[10];
411 int count=sizeof(*mpc);
412 unsigned char *mpt=((unsigned char *)mpc)+count;
413
414 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
415 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
416 *(u32 *)mpc->mpc_signature);
417 return 0;
418 }
419 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
420 printk(KERN_ERR "SMP mptable: checksum error!\n");
421 return 0;
422 }
423 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
424 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
425 mpc->mpc_spec);
426 return 0;
427 }
428 if (!mpc->mpc_lapic) {
429 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
430 return 0;
431 }
432 memcpy(oem,mpc->mpc_oem,8);
433 oem[8]=0;
434 printk(KERN_INFO "OEM ID: %s ",oem);
435
436 memcpy(str,mpc->mpc_productid,12);
437 str[12]=0;
438 printk("Product ID: %s ",str);
439
440 mps_oem_check(mpc, oem, str);
441
442 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
443
444 /*
445 * Save the local APIC address (it might be non-default) -- but only
446 * if we're not using ACPI.
447 */
448 if (!acpi_lapic)
449 mp_lapic_addr = mpc->mpc_lapic;
450
451 /*
452 * Now process the configuration blocks.
453 */
454 mpc_record = 0;
455 while (count < mpc->mpc_length) {
456 switch(*mpt) {
457 case MP_PROCESSOR:
458 {
459 struct mpc_config_processor *m=
460 (struct mpc_config_processor *)mpt;
461 /* ACPI may have already provided this data */
462 if (!acpi_lapic)
463 MP_processor_info(m);
464 mpt += sizeof(*m);
465 count += sizeof(*m);
466 break;
467 }
468 case MP_BUS:
469 {
470 struct mpc_config_bus *m=
471 (struct mpc_config_bus *)mpt;
472 MP_bus_info(m);
473 mpt += sizeof(*m);
474 count += sizeof(*m);
475 break;
476 }
477 case MP_IOAPIC:
478 {
479 struct mpc_config_ioapic *m=
480 (struct mpc_config_ioapic *)mpt;
481 MP_ioapic_info(m);
482 mpt+=sizeof(*m);
483 count+=sizeof(*m);
484 break;
485 }
486 case MP_INTSRC:
487 {
488 struct mpc_config_intsrc *m=
489 (struct mpc_config_intsrc *)mpt;
490
491 MP_intsrc_info(m);
492 mpt+=sizeof(*m);
493 count+=sizeof(*m);
494 break;
495 }
496 case MP_LINTSRC:
497 {
498 struct mpc_config_lintsrc *m=
499 (struct mpc_config_lintsrc *)mpt;
500 MP_lintsrc_info(m);
501 mpt+=sizeof(*m);
502 count+=sizeof(*m);
503 break;
504 }
505 default:
506 {
507 count = mpc->mpc_length;
508 break;
509 }
510 }
511 ++mpc_record;
512 }
513 setup_apic_routing();
514 if (!num_processors)
515 printk(KERN_ERR "SMP mptable: no processors registered!\n");
516 return num_processors;
517 }
518
519 static int __init ELCR_trigger(unsigned int irq)
520 {
521 unsigned int port;
522
523 port = 0x4d0 + (irq >> 3);
524 return (inb(port) >> (irq & 7)) & 1;
525 }
526
527 static void __init construct_default_ioirq_mptable(int mpc_default_type)
528 {
529 struct mpc_config_intsrc intsrc;
530 int i;
531 int ELCR_fallback = 0;
532
533 intsrc.mpc_type = MP_INTSRC;
534 intsrc.mpc_irqflag = 0; /* conforming */
535 intsrc.mpc_srcbus = 0;
536 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
537
538 intsrc.mpc_irqtype = mp_INT;
539
540 /*
541 * If true, we have an ISA/PCI system with no IRQ entries
542 * in the MP table. To prevent the PCI interrupts from being set up
543 * incorrectly, we try to use the ELCR. The sanity check to see if
544 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
545 * never be level sensitive, so we simply see if the ELCR agrees.
546 * If it does, we assume it's valid.
547 */
548 if (mpc_default_type == 5) {
549 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
550
551 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
552 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
553 else {
554 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
555 ELCR_fallback = 1;
556 }
557 }
558
559 for (i = 0; i < 16; i++) {
560 switch (mpc_default_type) {
561 case 2:
562 if (i == 0 || i == 13)
563 continue; /* IRQ0 & IRQ13 not connected */
564 /* fall through */
565 default:
566 if (i == 2)
567 continue; /* IRQ2 is never connected */
568 }
569
570 if (ELCR_fallback) {
571 /*
572 * If the ELCR indicates a level-sensitive interrupt, we
573 * copy that information over to the MP table in the
574 * irqflag field (level sensitive, active high polarity).
575 */
576 if (ELCR_trigger(i))
577 intsrc.mpc_irqflag = 13;
578 else
579 intsrc.mpc_irqflag = 0;
580 }
581
582 intsrc.mpc_srcbusirq = i;
583 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
584 MP_intsrc_info(&intsrc);
585 }
586
587 intsrc.mpc_irqtype = mp_ExtINT;
588 intsrc.mpc_srcbusirq = 0;
589 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
590 MP_intsrc_info(&intsrc);
591 }
592
593 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
594 {
595 struct mpc_config_processor processor;
596 struct mpc_config_bus bus;
597 struct mpc_config_ioapic ioapic;
598 struct mpc_config_lintsrc lintsrc;
599 int linttypes[2] = { mp_ExtINT, mp_NMI };
600 int i;
601
602 /*
603 * local APIC has default address
604 */
605 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
606
607 /*
608 * 2 CPUs, numbered 0 & 1.
609 */
610 processor.mpc_type = MP_PROCESSOR;
611 /* Either an integrated APIC or a discrete 82489DX. */
612 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
613 processor.mpc_cpuflag = CPU_ENABLED;
614 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
615 (boot_cpu_data.x86_model << 4) |
616 boot_cpu_data.x86_mask;
617 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
618 processor.mpc_reserved[0] = 0;
619 processor.mpc_reserved[1] = 0;
620 for (i = 0; i < 2; i++) {
621 processor.mpc_apicid = i;
622 MP_processor_info(&processor);
623 }
624
625 bus.mpc_type = MP_BUS;
626 bus.mpc_busid = 0;
627 switch (mpc_default_type) {
628 default:
629 printk("???\n");
630 printk(KERN_ERR "Unknown standard configuration %d\n",
631 mpc_default_type);
632 /* fall through */
633 case 1:
634 case 5:
635 memcpy(bus.mpc_bustype, "ISA ", 6);
636 break;
637 case 2:
638 case 6:
639 case 3:
640 memcpy(bus.mpc_bustype, "EISA ", 6);
641 break;
642 case 4:
643 case 7:
644 memcpy(bus.mpc_bustype, "MCA ", 6);
645 }
646 MP_bus_info(&bus);
647 if (mpc_default_type > 4) {
648 bus.mpc_busid = 1;
649 memcpy(bus.mpc_bustype, "PCI ", 6);
650 MP_bus_info(&bus);
651 }
652
653 ioapic.mpc_type = MP_IOAPIC;
654 ioapic.mpc_apicid = 2;
655 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
656 ioapic.mpc_flags = MPC_APIC_USABLE;
657 ioapic.mpc_apicaddr = 0xFEC00000;
658 MP_ioapic_info(&ioapic);
659
660 /*
661 * We set up most of the low 16 IO-APIC pins according to MPS rules.
662 */
663 construct_default_ioirq_mptable(mpc_default_type);
664
665 lintsrc.mpc_type = MP_LINTSRC;
666 lintsrc.mpc_irqflag = 0; /* conforming */
667 lintsrc.mpc_srcbusid = 0;
668 lintsrc.mpc_srcbusirq = 0;
669 lintsrc.mpc_destapic = MP_APIC_ALL;
670 for (i = 0; i < 2; i++) {
671 lintsrc.mpc_irqtype = linttypes[i];
672 lintsrc.mpc_destapiclint = i;
673 MP_lintsrc_info(&lintsrc);
674 }
675 }
676
677 static struct intel_mp_floating *mpf_found;
678
679 /*
680 * Scan the memory blocks for an SMP configuration block.
681 */
682 void __init get_smp_config (void)
683 {
684 struct intel_mp_floating *mpf = mpf_found;
685
686 /*
687 * ACPI supports both logical (e.g. Hyper-Threading) and physical
688 * processors, where MPS only supports physical.
689 */
690 if (acpi_lapic && acpi_ioapic) {
691 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
692 return;
693 }
694 else if (acpi_lapic)
695 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
696
697 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
698 if (mpf->mpf_feature2 & (1<<7)) {
699 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
700 pic_mode = 1;
701 } else {
702 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
703 pic_mode = 0;
704 }
705
706 /*
707 * Now see if we need to read further.
708 */
709 if (mpf->mpf_feature1 != 0) {
710
711 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
712 construct_default_ISA_mptable(mpf->mpf_feature1);
713
714 } else if (mpf->mpf_physptr) {
715
716 /*
717 * Read the physical hardware table. Anything here will
718 * override the defaults.
719 */
720 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
721 smp_found_config = 0;
722 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
723 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
724 return;
725 }
726 /*
727 * If there are no explicit MP IRQ entries, then we are
728 * broken. We set up most of the low 16 IO-APIC pins to
729 * ISA defaults and hope it will work.
730 */
731 if (!mp_irq_entries) {
732 struct mpc_config_bus bus;
733
734 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
735
736 bus.mpc_type = MP_BUS;
737 bus.mpc_busid = 0;
738 memcpy(bus.mpc_bustype, "ISA ", 6);
739 MP_bus_info(&bus);
740
741 construct_default_ioirq_mptable(0);
742 }
743
744 } else
745 BUG();
746
747 printk(KERN_INFO "Processors: %d\n", num_processors);
748 /*
749 * Only use the first configuration found.
750 */
751 }
752
753 static int __init smp_scan_config (unsigned long base, unsigned long length)
754 {
755 unsigned long *bp = phys_to_virt(base);
756 struct intel_mp_floating *mpf;
757
758 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
759 if (sizeof(*mpf) != 16)
760 printk("Error: MPF size\n");
761
762 while (length > 0) {
763 mpf = (struct intel_mp_floating *)bp;
764 if ((*bp == SMP_MAGIC_IDENT) &&
765 (mpf->mpf_length == 1) &&
766 !mpf_checksum((unsigned char *)bp, 16) &&
767 ((mpf->mpf_specification == 1)
768 || (mpf->mpf_specification == 4)) ) {
769
770 smp_found_config = 1;
771 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
772 mpf, virt_to_phys(mpf));
773 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
774 BOOTMEM_DEFAULT);
775 if (mpf->mpf_physptr) {
776 /*
777 * We cannot access to MPC table to compute
778 * table size yet, as only few megabytes from
779 * the bottom is mapped now.
780 * PC-9800's MPC table places on the very last
781 * of physical memory; so that simply reserving
782 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
783 * in reserve_bootmem.
784 */
785 unsigned long size = PAGE_SIZE;
786 unsigned long end = max_low_pfn * PAGE_SIZE;
787 if (mpf->mpf_physptr + size > end)
788 size = end - mpf->mpf_physptr;
789 reserve_bootmem(mpf->mpf_physptr, size,
790 BOOTMEM_DEFAULT);
791 }
792
793 mpf_found = mpf;
794 return 1;
795 }
796 bp += 4;
797 length -= 16;
798 }
799 return 0;
800 }
801
802 void __init find_smp_config (void)
803 {
804 unsigned int address;
805
806 /*
807 * FIXME: Linux assumes you have 640K of base ram..
808 * this continues the error...
809 *
810 * 1) Scan the bottom 1K for a signature
811 * 2) Scan the top 1K of base RAM
812 * 3) Scan the 64K of bios
813 */
814 if (smp_scan_config(0x0,0x400) ||
815 smp_scan_config(639*0x400,0x400) ||
816 smp_scan_config(0xF0000,0x10000))
817 return;
818 /*
819 * If it is an SMP machine we should know now, unless the
820 * configuration is in an EISA/MCA bus machine with an
821 * extended bios data area.
822 *
823 * there is a real-mode segmented pointer pointing to the
824 * 4K EBDA area at 0x40E, calculate and scan it here.
825 *
826 * NOTE! There are Linux loaders that will corrupt the EBDA
827 * area, and as such this kind of SMP config may be less
828 * trustworthy, simply because the SMP table may have been
829 * stomped on during early boot. These loaders are buggy and
830 * should be fixed.
831 *
832 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
833 */
834
835 address = get_bios_ebda();
836 if (address)
837 smp_scan_config(address, 0x400);
838 }
839
840 int es7000_plat;
841
842 /* --------------------------------------------------------------------------
843 ACPI-based MP Configuration
844 -------------------------------------------------------------------------- */
845
846 #ifdef CONFIG_ACPI
847
848 void __init mp_register_lapic_address(u64 address)
849 {
850 mp_lapic_addr = (unsigned long) address;
851
852 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
853
854 if (boot_cpu_physical_apicid == -1U)
855 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
856
857 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
858 }
859
860 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
861 {
862 struct mpc_config_processor processor;
863 int boot_cpu = 0;
864
865 if (MAX_APICS - id <= 0) {
866 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
867 id, MAX_APICS);
868 return;
869 }
870
871 if (id == boot_cpu_physical_apicid)
872 boot_cpu = 1;
873
874 processor.mpc_type = MP_PROCESSOR;
875 processor.mpc_apicid = id;
876 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
877 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
878 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
879 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
880 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
881 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
882 processor.mpc_reserved[0] = 0;
883 processor.mpc_reserved[1] = 0;
884
885 MP_processor_info(&processor);
886 }
887
888 #ifdef CONFIG_X86_IO_APIC
889
890 #define MP_ISA_BUS 0
891 #define MP_MAX_IOAPIC_PIN 127
892
893 static struct mp_ioapic_routing {
894 int apic_id;
895 int gsi_base;
896 int gsi_end;
897 u32 pin_programmed[4];
898 } mp_ioapic_routing[MAX_IO_APICS];
899
900 static int mp_find_ioapic (int gsi)
901 {
902 int i = 0;
903
904 /* Find the IOAPIC that manages this GSI. */
905 for (i = 0; i < nr_ioapics; i++) {
906 if ((gsi >= mp_ioapic_routing[i].gsi_base)
907 && (gsi <= mp_ioapic_routing[i].gsi_end))
908 return i;
909 }
910
911 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
912
913 return -1;
914 }
915
916 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
917 {
918 int idx = 0;
919 int tmpid;
920
921 if (nr_ioapics >= MAX_IO_APICS) {
922 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
923 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
924 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
925 }
926 if (!address) {
927 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
928 " found in MADT table, skipping!\n");
929 return;
930 }
931
932 idx = nr_ioapics++;
933
934 mp_ioapics[idx].mpc_type = MP_IOAPIC;
935 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
936 mp_ioapics[idx].mpc_apicaddr = address;
937
938 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
939 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
940 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
941 tmpid = io_apic_get_unique_id(idx, id);
942 else
943 tmpid = id;
944 if (tmpid == -1) {
945 nr_ioapics--;
946 return;
947 }
948 mp_ioapics[idx].mpc_apicid = tmpid;
949 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
950
951 /*
952 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
953 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
954 */
955 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
956 mp_ioapic_routing[idx].gsi_base = gsi_base;
957 mp_ioapic_routing[idx].gsi_end = gsi_base +
958 io_apic_get_redir_entries(idx);
959
960 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
961 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
962 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
963 mp_ioapic_routing[idx].gsi_base,
964 mp_ioapic_routing[idx].gsi_end);
965 }
966
967 void __init
968 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
969 {
970 struct mpc_config_intsrc intsrc;
971 int ioapic = -1;
972 int pin = -1;
973
974 /*
975 * Convert 'gsi' to 'ioapic.pin'.
976 */
977 ioapic = mp_find_ioapic(gsi);
978 if (ioapic < 0)
979 return;
980 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
981
982 /*
983 * TBD: This check is for faulty timer entries, where the override
984 * erroneously sets the trigger to level, resulting in a HUGE
985 * increase of timer interrupts!
986 */
987 if ((bus_irq == 0) && (trigger == 3))
988 trigger = 1;
989
990 intsrc.mpc_type = MP_INTSRC;
991 intsrc.mpc_irqtype = mp_INT;
992 intsrc.mpc_irqflag = (trigger << 2) | polarity;
993 intsrc.mpc_srcbus = MP_ISA_BUS;
994 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
995 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
996 intsrc.mpc_dstirq = pin; /* INTIN# */
997
998 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
999 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1000 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1001 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1002
1003 mp_irqs[mp_irq_entries] = intsrc;
1004 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1005 panic("Max # of irq sources exceeded!\n");
1006 }
1007
1008 void __init mp_config_acpi_legacy_irqs (void)
1009 {
1010 struct mpc_config_intsrc intsrc;
1011 int i = 0;
1012 int ioapic = -1;
1013
1014 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1015 /*
1016 * Fabricate the legacy ISA bus (bus #31).
1017 */
1018 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1019 #endif
1020 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1021 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1022
1023 /*
1024 * Older generations of ES7000 have no legacy identity mappings
1025 */
1026 if (es7000_plat == 1)
1027 return;
1028
1029 /*
1030 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1031 */
1032 ioapic = mp_find_ioapic(0);
1033 if (ioapic < 0)
1034 return;
1035
1036 intsrc.mpc_type = MP_INTSRC;
1037 intsrc.mpc_irqflag = 0; /* Conforming */
1038 intsrc.mpc_srcbus = MP_ISA_BUS;
1039 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1040
1041 /*
1042 * Use the default configuration for the IRQs 0-15. Unless
1043 * overridden by (MADT) interrupt source override entries.
1044 */
1045 for (i = 0; i < 16; i++) {
1046 int idx;
1047
1048 for (idx = 0; idx < mp_irq_entries; idx++) {
1049 struct mpc_config_intsrc *irq = mp_irqs + idx;
1050
1051 /* Do we already have a mapping for this ISA IRQ? */
1052 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1053 break;
1054
1055 /* Do we already have a mapping for this IOAPIC pin */
1056 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1057 (irq->mpc_dstirq == i))
1058 break;
1059 }
1060
1061 if (idx != mp_irq_entries) {
1062 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1063 continue; /* IRQ already used */
1064 }
1065
1066 intsrc.mpc_irqtype = mp_INT;
1067 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1068 intsrc.mpc_dstirq = i;
1069
1070 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1071 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1072 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1073 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1074 intsrc.mpc_dstirq);
1075
1076 mp_irqs[mp_irq_entries] = intsrc;
1077 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1078 panic("Max # of irq sources exceeded!\n");
1079 }
1080 }
1081
1082 #define MAX_GSI_NUM 4096
1083 #define IRQ_COMPRESSION_START 64
1084
1085 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1086 {
1087 int ioapic = -1;
1088 int ioapic_pin = 0;
1089 int idx, bit = 0;
1090 static int pci_irq = IRQ_COMPRESSION_START;
1091 /*
1092 * Mapping between Global System Interrupts, which
1093 * represent all possible interrupts, and IRQs
1094 * assigned to actual devices.
1095 */
1096 static int gsi_to_irq[MAX_GSI_NUM];
1097
1098 /* Don't set up the ACPI SCI because it's already set up */
1099 if (acpi_gbl_FADT.sci_interrupt == gsi)
1100 return gsi;
1101
1102 ioapic = mp_find_ioapic(gsi);
1103 if (ioapic < 0) {
1104 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1105 return gsi;
1106 }
1107
1108 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1109
1110 if (ioapic_renumber_irq)
1111 gsi = ioapic_renumber_irq(ioapic, gsi);
1112
1113 /*
1114 * Avoid pin reprogramming. PRTs typically include entries
1115 * with redundant pin->gsi mappings (but unique PCI devices);
1116 * we only program the IOAPIC on the first.
1117 */
1118 bit = ioapic_pin % 32;
1119 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1120 if (idx > 3) {
1121 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1122 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1123 ioapic_pin);
1124 return gsi;
1125 }
1126 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1127 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1128 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1129 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1130 }
1131
1132 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1133
1134 /*
1135 * For GSI >= 64, use IRQ compression
1136 */
1137 if ((gsi >= IRQ_COMPRESSION_START)
1138 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1139 /*
1140 * For PCI devices assign IRQs in order, avoiding gaps
1141 * due to unused I/O APIC pins.
1142 */
1143 int irq = gsi;
1144 if (gsi < MAX_GSI_NUM) {
1145 /*
1146 * Retain the VIA chipset work-around (gsi > 15), but
1147 * avoid a problem where the 8254 timer (IRQ0) is setup
1148 * via an override (so it's not on pin 0 of the ioapic),
1149 * and at the same time, the pin 0 interrupt is a PCI
1150 * type. The gsi > 15 test could cause these two pins
1151 * to be shared as IRQ0, and they are not shareable.
1152 * So test for this condition, and if necessary, avoid
1153 * the pin collision.
1154 */
1155 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1156 gsi = pci_irq++;
1157 /*
1158 * Don't assign IRQ used by ACPI SCI
1159 */
1160 if (gsi == acpi_gbl_FADT.sci_interrupt)
1161 gsi = pci_irq++;
1162 gsi_to_irq[irq] = gsi;
1163 } else {
1164 printk(KERN_ERR "GSI %u is too high\n", gsi);
1165 return gsi;
1166 }
1167 }
1168
1169 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1170 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1171 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1172 return gsi;
1173 }
1174
1175 #endif /* CONFIG_X86_IO_APIC */
1176 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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