2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
40 * Various Linux-internal data structures created from the
43 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
44 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
46 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
47 int mp_bus_id_to_pci_bus
[MAX_MP_BUSSES
] = {[0 ... MAX_MP_BUSSES
- 1] = -1 };
48 static int mp_current_pci_id
;
53 * Intel MP BIOS table parsing routines:
57 * Checksum an MP configuration block.
60 static int __init
mpf_checksum(unsigned char *mp
, int len
)
70 #ifdef CONFIG_X86_NUMAQ
72 * Have to match translation table entries to main table entries by counter
73 * hence the mpc_record variable .... can't see a less disgusting way of
77 static int mpc_record
;
78 static struct mpc_config_translation
*translation_table
[MAX_MPC_ENTRY
]
82 static void __cpuinit
MP_processor_info(struct mpc_config_processor
*m
)
85 char *bootup_cpu
= "";
87 if (!(m
->mpc_cpuflag
& CPU_ENABLED
)) {
91 #ifdef CONFIG_X86_NUMAQ
92 apicid
= mpc_apic_id(m
, translation_table
[mpc_record
]);
94 apicid
= m
->mpc_apicid
;
96 if (m
->mpc_cpuflag
& CPU_BOOTPROCESSOR
) {
97 bootup_cpu
= " (Bootup-CPU)";
98 boot_cpu_physical_apicid
= m
->mpc_apicid
;
101 printk(KERN_INFO
"Processor #%d%s\n", m
->mpc_apicid
, bootup_cpu
);
102 generic_processor_info(apicid
, m
->mpc_apicver
);
105 static void __init
MP_bus_info(struct mpc_config_bus
*m
)
109 memcpy(str
, m
->mpc_bustype
, 6);
112 #ifdef CONFIG_X86_NUMAQ
113 mpc_oem_bus_info(m
, str
, translation_table
[mpc_record
]);
115 Dprintk("Bus #%d is %s\n", m
->mpc_busid
, str
);
118 #if MAX_MP_BUSSES < 256
119 if (m
->mpc_busid
>= MAX_MP_BUSSES
) {
120 printk(KERN_WARNING
"MP table busid value (%d) for bustype %s "
121 " is too large, max. supported is %d\n",
122 m
->mpc_busid
, str
, MAX_MP_BUSSES
- 1);
127 set_bit(m
->mpc_busid
, mp_bus_not_pci
);
128 if (strncmp(str
, BUSTYPE_PCI
, sizeof(BUSTYPE_PCI
) - 1) == 0) {
129 #ifdef CONFIG_X86_NUMAQ
130 mpc_oem_pci_bus(m
, translation_table
[mpc_record
]);
132 clear_bit(m
->mpc_busid
, mp_bus_not_pci
);
133 mp_bus_id_to_pci_bus
[m
->mpc_busid
] = mp_current_pci_id
;
135 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
136 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_PCI
;
137 } else if (strncmp(str
, BUSTYPE_ISA
, sizeof(BUSTYPE_ISA
) - 1) == 0) {
138 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_ISA
;
139 } else if (strncmp(str
, BUSTYPE_EISA
, sizeof(BUSTYPE_EISA
) - 1) == 0) {
140 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_EISA
;
141 } else if (strncmp(str
, BUSTYPE_MCA
, sizeof(BUSTYPE_MCA
) - 1) == 0) {
142 mp_bus_id_to_type
[m
->mpc_busid
] = MP_BUS_MCA
;
144 printk(KERN_WARNING
"Unknown bustype %s - ignoring\n", str
);
149 #ifdef CONFIG_X86_IO_APIC
151 static int bad_ioapic(unsigned long address
)
153 if (nr_ioapics
>= MAX_IO_APICS
) {
154 printk(KERN_ERR
"ERROR: Max # of I/O APICs (%d) exceeded "
155 "(found %d)\n", MAX_IO_APICS
, nr_ioapics
);
156 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
159 printk(KERN_ERR
"WARNING: Bogus (zero) I/O APIC address"
160 " found in table, skipping!\n");
166 static void __init
MP_ioapic_info(struct mpc_config_ioapic
*m
)
168 if (!(m
->mpc_flags
& MPC_APIC_USABLE
))
171 printk(KERN_INFO
"I/O APIC #%d Version %d at 0x%X.\n",
172 m
->mpc_apicid
, m
->mpc_apicver
, m
->mpc_apicaddr
);
174 if (bad_ioapic(m
->mpc_apicaddr
))
177 mp_ioapics
[nr_ioapics
] = *m
;
181 static void __init
MP_intsrc_info(struct mpc_config_intsrc
*m
)
183 mp_irqs
[mp_irq_entries
] = *m
;
184 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
185 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
186 m
->mpc_irqtype
, m
->mpc_irqflag
& 3,
187 (m
->mpc_irqflag
>> 2) & 3, m
->mpc_srcbus
,
188 m
->mpc_srcbusirq
, m
->mpc_dstapic
, m
->mpc_dstirq
);
189 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
190 panic("Max # of irq sources exceeded!!\n");
195 static void __init
MP_lintsrc_info(struct mpc_config_lintsrc
*m
)
197 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
198 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
199 m
->mpc_irqtype
, m
->mpc_irqflag
& 3,
200 (m
->mpc_irqflag
>> 2) & 3, m
->mpc_srcbusid
,
201 m
->mpc_srcbusirq
, m
->mpc_destapic
, m
->mpc_destapiclint
);
204 #ifdef CONFIG_X86_NUMAQ
205 static void __init
MP_translation_info(struct mpc_config_translation
*m
)
208 "Translation: record %d, type %d, quad %d, global %d, local %d\n",
209 mpc_record
, m
->trans_type
, m
->trans_quad
, m
->trans_global
,
212 if (mpc_record
>= MAX_MPC_ENTRY
)
213 printk(KERN_ERR
"MAX_MPC_ENTRY exceeded!\n");
215 translation_table
[mpc_record
] = m
; /* stash this for later */
216 if (m
->trans_quad
< MAX_NUMNODES
&& !node_online(m
->trans_quad
))
217 node_set_online(m
->trans_quad
);
221 * Read/parse the MPC oem tables
224 static void __init
smp_read_mpc_oem(struct mp_config_oemtable
*oemtable
,
225 unsigned short oemsize
)
227 int count
= sizeof(*oemtable
); /* the header size */
228 unsigned char *oemptr
= ((unsigned char *)oemtable
) + count
;
231 printk(KERN_INFO
"Found an OEM MPC table at %8p - parsing it ... \n",
233 if (memcmp(oemtable
->oem_signature
, MPC_OEM_SIGNATURE
, 4)) {
235 "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
236 oemtable
->oem_signature
[0], oemtable
->oem_signature
[1],
237 oemtable
->oem_signature
[2], oemtable
->oem_signature
[3]);
240 if (mpf_checksum((unsigned char *)oemtable
, oemtable
->oem_length
)) {
241 printk(KERN_WARNING
"SMP oem mptable: checksum error!\n");
244 while (count
< oemtable
->oem_length
) {
248 struct mpc_config_translation
*m
=
249 (struct mpc_config_translation
*)oemptr
;
250 MP_translation_info(m
);
251 oemptr
+= sizeof(*m
);
259 "Unrecognised OEM table entry type! - %d\n",
267 static inline void mps_oem_check(struct mp_config_table
*mpc
, char *oem
,
270 if (strncmp(oem
, "IBM NUMA", 8))
271 printk("Warning! May not be a NUMA-Q system!\n");
273 smp_read_mpc_oem((struct mp_config_oemtable
*)mpc
->mpc_oemptr
,
276 #endif /* CONFIG_X86_NUMAQ */
282 static int __init
smp_read_mpc(struct mp_config_table
*mpc
, unsigned early
)
286 int count
= sizeof(*mpc
);
287 unsigned char *mpt
= ((unsigned char *)mpc
) + count
;
289 if (memcmp(mpc
->mpc_signature
, MPC_SIGNATURE
, 4)) {
290 printk(KERN_ERR
"SMP mptable: bad signature [0x%x]!\n",
291 *(u32
*) mpc
->mpc_signature
);
294 if (mpf_checksum((unsigned char *)mpc
, mpc
->mpc_length
)) {
295 printk(KERN_ERR
"SMP mptable: checksum error!\n");
298 if (mpc
->mpc_spec
!= 0x01 && mpc
->mpc_spec
!= 0x04) {
299 printk(KERN_ERR
"SMP mptable: bad table version (%d)!!\n",
303 if (!mpc
->mpc_lapic
) {
304 printk(KERN_ERR
"SMP mptable: null local APIC address!\n");
307 memcpy(oem
, mpc
->mpc_oem
, 8);
309 printk(KERN_INFO
"OEM ID: %s ", oem
);
311 memcpy(str
, mpc
->mpc_productid
, 12);
313 printk("Product ID: %s ", str
);
315 mps_oem_check(mpc
, oem
, str
);
317 printk("APIC at: 0x%X\n", mpc
->mpc_lapic
);
320 * Save the local APIC address (it might be non-default) -- but only
321 * if we're not using ACPI.
324 mp_lapic_addr
= mpc
->mpc_lapic
;
330 * Now process the configuration blocks.
332 #ifdef CONFIG_X86_NUMAQ
335 while (count
< mpc
->mpc_length
) {
339 struct mpc_config_processor
*m
=
340 (struct mpc_config_processor
*)mpt
;
341 /* ACPI may have already provided this data */
343 MP_processor_info(m
);
350 struct mpc_config_bus
*m
=
351 (struct mpc_config_bus
*)mpt
;
359 #ifdef CONFIG_X86_IO_APIC
360 struct mpc_config_ioapic
*m
=
361 (struct mpc_config_ioapic
*)mpt
;
364 mpt
+= sizeof(struct mpc_config_ioapic
);
365 count
+= sizeof(struct mpc_config_ioapic
);
370 #ifdef CONFIG_X86_IO_APIC
371 struct mpc_config_intsrc
*m
=
372 (struct mpc_config_intsrc
*)mpt
;
376 mpt
+= sizeof(struct mpc_config_intsrc
);
377 count
+= sizeof(struct mpc_config_intsrc
);
382 struct mpc_config_lintsrc
*m
=
383 (struct mpc_config_lintsrc
*)mpt
;
391 count
= mpc
->mpc_length
;
395 #ifdef CONFIG_X86_NUMAQ
399 setup_apic_routing();
401 printk(KERN_ERR
"SMP mptable: no processors registered!\n");
402 return num_processors
;
405 #ifdef CONFIG_X86_IO_APIC
407 static int __init
ELCR_trigger(unsigned int irq
)
411 port
= 0x4d0 + (irq
>> 3);
412 return (inb(port
) >> (irq
& 7)) & 1;
415 static void __init
construct_default_ioirq_mptable(int mpc_default_type
)
417 struct mpc_config_intsrc intsrc
;
419 int ELCR_fallback
= 0;
421 intsrc
.mpc_type
= MP_INTSRC
;
422 intsrc
.mpc_irqflag
= 0; /* conforming */
423 intsrc
.mpc_srcbus
= 0;
424 intsrc
.mpc_dstapic
= mp_ioapics
[0].mpc_apicid
;
426 intsrc
.mpc_irqtype
= mp_INT
;
429 * If true, we have an ISA/PCI system with no IRQ entries
430 * in the MP table. To prevent the PCI interrupts from being set up
431 * incorrectly, we try to use the ELCR. The sanity check to see if
432 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
433 * never be level sensitive, so we simply see if the ELCR agrees.
434 * If it does, we assume it's valid.
436 if (mpc_default_type
== 5) {
438 "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
440 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2)
443 "ELCR contains invalid data... not using ELCR\n");
446 "Using ELCR to identify PCI interrupts\n");
451 for (i
= 0; i
< 16; i
++) {
452 switch (mpc_default_type
) {
454 if (i
== 0 || i
== 13)
455 continue; /* IRQ0 & IRQ13 not connected */
459 continue; /* IRQ2 is never connected */
464 * If the ELCR indicates a level-sensitive interrupt, we
465 * copy that information over to the MP table in the
466 * irqflag field (level sensitive, active high polarity).
469 intsrc
.mpc_irqflag
= 13;
471 intsrc
.mpc_irqflag
= 0;
474 intsrc
.mpc_srcbusirq
= i
;
475 intsrc
.mpc_dstirq
= i
? i
: 2; /* IRQ0 to INTIN2 */
476 MP_intsrc_info(&intsrc
);
479 intsrc
.mpc_irqtype
= mp_ExtINT
;
480 intsrc
.mpc_srcbusirq
= 0;
481 intsrc
.mpc_dstirq
= 0; /* 8259A to INTIN0 */
482 MP_intsrc_info(&intsrc
);
487 static inline void __init
construct_default_ISA_mptable(int mpc_default_type
)
489 struct mpc_config_processor processor
;
490 struct mpc_config_bus bus
;
491 #ifdef CONFIG_X86_IO_APIC
492 struct mpc_config_ioapic ioapic
;
494 struct mpc_config_lintsrc lintsrc
;
495 int linttypes
[2] = { mp_ExtINT
, mp_NMI
};
499 * local APIC has default address
501 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
504 * 2 CPUs, numbered 0 & 1.
506 processor
.mpc_type
= MP_PROCESSOR
;
507 /* Either an integrated APIC or a discrete 82489DX. */
508 processor
.mpc_apicver
= mpc_default_type
> 4 ? 0x10 : 0x01;
509 processor
.mpc_cpuflag
= CPU_ENABLED
;
510 processor
.mpc_cpufeature
= (boot_cpu_data
.x86
<< 8) |
511 (boot_cpu_data
.x86_model
<< 4) | boot_cpu_data
.x86_mask
;
512 processor
.mpc_featureflag
= boot_cpu_data
.x86_capability
[0];
513 processor
.mpc_reserved
[0] = 0;
514 processor
.mpc_reserved
[1] = 0;
515 for (i
= 0; i
< 2; i
++) {
516 processor
.mpc_apicid
= i
;
517 MP_processor_info(&processor
);
520 bus
.mpc_type
= MP_BUS
;
522 switch (mpc_default_type
) {
525 printk(KERN_ERR
"Unknown standard configuration %d\n",
530 memcpy(bus
.mpc_bustype
, "ISA ", 6);
535 memcpy(bus
.mpc_bustype
, "EISA ", 6);
539 memcpy(bus
.mpc_bustype
, "MCA ", 6);
542 if (mpc_default_type
> 4) {
544 memcpy(bus
.mpc_bustype
, "PCI ", 6);
548 #ifdef CONFIG_X86_IO_APIC
549 ioapic
.mpc_type
= MP_IOAPIC
;
550 ioapic
.mpc_apicid
= 2;
551 ioapic
.mpc_apicver
= mpc_default_type
> 4 ? 0x10 : 0x01;
552 ioapic
.mpc_flags
= MPC_APIC_USABLE
;
553 ioapic
.mpc_apicaddr
= 0xFEC00000;
554 MP_ioapic_info(&ioapic
);
557 * We set up most of the low 16 IO-APIC pins according to MPS rules.
559 construct_default_ioirq_mptable(mpc_default_type
);
561 lintsrc
.mpc_type
= MP_LINTSRC
;
562 lintsrc
.mpc_irqflag
= 0; /* conforming */
563 lintsrc
.mpc_srcbusid
= 0;
564 lintsrc
.mpc_srcbusirq
= 0;
565 lintsrc
.mpc_destapic
= MP_APIC_ALL
;
566 for (i
= 0; i
< 2; i
++) {
567 lintsrc
.mpc_irqtype
= linttypes
[i
];
568 lintsrc
.mpc_destapiclint
= i
;
569 MP_lintsrc_info(&lintsrc
);
573 static struct intel_mp_floating
*mpf_found
;
576 * Scan the memory blocks for an SMP configuration block.
578 static void __init
__get_smp_config(unsigned early
)
580 struct intel_mp_floating
*mpf
= mpf_found
;
582 if (acpi_lapic
&& early
)
586 * ACPI supports both logical (e.g. Hyper-Threading) and physical
587 * processors, where MPS only supports physical.
589 if (acpi_lapic
&& acpi_ioapic
) {
591 "Using ACPI (MADT) for SMP configuration information\n");
593 } else if (acpi_lapic
)
595 "Using ACPI for processor (LAPIC) configuration information\n");
597 printk(KERN_INFO
"Intel MultiProcessor Specification v1.%d\n",
598 mpf
->mpf_specification
);
599 if (mpf
->mpf_feature2
& (1 << 7)) {
600 printk(KERN_INFO
" IMCR and PIC compatibility mode.\n");
603 printk(KERN_INFO
" Virtual Wire compatibility mode.\n");
608 * Now see if we need to read further.
610 if (mpf
->mpf_feature1
!= 0) {
613 * local APIC has default address
615 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
619 printk(KERN_INFO
"Default MP configuration #%d\n",
621 construct_default_ISA_mptable(mpf
->mpf_feature1
);
623 } else if (mpf
->mpf_physptr
) {
626 * Read the physical hardware table. Anything here will
627 * override the defaults.
629 if (!smp_read_mpc(phys_to_virt(mpf
->mpf_physptr
), early
)) {
630 smp_found_config
= 0;
632 "BIOS bug, MP table errors detected!...\n");
634 "... disabling SMP support. (tell your hw vendor)\n");
640 #ifdef CONFIG_X86_IO_APIC
642 * If there are no explicit MP IRQ entries, then we are
643 * broken. We set up most of the low 16 IO-APIC pins to
644 * ISA defaults and hope it will work.
646 if (!mp_irq_entries
) {
647 struct mpc_config_bus bus
;
650 "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
652 bus
.mpc_type
= MP_BUS
;
654 memcpy(bus
.mpc_bustype
, "ISA ", 6);
657 construct_default_ioirq_mptable(0);
664 printk(KERN_INFO
"Processors: %d\n", num_processors
);
666 * Only use the first configuration found.
670 void __init
early_get_smp_config(void)
675 void __init
get_smp_config(void)
680 static int __init
smp_scan_config(unsigned long base
, unsigned long length
,
683 unsigned long *bp
= phys_to_virt(base
);
684 struct intel_mp_floating
*mpf
;
686 printk(KERN_INFO
"Scan SMP from %p for %ld bytes.\n", bp
, length
);
687 if (sizeof(*mpf
) != 16)
688 printk("Error: MPF size\n");
691 mpf
= (struct intel_mp_floating
*)bp
;
692 if ((*bp
== SMP_MAGIC_IDENT
) &&
693 (mpf
->mpf_length
== 1) &&
694 !mpf_checksum((unsigned char *)bp
, 16) &&
695 ((mpf
->mpf_specification
== 1)
696 || (mpf
->mpf_specification
== 4))) {
698 smp_found_config
= 1;
699 printk(KERN_INFO
"found SMP MP-table at [%p] %08lx\n",
700 mpf
, virt_to_phys(mpf
));
701 reserve_bootmem(virt_to_phys(mpf
), PAGE_SIZE
,
703 if (mpf
->mpf_physptr
) {
705 * We cannot access to MPC table to compute
706 * table size yet, as only few megabytes from
707 * the bottom is mapped now.
708 * PC-9800's MPC table places on the very last
709 * of physical memory; so that simply reserving
710 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
711 * in reserve_bootmem.
713 unsigned long size
= PAGE_SIZE
;
714 unsigned long end
= max_low_pfn
* PAGE_SIZE
;
715 if (mpf
->mpf_physptr
+ size
> end
)
716 size
= end
- mpf
->mpf_physptr
;
717 reserve_bootmem(mpf
->mpf_physptr
, size
,
730 static void __init
__find_smp_config(unsigned reserve
)
732 unsigned int address
;
735 * FIXME: Linux assumes you have 640K of base ram..
736 * this continues the error...
738 * 1) Scan the bottom 1K for a signature
739 * 2) Scan the top 1K of base RAM
740 * 3) Scan the 64K of bios
742 if (smp_scan_config(0x0, 0x400, reserve
) ||
743 smp_scan_config(639 * 0x400, 0x400, reserve
) ||
744 smp_scan_config(0xF0000, 0x10000, reserve
))
747 * If it is an SMP machine we should know now, unless the
748 * configuration is in an EISA/MCA bus machine with an
749 * extended bios data area.
751 * there is a real-mode segmented pointer pointing to the
752 * 4K EBDA area at 0x40E, calculate and scan it here.
754 * NOTE! There are Linux loaders that will corrupt the EBDA
755 * area, and as such this kind of SMP config may be less
756 * trustworthy, simply because the SMP table may have been
757 * stomped on during early boot. These loaders are buggy and
760 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
763 address
= get_bios_ebda();
765 smp_scan_config(address
, 0x400, reserve
);
768 void __init
early_find_smp_config(void)
770 __find_smp_config(0);
773 void __init
find_smp_config(void)
775 __find_smp_config(1);
778 /* --------------------------------------------------------------------------
779 ACPI-based MP Configuration
780 -------------------------------------------------------------------------- */
784 #ifdef CONFIG_X86_IO_APIC
787 #define MP_MAX_IOAPIC_PIN 127
789 extern struct mp_ioapic_routing mp_ioapic_routing
[MAX_IO_APICS
];
791 static int mp_find_ioapic(int gsi
)
795 /* Find the IOAPIC that manages this GSI. */
796 for (i
= 0; i
< nr_ioapics
; i
++) {
797 if ((gsi
>= mp_ioapic_routing
[i
].gsi_base
)
798 && (gsi
<= mp_ioapic_routing
[i
].gsi_end
))
802 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
807 static u8
uniq_ioapic_id(u8 id
)
809 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
810 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
811 return io_apic_get_unique_id(nr_ioapics
, id
);
816 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
820 if (bad_ioapic(address
))
825 mp_ioapics
[idx
].mpc_type
= MP_IOAPIC
;
826 mp_ioapics
[idx
].mpc_flags
= MPC_APIC_USABLE
;
827 mp_ioapics
[idx
].mpc_apicaddr
= address
;
829 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
830 mp_ioapics
[idx
].mpc_apicid
= uniq_ioapic_id(id
);
831 mp_ioapics
[idx
].mpc_apicver
= io_apic_get_version(idx
);
834 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
835 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
837 mp_ioapic_routing
[idx
].apic_id
= mp_ioapics
[idx
].mpc_apicid
;
838 mp_ioapic_routing
[idx
].gsi_base
= gsi_base
;
839 mp_ioapic_routing
[idx
].gsi_end
= gsi_base
+
840 io_apic_get_redir_entries(idx
);
842 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
843 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].mpc_apicid
,
844 mp_ioapics
[idx
].mpc_apicver
,
845 mp_ioapics
[idx
].mpc_apicaddr
,
846 mp_ioapic_routing
[idx
].gsi_base
, mp_ioapic_routing
[idx
].gsi_end
);
851 void __init
mp_override_legacy_irq(u8 bus_irq
, u8 polarity
, u8 trigger
, u32 gsi
)
853 struct mpc_config_intsrc intsrc
;
858 * Convert 'gsi' to 'ioapic.pin'.
860 ioapic
= mp_find_ioapic(gsi
);
863 pin
= gsi
- mp_ioapic_routing
[ioapic
].gsi_base
;
866 * TBD: This check is for faulty timer entries, where the override
867 * erroneously sets the trigger to level, resulting in a HUGE
868 * increase of timer interrupts!
870 if ((bus_irq
== 0) && (trigger
== 3))
873 intsrc
.mpc_type
= MP_INTSRC
;
874 intsrc
.mpc_irqtype
= mp_INT
;
875 intsrc
.mpc_irqflag
= (trigger
<< 2) | polarity
;
876 intsrc
.mpc_srcbus
= MP_ISA_BUS
;
877 intsrc
.mpc_srcbusirq
= bus_irq
; /* IRQ */
878 intsrc
.mpc_dstapic
= mp_ioapics
[ioapic
].mpc_apicid
; /* APIC ID */
879 intsrc
.mpc_dstirq
= pin
; /* INTIN# */
881 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
882 intsrc
.mpc_irqtype
, intsrc
.mpc_irqflag
& 3,
883 (intsrc
.mpc_irqflag
>> 2) & 3, intsrc
.mpc_srcbus
,
884 intsrc
.mpc_srcbusirq
, intsrc
.mpc_dstapic
, intsrc
.mpc_dstirq
);
886 mp_irqs
[mp_irq_entries
] = intsrc
;
887 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
888 panic("Max # of irq sources exceeded!\n");
893 void __init
mp_config_acpi_legacy_irqs(void)
895 struct mpc_config_intsrc intsrc
;
899 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
901 * Fabricate the legacy ISA bus (bus #31).
903 mp_bus_id_to_type
[MP_ISA_BUS
] = MP_BUS_ISA
;
905 set_bit(MP_ISA_BUS
, mp_bus_not_pci
);
906 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS
);
909 * Older generations of ES7000 have no legacy identity mappings
911 if (es7000_plat
== 1)
915 * Locate the IOAPIC that manages the ISA IRQs (0-15).
917 ioapic
= mp_find_ioapic(0);
921 intsrc
.mpc_type
= MP_INTSRC
;
922 intsrc
.mpc_irqflag
= 0; /* Conforming */
923 intsrc
.mpc_srcbus
= MP_ISA_BUS
;
924 #ifdef CONFIG_X86_IO_APIC
925 intsrc
.mpc_dstapic
= mp_ioapics
[ioapic
].mpc_apicid
;
928 * Use the default configuration for the IRQs 0-15. Unless
929 * overridden by (MADT) interrupt source override entries.
931 for (i
= 0; i
< 16; i
++) {
934 for (idx
= 0; idx
< mp_irq_entries
; idx
++) {
935 struct mpc_config_intsrc
*irq
= mp_irqs
+ idx
;
937 /* Do we already have a mapping for this ISA IRQ? */
938 if (irq
->mpc_srcbus
== MP_ISA_BUS
939 && irq
->mpc_srcbusirq
== i
)
942 /* Do we already have a mapping for this IOAPIC pin */
943 if ((irq
->mpc_dstapic
== intsrc
.mpc_dstapic
) &&
944 (irq
->mpc_dstirq
== i
))
948 if (idx
!= mp_irq_entries
) {
949 printk(KERN_DEBUG
"ACPI: IRQ%d used by override.\n", i
);
950 continue; /* IRQ already used */
953 intsrc
.mpc_irqtype
= mp_INT
;
954 intsrc
.mpc_srcbusirq
= i
; /* Identity mapped */
955 intsrc
.mpc_dstirq
= i
;
957 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
958 "%d-%d\n", intsrc
.mpc_irqtype
, intsrc
.mpc_irqflag
& 3,
959 (intsrc
.mpc_irqflag
>> 2) & 3, intsrc
.mpc_srcbus
,
960 intsrc
.mpc_srcbusirq
, intsrc
.mpc_dstapic
,
963 mp_irqs
[mp_irq_entries
] = intsrc
;
964 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
965 panic("Max # of irq sources exceeded!\n");
969 #define MAX_GSI_NUM 4096
970 #define IRQ_COMPRESSION_START 64
972 int mp_register_gsi(u32 gsi
, int triggering
, int polarity
)
977 static int pci_irq
= IRQ_COMPRESSION_START
;
979 * Mapping between Global System Interrupts, which
980 * represent all possible interrupts, and IRQs
981 * assigned to actual devices.
983 static int gsi_to_irq
[MAX_GSI_NUM
];
985 /* Don't set up the ACPI SCI because it's already set up */
986 if (acpi_gbl_FADT
.sci_interrupt
== gsi
)
989 ioapic
= mp_find_ioapic(gsi
);
991 printk(KERN_WARNING
"No IOAPIC for GSI %u\n", gsi
);
995 ioapic_pin
= gsi
- mp_ioapic_routing
[ioapic
].gsi_base
;
997 if (ioapic_renumber_irq
)
998 gsi
= ioapic_renumber_irq(ioapic
, gsi
);
1001 * Avoid pin reprogramming. PRTs typically include entries
1002 * with redundant pin->gsi mappings (but unique PCI devices);
1003 * we only program the IOAPIC on the first.
1005 bit
= ioapic_pin
% 32;
1006 idx
= (ioapic_pin
< 32) ? 0 : (ioapic_pin
/ 32);
1008 printk(KERN_ERR
"Invalid reference to IOAPIC pin "
1009 "%d-%d\n", mp_ioapic_routing
[ioapic
].apic_id
,
1013 if ((1 << bit
) & mp_ioapic_routing
[ioapic
].pin_programmed
[idx
]) {
1014 Dprintk(KERN_DEBUG
"Pin %d-%d already programmed\n",
1015 mp_ioapic_routing
[ioapic
].apic_id
, ioapic_pin
);
1016 return (gsi
< IRQ_COMPRESSION_START
? gsi
: gsi_to_irq
[gsi
]);
1019 mp_ioapic_routing
[ioapic
].pin_programmed
[idx
] |= (1 << bit
);
1022 * For GSI >= 64, use IRQ compression
1024 if ((gsi
>= IRQ_COMPRESSION_START
)
1025 && (triggering
== ACPI_LEVEL_SENSITIVE
)) {
1027 * For PCI devices assign IRQs in order, avoiding gaps
1028 * due to unused I/O APIC pins.
1031 if (gsi
< MAX_GSI_NUM
) {
1033 * Retain the VIA chipset work-around (gsi > 15), but
1034 * avoid a problem where the 8254 timer (IRQ0) is setup
1035 * via an override (so it's not on pin 0 of the ioapic),
1036 * and at the same time, the pin 0 interrupt is a PCI
1037 * type. The gsi > 15 test could cause these two pins
1038 * to be shared as IRQ0, and they are not shareable.
1039 * So test for this condition, and if necessary, avoid
1040 * the pin collision.
1044 * Don't assign IRQ used by ACPI SCI
1046 if (gsi
== acpi_gbl_FADT
.sci_interrupt
)
1048 gsi_to_irq
[irq
] = gsi
;
1050 printk(KERN_ERR
"GSI %u is too high\n", gsi
);
1055 io_apic_set_pci_routing(ioapic
, ioapic_pin
, gsi
,
1056 triggering
== ACPI_EDGE_SENSITIVE
? 0 : 1,
1057 polarity
== ACPI_ACTIVE_HIGH
? 0 : 1);
1061 #endif /* CONFIG_X86_IO_APIC */
1062 #endif /* CONFIG_ACPI */