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x86: use disabled_cpus in i386
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30
31 #include <mach_apic.h>
32 #include <mach_apicdef.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 int mp_bus_id_to_node [MAX_MP_BUSSES];
47 int mp_bus_id_to_local [MAX_MP_BUSSES];
48 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
51
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57
58 /* MP IRQ source entries */
59 int mp_irq_entries;
60
61 int nr_ioapics;
62
63 int pic_mode;
64 unsigned long mp_lapic_addr;
65
66 unsigned int def_to_bigsmp = 0;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
72
73 unsigned disabled_cpus __cpuinitdata;
74
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
77
78 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
79
80 /*
81 * Intel MP BIOS table parsing routines:
82 */
83
84
85 /*
86 * Checksum an MP configuration block.
87 */
88
89 static int __init mpf_checksum(unsigned char *mp, int len)
90 {
91 int sum = 0;
92
93 while (len--)
94 sum += *mp++;
95
96 return sum & 0xFF;
97 }
98
99 /*
100 * Have to match translation table entries to main table entries by counter
101 * hence the mpc_record variable .... can't see a less disgusting way of
102 * doing this ....
103 */
104
105 static int mpc_record;
106 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
107
108 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
109 {
110 int ver, apicid;
111 physid_mask_t phys_cpu;
112
113 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
114 disabled_cpus++;
115 return;
116 }
117
118 apicid = mpc_apic_id(m, translation_table[mpc_record]);
119
120 if (m->mpc_featureflag&(1<<0))
121 Dprintk(" Floating point unit present.\n");
122 if (m->mpc_featureflag&(1<<7))
123 Dprintk(" Machine Exception supported.\n");
124 if (m->mpc_featureflag&(1<<8))
125 Dprintk(" 64 bit compare & exchange supported.\n");
126 if (m->mpc_featureflag&(1<<9))
127 Dprintk(" Internal APIC present.\n");
128 if (m->mpc_featureflag&(1<<11))
129 Dprintk(" SEP present.\n");
130 if (m->mpc_featureflag&(1<<12))
131 Dprintk(" MTRR present.\n");
132 if (m->mpc_featureflag&(1<<13))
133 Dprintk(" PGE present.\n");
134 if (m->mpc_featureflag&(1<<14))
135 Dprintk(" MCA present.\n");
136 if (m->mpc_featureflag&(1<<15))
137 Dprintk(" CMOV present.\n");
138 if (m->mpc_featureflag&(1<<16))
139 Dprintk(" PAT present.\n");
140 if (m->mpc_featureflag&(1<<17))
141 Dprintk(" PSE present.\n");
142 if (m->mpc_featureflag&(1<<18))
143 Dprintk(" PSN present.\n");
144 if (m->mpc_featureflag&(1<<19))
145 Dprintk(" Cache Line Flush Instruction present.\n");
146 /* 20 Reserved */
147 if (m->mpc_featureflag&(1<<21))
148 Dprintk(" Debug Trace and EMON Store present.\n");
149 if (m->mpc_featureflag&(1<<22))
150 Dprintk(" ACPI Thermal Throttle Registers present.\n");
151 if (m->mpc_featureflag&(1<<23))
152 Dprintk(" MMX present.\n");
153 if (m->mpc_featureflag&(1<<24))
154 Dprintk(" FXSR present.\n");
155 if (m->mpc_featureflag&(1<<25))
156 Dprintk(" XMM present.\n");
157 if (m->mpc_featureflag&(1<<26))
158 Dprintk(" Willamette New Instructions present.\n");
159 if (m->mpc_featureflag&(1<<27))
160 Dprintk(" Self Snoop present.\n");
161 if (m->mpc_featureflag&(1<<28))
162 Dprintk(" HT present.\n");
163 if (m->mpc_featureflag&(1<<29))
164 Dprintk(" Thermal Monitor present.\n");
165 /* 30, 31 Reserved */
166
167
168 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
169 Dprintk(" Bootup CPU\n");
170 boot_cpu_physical_apicid = m->mpc_apicid;
171 }
172
173 ver = m->mpc_apicver;
174
175 /*
176 * Validate version
177 */
178 if (ver == 0x0) {
179 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
180 "fixing up to 0x10. (tell your hw vendor)\n",
181 m->mpc_apicid);
182 ver = 0x10;
183 }
184 apic_version[m->mpc_apicid] = ver;
185
186 phys_cpu = apicid_to_cpu_present(apicid);
187 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
188
189 if (num_processors >= NR_CPUS) {
190 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
191 " Processor ignored.\n", NR_CPUS);
192 return;
193 }
194
195 if (num_processors >= maxcpus) {
196 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
197 " Processor ignored.\n", maxcpus);
198 return;
199 }
200
201 cpu_set(num_processors, cpu_possible_map);
202 num_processors++;
203
204 /*
205 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
206 * but we need to work other dependencies like SMP_SUSPEND etc
207 * before this can be done without some confusion.
208 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
209 * - Ashok Raj <ashok.raj@intel.com>
210 */
211 if (num_processors > 8) {
212 switch (boot_cpu_data.x86_vendor) {
213 case X86_VENDOR_INTEL:
214 if (!APIC_XAPIC(ver)) {
215 def_to_bigsmp = 0;
216 break;
217 }
218 /* If P4 and above fall through */
219 case X86_VENDOR_AMD:
220 def_to_bigsmp = 1;
221 }
222 }
223 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
224 }
225
226 static void __init MP_bus_info (struct mpc_config_bus *m)
227 {
228 char str[7];
229
230 memcpy(str, m->mpc_bustype, 6);
231 str[6] = 0;
232
233 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
234
235 #if MAX_MP_BUSSES < 256
236 if (m->mpc_busid >= MAX_MP_BUSSES) {
237 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
238 " is too large, max. supported is %d\n",
239 m->mpc_busid, str, MAX_MP_BUSSES - 1);
240 return;
241 }
242 #endif
243
244 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
245 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
246 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
247 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
248 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
249 mpc_oem_pci_bus(m, translation_table[mpc_record]);
250 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
251 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
252 mp_current_pci_id++;
253 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
254 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
255 } else {
256 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
257 }
258 }
259
260 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
261 {
262 if (!(m->mpc_flags & MPC_APIC_USABLE))
263 return;
264
265 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
266 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
267 if (nr_ioapics >= MAX_IO_APICS) {
268 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
269 MAX_IO_APICS, nr_ioapics);
270 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
271 }
272 if (!m->mpc_apicaddr) {
273 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
274 " found in MP table, skipping!\n");
275 return;
276 }
277 mp_ioapics[nr_ioapics] = *m;
278 nr_ioapics++;
279 }
280
281 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
282 {
283 mp_irqs [mp_irq_entries] = *m;
284 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
285 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
286 m->mpc_irqtype, m->mpc_irqflag & 3,
287 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
288 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
289 if (++mp_irq_entries == MAX_IRQ_SOURCES)
290 panic("Max # of irq sources exceeded!!\n");
291 }
292
293 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
294 {
295 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
296 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
297 m->mpc_irqtype, m->mpc_irqflag & 3,
298 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
299 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
300 }
301
302 #ifdef CONFIG_X86_NUMAQ
303 static void __init MP_translation_info (struct mpc_config_translation *m)
304 {
305 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
306
307 if (mpc_record >= MAX_MPC_ENTRY)
308 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
309 else
310 translation_table[mpc_record] = m; /* stash this for later */
311 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
312 node_set_online(m->trans_quad);
313 }
314
315 /*
316 * Read/parse the MPC oem tables
317 */
318
319 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
320 unsigned short oemsize)
321 {
322 int count = sizeof (*oemtable); /* the header size */
323 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
324
325 mpc_record = 0;
326 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
327 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
328 {
329 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
330 oemtable->oem_signature[0],
331 oemtable->oem_signature[1],
332 oemtable->oem_signature[2],
333 oemtable->oem_signature[3]);
334 return;
335 }
336 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
337 {
338 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
339 return;
340 }
341 while (count < oemtable->oem_length) {
342 switch (*oemptr) {
343 case MP_TRANSLATION:
344 {
345 struct mpc_config_translation *m=
346 (struct mpc_config_translation *)oemptr;
347 MP_translation_info(m);
348 oemptr += sizeof(*m);
349 count += sizeof(*m);
350 ++mpc_record;
351 break;
352 }
353 default:
354 {
355 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
356 return;
357 }
358 }
359 }
360 }
361
362 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
363 char *productid)
364 {
365 if (strncmp(oem, "IBM NUMA", 8))
366 printk("Warning! May not be a NUMA-Q system!\n");
367 if (mpc->mpc_oemptr)
368 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
369 mpc->mpc_oemsize);
370 }
371 #endif /* CONFIG_X86_NUMAQ */
372
373 /*
374 * Read/parse the MPC
375 */
376
377 static int __init smp_read_mpc(struct mp_config_table *mpc)
378 {
379 char str[16];
380 char oem[10];
381 int count=sizeof(*mpc);
382 unsigned char *mpt=((unsigned char *)mpc)+count;
383
384 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
385 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
386 *(u32 *)mpc->mpc_signature);
387 return 0;
388 }
389 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
390 printk(KERN_ERR "SMP mptable: checksum error!\n");
391 return 0;
392 }
393 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
394 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
395 mpc->mpc_spec);
396 return 0;
397 }
398 if (!mpc->mpc_lapic) {
399 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
400 return 0;
401 }
402 memcpy(oem,mpc->mpc_oem,8);
403 oem[8]=0;
404 printk(KERN_INFO "OEM ID: %s ",oem);
405
406 memcpy(str,mpc->mpc_productid,12);
407 str[12]=0;
408 printk("Product ID: %s ",str);
409
410 mps_oem_check(mpc, oem, str);
411
412 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
413
414 /*
415 * Save the local APIC address (it might be non-default) -- but only
416 * if we're not using ACPI.
417 */
418 if (!acpi_lapic)
419 mp_lapic_addr = mpc->mpc_lapic;
420
421 /*
422 * Now process the configuration blocks.
423 */
424 mpc_record = 0;
425 while (count < mpc->mpc_length) {
426 switch(*mpt) {
427 case MP_PROCESSOR:
428 {
429 struct mpc_config_processor *m=
430 (struct mpc_config_processor *)mpt;
431 /* ACPI may have already provided this data */
432 if (!acpi_lapic)
433 MP_processor_info(m);
434 mpt += sizeof(*m);
435 count += sizeof(*m);
436 break;
437 }
438 case MP_BUS:
439 {
440 struct mpc_config_bus *m=
441 (struct mpc_config_bus *)mpt;
442 MP_bus_info(m);
443 mpt += sizeof(*m);
444 count += sizeof(*m);
445 break;
446 }
447 case MP_IOAPIC:
448 {
449 struct mpc_config_ioapic *m=
450 (struct mpc_config_ioapic *)mpt;
451 MP_ioapic_info(m);
452 mpt+=sizeof(*m);
453 count+=sizeof(*m);
454 break;
455 }
456 case MP_INTSRC:
457 {
458 struct mpc_config_intsrc *m=
459 (struct mpc_config_intsrc *)mpt;
460
461 MP_intsrc_info(m);
462 mpt+=sizeof(*m);
463 count+=sizeof(*m);
464 break;
465 }
466 case MP_LINTSRC:
467 {
468 struct mpc_config_lintsrc *m=
469 (struct mpc_config_lintsrc *)mpt;
470 MP_lintsrc_info(m);
471 mpt+=sizeof(*m);
472 count+=sizeof(*m);
473 break;
474 }
475 default:
476 {
477 count = mpc->mpc_length;
478 break;
479 }
480 }
481 ++mpc_record;
482 }
483 setup_apic_routing();
484 if (!num_processors)
485 printk(KERN_ERR "SMP mptable: no processors registered!\n");
486 return num_processors;
487 }
488
489 static int __init ELCR_trigger(unsigned int irq)
490 {
491 unsigned int port;
492
493 port = 0x4d0 + (irq >> 3);
494 return (inb(port) >> (irq & 7)) & 1;
495 }
496
497 static void __init construct_default_ioirq_mptable(int mpc_default_type)
498 {
499 struct mpc_config_intsrc intsrc;
500 int i;
501 int ELCR_fallback = 0;
502
503 intsrc.mpc_type = MP_INTSRC;
504 intsrc.mpc_irqflag = 0; /* conforming */
505 intsrc.mpc_srcbus = 0;
506 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
507
508 intsrc.mpc_irqtype = mp_INT;
509
510 /*
511 * If true, we have an ISA/PCI system with no IRQ entries
512 * in the MP table. To prevent the PCI interrupts from being set up
513 * incorrectly, we try to use the ELCR. The sanity check to see if
514 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
515 * never be level sensitive, so we simply see if the ELCR agrees.
516 * If it does, we assume it's valid.
517 */
518 if (mpc_default_type == 5) {
519 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
520
521 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
522 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
523 else {
524 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
525 ELCR_fallback = 1;
526 }
527 }
528
529 for (i = 0; i < 16; i++) {
530 switch (mpc_default_type) {
531 case 2:
532 if (i == 0 || i == 13)
533 continue; /* IRQ0 & IRQ13 not connected */
534 /* fall through */
535 default:
536 if (i == 2)
537 continue; /* IRQ2 is never connected */
538 }
539
540 if (ELCR_fallback) {
541 /*
542 * If the ELCR indicates a level-sensitive interrupt, we
543 * copy that information over to the MP table in the
544 * irqflag field (level sensitive, active high polarity).
545 */
546 if (ELCR_trigger(i))
547 intsrc.mpc_irqflag = 13;
548 else
549 intsrc.mpc_irqflag = 0;
550 }
551
552 intsrc.mpc_srcbusirq = i;
553 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
554 MP_intsrc_info(&intsrc);
555 }
556
557 intsrc.mpc_irqtype = mp_ExtINT;
558 intsrc.mpc_srcbusirq = 0;
559 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
560 MP_intsrc_info(&intsrc);
561 }
562
563 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
564 {
565 struct mpc_config_processor processor;
566 struct mpc_config_bus bus;
567 struct mpc_config_ioapic ioapic;
568 struct mpc_config_lintsrc lintsrc;
569 int linttypes[2] = { mp_ExtINT, mp_NMI };
570 int i;
571
572 /*
573 * local APIC has default address
574 */
575 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
576
577 /*
578 * 2 CPUs, numbered 0 & 1.
579 */
580 processor.mpc_type = MP_PROCESSOR;
581 /* Either an integrated APIC or a discrete 82489DX. */
582 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
583 processor.mpc_cpuflag = CPU_ENABLED;
584 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
585 (boot_cpu_data.x86_model << 4) |
586 boot_cpu_data.x86_mask;
587 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
588 processor.mpc_reserved[0] = 0;
589 processor.mpc_reserved[1] = 0;
590 for (i = 0; i < 2; i++) {
591 processor.mpc_apicid = i;
592 MP_processor_info(&processor);
593 }
594
595 bus.mpc_type = MP_BUS;
596 bus.mpc_busid = 0;
597 switch (mpc_default_type) {
598 default:
599 printk("???\n");
600 printk(KERN_ERR "Unknown standard configuration %d\n",
601 mpc_default_type);
602 /* fall through */
603 case 1:
604 case 5:
605 memcpy(bus.mpc_bustype, "ISA ", 6);
606 break;
607 case 2:
608 case 6:
609 case 3:
610 memcpy(bus.mpc_bustype, "EISA ", 6);
611 break;
612 case 4:
613 case 7:
614 memcpy(bus.mpc_bustype, "MCA ", 6);
615 }
616 MP_bus_info(&bus);
617 if (mpc_default_type > 4) {
618 bus.mpc_busid = 1;
619 memcpy(bus.mpc_bustype, "PCI ", 6);
620 MP_bus_info(&bus);
621 }
622
623 ioapic.mpc_type = MP_IOAPIC;
624 ioapic.mpc_apicid = 2;
625 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
626 ioapic.mpc_flags = MPC_APIC_USABLE;
627 ioapic.mpc_apicaddr = 0xFEC00000;
628 MP_ioapic_info(&ioapic);
629
630 /*
631 * We set up most of the low 16 IO-APIC pins according to MPS rules.
632 */
633 construct_default_ioirq_mptable(mpc_default_type);
634
635 lintsrc.mpc_type = MP_LINTSRC;
636 lintsrc.mpc_irqflag = 0; /* conforming */
637 lintsrc.mpc_srcbusid = 0;
638 lintsrc.mpc_srcbusirq = 0;
639 lintsrc.mpc_destapic = MP_APIC_ALL;
640 for (i = 0; i < 2; i++) {
641 lintsrc.mpc_irqtype = linttypes[i];
642 lintsrc.mpc_destapiclint = i;
643 MP_lintsrc_info(&lintsrc);
644 }
645 }
646
647 static struct intel_mp_floating *mpf_found;
648
649 /*
650 * Scan the memory blocks for an SMP configuration block.
651 */
652 void __init get_smp_config (void)
653 {
654 struct intel_mp_floating *mpf = mpf_found;
655
656 /*
657 * ACPI supports both logical (e.g. Hyper-Threading) and physical
658 * processors, where MPS only supports physical.
659 */
660 if (acpi_lapic && acpi_ioapic) {
661 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
662 return;
663 }
664 else if (acpi_lapic)
665 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
666
667 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
668 if (mpf->mpf_feature2 & (1<<7)) {
669 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
670 pic_mode = 1;
671 } else {
672 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
673 pic_mode = 0;
674 }
675
676 /*
677 * Now see if we need to read further.
678 */
679 if (mpf->mpf_feature1 != 0) {
680
681 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
682 construct_default_ISA_mptable(mpf->mpf_feature1);
683
684 } else if (mpf->mpf_physptr) {
685
686 /*
687 * Read the physical hardware table. Anything here will
688 * override the defaults.
689 */
690 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
691 smp_found_config = 0;
692 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
693 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
694 return;
695 }
696 /*
697 * If there are no explicit MP IRQ entries, then we are
698 * broken. We set up most of the low 16 IO-APIC pins to
699 * ISA defaults and hope it will work.
700 */
701 if (!mp_irq_entries) {
702 struct mpc_config_bus bus;
703
704 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
705
706 bus.mpc_type = MP_BUS;
707 bus.mpc_busid = 0;
708 memcpy(bus.mpc_bustype, "ISA ", 6);
709 MP_bus_info(&bus);
710
711 construct_default_ioirq_mptable(0);
712 }
713
714 } else
715 BUG();
716
717 printk(KERN_INFO "Processors: %d\n", num_processors);
718 /*
719 * Only use the first configuration found.
720 */
721 }
722
723 static int __init smp_scan_config (unsigned long base, unsigned long length)
724 {
725 unsigned long *bp = phys_to_virt(base);
726 struct intel_mp_floating *mpf;
727
728 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
729 if (sizeof(*mpf) != 16)
730 printk("Error: MPF size\n");
731
732 while (length > 0) {
733 mpf = (struct intel_mp_floating *)bp;
734 if ((*bp == SMP_MAGIC_IDENT) &&
735 (mpf->mpf_length == 1) &&
736 !mpf_checksum((unsigned char *)bp, 16) &&
737 ((mpf->mpf_specification == 1)
738 || (mpf->mpf_specification == 4)) ) {
739
740 smp_found_config = 1;
741 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
742 mpf, virt_to_phys(mpf));
743 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
744 BOOTMEM_DEFAULT);
745 if (mpf->mpf_physptr) {
746 /*
747 * We cannot access to MPC table to compute
748 * table size yet, as only few megabytes from
749 * the bottom is mapped now.
750 * PC-9800's MPC table places on the very last
751 * of physical memory; so that simply reserving
752 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
753 * in reserve_bootmem.
754 */
755 unsigned long size = PAGE_SIZE;
756 unsigned long end = max_low_pfn * PAGE_SIZE;
757 if (mpf->mpf_physptr + size > end)
758 size = end - mpf->mpf_physptr;
759 reserve_bootmem(mpf->mpf_physptr, size,
760 BOOTMEM_DEFAULT);
761 }
762
763 mpf_found = mpf;
764 return 1;
765 }
766 bp += 4;
767 length -= 16;
768 }
769 return 0;
770 }
771
772 void __init find_smp_config (void)
773 {
774 unsigned int address;
775
776 /*
777 * FIXME: Linux assumes you have 640K of base ram..
778 * this continues the error...
779 *
780 * 1) Scan the bottom 1K for a signature
781 * 2) Scan the top 1K of base RAM
782 * 3) Scan the 64K of bios
783 */
784 if (smp_scan_config(0x0,0x400) ||
785 smp_scan_config(639*0x400,0x400) ||
786 smp_scan_config(0xF0000,0x10000))
787 return;
788 /*
789 * If it is an SMP machine we should know now, unless the
790 * configuration is in an EISA/MCA bus machine with an
791 * extended bios data area.
792 *
793 * there is a real-mode segmented pointer pointing to the
794 * 4K EBDA area at 0x40E, calculate and scan it here.
795 *
796 * NOTE! There are Linux loaders that will corrupt the EBDA
797 * area, and as such this kind of SMP config may be less
798 * trustworthy, simply because the SMP table may have been
799 * stomped on during early boot. These loaders are buggy and
800 * should be fixed.
801 *
802 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
803 */
804
805 address = get_bios_ebda();
806 if (address)
807 smp_scan_config(address, 0x400);
808 }
809
810 int es7000_plat;
811
812 /* --------------------------------------------------------------------------
813 ACPI-based MP Configuration
814 -------------------------------------------------------------------------- */
815
816 #ifdef CONFIG_ACPI
817
818 void __init mp_register_lapic_address(u64 address)
819 {
820 mp_lapic_addr = (unsigned long) address;
821
822 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
823
824 if (boot_cpu_physical_apicid == -1U)
825 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
826
827 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
828 }
829
830 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
831 {
832 struct mpc_config_processor processor;
833 int boot_cpu = 0;
834
835 if (MAX_APICS - id <= 0) {
836 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
837 id, MAX_APICS);
838 return;
839 }
840
841 if (id == boot_cpu_physical_apicid)
842 boot_cpu = 1;
843
844 processor.mpc_type = MP_PROCESSOR;
845 processor.mpc_apicid = id;
846 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
847 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
848 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
849 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
850 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
851 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
852 processor.mpc_reserved[0] = 0;
853 processor.mpc_reserved[1] = 0;
854
855 MP_processor_info(&processor);
856 }
857
858 #ifdef CONFIG_X86_IO_APIC
859
860 #define MP_ISA_BUS 0
861 #define MP_MAX_IOAPIC_PIN 127
862
863 static struct mp_ioapic_routing {
864 int apic_id;
865 int gsi_base;
866 int gsi_end;
867 u32 pin_programmed[4];
868 } mp_ioapic_routing[MAX_IO_APICS];
869
870 static int mp_find_ioapic (int gsi)
871 {
872 int i = 0;
873
874 /* Find the IOAPIC that manages this GSI. */
875 for (i = 0; i < nr_ioapics; i++) {
876 if ((gsi >= mp_ioapic_routing[i].gsi_base)
877 && (gsi <= mp_ioapic_routing[i].gsi_end))
878 return i;
879 }
880
881 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
882
883 return -1;
884 }
885
886 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
887 {
888 int idx = 0;
889 int tmpid;
890
891 if (nr_ioapics >= MAX_IO_APICS) {
892 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
893 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
894 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
895 }
896 if (!address) {
897 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
898 " found in MADT table, skipping!\n");
899 return;
900 }
901
902 idx = nr_ioapics++;
903
904 mp_ioapics[idx].mpc_type = MP_IOAPIC;
905 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
906 mp_ioapics[idx].mpc_apicaddr = address;
907
908 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
909 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
910 && !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
911 tmpid = io_apic_get_unique_id(idx, id);
912 else
913 tmpid = id;
914 if (tmpid == -1) {
915 nr_ioapics--;
916 return;
917 }
918 mp_ioapics[idx].mpc_apicid = tmpid;
919 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
920
921 /*
922 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
923 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
924 */
925 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
926 mp_ioapic_routing[idx].gsi_base = gsi_base;
927 mp_ioapic_routing[idx].gsi_end = gsi_base +
928 io_apic_get_redir_entries(idx);
929
930 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
931 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
932 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
933 mp_ioapic_routing[idx].gsi_base,
934 mp_ioapic_routing[idx].gsi_end);
935 }
936
937 void __init
938 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
939 {
940 struct mpc_config_intsrc intsrc;
941 int ioapic = -1;
942 int pin = -1;
943
944 /*
945 * Convert 'gsi' to 'ioapic.pin'.
946 */
947 ioapic = mp_find_ioapic(gsi);
948 if (ioapic < 0)
949 return;
950 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
951
952 /*
953 * TBD: This check is for faulty timer entries, where the override
954 * erroneously sets the trigger to level, resulting in a HUGE
955 * increase of timer interrupts!
956 */
957 if ((bus_irq == 0) && (trigger == 3))
958 trigger = 1;
959
960 intsrc.mpc_type = MP_INTSRC;
961 intsrc.mpc_irqtype = mp_INT;
962 intsrc.mpc_irqflag = (trigger << 2) | polarity;
963 intsrc.mpc_srcbus = MP_ISA_BUS;
964 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
965 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
966 intsrc.mpc_dstirq = pin; /* INTIN# */
967
968 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
969 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
970 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
971 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
972
973 mp_irqs[mp_irq_entries] = intsrc;
974 if (++mp_irq_entries == MAX_IRQ_SOURCES)
975 panic("Max # of irq sources exceeded!\n");
976 }
977
978 void __init mp_config_acpi_legacy_irqs (void)
979 {
980 struct mpc_config_intsrc intsrc;
981 int i = 0;
982 int ioapic = -1;
983
984 /*
985 * Fabricate the legacy ISA bus (bus #31).
986 */
987 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
988 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
989
990 /*
991 * Older generations of ES7000 have no legacy identity mappings
992 */
993 if (es7000_plat == 1)
994 return;
995
996 /*
997 * Locate the IOAPIC that manages the ISA IRQs (0-15).
998 */
999 ioapic = mp_find_ioapic(0);
1000 if (ioapic < 0)
1001 return;
1002
1003 intsrc.mpc_type = MP_INTSRC;
1004 intsrc.mpc_irqflag = 0; /* Conforming */
1005 intsrc.mpc_srcbus = MP_ISA_BUS;
1006 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1007
1008 /*
1009 * Use the default configuration for the IRQs 0-15. Unless
1010 * overridden by (MADT) interrupt source override entries.
1011 */
1012 for (i = 0; i < 16; i++) {
1013 int idx;
1014
1015 for (idx = 0; idx < mp_irq_entries; idx++) {
1016 struct mpc_config_intsrc *irq = mp_irqs + idx;
1017
1018 /* Do we already have a mapping for this ISA IRQ? */
1019 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1020 break;
1021
1022 /* Do we already have a mapping for this IOAPIC pin */
1023 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1024 (irq->mpc_dstirq == i))
1025 break;
1026 }
1027
1028 if (idx != mp_irq_entries) {
1029 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1030 continue; /* IRQ already used */
1031 }
1032
1033 intsrc.mpc_irqtype = mp_INT;
1034 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1035 intsrc.mpc_dstirq = i;
1036
1037 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1038 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1039 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1040 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1041 intsrc.mpc_dstirq);
1042
1043 mp_irqs[mp_irq_entries] = intsrc;
1044 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1045 panic("Max # of irq sources exceeded!\n");
1046 }
1047 }
1048
1049 #define MAX_GSI_NUM 4096
1050 #define IRQ_COMPRESSION_START 64
1051
1052 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1053 {
1054 int ioapic = -1;
1055 int ioapic_pin = 0;
1056 int idx, bit = 0;
1057 static int pci_irq = IRQ_COMPRESSION_START;
1058 /*
1059 * Mapping between Global System Interrupts, which
1060 * represent all possible interrupts, and IRQs
1061 * assigned to actual devices.
1062 */
1063 static int gsi_to_irq[MAX_GSI_NUM];
1064
1065 /* Don't set up the ACPI SCI because it's already set up */
1066 if (acpi_gbl_FADT.sci_interrupt == gsi)
1067 return gsi;
1068
1069 ioapic = mp_find_ioapic(gsi);
1070 if (ioapic < 0) {
1071 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1072 return gsi;
1073 }
1074
1075 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1076
1077 if (ioapic_renumber_irq)
1078 gsi = ioapic_renumber_irq(ioapic, gsi);
1079
1080 /*
1081 * Avoid pin reprogramming. PRTs typically include entries
1082 * with redundant pin->gsi mappings (but unique PCI devices);
1083 * we only program the IOAPIC on the first.
1084 */
1085 bit = ioapic_pin % 32;
1086 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1087 if (idx > 3) {
1088 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1089 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1090 ioapic_pin);
1091 return gsi;
1092 }
1093 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1094 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1095 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1096 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1097 }
1098
1099 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1100
1101 /*
1102 * For GSI >= 64, use IRQ compression
1103 */
1104 if ((gsi >= IRQ_COMPRESSION_START)
1105 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1106 /*
1107 * For PCI devices assign IRQs in order, avoiding gaps
1108 * due to unused I/O APIC pins.
1109 */
1110 int irq = gsi;
1111 if (gsi < MAX_GSI_NUM) {
1112 /*
1113 * Retain the VIA chipset work-around (gsi > 15), but
1114 * avoid a problem where the 8254 timer (IRQ0) is setup
1115 * via an override (so it's not on pin 0 of the ioapic),
1116 * and at the same time, the pin 0 interrupt is a PCI
1117 * type. The gsi > 15 test could cause these two pins
1118 * to be shared as IRQ0, and they are not shareable.
1119 * So test for this condition, and if necessary, avoid
1120 * the pin collision.
1121 */
1122 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1123 gsi = pci_irq++;
1124 /*
1125 * Don't assign IRQ used by ACPI SCI
1126 */
1127 if (gsi == acpi_gbl_FADT.sci_interrupt)
1128 gsi = pci_irq++;
1129 gsi_to_irq[irq] = gsi;
1130 } else {
1131 printk(KERN_ERR "GSI %u is too high\n", gsi);
1132 return gsi;
1133 }
1134 }
1135
1136 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1137 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1138 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1139 return gsi;
1140 }
1141
1142 #endif /* CONFIG_X86_IO_APIC */
1143 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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