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x86: remove mpc_oem_pci_bus()
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
46 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 #endif
48 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
49 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
50 static int mp_current_pci_id;
51
52 /* I/O APIC entries */
53 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54
55 /* # of MP IRQ source entries */
56 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57
58 /* MP IRQ source entries */
59 int mp_irq_entries;
60
61 int nr_ioapics;
62
63 int pic_mode;
64 unsigned long mp_lapic_addr;
65
66 unsigned int def_to_bigsmp = 0;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid = -1U;
70 /* Internal processor count */
71 unsigned int num_processors;
72
73 unsigned disabled_cpus __cpuinitdata;
74
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
77
78 #ifndef CONFIG_SMP
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
80 #endif
81
82 /*
83 * Intel MP BIOS table parsing routines:
84 */
85
86
87 /*
88 * Checksum an MP configuration block.
89 */
90
91 static int __init mpf_checksum(unsigned char *mp, int len)
92 {
93 int sum = 0;
94
95 while (len--)
96 sum += *mp++;
97
98 return sum & 0xFF;
99 }
100
101 /*
102 * Have to match translation table entries to main table entries by counter
103 * hence the mpc_record variable .... can't see a less disgusting way of
104 * doing this ....
105 */
106
107 static int mpc_record;
108 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
109
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
111 {
112 int ver, apicid, cpu;
113 cpumask_t tmp_map;
114 physid_mask_t phys_cpu;
115
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
117 disabled_cpus++;
118 return;
119 }
120
121 #ifdef CONFIG_X86_NUMAQ
122 apicid = mpc_apic_id(m, translation_table[mpc_record]);
123 #else
124 Dprintk("Processor #%d %u:%u APIC version %d\n",
125 m->mpc_apicid,
126 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
127 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
128 m->mpc_apicver);
129 apicid = m->mpc_apicid;
130 #endif
131
132 if (m->mpc_featureflag&(1<<0))
133 Dprintk(" Floating point unit present.\n");
134 if (m->mpc_featureflag&(1<<7))
135 Dprintk(" Machine Exception supported.\n");
136 if (m->mpc_featureflag&(1<<8))
137 Dprintk(" 64 bit compare & exchange supported.\n");
138 if (m->mpc_featureflag&(1<<9))
139 Dprintk(" Internal APIC present.\n");
140 if (m->mpc_featureflag&(1<<11))
141 Dprintk(" SEP present.\n");
142 if (m->mpc_featureflag&(1<<12))
143 Dprintk(" MTRR present.\n");
144 if (m->mpc_featureflag&(1<<13))
145 Dprintk(" PGE present.\n");
146 if (m->mpc_featureflag&(1<<14))
147 Dprintk(" MCA present.\n");
148 if (m->mpc_featureflag&(1<<15))
149 Dprintk(" CMOV present.\n");
150 if (m->mpc_featureflag&(1<<16))
151 Dprintk(" PAT present.\n");
152 if (m->mpc_featureflag&(1<<17))
153 Dprintk(" PSE present.\n");
154 if (m->mpc_featureflag&(1<<18))
155 Dprintk(" PSN present.\n");
156 if (m->mpc_featureflag&(1<<19))
157 Dprintk(" Cache Line Flush Instruction present.\n");
158 /* 20 Reserved */
159 if (m->mpc_featureflag&(1<<21))
160 Dprintk(" Debug Trace and EMON Store present.\n");
161 if (m->mpc_featureflag&(1<<22))
162 Dprintk(" ACPI Thermal Throttle Registers present.\n");
163 if (m->mpc_featureflag&(1<<23))
164 Dprintk(" MMX present.\n");
165 if (m->mpc_featureflag&(1<<24))
166 Dprintk(" FXSR present.\n");
167 if (m->mpc_featureflag&(1<<25))
168 Dprintk(" XMM present.\n");
169 if (m->mpc_featureflag&(1<<26))
170 Dprintk(" Willamette New Instructions present.\n");
171 if (m->mpc_featureflag&(1<<27))
172 Dprintk(" Self Snoop present.\n");
173 if (m->mpc_featureflag&(1<<28))
174 Dprintk(" HT present.\n");
175 if (m->mpc_featureflag&(1<<29))
176 Dprintk(" Thermal Monitor present.\n");
177 /* 30, 31 Reserved */
178
179
180 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
181 Dprintk(" Bootup CPU\n");
182 boot_cpu_physical_apicid = m->mpc_apicid;
183 }
184
185 ver = m->mpc_apicver;
186
187 /*
188 * Validate version
189 */
190 if (ver == 0x0) {
191 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
192 "fixing up to 0x10. (tell your hw vendor)\n",
193 m->mpc_apicid);
194 ver = 0x10;
195 }
196 apic_version[m->mpc_apicid] = ver;
197
198 phys_cpu = apicid_to_cpu_present(apicid);
199 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
200
201 if (num_processors >= NR_CPUS) {
202 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
203 " Processor ignored.\n", NR_CPUS);
204 return;
205 }
206
207 if (num_processors >= maxcpus) {
208 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
209 " Processor ignored.\n", maxcpus);
210 return;
211 }
212
213 cpu_set(num_processors, cpu_possible_map);
214 num_processors++;
215 cpus_complement(tmp_map, cpu_present_map);
216 cpu = first_cpu(tmp_map);
217
218 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
219 /*
220 * x86_bios_cpu_apicid is required to have processors listed
221 * in same order as logical cpu numbers. Hence the first
222 * entry is BSP, and so on.
223 */
224 cpu = 0;
225
226 /*
227 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
228 * but we need to work other dependencies like SMP_SUSPEND etc
229 * before this can be done without some confusion.
230 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
231 * - Ashok Raj <ashok.raj@intel.com>
232 */
233 if (num_processors > 8) {
234 switch (boot_cpu_data.x86_vendor) {
235 case X86_VENDOR_INTEL:
236 if (!APIC_XAPIC(ver)) {
237 def_to_bigsmp = 0;
238 break;
239 }
240 /* If P4 and above fall through */
241 case X86_VENDOR_AMD:
242 def_to_bigsmp = 1;
243 }
244 }
245 #ifdef CONFIG_SMP
246 /* are we being called early in kernel startup? */
247 if (x86_cpu_to_apicid_early_ptr) {
248 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
249 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
250
251 cpu_to_apicid[cpu] = m->mpc_apicid;
252 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
253 } else {
254 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
255 per_cpu(x86_bios_cpu_apicid, cpu) = m->mpc_apicid;
256 }
257 #endif
258 cpu_set(cpu, cpu_present_map);
259 }
260
261 static void __init MP_bus_info (struct mpc_config_bus *m)
262 {
263 char str[7];
264
265 memcpy(str, m->mpc_bustype, 6);
266 str[6] = 0;
267
268 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
269
270 #if MAX_MP_BUSSES < 256
271 if (m->mpc_busid >= MAX_MP_BUSSES) {
272 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
273 " is too large, max. supported is %d\n",
274 m->mpc_busid, str, MAX_MP_BUSSES - 1);
275 return;
276 }
277 #endif
278
279 set_bit(m->mpc_busid, mp_bus_not_pci);
280 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
281 #ifdef CONFIG_X86_NUMAQ
282 mpc_oem_pci_bus(m, translation_table[mpc_record]);
283 #endif
284 clear_bit(m->mpc_busid, mp_bus_not_pci);
285 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
286 mp_current_pci_id++;
287 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
288 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
289 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
290 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
291 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
292 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
293 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
294 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
295 } else {
296 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
297 #endif
298 }
299 }
300
301 static int bad_ioapic(unsigned long address)
302 {
303 if (nr_ioapics >= MAX_IO_APICS) {
304 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
305 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
306 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
307 }
308 if (!address) {
309 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
310 " found in table, skipping!\n");
311 return 1;
312 }
313 return 0;
314 }
315
316 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
317 {
318 if (!(m->mpc_flags & MPC_APIC_USABLE))
319 return;
320
321 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
322 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
323
324 if (bad_ioapic(m->mpc_apicaddr))
325 return;
326
327 mp_ioapics[nr_ioapics] = *m;
328 nr_ioapics++;
329 }
330
331 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
332 {
333 mp_irqs [mp_irq_entries] = *m;
334 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
335 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
336 m->mpc_irqtype, m->mpc_irqflag & 3,
337 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
338 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
339 if (++mp_irq_entries == MAX_IRQ_SOURCES)
340 panic("Max # of irq sources exceeded!!\n");
341 }
342
343 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
344 {
345 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
346 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
347 m->mpc_irqtype, m->mpc_irqflag & 3,
348 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
349 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
350 }
351
352 #ifdef CONFIG_X86_NUMAQ
353 static void __init MP_translation_info (struct mpc_config_translation *m)
354 {
355 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
356
357 if (mpc_record >= MAX_MPC_ENTRY)
358 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
359 else
360 translation_table[mpc_record] = m; /* stash this for later */
361 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
362 node_set_online(m->trans_quad);
363 }
364
365 /*
366 * Read/parse the MPC oem tables
367 */
368
369 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
370 unsigned short oemsize)
371 {
372 int count = sizeof (*oemtable); /* the header size */
373 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
374
375 mpc_record = 0;
376 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
377 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
378 {
379 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
380 oemtable->oem_signature[0],
381 oemtable->oem_signature[1],
382 oemtable->oem_signature[2],
383 oemtable->oem_signature[3]);
384 return;
385 }
386 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
387 {
388 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
389 return;
390 }
391 while (count < oemtable->oem_length) {
392 switch (*oemptr) {
393 case MP_TRANSLATION:
394 {
395 struct mpc_config_translation *m=
396 (struct mpc_config_translation *)oemptr;
397 MP_translation_info(m);
398 oemptr += sizeof(*m);
399 count += sizeof(*m);
400 ++mpc_record;
401 break;
402 }
403 default:
404 {
405 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
406 return;
407 }
408 }
409 }
410 }
411
412 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
413 char *productid)
414 {
415 if (strncmp(oem, "IBM NUMA", 8))
416 printk("Warning! May not be a NUMA-Q system!\n");
417 if (mpc->mpc_oemptr)
418 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
419 mpc->mpc_oemsize);
420 }
421 #endif /* CONFIG_X86_NUMAQ */
422
423 /*
424 * Read/parse the MPC
425 */
426
427 static int __init smp_read_mpc(struct mp_config_table *mpc)
428 {
429 char str[16];
430 char oem[10];
431 int count=sizeof(*mpc);
432 unsigned char *mpt=((unsigned char *)mpc)+count;
433
434 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
435 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
436 *(u32 *)mpc->mpc_signature);
437 return 0;
438 }
439 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
440 printk(KERN_ERR "SMP mptable: checksum error!\n");
441 return 0;
442 }
443 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
444 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
445 mpc->mpc_spec);
446 return 0;
447 }
448 if (!mpc->mpc_lapic) {
449 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
450 return 0;
451 }
452 memcpy(oem,mpc->mpc_oem,8);
453 oem[8]=0;
454 printk(KERN_INFO "OEM ID: %s ",oem);
455
456 memcpy(str,mpc->mpc_productid,12);
457 str[12]=0;
458 printk("Product ID: %s ",str);
459
460 mps_oem_check(mpc, oem, str);
461
462 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
463
464 /*
465 * Save the local APIC address (it might be non-default) -- but only
466 * if we're not using ACPI.
467 */
468 if (!acpi_lapic)
469 mp_lapic_addr = mpc->mpc_lapic;
470
471 /*
472 * Now process the configuration blocks.
473 */
474 mpc_record = 0;
475 while (count < mpc->mpc_length) {
476 switch(*mpt) {
477 case MP_PROCESSOR:
478 {
479 struct mpc_config_processor *m=
480 (struct mpc_config_processor *)mpt;
481 /* ACPI may have already provided this data */
482 if (!acpi_lapic)
483 MP_processor_info(m);
484 mpt += sizeof(*m);
485 count += sizeof(*m);
486 break;
487 }
488 case MP_BUS:
489 {
490 struct mpc_config_bus *m=
491 (struct mpc_config_bus *)mpt;
492 MP_bus_info(m);
493 mpt += sizeof(*m);
494 count += sizeof(*m);
495 break;
496 }
497 case MP_IOAPIC:
498 {
499 struct mpc_config_ioapic *m=
500 (struct mpc_config_ioapic *)mpt;
501 MP_ioapic_info(m);
502 mpt+=sizeof(*m);
503 count+=sizeof(*m);
504 break;
505 }
506 case MP_INTSRC:
507 {
508 struct mpc_config_intsrc *m=
509 (struct mpc_config_intsrc *)mpt;
510
511 MP_intsrc_info(m);
512 mpt+=sizeof(*m);
513 count+=sizeof(*m);
514 break;
515 }
516 case MP_LINTSRC:
517 {
518 struct mpc_config_lintsrc *m=
519 (struct mpc_config_lintsrc *)mpt;
520 MP_lintsrc_info(m);
521 mpt+=sizeof(*m);
522 count+=sizeof(*m);
523 break;
524 }
525 default:
526 {
527 count = mpc->mpc_length;
528 break;
529 }
530 }
531 ++mpc_record;
532 }
533 setup_apic_routing();
534 if (!num_processors)
535 printk(KERN_ERR "SMP mptable: no processors registered!\n");
536 return num_processors;
537 }
538
539 static int __init ELCR_trigger(unsigned int irq)
540 {
541 unsigned int port;
542
543 port = 0x4d0 + (irq >> 3);
544 return (inb(port) >> (irq & 7)) & 1;
545 }
546
547 static void __init construct_default_ioirq_mptable(int mpc_default_type)
548 {
549 struct mpc_config_intsrc intsrc;
550 int i;
551 int ELCR_fallback = 0;
552
553 intsrc.mpc_type = MP_INTSRC;
554 intsrc.mpc_irqflag = 0; /* conforming */
555 intsrc.mpc_srcbus = 0;
556 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
557
558 intsrc.mpc_irqtype = mp_INT;
559
560 /*
561 * If true, we have an ISA/PCI system with no IRQ entries
562 * in the MP table. To prevent the PCI interrupts from being set up
563 * incorrectly, we try to use the ELCR. The sanity check to see if
564 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
565 * never be level sensitive, so we simply see if the ELCR agrees.
566 * If it does, we assume it's valid.
567 */
568 if (mpc_default_type == 5) {
569 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
570
571 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
572 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
573 else {
574 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
575 ELCR_fallback = 1;
576 }
577 }
578
579 for (i = 0; i < 16; i++) {
580 switch (mpc_default_type) {
581 case 2:
582 if (i == 0 || i == 13)
583 continue; /* IRQ0 & IRQ13 not connected */
584 /* fall through */
585 default:
586 if (i == 2)
587 continue; /* IRQ2 is never connected */
588 }
589
590 if (ELCR_fallback) {
591 /*
592 * If the ELCR indicates a level-sensitive interrupt, we
593 * copy that information over to the MP table in the
594 * irqflag field (level sensitive, active high polarity).
595 */
596 if (ELCR_trigger(i))
597 intsrc.mpc_irqflag = 13;
598 else
599 intsrc.mpc_irqflag = 0;
600 }
601
602 intsrc.mpc_srcbusirq = i;
603 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
604 MP_intsrc_info(&intsrc);
605 }
606
607 intsrc.mpc_irqtype = mp_ExtINT;
608 intsrc.mpc_srcbusirq = 0;
609 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
610 MP_intsrc_info(&intsrc);
611 }
612
613 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
614 {
615 struct mpc_config_processor processor;
616 struct mpc_config_bus bus;
617 struct mpc_config_ioapic ioapic;
618 struct mpc_config_lintsrc lintsrc;
619 int linttypes[2] = { mp_ExtINT, mp_NMI };
620 int i;
621
622 /*
623 * local APIC has default address
624 */
625 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
626
627 /*
628 * 2 CPUs, numbered 0 & 1.
629 */
630 processor.mpc_type = MP_PROCESSOR;
631 /* Either an integrated APIC or a discrete 82489DX. */
632 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
633 processor.mpc_cpuflag = CPU_ENABLED;
634 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
635 (boot_cpu_data.x86_model << 4) |
636 boot_cpu_data.x86_mask;
637 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
638 processor.mpc_reserved[0] = 0;
639 processor.mpc_reserved[1] = 0;
640 for (i = 0; i < 2; i++) {
641 processor.mpc_apicid = i;
642 MP_processor_info(&processor);
643 }
644
645 bus.mpc_type = MP_BUS;
646 bus.mpc_busid = 0;
647 switch (mpc_default_type) {
648 default:
649 printk("???\n");
650 printk(KERN_ERR "Unknown standard configuration %d\n",
651 mpc_default_type);
652 /* fall through */
653 case 1:
654 case 5:
655 memcpy(bus.mpc_bustype, "ISA ", 6);
656 break;
657 case 2:
658 case 6:
659 case 3:
660 memcpy(bus.mpc_bustype, "EISA ", 6);
661 break;
662 case 4:
663 case 7:
664 memcpy(bus.mpc_bustype, "MCA ", 6);
665 }
666 MP_bus_info(&bus);
667 if (mpc_default_type > 4) {
668 bus.mpc_busid = 1;
669 memcpy(bus.mpc_bustype, "PCI ", 6);
670 MP_bus_info(&bus);
671 }
672
673 ioapic.mpc_type = MP_IOAPIC;
674 ioapic.mpc_apicid = 2;
675 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
676 ioapic.mpc_flags = MPC_APIC_USABLE;
677 ioapic.mpc_apicaddr = 0xFEC00000;
678 MP_ioapic_info(&ioapic);
679
680 /*
681 * We set up most of the low 16 IO-APIC pins according to MPS rules.
682 */
683 construct_default_ioirq_mptable(mpc_default_type);
684
685 lintsrc.mpc_type = MP_LINTSRC;
686 lintsrc.mpc_irqflag = 0; /* conforming */
687 lintsrc.mpc_srcbusid = 0;
688 lintsrc.mpc_srcbusirq = 0;
689 lintsrc.mpc_destapic = MP_APIC_ALL;
690 for (i = 0; i < 2; i++) {
691 lintsrc.mpc_irqtype = linttypes[i];
692 lintsrc.mpc_destapiclint = i;
693 MP_lintsrc_info(&lintsrc);
694 }
695 }
696
697 static struct intel_mp_floating *mpf_found;
698
699 /*
700 * Scan the memory blocks for an SMP configuration block.
701 */
702 void __init get_smp_config (void)
703 {
704 struct intel_mp_floating *mpf = mpf_found;
705
706 /*
707 * ACPI supports both logical (e.g. Hyper-Threading) and physical
708 * processors, where MPS only supports physical.
709 */
710 if (acpi_lapic && acpi_ioapic) {
711 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
712 return;
713 }
714 else if (acpi_lapic)
715 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
716
717 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
718 if (mpf->mpf_feature2 & (1<<7)) {
719 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
720 pic_mode = 1;
721 } else {
722 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
723 pic_mode = 0;
724 }
725
726 /*
727 * Now see if we need to read further.
728 */
729 if (mpf->mpf_feature1 != 0) {
730
731 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
732 construct_default_ISA_mptable(mpf->mpf_feature1);
733
734 } else if (mpf->mpf_physptr) {
735
736 /*
737 * Read the physical hardware table. Anything here will
738 * override the defaults.
739 */
740 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
741 smp_found_config = 0;
742 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
743 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
744 return;
745 }
746 /*
747 * If there are no explicit MP IRQ entries, then we are
748 * broken. We set up most of the low 16 IO-APIC pins to
749 * ISA defaults and hope it will work.
750 */
751 if (!mp_irq_entries) {
752 struct mpc_config_bus bus;
753
754 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
755
756 bus.mpc_type = MP_BUS;
757 bus.mpc_busid = 0;
758 memcpy(bus.mpc_bustype, "ISA ", 6);
759 MP_bus_info(&bus);
760
761 construct_default_ioirq_mptable(0);
762 }
763
764 } else
765 BUG();
766
767 printk(KERN_INFO "Processors: %d\n", num_processors);
768 /*
769 * Only use the first configuration found.
770 */
771 }
772
773 static int __init smp_scan_config (unsigned long base, unsigned long length)
774 {
775 unsigned long *bp = phys_to_virt(base);
776 struct intel_mp_floating *mpf;
777
778 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
779 if (sizeof(*mpf) != 16)
780 printk("Error: MPF size\n");
781
782 while (length > 0) {
783 mpf = (struct intel_mp_floating *)bp;
784 if ((*bp == SMP_MAGIC_IDENT) &&
785 (mpf->mpf_length == 1) &&
786 !mpf_checksum((unsigned char *)bp, 16) &&
787 ((mpf->mpf_specification == 1)
788 || (mpf->mpf_specification == 4)) ) {
789
790 smp_found_config = 1;
791 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
792 mpf, virt_to_phys(mpf));
793 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
794 BOOTMEM_DEFAULT);
795 if (mpf->mpf_physptr) {
796 /*
797 * We cannot access to MPC table to compute
798 * table size yet, as only few megabytes from
799 * the bottom is mapped now.
800 * PC-9800's MPC table places on the very last
801 * of physical memory; so that simply reserving
802 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
803 * in reserve_bootmem.
804 */
805 unsigned long size = PAGE_SIZE;
806 unsigned long end = max_low_pfn * PAGE_SIZE;
807 if (mpf->mpf_physptr + size > end)
808 size = end - mpf->mpf_physptr;
809 reserve_bootmem(mpf->mpf_physptr, size,
810 BOOTMEM_DEFAULT);
811 }
812
813 mpf_found = mpf;
814 return 1;
815 }
816 bp += 4;
817 length -= 16;
818 }
819 return 0;
820 }
821
822 void __init find_smp_config (void)
823 {
824 unsigned int address;
825
826 /*
827 * FIXME: Linux assumes you have 640K of base ram..
828 * this continues the error...
829 *
830 * 1) Scan the bottom 1K for a signature
831 * 2) Scan the top 1K of base RAM
832 * 3) Scan the 64K of bios
833 */
834 if (smp_scan_config(0x0,0x400) ||
835 smp_scan_config(639*0x400,0x400) ||
836 smp_scan_config(0xF0000,0x10000))
837 return;
838 /*
839 * If it is an SMP machine we should know now, unless the
840 * configuration is in an EISA/MCA bus machine with an
841 * extended bios data area.
842 *
843 * there is a real-mode segmented pointer pointing to the
844 * 4K EBDA area at 0x40E, calculate and scan it here.
845 *
846 * NOTE! There are Linux loaders that will corrupt the EBDA
847 * area, and as such this kind of SMP config may be less
848 * trustworthy, simply because the SMP table may have been
849 * stomped on during early boot. These loaders are buggy and
850 * should be fixed.
851 *
852 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
853 */
854
855 address = get_bios_ebda();
856 if (address)
857 smp_scan_config(address, 0x400);
858 }
859
860 int es7000_plat;
861
862 /* --------------------------------------------------------------------------
863 ACPI-based MP Configuration
864 -------------------------------------------------------------------------- */
865
866 #ifdef CONFIG_ACPI
867
868 void __init mp_register_lapic_address(u64 address)
869 {
870 mp_lapic_addr = (unsigned long) address;
871
872 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
873
874 if (boot_cpu_physical_apicid == -1U)
875 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
876
877 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
878 }
879
880 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
881 {
882 struct mpc_config_processor processor;
883 int boot_cpu = 0;
884
885 if (MAX_APICS - id <= 0) {
886 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
887 id, MAX_APICS);
888 return;
889 }
890
891 if (id == boot_cpu_physical_apicid)
892 boot_cpu = 1;
893
894 processor.mpc_type = MP_PROCESSOR;
895 processor.mpc_apicid = id;
896 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
897 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
898 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
899 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
900 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
901 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
902 processor.mpc_reserved[0] = 0;
903 processor.mpc_reserved[1] = 0;
904
905 MP_processor_info(&processor);
906 }
907
908 #ifdef CONFIG_X86_IO_APIC
909
910 #define MP_ISA_BUS 0
911 #define MP_MAX_IOAPIC_PIN 127
912
913 static struct mp_ioapic_routing {
914 int apic_id;
915 int gsi_base;
916 int gsi_end;
917 u32 pin_programmed[4];
918 } mp_ioapic_routing[MAX_IO_APICS];
919
920 static int mp_find_ioapic (int gsi)
921 {
922 int i = 0;
923
924 /* Find the IOAPIC that manages this GSI. */
925 for (i = 0; i < nr_ioapics; i++) {
926 if ((gsi >= mp_ioapic_routing[i].gsi_base)
927 && (gsi <= mp_ioapic_routing[i].gsi_end))
928 return i;
929 }
930
931 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
932
933 return -1;
934 }
935
936 static u8 uniq_ioapic_id(u8 id)
937 {
938 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
939 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
940 return io_apic_get_unique_id(nr_ioapics, id);
941 else
942 return id;
943 }
944
945 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
946 {
947 int idx = 0;
948
949 if (bad_ioapic(address))
950 return;
951
952 idx = nr_ioapics;
953
954 mp_ioapics[idx].mpc_type = MP_IOAPIC;
955 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
956 mp_ioapics[idx].mpc_apicaddr = address;
957
958 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
959 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
960 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
961
962 /*
963 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
964 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
965 */
966 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
967 mp_ioapic_routing[idx].gsi_base = gsi_base;
968 mp_ioapic_routing[idx].gsi_end = gsi_base +
969 io_apic_get_redir_entries(idx);
970
971 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
972 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
973 mp_ioapics[idx].mpc_apicver,
974 mp_ioapics[idx].mpc_apicaddr,
975 mp_ioapic_routing[idx].gsi_base,
976 mp_ioapic_routing[idx].gsi_end);
977
978 nr_ioapics++;
979 }
980
981 void __init
982 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
983 {
984 struct mpc_config_intsrc intsrc;
985 int ioapic = -1;
986 int pin = -1;
987
988 /*
989 * Convert 'gsi' to 'ioapic.pin'.
990 */
991 ioapic = mp_find_ioapic(gsi);
992 if (ioapic < 0)
993 return;
994 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
995
996 /*
997 * TBD: This check is for faulty timer entries, where the override
998 * erroneously sets the trigger to level, resulting in a HUGE
999 * increase of timer interrupts!
1000 */
1001 if ((bus_irq == 0) && (trigger == 3))
1002 trigger = 1;
1003
1004 intsrc.mpc_type = MP_INTSRC;
1005 intsrc.mpc_irqtype = mp_INT;
1006 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1007 intsrc.mpc_srcbus = MP_ISA_BUS;
1008 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1009 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1010 intsrc.mpc_dstirq = pin; /* INTIN# */
1011
1012 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1013 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1014 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1015 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1016
1017 mp_irqs[mp_irq_entries] = intsrc;
1018 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1019 panic("Max # of irq sources exceeded!\n");
1020 }
1021
1022 void __init mp_config_acpi_legacy_irqs (void)
1023 {
1024 struct mpc_config_intsrc intsrc;
1025 int i = 0;
1026 int ioapic = -1;
1027
1028 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1029 /*
1030 * Fabricate the legacy ISA bus (bus #31).
1031 */
1032 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1033 #endif
1034 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1035 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1036
1037 /*
1038 * Older generations of ES7000 have no legacy identity mappings
1039 */
1040 if (es7000_plat == 1)
1041 return;
1042
1043 /*
1044 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1045 */
1046 ioapic = mp_find_ioapic(0);
1047 if (ioapic < 0)
1048 return;
1049
1050 intsrc.mpc_type = MP_INTSRC;
1051 intsrc.mpc_irqflag = 0; /* Conforming */
1052 intsrc.mpc_srcbus = MP_ISA_BUS;
1053 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1054
1055 /*
1056 * Use the default configuration for the IRQs 0-15. Unless
1057 * overridden by (MADT) interrupt source override entries.
1058 */
1059 for (i = 0; i < 16; i++) {
1060 int idx;
1061
1062 for (idx = 0; idx < mp_irq_entries; idx++) {
1063 struct mpc_config_intsrc *irq = mp_irqs + idx;
1064
1065 /* Do we already have a mapping for this ISA IRQ? */
1066 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1067 break;
1068
1069 /* Do we already have a mapping for this IOAPIC pin */
1070 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1071 (irq->mpc_dstirq == i))
1072 break;
1073 }
1074
1075 if (idx != mp_irq_entries) {
1076 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1077 continue; /* IRQ already used */
1078 }
1079
1080 intsrc.mpc_irqtype = mp_INT;
1081 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1082 intsrc.mpc_dstirq = i;
1083
1084 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1085 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1086 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1087 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1088 intsrc.mpc_dstirq);
1089
1090 mp_irqs[mp_irq_entries] = intsrc;
1091 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1092 panic("Max # of irq sources exceeded!\n");
1093 }
1094 }
1095
1096 #define MAX_GSI_NUM 4096
1097 #define IRQ_COMPRESSION_START 64
1098
1099 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1100 {
1101 int ioapic = -1;
1102 int ioapic_pin = 0;
1103 int idx, bit = 0;
1104 static int pci_irq = IRQ_COMPRESSION_START;
1105 /*
1106 * Mapping between Global System Interrupts, which
1107 * represent all possible interrupts, and IRQs
1108 * assigned to actual devices.
1109 */
1110 static int gsi_to_irq[MAX_GSI_NUM];
1111
1112 /* Don't set up the ACPI SCI because it's already set up */
1113 if (acpi_gbl_FADT.sci_interrupt == gsi)
1114 return gsi;
1115
1116 ioapic = mp_find_ioapic(gsi);
1117 if (ioapic < 0) {
1118 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1119 return gsi;
1120 }
1121
1122 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1123
1124 if (ioapic_renumber_irq)
1125 gsi = ioapic_renumber_irq(ioapic, gsi);
1126
1127 /*
1128 * Avoid pin reprogramming. PRTs typically include entries
1129 * with redundant pin->gsi mappings (but unique PCI devices);
1130 * we only program the IOAPIC on the first.
1131 */
1132 bit = ioapic_pin % 32;
1133 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1134 if (idx > 3) {
1135 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1136 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1137 ioapic_pin);
1138 return gsi;
1139 }
1140 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1141 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1142 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1143 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1144 }
1145
1146 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1147
1148 /*
1149 * For GSI >= 64, use IRQ compression
1150 */
1151 if ((gsi >= IRQ_COMPRESSION_START)
1152 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1153 /*
1154 * For PCI devices assign IRQs in order, avoiding gaps
1155 * due to unused I/O APIC pins.
1156 */
1157 int irq = gsi;
1158 if (gsi < MAX_GSI_NUM) {
1159 /*
1160 * Retain the VIA chipset work-around (gsi > 15), but
1161 * avoid a problem where the 8254 timer (IRQ0) is setup
1162 * via an override (so it's not on pin 0 of the ioapic),
1163 * and at the same time, the pin 0 interrupt is a PCI
1164 * type. The gsi > 15 test could cause these two pins
1165 * to be shared as IRQ0, and they are not shareable.
1166 * So test for this condition, and if necessary, avoid
1167 * the pin collision.
1168 */
1169 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
1170 gsi = pci_irq++;
1171 /*
1172 * Don't assign IRQ used by ACPI SCI
1173 */
1174 if (gsi == acpi_gbl_FADT.sci_interrupt)
1175 gsi = pci_irq++;
1176 gsi_to_irq[irq] = gsi;
1177 } else {
1178 printk(KERN_ERR "GSI %u is too high\n", gsi);
1179 return gsi;
1180 }
1181 }
1182
1183 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1184 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1185 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1186 return gsi;
1187 }
1188
1189 #endif /* CONFIG_X86_IO_APIC */
1190 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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