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x86: mpparse, move boot cpu physical apicid to apic_32.c, fix
[deliverable/linux.git] / arch / x86 / kernel / mpparse_32.c
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
24
25 #include <asm/smp.h>
26 #include <asm/acpi.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
31
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
35
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
46 #endif
47 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 static int mp_current_pci_id;
50
51 /* I/O APIC entries */
52 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53
54 /* # of MP IRQ source entries */
55 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56
57 /* MP IRQ source entries */
58 int mp_irq_entries;
59
60 int nr_ioapics;
61
62 int pic_mode;
63
64 /* Make it easy to share the UP and SMP code: */
65 #ifndef CONFIG_X86_SMP
66 unsigned int num_processors;
67 unsigned disabled_cpus __cpuinitdata;
68 #ifndef CONFIG_X86_LOCAL_APIC
69 unsigned int boot_cpu_physical_apicid = -1U;
70 #endif
71 #endif
72
73 /* Make it easy to share the UP and SMP code: */
74 #ifndef CONFIG_X86_SMP
75 physid_mask_t phys_cpu_present_map;
76 #endif
77
78 #ifndef CONFIG_SMP
79 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
80 #endif
81
82 /*
83 * Intel MP BIOS table parsing routines:
84 */
85
86
87 /*
88 * Checksum an MP configuration block.
89 */
90
91 static int __init mpf_checksum(unsigned char *mp, int len)
92 {
93 int sum = 0;
94
95 while (len--)
96 sum += *mp++;
97
98 return sum & 0xFF;
99 }
100
101 #ifdef CONFIG_X86_NUMAQ
102 /*
103 * Have to match translation table entries to main table entries by counter
104 * hence the mpc_record variable .... can't see a less disgusting way of
105 * doing this ....
106 */
107
108 static int mpc_record;
109 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
110 #endif
111
112 static void __cpuinit generic_processor_info(int apicid, int version)
113 {
114 int cpu;
115 cpumask_t tmp_map;
116 physid_mask_t phys_cpu;
117
118 /*
119 * Validate version
120 */
121 if (version == 0x0) {
122 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
123 "fixing up to 0x10. (tell your hw vendor)\n",
124 version);
125 version = 0x10;
126 }
127 apic_version[apicid] = version;
128
129 phys_cpu = apicid_to_cpu_present(apicid);
130 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
131
132 if (num_processors >= NR_CPUS) {
133 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
134 " Processor ignored.\n", NR_CPUS);
135 return;
136 }
137
138 if (num_processors >= maxcpus) {
139 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
140 " Processor ignored.\n", maxcpus);
141 return;
142 }
143
144 num_processors++;
145 cpus_complement(tmp_map, cpu_present_map);
146 cpu = first_cpu(tmp_map);
147
148 if (apicid == boot_cpu_physical_apicid)
149 /*
150 * x86_bios_cpu_apicid is required to have processors listed
151 * in same order as logical cpu numbers. Hence the first
152 * entry is BSP, and so on.
153 */
154 cpu = 0;
155
156 /*
157 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
158 * but we need to work other dependencies like SMP_SUSPEND etc
159 * before this can be done without some confusion.
160 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
161 * - Ashok Raj <ashok.raj@intel.com>
162 */
163 if (num_processors > 8) {
164 switch (boot_cpu_data.x86_vendor) {
165 case X86_VENDOR_INTEL:
166 if (!APIC_XAPIC(version)) {
167 def_to_bigsmp = 0;
168 break;
169 }
170 /* If P4 and above fall through */
171 case X86_VENDOR_AMD:
172 def_to_bigsmp = 1;
173 }
174 }
175 #ifdef CONFIG_SMP
176 /* are we being called early in kernel startup? */
177 if (x86_cpu_to_apicid_early_ptr) {
178 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
179 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
180
181 cpu_to_apicid[cpu] = apicid;
182 bios_cpu_apicid[cpu] = apicid;
183 } else {
184 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
185 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
186 }
187 #endif
188 cpu_set(cpu, cpu_possible_map);
189 cpu_set(cpu, cpu_present_map);
190 }
191
192 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
193 {
194 int apicid;
195
196 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
197 #ifdef CONFIG_X86_SMP
198 disabled_cpus++;
199 #endif
200 return;
201 }
202
203 #ifdef CONFIG_X86_NUMAQ
204 apicid = mpc_apic_id(m, translation_table[mpc_record]);
205 #else
206 Dprintk("Processor #%d %u:%u APIC version %d\n",
207 m->mpc_apicid,
208 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
209 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
210 m->mpc_apicver);
211 apicid = m->mpc_apicid;
212 #endif
213
214 if (m->mpc_featureflag&(1<<0))
215 Dprintk(" Floating point unit present.\n");
216 if (m->mpc_featureflag&(1<<7))
217 Dprintk(" Machine Exception supported.\n");
218 if (m->mpc_featureflag&(1<<8))
219 Dprintk(" 64 bit compare & exchange supported.\n");
220 if (m->mpc_featureflag&(1<<9))
221 Dprintk(" Internal APIC present.\n");
222 if (m->mpc_featureflag&(1<<11))
223 Dprintk(" SEP present.\n");
224 if (m->mpc_featureflag&(1<<12))
225 Dprintk(" MTRR present.\n");
226 if (m->mpc_featureflag&(1<<13))
227 Dprintk(" PGE present.\n");
228 if (m->mpc_featureflag&(1<<14))
229 Dprintk(" MCA present.\n");
230 if (m->mpc_featureflag&(1<<15))
231 Dprintk(" CMOV present.\n");
232 if (m->mpc_featureflag&(1<<16))
233 Dprintk(" PAT present.\n");
234 if (m->mpc_featureflag&(1<<17))
235 Dprintk(" PSE present.\n");
236 if (m->mpc_featureflag&(1<<18))
237 Dprintk(" PSN present.\n");
238 if (m->mpc_featureflag&(1<<19))
239 Dprintk(" Cache Line Flush Instruction present.\n");
240 /* 20 Reserved */
241 if (m->mpc_featureflag&(1<<21))
242 Dprintk(" Debug Trace and EMON Store present.\n");
243 if (m->mpc_featureflag&(1<<22))
244 Dprintk(" ACPI Thermal Throttle Registers present.\n");
245 if (m->mpc_featureflag&(1<<23))
246 Dprintk(" MMX present.\n");
247 if (m->mpc_featureflag&(1<<24))
248 Dprintk(" FXSR present.\n");
249 if (m->mpc_featureflag&(1<<25))
250 Dprintk(" XMM present.\n");
251 if (m->mpc_featureflag&(1<<26))
252 Dprintk(" Willamette New Instructions present.\n");
253 if (m->mpc_featureflag&(1<<27))
254 Dprintk(" Self Snoop present.\n");
255 if (m->mpc_featureflag&(1<<28))
256 Dprintk(" HT present.\n");
257 if (m->mpc_featureflag&(1<<29))
258 Dprintk(" Thermal Monitor present.\n");
259 /* 30, 31 Reserved */
260
261
262 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
263 Dprintk(" Bootup CPU\n");
264 boot_cpu_physical_apicid = m->mpc_apicid;
265 }
266
267 generic_processor_info(apicid, m->mpc_apicver);
268 }
269
270 static void __init MP_bus_info (struct mpc_config_bus *m)
271 {
272 char str[7];
273
274 memcpy(str, m->mpc_bustype, 6);
275 str[6] = 0;
276
277 #ifdef CONFIG_X86_NUMAQ
278 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
279 #else
280 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
281 #endif
282
283 #if MAX_MP_BUSSES < 256
284 if (m->mpc_busid >= MAX_MP_BUSSES) {
285 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
286 " is too large, max. supported is %d\n",
287 m->mpc_busid, str, MAX_MP_BUSSES - 1);
288 return;
289 }
290 #endif
291
292 set_bit(m->mpc_busid, mp_bus_not_pci);
293 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
294 #ifdef CONFIG_X86_NUMAQ
295 mpc_oem_pci_bus(m, translation_table[mpc_record]);
296 #endif
297 clear_bit(m->mpc_busid, mp_bus_not_pci);
298 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
299 mp_current_pci_id++;
300 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
301 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
302 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
303 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
304 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
305 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
306 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
307 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
308 } else {
309 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
310 #endif
311 }
312 }
313
314 static int bad_ioapic(unsigned long address)
315 {
316 if (nr_ioapics >= MAX_IO_APICS) {
317 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
318 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
319 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
320 }
321 if (!address) {
322 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
323 " found in table, skipping!\n");
324 return 1;
325 }
326 return 0;
327 }
328
329 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
330 {
331 if (!(m->mpc_flags & MPC_APIC_USABLE))
332 return;
333
334 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
335 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
336
337 if (bad_ioapic(m->mpc_apicaddr))
338 return;
339
340 mp_ioapics[nr_ioapics] = *m;
341 nr_ioapics++;
342 }
343
344 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
345 {
346 mp_irqs [mp_irq_entries] = *m;
347 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
348 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
349 m->mpc_irqtype, m->mpc_irqflag & 3,
350 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
351 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
352 if (++mp_irq_entries == MAX_IRQ_SOURCES)
353 panic("Max # of irq sources exceeded!!\n");
354 }
355
356 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
357 {
358 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
359 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
360 m->mpc_irqtype, m->mpc_irqflag & 3,
361 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
362 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
363 }
364
365 #ifdef CONFIG_X86_NUMAQ
366 static void __init MP_translation_info (struct mpc_config_translation *m)
367 {
368 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
369
370 if (mpc_record >= MAX_MPC_ENTRY)
371 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
372 else
373 translation_table[mpc_record] = m; /* stash this for later */
374 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
375 node_set_online(m->trans_quad);
376 }
377
378 /*
379 * Read/parse the MPC oem tables
380 */
381
382 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
383 unsigned short oemsize)
384 {
385 int count = sizeof (*oemtable); /* the header size */
386 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
387
388 mpc_record = 0;
389 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
390 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
391 {
392 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
393 oemtable->oem_signature[0],
394 oemtable->oem_signature[1],
395 oemtable->oem_signature[2],
396 oemtable->oem_signature[3]);
397 return;
398 }
399 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
400 {
401 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
402 return;
403 }
404 while (count < oemtable->oem_length) {
405 switch (*oemptr) {
406 case MP_TRANSLATION:
407 {
408 struct mpc_config_translation *m=
409 (struct mpc_config_translation *)oemptr;
410 MP_translation_info(m);
411 oemptr += sizeof(*m);
412 count += sizeof(*m);
413 ++mpc_record;
414 break;
415 }
416 default:
417 {
418 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
419 return;
420 }
421 }
422 }
423 }
424
425 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
426 char *productid)
427 {
428 if (strncmp(oem, "IBM NUMA", 8))
429 printk("Warning! May not be a NUMA-Q system!\n");
430 if (mpc->mpc_oemptr)
431 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
432 mpc->mpc_oemsize);
433 }
434 #endif /* CONFIG_X86_NUMAQ */
435
436 /*
437 * Read/parse the MPC
438 */
439
440 static int __init smp_read_mpc(struct mp_config_table *mpc)
441 {
442 char str[16];
443 char oem[10];
444 int count=sizeof(*mpc);
445 unsigned char *mpt=((unsigned char *)mpc)+count;
446
447 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
448 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
449 *(u32 *)mpc->mpc_signature);
450 return 0;
451 }
452 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
453 printk(KERN_ERR "SMP mptable: checksum error!\n");
454 return 0;
455 }
456 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
457 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
458 mpc->mpc_spec);
459 return 0;
460 }
461 if (!mpc->mpc_lapic) {
462 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
463 return 0;
464 }
465 memcpy(oem,mpc->mpc_oem,8);
466 oem[8]=0;
467 printk(KERN_INFO "OEM ID: %s ",oem);
468
469 memcpy(str,mpc->mpc_productid,12);
470 str[12]=0;
471 printk("Product ID: %s ",str);
472
473 mps_oem_check(mpc, oem, str);
474
475 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
476
477 /*
478 * Save the local APIC address (it might be non-default) -- but only
479 * if we're not using ACPI.
480 */
481 if (!acpi_lapic)
482 mp_lapic_addr = mpc->mpc_lapic;
483
484 /*
485 * Now process the configuration blocks.
486 */
487 #ifdef CONFIG_X86_NUMAQ
488 mpc_record = 0;
489 #endif
490 while (count < mpc->mpc_length) {
491 switch(*mpt) {
492 case MP_PROCESSOR:
493 {
494 struct mpc_config_processor *m=
495 (struct mpc_config_processor *)mpt;
496 /* ACPI may have already provided this data */
497 if (!acpi_lapic)
498 MP_processor_info(m);
499 mpt += sizeof(*m);
500 count += sizeof(*m);
501 break;
502 }
503 case MP_BUS:
504 {
505 struct mpc_config_bus *m=
506 (struct mpc_config_bus *)mpt;
507 MP_bus_info(m);
508 mpt += sizeof(*m);
509 count += sizeof(*m);
510 break;
511 }
512 case MP_IOAPIC:
513 {
514 struct mpc_config_ioapic *m=
515 (struct mpc_config_ioapic *)mpt;
516 MP_ioapic_info(m);
517 mpt+=sizeof(*m);
518 count+=sizeof(*m);
519 break;
520 }
521 case MP_INTSRC:
522 {
523 struct mpc_config_intsrc *m=
524 (struct mpc_config_intsrc *)mpt;
525
526 MP_intsrc_info(m);
527 mpt+=sizeof(*m);
528 count+=sizeof(*m);
529 break;
530 }
531 case MP_LINTSRC:
532 {
533 struct mpc_config_lintsrc *m=
534 (struct mpc_config_lintsrc *)mpt;
535 MP_lintsrc_info(m);
536 mpt+=sizeof(*m);
537 count+=sizeof(*m);
538 break;
539 }
540 default:
541 {
542 count = mpc->mpc_length;
543 break;
544 }
545 }
546 #ifdef CONFIG_X86_NUMAQ
547 ++mpc_record;
548 #endif
549 }
550 setup_apic_routing();
551 if (!num_processors)
552 printk(KERN_ERR "SMP mptable: no processors registered!\n");
553 return num_processors;
554 }
555
556 static int __init ELCR_trigger(unsigned int irq)
557 {
558 unsigned int port;
559
560 port = 0x4d0 + (irq >> 3);
561 return (inb(port) >> (irq & 7)) & 1;
562 }
563
564 static void __init construct_default_ioirq_mptable(int mpc_default_type)
565 {
566 struct mpc_config_intsrc intsrc;
567 int i;
568 int ELCR_fallback = 0;
569
570 intsrc.mpc_type = MP_INTSRC;
571 intsrc.mpc_irqflag = 0; /* conforming */
572 intsrc.mpc_srcbus = 0;
573 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
574
575 intsrc.mpc_irqtype = mp_INT;
576
577 /*
578 * If true, we have an ISA/PCI system with no IRQ entries
579 * in the MP table. To prevent the PCI interrupts from being set up
580 * incorrectly, we try to use the ELCR. The sanity check to see if
581 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
582 * never be level sensitive, so we simply see if the ELCR agrees.
583 * If it does, we assume it's valid.
584 */
585 if (mpc_default_type == 5) {
586 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
587
588 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
589 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
590 else {
591 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
592 ELCR_fallback = 1;
593 }
594 }
595
596 for (i = 0; i < 16; i++) {
597 switch (mpc_default_type) {
598 case 2:
599 if (i == 0 || i == 13)
600 continue; /* IRQ0 & IRQ13 not connected */
601 /* fall through */
602 default:
603 if (i == 2)
604 continue; /* IRQ2 is never connected */
605 }
606
607 if (ELCR_fallback) {
608 /*
609 * If the ELCR indicates a level-sensitive interrupt, we
610 * copy that information over to the MP table in the
611 * irqflag field (level sensitive, active high polarity).
612 */
613 if (ELCR_trigger(i))
614 intsrc.mpc_irqflag = 13;
615 else
616 intsrc.mpc_irqflag = 0;
617 }
618
619 intsrc.mpc_srcbusirq = i;
620 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
621 MP_intsrc_info(&intsrc);
622 }
623
624 intsrc.mpc_irqtype = mp_ExtINT;
625 intsrc.mpc_srcbusirq = 0;
626 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
627 MP_intsrc_info(&intsrc);
628 }
629
630 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
631 {
632 struct mpc_config_processor processor;
633 struct mpc_config_bus bus;
634 struct mpc_config_ioapic ioapic;
635 struct mpc_config_lintsrc lintsrc;
636 int linttypes[2] = { mp_ExtINT, mp_NMI };
637 int i;
638
639 /*
640 * local APIC has default address
641 */
642 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
643
644 /*
645 * 2 CPUs, numbered 0 & 1.
646 */
647 processor.mpc_type = MP_PROCESSOR;
648 /* Either an integrated APIC or a discrete 82489DX. */
649 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
650 processor.mpc_cpuflag = CPU_ENABLED;
651 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
652 (boot_cpu_data.x86_model << 4) |
653 boot_cpu_data.x86_mask;
654 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
655 processor.mpc_reserved[0] = 0;
656 processor.mpc_reserved[1] = 0;
657 for (i = 0; i < 2; i++) {
658 processor.mpc_apicid = i;
659 MP_processor_info(&processor);
660 }
661
662 bus.mpc_type = MP_BUS;
663 bus.mpc_busid = 0;
664 switch (mpc_default_type) {
665 default:
666 printk("???\n");
667 printk(KERN_ERR "Unknown standard configuration %d\n",
668 mpc_default_type);
669 /* fall through */
670 case 1:
671 case 5:
672 memcpy(bus.mpc_bustype, "ISA ", 6);
673 break;
674 case 2:
675 case 6:
676 case 3:
677 memcpy(bus.mpc_bustype, "EISA ", 6);
678 break;
679 case 4:
680 case 7:
681 memcpy(bus.mpc_bustype, "MCA ", 6);
682 }
683 MP_bus_info(&bus);
684 if (mpc_default_type > 4) {
685 bus.mpc_busid = 1;
686 memcpy(bus.mpc_bustype, "PCI ", 6);
687 MP_bus_info(&bus);
688 }
689
690 ioapic.mpc_type = MP_IOAPIC;
691 ioapic.mpc_apicid = 2;
692 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
693 ioapic.mpc_flags = MPC_APIC_USABLE;
694 ioapic.mpc_apicaddr = 0xFEC00000;
695 MP_ioapic_info(&ioapic);
696
697 /*
698 * We set up most of the low 16 IO-APIC pins according to MPS rules.
699 */
700 construct_default_ioirq_mptable(mpc_default_type);
701
702 lintsrc.mpc_type = MP_LINTSRC;
703 lintsrc.mpc_irqflag = 0; /* conforming */
704 lintsrc.mpc_srcbusid = 0;
705 lintsrc.mpc_srcbusirq = 0;
706 lintsrc.mpc_destapic = MP_APIC_ALL;
707 for (i = 0; i < 2; i++) {
708 lintsrc.mpc_irqtype = linttypes[i];
709 lintsrc.mpc_destapiclint = i;
710 MP_lintsrc_info(&lintsrc);
711 }
712 }
713
714 static struct intel_mp_floating *mpf_found;
715
716 /*
717 * Scan the memory blocks for an SMP configuration block.
718 */
719 void __init get_smp_config (void)
720 {
721 struct intel_mp_floating *mpf = mpf_found;
722
723 /*
724 * ACPI supports both logical (e.g. Hyper-Threading) and physical
725 * processors, where MPS only supports physical.
726 */
727 if (acpi_lapic && acpi_ioapic) {
728 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
729 return;
730 }
731 else if (acpi_lapic)
732 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
733
734 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
735 if (mpf->mpf_feature2 & (1<<7)) {
736 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
737 pic_mode = 1;
738 } else {
739 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
740 pic_mode = 0;
741 }
742
743 /*
744 * Now see if we need to read further.
745 */
746 if (mpf->mpf_feature1 != 0) {
747
748 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
749 construct_default_ISA_mptable(mpf->mpf_feature1);
750
751 } else if (mpf->mpf_physptr) {
752
753 /*
754 * Read the physical hardware table. Anything here will
755 * override the defaults.
756 */
757 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
758 smp_found_config = 0;
759 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
760 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
761 return;
762 }
763 /*
764 * If there are no explicit MP IRQ entries, then we are
765 * broken. We set up most of the low 16 IO-APIC pins to
766 * ISA defaults and hope it will work.
767 */
768 if (!mp_irq_entries) {
769 struct mpc_config_bus bus;
770
771 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
772
773 bus.mpc_type = MP_BUS;
774 bus.mpc_busid = 0;
775 memcpy(bus.mpc_bustype, "ISA ", 6);
776 MP_bus_info(&bus);
777
778 construct_default_ioirq_mptable(0);
779 }
780
781 } else
782 BUG();
783
784 printk(KERN_INFO "Processors: %d\n", num_processors);
785 /*
786 * Only use the first configuration found.
787 */
788 }
789
790 static int __init smp_scan_config (unsigned long base, unsigned long length)
791 {
792 unsigned long *bp = phys_to_virt(base);
793 struct intel_mp_floating *mpf;
794
795 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
796 if (sizeof(*mpf) != 16)
797 printk("Error: MPF size\n");
798
799 while (length > 0) {
800 mpf = (struct intel_mp_floating *)bp;
801 if ((*bp == SMP_MAGIC_IDENT) &&
802 (mpf->mpf_length == 1) &&
803 !mpf_checksum((unsigned char *)bp, 16) &&
804 ((mpf->mpf_specification == 1)
805 || (mpf->mpf_specification == 4)) ) {
806
807 smp_found_config = 1;
808 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
809 mpf, virt_to_phys(mpf));
810 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
811 BOOTMEM_DEFAULT);
812 if (mpf->mpf_physptr) {
813 /*
814 * We cannot access to MPC table to compute
815 * table size yet, as only few megabytes from
816 * the bottom is mapped now.
817 * PC-9800's MPC table places on the very last
818 * of physical memory; so that simply reserving
819 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
820 * in reserve_bootmem.
821 */
822 unsigned long size = PAGE_SIZE;
823 unsigned long end = max_low_pfn * PAGE_SIZE;
824 if (mpf->mpf_physptr + size > end)
825 size = end - mpf->mpf_physptr;
826 reserve_bootmem(mpf->mpf_physptr, size,
827 BOOTMEM_DEFAULT);
828 }
829
830 mpf_found = mpf;
831 return 1;
832 }
833 bp += 4;
834 length -= 16;
835 }
836 return 0;
837 }
838
839 void __init find_smp_config (void)
840 {
841 unsigned int address;
842
843 /*
844 * FIXME: Linux assumes you have 640K of base ram..
845 * this continues the error...
846 *
847 * 1) Scan the bottom 1K for a signature
848 * 2) Scan the top 1K of base RAM
849 * 3) Scan the 64K of bios
850 */
851 if (smp_scan_config(0x0,0x400) ||
852 smp_scan_config(639*0x400,0x400) ||
853 smp_scan_config(0xF0000,0x10000))
854 return;
855 /*
856 * If it is an SMP machine we should know now, unless the
857 * configuration is in an EISA/MCA bus machine with an
858 * extended bios data area.
859 *
860 * there is a real-mode segmented pointer pointing to the
861 * 4K EBDA area at 0x40E, calculate and scan it here.
862 *
863 * NOTE! There are Linux loaders that will corrupt the EBDA
864 * area, and as such this kind of SMP config may be less
865 * trustworthy, simply because the SMP table may have been
866 * stomped on during early boot. These loaders are buggy and
867 * should be fixed.
868 *
869 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
870 */
871
872 address = get_bios_ebda();
873 if (address)
874 smp_scan_config(address, 0x400);
875 }
876
877 /* --------------------------------------------------------------------------
878 ACPI-based MP Configuration
879 -------------------------------------------------------------------------- */
880
881 #ifdef CONFIG_ACPI
882
883 void __init mp_register_lapic_address(u64 address)
884 {
885 mp_lapic_addr = (unsigned long) address;
886
887 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
888
889 if (boot_cpu_physical_apicid == -1U)
890 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
891
892 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
893 }
894
895 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
896 {
897 if (MAX_APICS - id <= 0) {
898 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
899 id, MAX_APICS);
900 return;
901 }
902
903 if (!enabled) {
904 #ifdef CONFIG_X86_SMP
905 ++disabled_cpus;
906 #endif
907 return;
908 }
909
910 generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR)));
911 }
912
913 #ifdef CONFIG_X86_IO_APIC
914
915 #define MP_ISA_BUS 0
916 #define MP_MAX_IOAPIC_PIN 127
917
918 static struct mp_ioapic_routing {
919 int apic_id;
920 int gsi_base;
921 int gsi_end;
922 u32 pin_programmed[4];
923 } mp_ioapic_routing[MAX_IO_APICS];
924
925 static int mp_find_ioapic (int gsi)
926 {
927 int i = 0;
928
929 /* Find the IOAPIC that manages this GSI. */
930 for (i = 0; i < nr_ioapics; i++) {
931 if ((gsi >= mp_ioapic_routing[i].gsi_base)
932 && (gsi <= mp_ioapic_routing[i].gsi_end))
933 return i;
934 }
935
936 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
937
938 return -1;
939 }
940
941 static u8 uniq_ioapic_id(u8 id)
942 {
943 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
944 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
945 return io_apic_get_unique_id(nr_ioapics, id);
946 else
947 return id;
948 }
949
950 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
951 {
952 int idx = 0;
953
954 if (bad_ioapic(address))
955 return;
956
957 idx = nr_ioapics;
958
959 mp_ioapics[idx].mpc_type = MP_IOAPIC;
960 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
961 mp_ioapics[idx].mpc_apicaddr = address;
962
963 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
964 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
965 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
966
967 /*
968 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
969 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
970 */
971 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
972 mp_ioapic_routing[idx].gsi_base = gsi_base;
973 mp_ioapic_routing[idx].gsi_end = gsi_base +
974 io_apic_get_redir_entries(idx);
975
976 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
977 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
978 mp_ioapics[idx].mpc_apicver,
979 mp_ioapics[idx].mpc_apicaddr,
980 mp_ioapic_routing[idx].gsi_base,
981 mp_ioapic_routing[idx].gsi_end);
982
983 nr_ioapics++;
984 }
985
986 void __init
987 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
988 {
989 struct mpc_config_intsrc intsrc;
990 int ioapic = -1;
991 int pin = -1;
992
993 /*
994 * Convert 'gsi' to 'ioapic.pin'.
995 */
996 ioapic = mp_find_ioapic(gsi);
997 if (ioapic < 0)
998 return;
999 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1000
1001 /*
1002 * TBD: This check is for faulty timer entries, where the override
1003 * erroneously sets the trigger to level, resulting in a HUGE
1004 * increase of timer interrupts!
1005 */
1006 if ((bus_irq == 0) && (trigger == 3))
1007 trigger = 1;
1008
1009 intsrc.mpc_type = MP_INTSRC;
1010 intsrc.mpc_irqtype = mp_INT;
1011 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1012 intsrc.mpc_srcbus = MP_ISA_BUS;
1013 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1014 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1015 intsrc.mpc_dstirq = pin; /* INTIN# */
1016
1017 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1018 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1019 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1020 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1021
1022 mp_irqs[mp_irq_entries] = intsrc;
1023 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1024 panic("Max # of irq sources exceeded!\n");
1025 }
1026
1027 int es7000_plat;
1028
1029 void __init mp_config_acpi_legacy_irqs (void)
1030 {
1031 struct mpc_config_intsrc intsrc;
1032 int i = 0;
1033 int ioapic = -1;
1034
1035 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1036 /*
1037 * Fabricate the legacy ISA bus (bus #31).
1038 */
1039 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1040 #endif
1041 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1042 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1043
1044 /*
1045 * Older generations of ES7000 have no legacy identity mappings
1046 */
1047 if (es7000_plat == 1)
1048 return;
1049
1050 /*
1051 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1052 */
1053 ioapic = mp_find_ioapic(0);
1054 if (ioapic < 0)
1055 return;
1056
1057 intsrc.mpc_type = MP_INTSRC;
1058 intsrc.mpc_irqflag = 0; /* Conforming */
1059 intsrc.mpc_srcbus = MP_ISA_BUS;
1060 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1061
1062 /*
1063 * Use the default configuration for the IRQs 0-15. Unless
1064 * overridden by (MADT) interrupt source override entries.
1065 */
1066 for (i = 0; i < 16; i++) {
1067 int idx;
1068
1069 for (idx = 0; idx < mp_irq_entries; idx++) {
1070 struct mpc_config_intsrc *irq = mp_irqs + idx;
1071
1072 /* Do we already have a mapping for this ISA IRQ? */
1073 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1074 break;
1075
1076 /* Do we already have a mapping for this IOAPIC pin */
1077 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1078 (irq->mpc_dstirq == i))
1079 break;
1080 }
1081
1082 if (idx != mp_irq_entries) {
1083 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1084 continue; /* IRQ already used */
1085 }
1086
1087 intsrc.mpc_irqtype = mp_INT;
1088 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1089 intsrc.mpc_dstirq = i;
1090
1091 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1092 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1093 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1094 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1095 intsrc.mpc_dstirq);
1096
1097 mp_irqs[mp_irq_entries] = intsrc;
1098 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1099 panic("Max # of irq sources exceeded!\n");
1100 }
1101 }
1102
1103 #define MAX_GSI_NUM 4096
1104 #define IRQ_COMPRESSION_START 64
1105
1106 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1107 {
1108 int ioapic = -1;
1109 int ioapic_pin = 0;
1110 int idx, bit = 0;
1111 static int pci_irq = IRQ_COMPRESSION_START;
1112 /*
1113 * Mapping between Global System Interrupts, which
1114 * represent all possible interrupts, and IRQs
1115 * assigned to actual devices.
1116 */
1117 static int gsi_to_irq[MAX_GSI_NUM];
1118
1119 /* Don't set up the ACPI SCI because it's already set up */
1120 if (acpi_gbl_FADT.sci_interrupt == gsi)
1121 return gsi;
1122
1123 ioapic = mp_find_ioapic(gsi);
1124 if (ioapic < 0) {
1125 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1126 return gsi;
1127 }
1128
1129 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1130
1131 if (ioapic_renumber_irq)
1132 gsi = ioapic_renumber_irq(ioapic, gsi);
1133
1134 /*
1135 * Avoid pin reprogramming. PRTs typically include entries
1136 * with redundant pin->gsi mappings (but unique PCI devices);
1137 * we only program the IOAPIC on the first.
1138 */
1139 bit = ioapic_pin % 32;
1140 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1141 if (idx > 3) {
1142 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1143 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1144 ioapic_pin);
1145 return gsi;
1146 }
1147 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1148 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1149 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1150 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1151 }
1152
1153 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1154
1155 /*
1156 * For GSI >= 64, use IRQ compression
1157 */
1158 if ((gsi >= IRQ_COMPRESSION_START)
1159 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1160 /*
1161 * For PCI devices assign IRQs in order, avoiding gaps
1162 * due to unused I/O APIC pins.
1163 */
1164 int irq = gsi;
1165 if (gsi < MAX_GSI_NUM) {
1166 /*
1167 * Retain the VIA chipset work-around (gsi > 15), but
1168 * avoid a problem where the 8254 timer (IRQ0) is setup
1169 * via an override (so it's not on pin 0 of the ioapic),
1170 * and at the same time, the pin 0 interrupt is a PCI
1171 * type. The gsi > 15 test could cause these two pins
1172 * to be shared as IRQ0, and they are not shareable.
1173 * So test for this condition, and if necessary, avoid
1174 * the pin collision.
1175 */
1176 gsi = pci_irq++;
1177 /*
1178 * Don't assign IRQ used by ACPI SCI
1179 */
1180 if (gsi == acpi_gbl_FADT.sci_interrupt)
1181 gsi = pci_irq++;
1182 gsi_to_irq[irq] = gsi;
1183 } else {
1184 printk(KERN_ERR "GSI %u is too high\n", gsi);
1185 return gsi;
1186 }
1187 }
1188
1189 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1190 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1191 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1192 return gsi;
1193 }
1194
1195 #endif /* CONFIG_X86_IO_APIC */
1196 #endif /* CONFIG_ACPI */
Linux kernel - Deliverables
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