2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright IBM Corporation, 2006-2007
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/pci_ids.h>
35 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/scatterlist.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
47 int use_calgary __read_mostly
= 1;
49 int use_calgary __read_mostly
= 0;
50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
55 /* register offsets inside the host bridge space */
56 #define CALGARY_CONFIG_REG 0x0108
57 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
58 #define PHB_PLSSR_OFFSET 0x0120
59 #define PHB_CONFIG_RW_OFFSET 0x0160
60 #define PHB_IOBASE_BAR_LOW 0x0170
61 #define PHB_IOBASE_BAR_HIGH 0x0180
62 #define PHB_MEM_1_LOW 0x0190
63 #define PHB_MEM_1_HIGH 0x01A0
64 #define PHB_IO_ADDR_SIZE 0x01B0
65 #define PHB_MEM_1_SIZE 0x01C0
66 #define PHB_MEM_ST_OFFSET 0x01D0
67 #define PHB_AER_OFFSET 0x0200
68 #define PHB_CONFIG_0_HIGH 0x0220
69 #define PHB_CONFIG_0_LOW 0x0230
70 #define PHB_CONFIG_0_END 0x0240
71 #define PHB_MEM_2_LOW 0x02B0
72 #define PHB_MEM_2_HIGH 0x02C0
73 #define PHB_MEM_2_SIZE_HIGH 0x02D0
74 #define PHB_MEM_2_SIZE_LOW 0x02E0
75 #define PHB_DOSHOLE_OFFSET 0x08E0
77 /* CalIOC2 specific */
78 #define PHB_SAVIOR_L2 0x0DB0
79 #define PHB_PAGE_MIG_CTRL 0x0DA8
80 #define PHB_PAGE_MIG_DEBUG 0x0DA0
81 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
84 #define PHB_TCE_ENABLE 0x20000000
85 #define PHB_SLOT_DISABLE 0x1C000000
86 #define PHB_DAC_DISABLE 0x01000000
87 #define PHB_MEM2_ENABLE 0x00400000
88 #define PHB_MCSR_ENABLE 0x00100000
89 /* TAR (Table Address Register) */
90 #define TAR_SW_BITS 0x0000ffffffff800fUL
91 #define TAR_VALID 0x0000000000000008UL
92 /* CSR (Channel/DMA Status Register) */
93 #define CSR_AGENT_MASK 0xffe0ffff
94 /* CCR (Calgary Configuration Register) */
95 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
96 /* PMCR/PMDR (Page Migration Control/Debug Registers */
97 #define PMR_SOFTSTOP 0x80000000
98 #define PMR_SOFTSTOPFAULT 0x40000000
99 #define PMR_HARDSTOP 0x20000000
101 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
102 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
103 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
104 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
105 #define PHBS_PER_CALGARY 4
107 /* register offsets in Calgary's internal register space */
108 static const unsigned long tar_offsets
[] = {
115 static const unsigned long split_queue_offsets
[] = {
116 0x4870 /* SPLIT QUEUE 0 */,
117 0x5870 /* SPLIT QUEUE 1 */,
118 0x6870 /* SPLIT QUEUE 2 */,
119 0x7870 /* SPLIT QUEUE 3 */
122 static const unsigned long phb_offsets
[] = {
129 /* PHB debug registers */
131 static const unsigned long phb_debug_offsets
[] = {
132 0x4000 /* PHB 0 DEBUG */,
133 0x5000 /* PHB 1 DEBUG */,
134 0x6000 /* PHB 2 DEBUG */,
135 0x7000 /* PHB 3 DEBUG */
139 * STUFF register for each debug PHB,
140 * byte 1 = start bus number, byte 2 = end bus number
143 #define PHB_DEBUG_STUFF_OFFSET 0x0020
145 #define EMERGENCY_PAGES 32 /* = 128KB */
147 unsigned int specified_table_size
= TCE_TABLE_SIZE_UNSPECIFIED
;
148 static int translate_empty_slots __read_mostly
= 0;
149 static int calgary_detected __read_mostly
= 0;
151 static struct rio_table_hdr
*rio_table_hdr __initdata
;
152 static struct scal_detail
*scal_devs
[MAX_NUMNODES
] __initdata
;
153 static struct rio_detail
*rio_devs
[MAX_NUMNODES
* 4] __initdata
;
155 struct calgary_bus_info
{
157 unsigned char translation_disabled
;
162 static void calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
163 static void calgary_tce_cache_blast(struct iommu_table
*tbl
);
164 static void calgary_dump_error_regs(struct iommu_table
*tbl
);
165 static void calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
);
166 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
);
167 static void calioc2_dump_error_regs(struct iommu_table
*tbl
);
169 static struct cal_chipset_ops calgary_chip_ops
= {
170 .handle_quirks
= calgary_handle_quirks
,
171 .tce_cache_blast
= calgary_tce_cache_blast
,
172 .dump_error_regs
= calgary_dump_error_regs
175 static struct cal_chipset_ops calioc2_chip_ops
= {
176 .handle_quirks
= calioc2_handle_quirks
,
177 .tce_cache_blast
= calioc2_tce_cache_blast
,
178 .dump_error_regs
= calioc2_dump_error_regs
181 static struct calgary_bus_info bus_info
[MAX_PHB_BUS_NUM
] = { { NULL
, 0, 0 }, };
183 /* enable this to stress test the chip's TCE cache */
184 #ifdef CONFIG_IOMMU_DEBUG
185 static int debugging
= 1;
187 static inline unsigned long verify_bit_range(unsigned long* bitmap
,
188 int expected
, unsigned long start
, unsigned long end
)
190 unsigned long idx
= start
;
192 BUG_ON(start
>= end
);
195 if (!!test_bit(idx
, bitmap
) != expected
)
200 /* all bits have the expected value */
203 #else /* debugging is disabled */
204 static int debugging
;
206 static inline unsigned long verify_bit_range(unsigned long* bitmap
,
207 int expected
, unsigned long start
, unsigned long end
)
212 #endif /* CONFIG_IOMMU_DEBUG */
214 static inline unsigned int num_dma_pages(unsigned long dma
, unsigned int dmalen
)
218 npages
= PAGE_ALIGN(dma
+ dmalen
) - (dma
& PAGE_MASK
);
219 npages
>>= PAGE_SHIFT
;
224 static inline int translation_enabled(struct iommu_table
*tbl
)
226 /* only PHBs with translation enabled have an IOMMU table */
227 return (tbl
!= NULL
);
230 static void iommu_range_reserve(struct iommu_table
*tbl
,
231 unsigned long start_addr
, unsigned int npages
)
235 unsigned long badbit
;
238 index
= start_addr
>> PAGE_SHIFT
;
240 /* bail out if we're asked to reserve a region we don't cover */
241 if (index
>= tbl
->it_size
)
244 end
= index
+ npages
;
245 if (end
> tbl
->it_size
) /* don't go off the table */
248 spin_lock_irqsave(&tbl
->it_lock
, flags
);
250 badbit
= verify_bit_range(tbl
->it_map
, 0, index
, end
);
251 if (badbit
!= ~0UL) {
252 if (printk_ratelimit())
253 printk(KERN_ERR
"Calgary: entry already allocated at "
254 "0x%lx tbl %p dma 0x%lx npages %u\n",
255 badbit
, tbl
, start_addr
, npages
);
258 set_bit_string(tbl
->it_map
, index
, npages
);
260 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
263 static unsigned long iommu_range_alloc(struct iommu_table
*tbl
,
267 unsigned long offset
;
271 spin_lock_irqsave(&tbl
->it_lock
, flags
);
273 offset
= find_next_zero_string(tbl
->it_map
, tbl
->it_hint
,
274 tbl
->it_size
, npages
);
275 if (offset
== ~0UL) {
276 tbl
->chip_ops
->tce_cache_blast(tbl
);
277 offset
= find_next_zero_string(tbl
->it_map
, 0,
278 tbl
->it_size
, npages
);
279 if (offset
== ~0UL) {
280 printk(KERN_WARNING
"Calgary: IOMMU full.\n");
281 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
282 if (panic_on_overflow
)
283 panic("Calgary: fix the allocator.\n");
285 return bad_dma_address
;
289 set_bit_string(tbl
->it_map
, offset
, npages
);
290 tbl
->it_hint
= offset
+ npages
;
291 BUG_ON(tbl
->it_hint
> tbl
->it_size
);
293 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
298 static dma_addr_t
iommu_alloc(struct iommu_table
*tbl
, void *vaddr
,
299 unsigned int npages
, int direction
)
302 dma_addr_t ret
= bad_dma_address
;
304 entry
= iommu_range_alloc(tbl
, npages
);
306 if (unlikely(entry
== bad_dma_address
))
309 /* set the return dma address */
310 ret
= (entry
<< PAGE_SHIFT
) | ((unsigned long)vaddr
& ~PAGE_MASK
);
312 /* put the TCEs in the HW table */
313 tce_build(tbl
, entry
, npages
, (unsigned long)vaddr
& PAGE_MASK
,
319 printk(KERN_WARNING
"Calgary: failed to allocate %u pages in "
320 "iommu %p\n", npages
, tbl
);
321 return bad_dma_address
;
324 static void iommu_free(struct iommu_table
*tbl
, dma_addr_t dma_addr
,
328 unsigned long badbit
;
329 unsigned long badend
;
332 /* were we called with bad_dma_address? */
333 badend
= bad_dma_address
+ (EMERGENCY_PAGES
* PAGE_SIZE
);
334 if (unlikely((dma_addr
>= bad_dma_address
) && (dma_addr
< badend
))) {
335 printk(KERN_ERR
"Calgary: driver tried unmapping bad DMA "
336 "address 0x%Lx\n", dma_addr
);
341 entry
= dma_addr
>> PAGE_SHIFT
;
343 BUG_ON(entry
+ npages
> tbl
->it_size
);
345 tce_free(tbl
, entry
, npages
);
347 spin_lock_irqsave(&tbl
->it_lock
, flags
);
349 badbit
= verify_bit_range(tbl
->it_map
, 1, entry
, entry
+ npages
);
350 if (badbit
!= ~0UL) {
351 if (printk_ratelimit())
352 printk(KERN_ERR
"Calgary: bit is off at 0x%lx "
353 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
354 badbit
, tbl
, dma_addr
, entry
, npages
);
357 __clear_bit_string(tbl
->it_map
, entry
, npages
);
359 spin_unlock_irqrestore(&tbl
->it_lock
, flags
);
362 static inline struct iommu_table
*find_iommu_table(struct device
*dev
)
364 struct pci_dev
*pdev
;
365 struct pci_bus
*pbus
;
366 struct iommu_table
*tbl
;
368 pdev
= to_pci_dev(dev
);
372 /* is the device behind a bridge? Look for the root bus */
376 tbl
= pci_iommu(pbus
);
378 BUG_ON(tbl
&& (tbl
->it_busno
!= pbus
->number
));
383 static void calgary_unmap_sg(struct device
*dev
,
384 struct scatterlist
*sglist
, int nelems
, int direction
)
386 struct iommu_table
*tbl
= find_iommu_table(dev
);
387 struct scatterlist
*s
;
390 if (!translation_enabled(tbl
))
393 for_each_sg(sglist
, s
, nelems
, i
) {
395 dma_addr_t dma
= s
->dma_address
;
396 unsigned int dmalen
= s
->dma_length
;
401 npages
= num_dma_pages(dma
, dmalen
);
402 iommu_free(tbl
, dma
, npages
);
406 static int calgary_nontranslate_map_sg(struct device
* dev
,
407 struct scatterlist
*sg
, int nelems
, int direction
)
409 struct scatterlist
*s
;
412 for_each_sg(sg
, s
, nelems
, i
) {
413 struct page
*p
= sg_page(s
);
416 s
->dma_address
= virt_to_bus(sg_virt(s
));
417 s
->dma_length
= s
->length
;
422 static int calgary_map_sg(struct device
*dev
, struct scatterlist
*sg
,
423 int nelems
, int direction
)
425 struct iommu_table
*tbl
= find_iommu_table(dev
);
426 struct scatterlist
*s
;
432 if (!translation_enabled(tbl
))
433 return calgary_nontranslate_map_sg(dev
, sg
, nelems
, direction
);
435 for_each_sg(sg
, s
, nelems
, i
) {
438 vaddr
= (unsigned long) sg_virt(s
);
439 npages
= num_dma_pages(vaddr
, s
->length
);
441 entry
= iommu_range_alloc(tbl
, npages
);
442 if (entry
== bad_dma_address
) {
443 /* makes sure unmap knows to stop */
448 s
->dma_address
= (entry
<< PAGE_SHIFT
) | s
->offset
;
450 /* insert into HW table */
451 tce_build(tbl
, entry
, npages
, vaddr
& PAGE_MASK
,
454 s
->dma_length
= s
->length
;
459 calgary_unmap_sg(dev
, sg
, nelems
, direction
);
460 for_each_sg(sg
, s
, nelems
, i
) {
461 sg
->dma_address
= bad_dma_address
;
467 static dma_addr_t
calgary_map_single(struct device
*dev
, void *vaddr
,
468 size_t size
, int direction
)
470 dma_addr_t dma_handle
= bad_dma_address
;
473 struct iommu_table
*tbl
= find_iommu_table(dev
);
475 uaddr
= (unsigned long)vaddr
;
476 npages
= num_dma_pages(uaddr
, size
);
478 if (translation_enabled(tbl
))
479 dma_handle
= iommu_alloc(tbl
, vaddr
, npages
, direction
);
481 dma_handle
= virt_to_bus(vaddr
);
486 static void calgary_unmap_single(struct device
*dev
, dma_addr_t dma_handle
,
487 size_t size
, int direction
)
489 struct iommu_table
*tbl
= find_iommu_table(dev
);
492 if (!translation_enabled(tbl
))
495 npages
= num_dma_pages(dma_handle
, size
);
496 iommu_free(tbl
, dma_handle
, npages
);
499 static void* calgary_alloc_coherent(struct device
*dev
, size_t size
,
500 dma_addr_t
*dma_handle
, gfp_t flag
)
504 unsigned int npages
, order
;
505 struct iommu_table
*tbl
= find_iommu_table(dev
);
507 size
= PAGE_ALIGN(size
); /* size rounded up to full pages */
508 npages
= size
>> PAGE_SHIFT
;
509 order
= get_order(size
);
511 /* alloc enough pages (and possibly more) */
512 ret
= (void *)__get_free_pages(flag
, order
);
515 memset(ret
, 0, size
);
517 if (translation_enabled(tbl
)) {
518 /* set up tces to cover the allocated range */
519 mapping
= iommu_alloc(tbl
, ret
, npages
, DMA_BIDIRECTIONAL
);
520 if (mapping
== bad_dma_address
)
523 *dma_handle
= mapping
;
524 } else /* non translated slot */
525 *dma_handle
= virt_to_bus(ret
);
530 free_pages((unsigned long)ret
, get_order(size
));
536 static const struct dma_mapping_ops calgary_dma_ops
= {
537 .alloc_coherent
= calgary_alloc_coherent
,
538 .map_single
= calgary_map_single
,
539 .unmap_single
= calgary_unmap_single
,
540 .map_sg
= calgary_map_sg
,
541 .unmap_sg
= calgary_unmap_sg
,
544 static inline void __iomem
* busno_to_bbar(unsigned char num
)
546 return bus_info
[num
].bbar
;
549 static inline int busno_to_phbid(unsigned char num
)
551 return bus_info
[num
].phbid
;
554 static inline unsigned long split_queue_offset(unsigned char num
)
556 size_t idx
= busno_to_phbid(num
);
558 return split_queue_offsets
[idx
];
561 static inline unsigned long tar_offset(unsigned char num
)
563 size_t idx
= busno_to_phbid(num
);
565 return tar_offsets
[idx
];
568 static inline unsigned long phb_offset(unsigned char num
)
570 size_t idx
= busno_to_phbid(num
);
572 return phb_offsets
[idx
];
575 static inline void __iomem
* calgary_reg(void __iomem
*bar
, unsigned long offset
)
577 unsigned long target
= ((unsigned long)bar
) | offset
;
578 return (void __iomem
*)target
;
581 static inline int is_calioc2(unsigned short device
)
583 return (device
== PCI_DEVICE_ID_IBM_CALIOC2
);
586 static inline int is_calgary(unsigned short device
)
588 return (device
== PCI_DEVICE_ID_IBM_CALGARY
);
591 static inline int is_cal_pci_dev(unsigned short device
)
593 return (is_calgary(device
) || is_calioc2(device
));
596 static void calgary_tce_cache_blast(struct iommu_table
*tbl
)
601 void __iomem
*bbar
= tbl
->bbar
;
602 void __iomem
*target
;
604 /* disable arbitration on the bus */
605 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
609 /* read plssr to ensure it got there */
610 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
613 /* poll split queues until all DMA activity is done */
614 target
= calgary_reg(bbar
, split_queue_offset(tbl
->it_busno
));
618 } while ((val
& 0xff) != 0xff && i
< 100);
620 printk(KERN_WARNING
"Calgary: PCI bus not quiesced, "
621 "continuing anyway\n");
623 /* invalidate TCE cache */
624 target
= calgary_reg(bbar
, tar_offset(tbl
->it_busno
));
625 writeq(tbl
->tar_val
, target
);
627 /* enable arbitration */
628 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_AER_OFFSET
);
630 (void)readl(target
); /* flush */
633 static void calioc2_tce_cache_blast(struct iommu_table
*tbl
)
635 void __iomem
*bbar
= tbl
->bbar
;
636 void __iomem
*target
;
641 unsigned char bus
= tbl
->it_busno
;
644 printk(KERN_DEBUG
"Calgary: CalIOC2 bus 0x%x entering tce cache blast "
645 "sequence - count %d\n", bus
, count
);
647 /* 1. using the Page Migration Control reg set SoftStop */
648 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
649 val
= be32_to_cpu(readl(target
));
650 printk(KERN_DEBUG
"1a. read 0x%x [LE] from %p\n", val
, target
);
652 printk(KERN_DEBUG
"1b. writing 0x%x [LE] to %p\n", val
, target
);
653 writel(cpu_to_be32(val
), target
);
655 /* 2. poll split queues until all DMA activity is done */
656 printk(KERN_DEBUG
"2a. starting to poll split queues\n");
657 target
= calgary_reg(bbar
, split_queue_offset(bus
));
659 val64
= readq(target
);
661 } while ((val64
& 0xff) != 0xff && i
< 100);
663 printk(KERN_WARNING
"CalIOC2: PCI bus not quiesced, "
664 "continuing anyway\n");
666 /* 3. poll Page Migration DEBUG for SoftStopFault */
667 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
668 val
= be32_to_cpu(readl(target
));
669 printk(KERN_DEBUG
"3. read 0x%x [LE] from %p\n", val
, target
);
671 /* 4. if SoftStopFault - goto (1) */
672 if (val
& PMR_SOFTSTOPFAULT
) {
676 printk(KERN_WARNING
"CalIOC2: too many SoftStopFaults, "
677 "aborting TCE cache flush sequence!\n");
678 return; /* pray for the best */
682 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
683 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
684 printk(KERN_DEBUG
"5a. slamming into HardStop by reading %p\n", target
);
685 val
= be32_to_cpu(readl(target
));
686 printk(KERN_DEBUG
"5b. read 0x%x [LE] from %p\n", val
, target
);
687 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_DEBUG
);
688 val
= be32_to_cpu(readl(target
));
689 printk(KERN_DEBUG
"5c. read 0x%x [LE] from %p (debug)\n", val
, target
);
691 /* 6. invalidate TCE cache */
692 printk(KERN_DEBUG
"6. invalidating TCE cache\n");
693 target
= calgary_reg(bbar
, tar_offset(bus
));
694 writeq(tbl
->tar_val
, target
);
696 /* 7. Re-read PMCR */
697 printk(KERN_DEBUG
"7a. Re-reading PMCR\n");
698 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
699 val
= be32_to_cpu(readl(target
));
700 printk(KERN_DEBUG
"7b. read 0x%x [LE] from %p\n", val
, target
);
702 /* 8. Remove HardStop */
703 printk(KERN_DEBUG
"8a. removing HardStop from PMCR\n");
704 target
= calgary_reg(bbar
, phb_offset(bus
) | PHB_PAGE_MIG_CTRL
);
706 printk(KERN_DEBUG
"8b. writing 0x%x [LE] to %p\n", val
, target
);
707 writel(cpu_to_be32(val
), target
);
708 val
= be32_to_cpu(readl(target
));
709 printk(KERN_DEBUG
"8c. read 0x%x [LE] from %p\n", val
, target
);
712 static void __init
calgary_reserve_mem_region(struct pci_dev
*dev
, u64 start
,
715 unsigned int numpages
;
717 limit
= limit
| 0xfffff;
720 numpages
= ((limit
- start
) >> PAGE_SHIFT
);
721 iommu_range_reserve(pci_iommu(dev
->bus
), start
, numpages
);
724 static void __init
calgary_reserve_peripheral_mem_1(struct pci_dev
*dev
)
726 void __iomem
*target
;
727 u64 low
, high
, sizelow
;
729 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
730 unsigned char busnum
= dev
->bus
->number
;
731 void __iomem
*bbar
= tbl
->bbar
;
733 /* peripheral MEM_1 region */
734 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_LOW
);
735 low
= be32_to_cpu(readl(target
));
736 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_HIGH
);
737 high
= be32_to_cpu(readl(target
));
738 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_1_SIZE
);
739 sizelow
= be32_to_cpu(readl(target
));
741 start
= (high
<< 32) | low
;
744 calgary_reserve_mem_region(dev
, start
, limit
);
747 static void __init
calgary_reserve_peripheral_mem_2(struct pci_dev
*dev
)
749 void __iomem
*target
;
751 u64 low
, high
, sizelow
, sizehigh
;
753 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
754 unsigned char busnum
= dev
->bus
->number
;
755 void __iomem
*bbar
= tbl
->bbar
;
758 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
759 val32
= be32_to_cpu(readl(target
));
760 if (!(val32
& PHB_MEM2_ENABLE
))
763 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_LOW
);
764 low
= be32_to_cpu(readl(target
));
765 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_HIGH
);
766 high
= be32_to_cpu(readl(target
));
767 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_LOW
);
768 sizelow
= be32_to_cpu(readl(target
));
769 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_MEM_2_SIZE_HIGH
);
770 sizehigh
= be32_to_cpu(readl(target
));
772 start
= (high
<< 32) | low
;
773 limit
= (sizehigh
<< 32) | sizelow
;
775 calgary_reserve_mem_region(dev
, start
, limit
);
779 * some regions of the IO address space do not get translated, so we
780 * must not give devices IO addresses in those regions. The regions
781 * are the 640KB-1MB region and the two PCI peripheral memory holes.
782 * Reserve all of them in the IOMMU bitmap to avoid giving them out
785 static void __init
calgary_reserve_regions(struct pci_dev
*dev
)
789 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
791 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
792 iommu_range_reserve(tbl
, bad_dma_address
, EMERGENCY_PAGES
);
794 /* avoid the BIOS/VGA first 640KB-1MB region */
795 /* for CalIOC2 - avoid the entire first MB */
796 if (is_calgary(dev
->device
)) {
797 start
= (640 * 1024);
798 npages
= ((1024 - 640) * 1024) >> PAGE_SHIFT
;
799 } else { /* calioc2 */
801 npages
= (1 * 1024 * 1024) >> PAGE_SHIFT
;
803 iommu_range_reserve(tbl
, start
, npages
);
805 /* reserve the two PCI peripheral memory regions in IO space */
806 calgary_reserve_peripheral_mem_1(dev
);
807 calgary_reserve_peripheral_mem_2(dev
);
810 static int __init
calgary_setup_tar(struct pci_dev
*dev
, void __iomem
*bbar
)
814 void __iomem
*target
;
816 struct iommu_table
*tbl
;
818 /* build TCE tables for each PHB */
819 ret
= build_tce_table(dev
, bbar
);
823 tbl
= pci_iommu(dev
->bus
);
824 tbl
->it_base
= (unsigned long)bus_info
[dev
->bus
->number
].tce_space
;
825 tce_free(tbl
, 0, tbl
->it_size
);
827 if (is_calgary(dev
->device
))
828 tbl
->chip_ops
= &calgary_chip_ops
;
829 else if (is_calioc2(dev
->device
))
830 tbl
->chip_ops
= &calioc2_chip_ops
;
834 calgary_reserve_regions(dev
);
836 /* set TARs for each PHB */
837 target
= calgary_reg(bbar
, tar_offset(dev
->bus
->number
));
838 val64
= be64_to_cpu(readq(target
));
840 /* zero out all TAR bits under sw control */
841 val64
&= ~TAR_SW_BITS
;
842 table_phys
= (u64
)__pa(tbl
->it_base
);
846 BUG_ON(specified_table_size
> TCE_TABLE_SIZE_8M
);
847 val64
|= (u64
) specified_table_size
;
849 tbl
->tar_val
= cpu_to_be64(val64
);
851 writeq(tbl
->tar_val
, target
);
852 readq(target
); /* flush */
857 static void __init
calgary_free_bus(struct pci_dev
*dev
)
860 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
861 void __iomem
*target
;
862 unsigned int bitmapsz
;
864 target
= calgary_reg(tbl
->bbar
, tar_offset(dev
->bus
->number
));
865 val64
= be64_to_cpu(readq(target
));
866 val64
&= ~TAR_SW_BITS
;
867 writeq(cpu_to_be64(val64
), target
);
868 readq(target
); /* flush */
870 bitmapsz
= tbl
->it_size
/ BITS_PER_BYTE
;
871 free_pages((unsigned long)tbl
->it_map
, get_order(bitmapsz
));
876 set_pci_iommu(dev
->bus
, NULL
);
878 /* Can't free bootmem allocated memory after system is up :-( */
879 bus_info
[dev
->bus
->number
].tce_space
= NULL
;
882 static void calgary_dump_error_regs(struct iommu_table
*tbl
)
884 void __iomem
*bbar
= tbl
->bbar
;
885 void __iomem
*target
;
888 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
889 csr
= be32_to_cpu(readl(target
));
891 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_PLSSR_OFFSET
);
892 plssr
= be32_to_cpu(readl(target
));
894 /* If no error, the agent ID in the CSR is not valid */
895 printk(KERN_EMERG
"Calgary: DMA error on Calgary PHB 0x%x, "
896 "0x%08x@CSR 0x%08x@PLSSR\n", tbl
->it_busno
, csr
, plssr
);
899 static void calioc2_dump_error_regs(struct iommu_table
*tbl
)
901 void __iomem
*bbar
= tbl
->bbar
;
902 u32 csr
, csmr
, plssr
, mck
, rcstat
;
903 void __iomem
*target
;
904 unsigned long phboff
= phb_offset(tbl
->it_busno
);
905 unsigned long erroff
;
910 target
= calgary_reg(bbar
, phboff
| PHB_CSR_OFFSET
);
911 csr
= be32_to_cpu(readl(target
));
913 target
= calgary_reg(bbar
, phboff
| PHB_PLSSR_OFFSET
);
914 plssr
= be32_to_cpu(readl(target
));
916 target
= calgary_reg(bbar
, phboff
| 0x290);
917 csmr
= be32_to_cpu(readl(target
));
919 target
= calgary_reg(bbar
, phboff
| 0x800);
920 mck
= be32_to_cpu(readl(target
));
922 printk(KERN_EMERG
"Calgary: DMA error on CalIOC2 PHB 0x%x\n",
925 printk(KERN_EMERG
"Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
926 csr
, plssr
, csmr
, mck
);
928 /* dump rest of error regs */
929 printk(KERN_EMERG
"Calgary: ");
930 for (i
= 0; i
< ARRAY_SIZE(errregs
); i
++) {
931 /* err regs are at 0x810 - 0x870 */
932 erroff
= (0x810 + (i
* 0x10));
933 target
= calgary_reg(bbar
, phboff
| erroff
);
934 errregs
[i
] = be32_to_cpu(readl(target
));
935 printk("0x%08x@0x%lx ", errregs
[i
], erroff
);
939 /* root complex status */
940 target
= calgary_reg(bbar
, phboff
| PHB_ROOT_COMPLEX_STATUS
);
941 rcstat
= be32_to_cpu(readl(target
));
942 printk(KERN_EMERG
"Calgary: 0x%08x@0x%x\n", rcstat
,
943 PHB_ROOT_COMPLEX_STATUS
);
946 static void calgary_watchdog(unsigned long data
)
948 struct pci_dev
*dev
= (struct pci_dev
*)data
;
949 struct iommu_table
*tbl
= pci_iommu(dev
->bus
);
950 void __iomem
*bbar
= tbl
->bbar
;
952 void __iomem
*target
;
954 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) | PHB_CSR_OFFSET
);
955 val32
= be32_to_cpu(readl(target
));
957 /* If no error, the agent ID in the CSR is not valid */
958 if (val32
& CSR_AGENT_MASK
) {
959 tbl
->chip_ops
->dump_error_regs(tbl
);
964 /* Disable bus that caused the error */
965 target
= calgary_reg(bbar
, phb_offset(tbl
->it_busno
) |
966 PHB_CONFIG_RW_OFFSET
);
967 val32
= be32_to_cpu(readl(target
));
968 val32
|= PHB_SLOT_DISABLE
;
969 writel(cpu_to_be32(val32
), target
);
970 readl(target
); /* flush */
972 /* Reset the timer */
973 mod_timer(&tbl
->watchdog_timer
, jiffies
+ 2 * HZ
);
977 static void __init
calgary_set_split_completion_timeout(void __iomem
*bbar
,
978 unsigned char busnum
, unsigned long timeout
)
981 void __iomem
*target
;
982 unsigned int phb_shift
= ~0; /* silence gcc */
985 switch (busno_to_phbid(busnum
)) {
986 case 0: phb_shift
= (63 - 19);
988 case 1: phb_shift
= (63 - 23);
990 case 2: phb_shift
= (63 - 27);
992 case 3: phb_shift
= (63 - 35);
995 BUG_ON(busno_to_phbid(busnum
));
998 target
= calgary_reg(bbar
, CALGARY_CONFIG_REG
);
999 val64
= be64_to_cpu(readq(target
));
1001 /* zero out this PHB's timer bits */
1002 mask
= ~(0xFUL
<< phb_shift
);
1004 val64
|= (timeout
<< phb_shift
);
1005 writeq(cpu_to_be64(val64
), target
);
1006 readq(target
); /* flush */
1009 static void calioc2_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
1011 unsigned char busnum
= dev
->bus
->number
;
1012 void __iomem
*bbar
= tbl
->bbar
;
1013 void __iomem
*target
;
1017 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1019 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_SAVIOR_L2
);
1020 val
= cpu_to_be32(readl(target
));
1022 writel(cpu_to_be32(val
), target
);
1025 static void calgary_handle_quirks(struct iommu_table
*tbl
, struct pci_dev
*dev
)
1027 unsigned char busnum
= dev
->bus
->number
;
1030 * Give split completion a longer timeout on bus 1 for aic94xx
1031 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1033 if (is_calgary(dev
->device
) && (busnum
== 1))
1034 calgary_set_split_completion_timeout(tbl
->bbar
, busnum
,
1038 static void __init
calgary_enable_translation(struct pci_dev
*dev
)
1041 unsigned char busnum
;
1042 void __iomem
*target
;
1044 struct iommu_table
*tbl
;
1046 busnum
= dev
->bus
->number
;
1047 tbl
= pci_iommu(dev
->bus
);
1050 /* enable TCE in PHB Config Register */
1051 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1052 val32
= be32_to_cpu(readl(target
));
1053 val32
|= PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
;
1055 printk(KERN_INFO
"Calgary: enabling translation on %s PHB %#x\n",
1056 (dev
->device
== PCI_DEVICE_ID_IBM_CALGARY
) ?
1057 "Calgary" : "CalIOC2", busnum
);
1058 printk(KERN_INFO
"Calgary: errant DMAs will now be prevented on this "
1061 writel(cpu_to_be32(val32
), target
);
1062 readl(target
); /* flush */
1064 init_timer(&tbl
->watchdog_timer
);
1065 tbl
->watchdog_timer
.function
= &calgary_watchdog
;
1066 tbl
->watchdog_timer
.data
= (unsigned long)dev
;
1067 mod_timer(&tbl
->watchdog_timer
, jiffies
);
1070 static void __init
calgary_disable_translation(struct pci_dev
*dev
)
1073 unsigned char busnum
;
1074 void __iomem
*target
;
1076 struct iommu_table
*tbl
;
1078 busnum
= dev
->bus
->number
;
1079 tbl
= pci_iommu(dev
->bus
);
1082 /* disable TCE in PHB Config Register */
1083 target
= calgary_reg(bbar
, phb_offset(busnum
) | PHB_CONFIG_RW_OFFSET
);
1084 val32
= be32_to_cpu(readl(target
));
1085 val32
&= ~(PHB_TCE_ENABLE
| PHB_DAC_DISABLE
| PHB_MCSR_ENABLE
);
1087 printk(KERN_INFO
"Calgary: disabling translation on PHB %#x!\n", busnum
);
1088 writel(cpu_to_be32(val32
), target
);
1089 readl(target
); /* flush */
1091 del_timer_sync(&tbl
->watchdog_timer
);
1094 static void __init
calgary_init_one_nontraslated(struct pci_dev
*dev
)
1097 set_pci_iommu(dev
->bus
, NULL
);
1099 /* is the device behind a bridge? */
1100 if (dev
->bus
->parent
)
1101 dev
->bus
->parent
->self
= dev
;
1103 dev
->bus
->self
= dev
;
1106 static int __init
calgary_init_one(struct pci_dev
*dev
)
1109 struct iommu_table
*tbl
;
1112 BUG_ON(dev
->bus
->number
>= MAX_PHB_BUS_NUM
);
1114 bbar
= busno_to_bbar(dev
->bus
->number
);
1115 ret
= calgary_setup_tar(dev
, bbar
);
1121 if (dev
->bus
->parent
) {
1122 if (dev
->bus
->parent
->self
)
1123 printk(KERN_WARNING
"Calgary: IEEEE, dev %p has "
1124 "bus->parent->self!\n", dev
);
1125 dev
->bus
->parent
->self
= dev
;
1127 dev
->bus
->self
= dev
;
1129 tbl
= pci_iommu(dev
->bus
);
1130 tbl
->chip_ops
->handle_quirks(tbl
, dev
);
1132 calgary_enable_translation(dev
);
1140 static int __init
calgary_locate_bbars(void)
1143 int rioidx
, phb
, bus
;
1145 void __iomem
*target
;
1146 unsigned long offset
;
1147 u8 start_bus
, end_bus
;
1151 for (rioidx
= 0; rioidx
< rio_table_hdr
->num_rio_dev
; rioidx
++) {
1152 struct rio_detail
*rio
= rio_devs
[rioidx
];
1154 if ((rio
->type
!= COMPAT_CALGARY
) && (rio
->type
!= ALT_CALGARY
))
1157 /* map entire 1MB of Calgary config space */
1158 bbar
= ioremap_nocache(rio
->BBAR
, 1024 * 1024);
1162 for (phb
= 0; phb
< PHBS_PER_CALGARY
; phb
++) {
1163 offset
= phb_debug_offsets
[phb
] | PHB_DEBUG_STUFF_OFFSET
;
1164 target
= calgary_reg(bbar
, offset
);
1166 val
= be32_to_cpu(readl(target
));
1168 start_bus
= (u8
)((val
& 0x00FF0000) >> 16);
1169 end_bus
= (u8
)((val
& 0x0000FF00) >> 8);
1172 for (bus
= start_bus
; bus
<= end_bus
; bus
++) {
1173 bus_info
[bus
].bbar
= bbar
;
1174 bus_info
[bus
].phbid
= phb
;
1177 bus_info
[start_bus
].bbar
= bbar
;
1178 bus_info
[start_bus
].phbid
= phb
;
1186 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1187 for (bus
= 0; bus
< ARRAY_SIZE(bus_info
); bus
++)
1188 if (bus_info
[bus
].bbar
)
1189 iounmap(bus_info
[bus
].bbar
);
1194 static int __init
calgary_init(void)
1197 struct pci_dev
*dev
= NULL
;
1198 struct calgary_bus_info
*info
;
1200 ret
= calgary_locate_bbars();
1205 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1208 if (!is_cal_pci_dev(dev
->device
))
1211 info
= &bus_info
[dev
->bus
->number
];
1212 if (info
->translation_disabled
) {
1213 calgary_init_one_nontraslated(dev
);
1217 if (!info
->tce_space
&& !translate_empty_slots
)
1220 ret
= calgary_init_one(dev
);
1229 dev
= pci_get_device_reverse(PCI_VENDOR_ID_IBM
,
1233 if (!is_cal_pci_dev(dev
->device
))
1236 info
= &bus_info
[dev
->bus
->number
];
1237 if (info
->translation_disabled
) {
1241 if (!info
->tce_space
&& !translate_empty_slots
)
1244 calgary_disable_translation(dev
);
1245 calgary_free_bus(dev
);
1246 pci_dev_put(dev
); /* Undo calgary_init_one()'s pci_dev_get() */
1252 static inline int __init
determine_tce_table_size(u64 ram
)
1256 if (specified_table_size
!= TCE_TABLE_SIZE_UNSPECIFIED
)
1257 return specified_table_size
;
1260 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1261 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1262 * larger table size has twice as many entries, so shift the
1263 * max ram address by 13 to divide by 8K and then look at the
1264 * order of the result to choose between 0-7.
1266 ret
= get_order(ram
>> 13);
1267 if (ret
> TCE_TABLE_SIZE_8M
)
1268 ret
= TCE_TABLE_SIZE_8M
;
1273 static int __init
build_detail_arrays(void)
1276 int i
, scal_detail_size
, rio_detail_size
;
1278 if (rio_table_hdr
->num_scal_dev
> MAX_NUMNODES
){
1280 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1281 "but system has %d nodes.\n",
1282 MAX_NUMNODES
, rio_table_hdr
->num_scal_dev
);
1286 switch (rio_table_hdr
->version
){
1288 scal_detail_size
= 11;
1289 rio_detail_size
= 13;
1292 scal_detail_size
= 12;
1293 rio_detail_size
= 15;
1297 "Calgary: Invalid Rio Grande Table Version: %d\n",
1298 rio_table_hdr
->version
);
1302 ptr
= ((unsigned long)rio_table_hdr
) + 3;
1303 for (i
= 0; i
< rio_table_hdr
->num_scal_dev
;
1304 i
++, ptr
+= scal_detail_size
)
1305 scal_devs
[i
] = (struct scal_detail
*)ptr
;
1307 for (i
= 0; i
< rio_table_hdr
->num_rio_dev
;
1308 i
++, ptr
+= rio_detail_size
)
1309 rio_devs
[i
] = (struct rio_detail
*)ptr
;
1314 static int __init
calgary_bus_has_devices(int bus
, unsigned short pci_dev
)
1319 if (pci_dev
== PCI_DEVICE_ID_IBM_CALIOC2
) {
1321 * FIXME: properly scan for devices accross the
1322 * PCI-to-PCI bridge on every CalIOC2 port.
1327 for (dev
= 1; dev
< 8; dev
++) {
1328 val
= read_pci_config(bus
, dev
, 0, 0);
1329 if (val
!= 0xffffffff)
1332 return (val
!= 0xffffffff);
1335 void __init
detect_calgary(void)
1339 int calgary_found
= 0;
1341 unsigned int offset
, prev_offset
;
1345 * if the user specified iommu=off or iommu=soft or we found
1346 * another HW IOMMU already, bail out.
1348 if (swiotlb
|| no_iommu
|| iommu_detected
)
1354 if (!early_pci_allowed())
1357 printk(KERN_DEBUG
"Calgary: detecting Calgary via BIOS EBDA area\n");
1359 ptr
= (unsigned long)phys_to_virt(get_bios_ebda());
1361 rio_table_hdr
= NULL
;
1365 * The next offset is stored in the 1st word.
1366 * Only parse up until the offset increases:
1368 while (offset
> prev_offset
) {
1369 /* The block id is stored in the 2nd word */
1370 if (*((unsigned short *)(ptr
+ offset
+ 2)) == 0x4752){
1371 /* set the pointer past the offset & block id */
1372 rio_table_hdr
= (struct rio_table_hdr
*)(ptr
+ offset
+ 4);
1375 prev_offset
= offset
;
1376 offset
= *((unsigned short *)(ptr
+ offset
));
1378 if (!rio_table_hdr
) {
1379 printk(KERN_DEBUG
"Calgary: Unable to locate Rio Grande table "
1380 "in EBDA - bailing!\n");
1384 ret
= build_detail_arrays();
1386 printk(KERN_DEBUG
"Calgary: build_detail_arrays ret %d\n", ret
);
1390 specified_table_size
= determine_tce_table_size(end_pfn
* PAGE_SIZE
);
1392 for (bus
= 0; bus
< MAX_PHB_BUS_NUM
; bus
++) {
1393 struct calgary_bus_info
*info
= &bus_info
[bus
];
1394 unsigned short pci_device
;
1397 val
= read_pci_config(bus
, 0, 0, 0);
1398 pci_device
= (val
& 0xFFFF0000) >> 16;
1400 if (!is_cal_pci_dev(pci_device
))
1403 if (info
->translation_disabled
)
1406 if (calgary_bus_has_devices(bus
, pci_device
) ||
1407 translate_empty_slots
) {
1408 tbl
= alloc_tce_table();
1411 info
->tce_space
= tbl
;
1416 printk(KERN_DEBUG
"Calgary: finished detection, Calgary %s\n",
1417 calgary_found
? "found" : "not found");
1419 if (calgary_found
) {
1421 calgary_detected
= 1;
1422 printk(KERN_INFO
"PCI-DMA: Calgary IOMMU detected.\n");
1423 printk(KERN_INFO
"PCI-DMA: Calgary TCE table spec is %d, "
1424 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size
,
1425 debugging
? "enabled" : "disabled");
1430 for (--bus
; bus
>= 0; --bus
) {
1431 struct calgary_bus_info
*info
= &bus_info
[bus
];
1433 if (info
->tce_space
)
1434 free_tce_table(info
->tce_space
);
1438 int __init
calgary_iommu_init(void)
1442 if (no_iommu
|| swiotlb
)
1445 if (!calgary_detected
)
1448 /* ok, we're trying to use Calgary - let's roll */
1449 printk(KERN_INFO
"PCI-DMA: Using Calgary IOMMU\n");
1451 ret
= calgary_init();
1453 printk(KERN_ERR
"PCI-DMA: Calgary init failed %d, "
1454 "falling back to no_iommu\n", ret
);
1455 if (end_pfn
> MAX_DMA32_PFN
)
1456 printk(KERN_ERR
"WARNING more than 4GB of memory, "
1457 "32bit PCI may malfunction.\n");
1462 bad_dma_address
= 0x0;
1463 dma_ops
= &calgary_dma_ops
;
1468 static int __init
calgary_parse_options(char *p
)
1470 unsigned int bridge
;
1475 if (!strncmp(p
, "64k", 3))
1476 specified_table_size
= TCE_TABLE_SIZE_64K
;
1477 else if (!strncmp(p
, "128k", 4))
1478 specified_table_size
= TCE_TABLE_SIZE_128K
;
1479 else if (!strncmp(p
, "256k", 4))
1480 specified_table_size
= TCE_TABLE_SIZE_256K
;
1481 else if (!strncmp(p
, "512k", 4))
1482 specified_table_size
= TCE_TABLE_SIZE_512K
;
1483 else if (!strncmp(p
, "1M", 2))
1484 specified_table_size
= TCE_TABLE_SIZE_1M
;
1485 else if (!strncmp(p
, "2M", 2))
1486 specified_table_size
= TCE_TABLE_SIZE_2M
;
1487 else if (!strncmp(p
, "4M", 2))
1488 specified_table_size
= TCE_TABLE_SIZE_4M
;
1489 else if (!strncmp(p
, "8M", 2))
1490 specified_table_size
= TCE_TABLE_SIZE_8M
;
1492 len
= strlen("translate_empty_slots");
1493 if (!strncmp(p
, "translate_empty_slots", len
))
1494 translate_empty_slots
= 1;
1496 len
= strlen("disable");
1497 if (!strncmp(p
, "disable", len
)) {
1503 bridge
= simple_strtol(p
, &endp
, 0);
1507 if (bridge
< MAX_PHB_BUS_NUM
) {
1508 printk(KERN_INFO
"Calgary: disabling "
1509 "translation for PHB %#x\n", bridge
);
1510 bus_info
[bridge
].translation_disabled
= 1;
1514 p
= strpbrk(p
, ",");
1522 __setup("calgary=", calgary_parse_options
);
1524 static void __init
calgary_fixup_one_tce_space(struct pci_dev
*dev
)
1526 struct iommu_table
*tbl
;
1527 unsigned int npages
;
1530 tbl
= pci_iommu(dev
->bus
);
1532 for (i
= 0; i
< 4; i
++) {
1533 struct resource
*r
= &dev
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
1535 /* Don't give out TCEs that map MEM resources */
1536 if (!(r
->flags
& IORESOURCE_MEM
))
1539 /* 0-based? we reserve the whole 1st MB anyway */
1543 /* cover the whole region */
1544 npages
= (r
->end
- r
->start
) >> PAGE_SHIFT
;
1547 iommu_range_reserve(tbl
, r
->start
, npages
);
1551 static int __init
calgary_fixup_tce_spaces(void)
1553 struct pci_dev
*dev
= NULL
;
1554 struct calgary_bus_info
*info
;
1556 if (no_iommu
|| swiotlb
|| !calgary_detected
)
1559 printk(KERN_DEBUG
"Calgary: fixing up tce spaces\n");
1562 dev
= pci_get_device(PCI_VENDOR_ID_IBM
, PCI_ANY_ID
, dev
);
1565 if (!is_cal_pci_dev(dev
->device
))
1568 info
= &bus_info
[dev
->bus
->number
];
1569 if (info
->translation_disabled
)
1572 if (!info
->tce_space
)
1575 calgary_fixup_one_tce_space(dev
);
1583 * We need to be call after pcibios_assign_resources (fs_initcall level)
1584 * and before device_initcall.
1586 rootfs_initcall(calgary_fixup_tce_spaces
);