arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/random.h>
  12 #include <linux/user-return-notifier.h>
  13 #include <trace/events/power.h>
  14 #include <linux/hw_breakpoint.h>
  15 #include <asm/system.h>
  16 #include <asm/apic.h>
  17 #include <asm/syscalls.h>
  18 #include <asm/idle.h>
  19 #include <asm/uaccess.h>
  20 #include <asm/i387.h>
  21 #include <asm/ds.h>
  22 #include <asm/debugreg.h>
  23
  24 unsigned long idle_halt;
  25 EXPORT_SYMBOL(idle_halt);
  26 unsigned long idle_nomwait;
  27 EXPORT_SYMBOL(idle_nomwait);
  28
  29 struct kmem_cache *task_xstate_cachep;
  30
  31 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  32 {
  33         *dst = *src;
  34         if (src->thread.xstate) {
  35                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  36                                                       GFP_KERNEL);
  37                 if (!dst->thread.xstate)
  38                         return -ENOMEM;
  39                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  40                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  41         }
  42         return 0;
  43 }
  44
  45 void free_thread_xstate(struct task_struct *tsk)
  46 {
  47         if (tsk->thread.xstate) {
  48                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  49                 tsk->thread.xstate = NULL;
  50         }
  51
  52         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
  53 }
  54
  55 void free_thread_info(struct thread_info *ti)
  56 {
  57         free_thread_xstate(ti->task);
  58         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  59 }
  60
  61 void arch_task_cache_init(void)
  62 {
  63         task_xstate_cachep =
  64                 kmem_cache_create("task_xstate", xstate_size,
  65                                   __alignof__(union thread_xstate),
  66                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  67 }
  68
  69 /*
  70  * Free current thread data structures etc..
  71  */
  72 void exit_thread(void)
  73 {
  74         struct task_struct *me = current;
  75         struct thread_struct *t = &me->thread;
  76         unsigned long *bp = t->io_bitmap_ptr;
  77
  78         if (bp) {
  79                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  80
  81                 t->io_bitmap_ptr = NULL;
  82                 clear_thread_flag(TIF_IO_BITMAP);
  83                 /*
  84                  * Careful, clear this in the TSS too:
  85                  */
  86                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  87                 t->io_bitmap_max = 0;
  88                 put_cpu();
  89                 kfree(bp);
  90         }
  91 }
  92
  93 void flush_thread(void)
  94 {
  95         struct task_struct *tsk = current;
  96
  97 #ifdef CONFIG_X86_64
  98         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
  99                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
 100                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
 101                         clear_tsk_thread_flag(tsk, TIF_IA32);
 102                 } else {
 103                         set_tsk_thread_flag(tsk, TIF_IA32);
 104                         current_thread_info()->status |= TS_COMPAT;
 105                 }
 106         }
 107 #endif
 108
 109         flush_ptrace_hw_breakpoint(tsk);
 110         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 111         /*
 112          * Forget coprocessor state..
 113          */
 114         tsk->fpu_counter = 0;
 115         clear_fpu(tsk);
 116         clear_used_math();
 117 }
 118
 119 static void hard_disable_TSC(void)
 120 {
 121         write_cr4(read_cr4() | X86_CR4_TSD);
 122 }
 123
 124 void disable_TSC(void)
 125 {
 126         preempt_disable();
 127         if (!test_and_set_thread_flag(TIF_NOTSC))
 128                 /*
 129                  * Must flip the CPU state synchronously with
 130                  * TIF_NOTSC in the current running context.
 131                  */
 132                 hard_disable_TSC();
 133         preempt_enable();
 134 }
 135
 136 static void hard_enable_TSC(void)
 137 {
 138         write_cr4(read_cr4() & ~X86_CR4_TSD);
 139 }
 140
 141 static void enable_TSC(void)
 142 {
 143         preempt_disable();
 144         if (test_and_clear_thread_flag(TIF_NOTSC))
 145                 /*
 146                  * Must flip the CPU state synchronously with
 147                  * TIF_NOTSC in the current running context.
 148                  */
 149                 hard_enable_TSC();
 150         preempt_enable();
 151 }
 152
 153 int get_tsc_mode(unsigned long adr)
 154 {
 155         unsigned int val;
 156
 157         if (test_thread_flag(TIF_NOTSC))
 158                 val = PR_TSC_SIGSEGV;
 159         else
 160                 val = PR_TSC_ENABLE;
 161
 162         return put_user(val, (unsigned int __user *)adr);
 163 }
 164
 165 int set_tsc_mode(unsigned int val)
 166 {
 167         if (val == PR_TSC_SIGSEGV)
 168                 disable_TSC();
 169         else if (val == PR_TSC_ENABLE)
 170                 enable_TSC();
 171         else
 172                 return -EINVAL;
 173
 174         return 0;
 175 }
 176
 177 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 178                       struct tss_struct *tss)
 179 {
 180         struct thread_struct *prev, *next;
 181
 182         prev = &prev_p->thread;
 183         next = &next_p->thread;
 184
 185         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 186             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 187                 ds_switch_to(prev_p, next_p);
 188         else if (next->debugctlmsr != prev->debugctlmsr)
 189                 update_debugctlmsr(next->debugctlmsr);
 190
 191         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 192             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 193                 /* prev and next are different */
 194                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 195                         hard_disable_TSC();
 196                 else
 197                         hard_enable_TSC();
 198         }
 199
 200         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 201                 /*
 202                  * Copy the relevant range of the IO bitmap.
 203                  * Normally this is 128 bytes or less:
 204                  */
 205                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 206                        max(prev->io_bitmap_max, next->io_bitmap_max));
 207         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 208                 /*
 209                  * Clear any possible leftover bits:
 210                  */
 211                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 212         }
 213         propagate_user_return_notify(prev_p, next_p);
 214 }
 215
 216 int sys_fork(struct pt_regs *regs)
 217 {
 218         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 219 }
 220
 221 /*
 222  * This is trivial, and on the face of it looks like it
 223  * could equally well be done in user mode.
 224  *
 225  * Not so, for quite unobvious reasons - register pressure.
 226  * In user mode vfork() cannot have a stack frame, and if
 227  * done by calling the "clone()" system call directly, you
 228  * do not have enough call-clobbered registers to hold all
 229  * the information you need.
 230  */
 231 int sys_vfork(struct pt_regs *regs)
 232 {
 233         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 234                        NULL, NULL);
 235 }
 236
 237
 238 /*
 239  * sys_execve() executes a new program.
 240  */
 241 long sys_execve(char __user *name, char __user * __user *argv,
 242                 char __user * __user *envp, struct pt_regs *regs)
 243 {
 244         long error;
 245         char *filename;
 246
 247         filename = getname(name);
 248         error = PTR_ERR(filename);
 249         if (IS_ERR(filename))
 250                 return error;
 251         error = do_execve(filename, argv, envp, regs);
 252
 253 #ifdef CONFIG_X86_32
 254         if (error == 0) {
 255                 /* Make sure we don't return using sysenter.. */
 256                 set_thread_flag(TIF_IRET);
 257         }
 258 #endif
 259
 260         putname(filename);
 261         return error;
 262 }
 263
 264 /*
 265  * Idle related variables and functions
 266  */
 267 unsigned long boot_option_idle_override = 0;
 268 EXPORT_SYMBOL(boot_option_idle_override);
 269
 270 /*
 271  * Powermanagement idle function, if any..
 272  */
 273 void (*pm_idle)(void);
 274 EXPORT_SYMBOL(pm_idle);
 275
 276 #ifdef CONFIG_X86_32
 277 /*
 278  * This halt magic was a workaround for ancient floppy DMA
 279  * wreckage. It should be safe to remove.
 280  */
 281 static int hlt_counter;
 282 void disable_hlt(void)
 283 {
 284         hlt_counter++;
 285 }
 286 EXPORT_SYMBOL(disable_hlt);
 287
 288 void enable_hlt(void)
 289 {
 290         hlt_counter--;
 291 }
 292 EXPORT_SYMBOL(enable_hlt);
 293
 294 static inline int hlt_use_halt(void)
 295 {
 296         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 297 }
 298 #else
 299 static inline int hlt_use_halt(void)
 300 {
 301         return 1;
 302 }
 303 #endif
 304
 305 /*
 306  * We use this if we don't have any better
 307  * idle routine..
 308  */
 309 void default_idle(void)
 310 {
 311         if (hlt_use_halt()) {
 312                 trace_power_start(POWER_CSTATE, 1);
 313                 current_thread_info()->status &= ~TS_POLLING;
 314                 /*
 315                  * TS_POLLING-cleared state must be visible before we
 316                  * test NEED_RESCHED:
 317                  */
 318                 smp_mb();
 319
 320                 if (!need_resched())
 321                         safe_halt();    /* enables interrupts racelessly */
 322                 else
 323                         local_irq_enable();
 324                 current_thread_info()->status |= TS_POLLING;
 325         } else {
 326                 local_irq_enable();
 327                 /* loop is done by the caller */
 328                 cpu_relax();
 329         }
 330 }
 331 #ifdef CONFIG_APM_MODULE
 332 EXPORT_SYMBOL(default_idle);
 333 #endif
 334
 335 void stop_this_cpu(void *dummy)
 336 {
 337         local_irq_disable();
 338         /*
 339          * Remove this CPU:
 340          */
 341         set_cpu_online(smp_processor_id(), false);
 342         disable_local_APIC();
 343
 344         for (;;) {
 345                 if (hlt_works(smp_processor_id()))
 346                         halt();
 347         }
 348 }
 349
 350 static void do_nothing(void *unused)
 351 {
 352 }
 353
 354 /*
 355  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 356  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 357  * handler on SMP systems.
 358  *
 359  * Caller must have changed pm_idle to the new value before the call. Old
 360  * pm_idle value will not be used by any CPU after the return of this function.
 361  */
 362 void cpu_idle_wait(void)
 363 {
 364         smp_mb();
 365         /* kick all the CPUs so that they exit out of pm_idle */
 366         smp_call_function(do_nothing, NULL, 1);
 367 }
 368 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 369
 370 /*
 371  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 372  * which can obviate IPI to trigger checking of need_resched.
 373  * We execute MONITOR against need_resched and enter optimized wait state
 374  * through MWAIT. Whenever someone changes need_resched, we would be woken
 375  * up from MWAIT (without an IPI).
 376  *
 377  * New with Core Duo processors, MWAIT can take some hints based on CPU
 378  * capability.
 379  */
 380 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 381 {
 382         trace_power_start(POWER_CSTATE, (ax>>4)+1);
 383         if (!need_resched()) {
 384                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 385                         clflush((void *)&current_thread_info()->flags);
 386
 387                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 388                 smp_mb();
 389                 if (!need_resched())
 390                         __mwait(ax, cx);
 391         }
 392 }
 393
 394 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 395 static void mwait_idle(void)
 396 {
 397         if (!need_resched()) {
 398                 trace_power_start(POWER_CSTATE, 1);
 399                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 400                         clflush((void *)&current_thread_info()->flags);
 401
 402                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 403                 smp_mb();
 404                 if (!need_resched())
 405                         __sti_mwait(0, 0);
 406                 else
 407                         local_irq_enable();
 408         } else
 409                 local_irq_enable();
 410 }
 411
 412 /*
 413  * On SMP it's slightly faster (but much more power-consuming!)
 414  * to poll the ->work.need_resched flag instead of waiting for the
 415  * cross-CPU IPI to arrive. Use this option with caution.
 416  */
 417 static void poll_idle(void)
 418 {
 419         trace_power_start(POWER_CSTATE, 0);
 420         local_irq_enable();
 421         while (!need_resched())
 422                 cpu_relax();
 423         trace_power_end(0);
 424 }
 425
 426 /*
 427  * mwait selection logic:
 428  *
 429  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 430  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 431  * then depend on a clock divisor and current Pstate of the core. If
 432  * all cores of a processor are in halt state (C1) the processor can
 433  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 434  * happen.
 435  *
 436  * idle=mwait overrides this decision and forces the usage of mwait.
 437  */
 438 static int __cpuinitdata force_mwait;
 439
 440 #define MWAIT_INFO                      0x05
 441 #define MWAIT_ECX_EXTENDED_INFO         0x01
 442 #define MWAIT_EDX_C1                    0xf0
 443
 444 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 445 {
 446         u32 eax, ebx, ecx, edx;
 447
 448         if (force_mwait)
 449                 return 1;
 450
 451         if (c->cpuid_level < MWAIT_INFO)
 452                 return 0;
 453
 454         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 455         /* Check, whether EDX has extended info about MWAIT */
 456         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 457                 return 1;
 458
 459         /*
 460          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 461          * C1  supports MWAIT
 462          */
 463         return (edx & MWAIT_EDX_C1);
 464 }
 465
 466 /*
 467  * Check for AMD CPUs, which have potentially C1E support
 468  */
 469 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 470 {
 471         if (c->x86_vendor != X86_VENDOR_AMD)
 472                 return 0;
 473
 474         if (c->x86 < 0x0F)
 475                 return 0;
 476
 477         /* Family 0x0f models < rev F do not have C1E */
 478         if (c->x86 == 0x0f && c->x86_model < 0x40)
 479                 return 0;
 480
 481         return 1;
 482 }
 483
 484 static cpumask_var_t c1e_mask;
 485 static int c1e_detected;
 486
 487 void c1e_remove_cpu(int cpu)
 488 {
 489         if (c1e_mask != NULL)
 490                 cpumask_clear_cpu(cpu, c1e_mask);
 491 }
 492
 493 /*
 494  * C1E aware idle routine. We check for C1E active in the interrupt
 495  * pending message MSR. If we detect C1E, then we handle it the same
 496  * way as C3 power states (local apic timer and TSC stop)
 497  */
 498 static void c1e_idle(void)
 499 {
 500         if (need_resched())
 501                 return;
 502
 503         if (!c1e_detected) {
 504                 u32 lo, hi;
 505
 506                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 507                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 508                         c1e_detected = 1;
 509                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 510                                 mark_tsc_unstable("TSC halt in AMD C1E");
 511                         printk(KERN_INFO "System has AMD C1E enabled\n");
 512                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 513                 }
 514         }
 515
 516         if (c1e_detected) {
 517                 int cpu = smp_processor_id();
 518
 519                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
 520                         cpumask_set_cpu(cpu, c1e_mask);
 521                         /*
 522                          * Force broadcast so ACPI can not interfere.
 523                          */
 524                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 525                                            &cpu);
 526                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 527                                cpu);
 528                 }
 529                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 530
 531                 default_idle();
 532
 533                 /*
 534                  * The switch back from broadcast mode needs to be
 535                  * called with interrupts disabled.
 536                  */
 537                  local_irq_disable();
 538                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 539                  local_irq_enable();
 540         } else
 541                 default_idle();
 542 }
 543
 544 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 545 {
 546 #ifdef CONFIG_SMP
 547         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 548                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 549                         " performance may degrade.\n");
 550         }
 551 #endif
 552         if (pm_idle)
 553                 return;
 554
 555         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 556                 /*
 557                  * One CPU supports mwait => All CPUs supports mwait
 558                  */
 559                 printk(KERN_INFO "using mwait in idle threads.\n");
 560                 pm_idle = mwait_idle;
 561         } else if (check_c1e_idle(c)) {
 562                 printk(KERN_INFO "using C1E aware idle routine\n");
 563                 pm_idle = c1e_idle;
 564         } else
 565                 pm_idle = default_idle;
 566 }
 567
 568 void __init init_c1e_mask(void)
 569 {
 570         /* If we're using c1e_idle, we need to allocate c1e_mask. */
 571         if (pm_idle == c1e_idle)
 572                 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
 573 }
 574
 575 static int __init idle_setup(char *str)
 576 {
 577         if (!str)
 578                 return -EINVAL;
 579
 580         if (!strcmp(str, "poll")) {
 581                 printk("using polling idle threads.\n");
 582                 pm_idle = poll_idle;
 583         } else if (!strcmp(str, "mwait"))
 584                 force_mwait = 1;
 585         else if (!strcmp(str, "halt")) {
 586                 /*
 587                  * When the boot option of idle=halt is added, halt is
 588                  * forced to be used for CPU idle. In such case CPU C2/C3
 589                  * won't be used again.
 590                  * To continue to load the CPU idle driver, don't touch
 591                  * the boot_option_idle_override.
 592                  */
 593                 pm_idle = default_idle;
 594                 idle_halt = 1;
 595                 return 0;
 596         } else if (!strcmp(str, "nomwait")) {
 597                 /*
 598                  * If the boot option of "idle=nomwait" is added,
 599                  * it means that mwait will be disabled for CPU C2/C3
 600                  * states. In such case it won't touch the variable
 601                  * of boot_option_idle_override.
 602                  */
 603                 idle_nomwait = 1;
 604                 return 0;
 605         } else
 606                 return -1;
 607
 608         boot_option_idle_override = 1;
 609         return 0;
 610 }
 611 early_param("idle", idle_setup);
 612
 613 unsigned long arch_align_stack(unsigned long sp)
 614 {
 615         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 616                 sp -= get_random_int() % 8192;
 617         return sp & ~0xf;
 618 }
 619
 620 unsigned long arch_randomize_brk(struct mm_struct *mm)
 621 {
 622         unsigned long range_end = mm->brk + 0x02000000;
 623         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 624 }
 625