2 * Copyright (C) 1995 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * CPU hotplug support - ashok.raj@intel.com
14 * This file handles the architecture-dependent parts of process handling..
17 #include <linux/cpu.h>
18 #include <linux/errno.h>
19 #include <linux/sched.h>
21 #include <linux/kernel.h>
23 #include <linux/elfcore.h>
24 #include <linux/smp.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/module.h>
30 #include <linux/ptrace.h>
31 #include <linux/notifier.h>
32 #include <linux/kprobes.h>
33 #include <linux/kdebug.h>
34 #include <linux/prctl.h>
35 #include <linux/uaccess.h>
37 #include <linux/ftrace.h>
39 #include <asm/pgtable.h>
40 #include <asm/processor.h>
41 #include <asm/fpu/internal.h>
42 #include <asm/mmu_context.h>
43 #include <asm/prctl.h>
45 #include <asm/proto.h>
48 #include <asm/syscalls.h>
49 #include <asm/debugreg.h>
50 #include <asm/switch_to.h>
52 asmlinkage
extern void ret_from_fork(void);
54 __visible
DEFINE_PER_CPU(unsigned long, rsp_scratch
);
56 /* Prints also some state that isn't saved in the pt_regs */
57 void __show_regs(struct pt_regs
*regs
, int all
)
59 unsigned long cr0
= 0L, cr2
= 0L, cr3
= 0L, cr4
= 0L, fs
, gs
, shadowgs
;
60 unsigned long d0
, d1
, d2
, d3
, d6
, d7
;
61 unsigned int fsindex
, gsindex
;
62 unsigned int ds
, cs
, es
;
64 printk(KERN_DEFAULT
"RIP: %04lx:[<%016lx>] ", regs
->cs
& 0xffff, regs
->ip
);
65 printk_address(regs
->ip
);
66 printk(KERN_DEFAULT
"RSP: %04lx:%016lx EFLAGS: %08lx\n", regs
->ss
,
67 regs
->sp
, regs
->flags
);
68 printk(KERN_DEFAULT
"RAX: %016lx RBX: %016lx RCX: %016lx\n",
69 regs
->ax
, regs
->bx
, regs
->cx
);
70 printk(KERN_DEFAULT
"RDX: %016lx RSI: %016lx RDI: %016lx\n",
71 regs
->dx
, regs
->si
, regs
->di
);
72 printk(KERN_DEFAULT
"RBP: %016lx R08: %016lx R09: %016lx\n",
73 regs
->bp
, regs
->r8
, regs
->r9
);
74 printk(KERN_DEFAULT
"R10: %016lx R11: %016lx R12: %016lx\n",
75 regs
->r10
, regs
->r11
, regs
->r12
);
76 printk(KERN_DEFAULT
"R13: %016lx R14: %016lx R15: %016lx\n",
77 regs
->r13
, regs
->r14
, regs
->r15
);
79 asm("movl %%ds,%0" : "=r" (ds
));
80 asm("movl %%cs,%0" : "=r" (cs
));
81 asm("movl %%es,%0" : "=r" (es
));
82 asm("movl %%fs,%0" : "=r" (fsindex
));
83 asm("movl %%gs,%0" : "=r" (gsindex
));
85 rdmsrl(MSR_FS_BASE
, fs
);
86 rdmsrl(MSR_GS_BASE
, gs
);
87 rdmsrl(MSR_KERNEL_GS_BASE
, shadowgs
);
97 printk(KERN_DEFAULT
"FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n",
98 fs
, fsindex
, gs
, gsindex
, shadowgs
);
99 printk(KERN_DEFAULT
"CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs
, ds
,
101 printk(KERN_DEFAULT
"CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2
, cr3
,
111 /* Only print out debug registers if they are in their non-default state. */
112 if ((d0
== 0) && (d1
== 0) && (d2
== 0) && (d3
== 0) &&
113 (d6
== DR6_RESERVED
) && (d7
== 0x400))
116 printk(KERN_DEFAULT
"DR0: %016lx DR1: %016lx DR2: %016lx\n", d0
, d1
, d2
);
117 printk(KERN_DEFAULT
"DR3: %016lx DR6: %016lx DR7: %016lx\n", d3
, d6
, d7
);
119 if (boot_cpu_has(X86_FEATURE_OSPKE
))
120 printk(KERN_DEFAULT
"PKRU: %08x\n", read_pkru());
123 void release_thread(struct task_struct
*dead_task
)
126 #ifdef CONFIG_MODIFY_LDT_SYSCALL
127 if (dead_task
->mm
->context
.ldt
) {
128 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n",
130 dead_task
->mm
->context
.ldt
->entries
,
131 dead_task
->mm
->context
.ldt
->size
);
138 static inline void set_32bit_tls(struct task_struct
*t
, int tls
, u32 addr
)
140 struct user_desc ud
= {
147 struct desc_struct
*desc
= t
->thread
.tls_array
;
152 static inline u32
read_32bit_tls(struct task_struct
*t
, int tls
)
154 return get_desc_base(&t
->thread
.tls_array
[tls
]);
157 int copy_thread_tls(unsigned long clone_flags
, unsigned long sp
,
158 unsigned long arg
, struct task_struct
*p
, unsigned long tls
)
161 struct pt_regs
*childregs
;
162 struct task_struct
*me
= current
;
164 p
->thread
.sp0
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
165 childregs
= task_pt_regs(p
);
166 p
->thread
.sp
= (unsigned long) childregs
;
167 set_tsk_thread_flag(p
, TIF_FORK
);
168 p
->thread
.io_bitmap_ptr
= NULL
;
170 savesegment(gs
, p
->thread
.gsindex
);
171 p
->thread
.gs
= p
->thread
.gsindex
? 0 : me
->thread
.gs
;
172 savesegment(fs
, p
->thread
.fsindex
);
173 p
->thread
.fs
= p
->thread
.fsindex
? 0 : me
->thread
.fs
;
174 savesegment(es
, p
->thread
.es
);
175 savesegment(ds
, p
->thread
.ds
);
176 memset(p
->thread
.ptrace_bps
, 0, sizeof(p
->thread
.ptrace_bps
));
178 if (unlikely(p
->flags
& PF_KTHREAD
)) {
180 memset(childregs
, 0, sizeof(struct pt_regs
));
181 childregs
->sp
= (unsigned long)childregs
;
182 childregs
->ss
= __KERNEL_DS
;
183 childregs
->bx
= sp
; /* function */
185 childregs
->orig_ax
= -1;
186 childregs
->cs
= __KERNEL_CS
| get_kernel_rpl();
187 childregs
->flags
= X86_EFLAGS_IF
| X86_EFLAGS_FIXED
;
190 *childregs
= *current_pt_regs();
197 if (unlikely(test_tsk_thread_flag(me
, TIF_IO_BITMAP
))) {
198 p
->thread
.io_bitmap_ptr
= kmemdup(me
->thread
.io_bitmap_ptr
,
199 IO_BITMAP_BYTES
, GFP_KERNEL
);
200 if (!p
->thread
.io_bitmap_ptr
) {
201 p
->thread
.io_bitmap_max
= 0;
204 set_tsk_thread_flag(p
, TIF_IO_BITMAP
);
208 * Set a new TLS for the child thread?
210 if (clone_flags
& CLONE_SETTLS
) {
211 #ifdef CONFIG_IA32_EMULATION
213 err
= do_set_thread_area(p
, -1,
214 (struct user_desc __user
*)tls
, 0);
217 err
= do_arch_prctl(p
, ARCH_SET_FS
, tls
);
223 if (err
&& p
->thread
.io_bitmap_ptr
) {
224 kfree(p
->thread
.io_bitmap_ptr
);
225 p
->thread
.io_bitmap_max
= 0;
232 start_thread_common(struct pt_regs
*regs
, unsigned long new_ip
,
233 unsigned long new_sp
,
234 unsigned int _cs
, unsigned int _ss
, unsigned int _ds
)
237 loadsegment(es
, _ds
);
238 loadsegment(ds
, _ds
);
244 regs
->flags
= X86_EFLAGS_IF
;
249 start_thread(struct pt_regs
*regs
, unsigned long new_ip
, unsigned long new_sp
)
251 start_thread_common(regs
, new_ip
, new_sp
,
252 __USER_CS
, __USER_DS
, 0);
256 void compat_start_thread(struct pt_regs
*regs
, u32 new_ip
, u32 new_sp
)
258 start_thread_common(regs
, new_ip
, new_sp
,
259 test_thread_flag(TIF_X32
)
260 ? __USER_CS
: __USER32_CS
,
261 __USER_DS
, __USER_DS
);
266 * switch_to(x,y) should switch tasks from x to y.
268 * This could still be optimized:
269 * - fold all the options into a flag word and test it with a single test.
270 * - could test fs/gs bitsliced
272 * Kprobes not supported here. Set the probe on schedule instead.
273 * Function graph tracer not supported too.
275 __visible __notrace_funcgraph
struct task_struct
*
276 __switch_to(struct task_struct
*prev_p
, struct task_struct
*next_p
)
278 struct thread_struct
*prev
= &prev_p
->thread
;
279 struct thread_struct
*next
= &next_p
->thread
;
280 struct fpu
*prev_fpu
= &prev
->fpu
;
281 struct fpu
*next_fpu
= &next
->fpu
;
282 int cpu
= smp_processor_id();
283 struct tss_struct
*tss
= &per_cpu(cpu_tss
, cpu
);
284 unsigned fsindex
, gsindex
;
285 fpu_switch_t fpu_switch
;
287 fpu_switch
= switch_fpu_prepare(prev_fpu
, next_fpu
, cpu
);
289 /* We must save %fs and %gs before load_TLS() because
290 * %fs and %gs may be cleared by load_TLS().
292 * (e.g. xen_load_tls())
294 savesegment(fs
, fsindex
);
295 savesegment(gs
, gsindex
);
298 * Load TLS before restoring any segments so that segment loads
299 * reference the correct GDT entries.
304 * Leave lazy mode, flushing any hypercalls made here. This
305 * must be done after loading TLS entries in the GDT but before
306 * loading segments that might reference them, and and it must
307 * be done before fpu__restore(), so the TS bit is up to
310 arch_end_context_switch(next_p
);
314 * Reading them only returns the selectors, but writing them (if
315 * nonzero) loads the full descriptor from the GDT or LDT. The
316 * LDT for next is loaded in switch_mm, and the GDT is loaded
319 * We therefore need to write new values to the segment
320 * registers on every context switch unless both the new and old
323 * Note that we don't need to do anything for CS and SS, as
324 * those are saved and restored as part of pt_regs.
326 savesegment(es
, prev
->es
);
327 if (unlikely(next
->es
| prev
->es
))
328 loadsegment(es
, next
->es
);
330 savesegment(ds
, prev
->ds
);
331 if (unlikely(next
->ds
| prev
->ds
))
332 loadsegment(ds
, next
->ds
);
337 * These are even more complicated than DS and ES: they have
338 * 64-bit bases are that controlled by arch_prctl. Those bases
339 * only differ from the values in the GDT or LDT if the selector
342 * Loading the segment register resets the hidden base part of
343 * the register to 0 or the value from the GDT / LDT. If the
344 * next base address zero, writing 0 to the segment register is
345 * much faster than using wrmsr to explicitly zero the base.
347 * The thread_struct.fs and thread_struct.gs values are 0
348 * if the fs and gs bases respectively are not overridden
349 * from the values implied by fsindex and gsindex. They
350 * are nonzero, and store the nonzero base addresses, if
351 * the bases are overridden.
353 * (fs != 0 && fsindex != 0) || (gs != 0 && gsindex != 0) should
356 * Therefore we need to reload the segment registers if either
357 * the old or new selector is nonzero, and we need to override
358 * the base address if next thread expects it to be overridden.
360 * This code is unnecessarily slow in the case where the old and
361 * new indexes are zero and the new base is nonzero -- it will
362 * unnecessarily write 0 to the selector before writing the new
365 * Note: This all depends on arch_prctl being the only way that
366 * user code can override the segment base. Once wrfsbase and
367 * wrgsbase are enabled, most of this code will need to change.
369 if (unlikely(fsindex
| next
->fsindex
| prev
->fs
)) {
370 loadsegment(fs
, next
->fsindex
);
373 * If user code wrote a nonzero value to FS, then it also
374 * cleared the overridden base address.
376 * XXX: if user code wrote 0 to FS and cleared the base
377 * address itself, we won't notice and we'll incorrectly
378 * restore the prior base address next time we reschdule
385 wrmsrl(MSR_FS_BASE
, next
->fs
);
386 prev
->fsindex
= fsindex
;
388 if (unlikely(gsindex
| next
->gsindex
| prev
->gs
)) {
389 load_gs_index(next
->gsindex
);
391 /* This works (and fails) the same way as fsindex above. */
396 wrmsrl(MSR_KERNEL_GS_BASE
, next
->gs
);
397 prev
->gsindex
= gsindex
;
399 switch_fpu_finish(next_fpu
, fpu_switch
);
402 * Switch the PDA and FPU contexts.
404 this_cpu_write(current_task
, next_p
);
406 /* Reload esp0 and ss1. This changes current_thread_info(). */
410 * Now maybe reload the debug registers and handle I/O bitmaps
412 if (unlikely(task_thread_info(next_p
)->flags
& _TIF_WORK_CTXSW_NEXT
||
413 task_thread_info(prev_p
)->flags
& _TIF_WORK_CTXSW_PREV
))
414 __switch_to_xtra(prev_p
, next_p
, tss
);
416 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS
)) {
418 * AMD CPUs have a misfeature: SYSRET sets the SS selector but
419 * does not update the cached descriptor. As a result, if we
420 * do SYSRET while SS is NULL, we'll end up in user mode with
421 * SS apparently equal to __USER_DS but actually unusable.
423 * The straightforward workaround would be to fix it up just
424 * before SYSRET, but that would slow down the system call
425 * fast paths. Instead, we ensure that SS is never NULL in
426 * system call context. We do this by replacing NULL SS
427 * selectors at every context switch. SYSCALL sets up a valid
428 * SS, so the only way to get NULL is to re-enter the kernel
429 * from CPL 3 through an interrupt. Since that can't happen
430 * in the same task as a running syscall, we are guaranteed to
431 * context switch between every interrupt vector entry and a
434 * We read SS first because SS reads are much faster than
435 * writes. Out of caution, we force SS to __KERNEL_DS even if
436 * it previously had a different non-NULL value.
438 unsigned short ss_sel
;
439 savesegment(ss
, ss_sel
);
440 if (ss_sel
!= __KERNEL_DS
)
441 loadsegment(ss
, __KERNEL_DS
);
447 void set_personality_64bit(void)
449 /* inherit personality from parent */
451 /* Make sure to be in 64bit mode */
452 clear_thread_flag(TIF_IA32
);
453 clear_thread_flag(TIF_ADDR32
);
454 clear_thread_flag(TIF_X32
);
456 /* Ensure the corresponding mm is not marked. */
458 current
->mm
->context
.ia32_compat
= 0;
460 /* TBD: overwrites user setup. Should have two bits.
461 But 64bit processes have always behaved this way,
462 so it's not too bad. The main problem is just that
463 32bit childs are affected again. */
464 current
->personality
&= ~READ_IMPLIES_EXEC
;
467 void set_personality_ia32(bool x32
)
469 /* inherit personality from parent */
471 /* Make sure to be in 32bit mode */
472 set_thread_flag(TIF_ADDR32
);
474 /* Mark the associated mm as containing 32-bit tasks. */
476 clear_thread_flag(TIF_IA32
);
477 set_thread_flag(TIF_X32
);
479 current
->mm
->context
.ia32_compat
= TIF_X32
;
480 current
->personality
&= ~READ_IMPLIES_EXEC
;
481 /* is_compat_task() uses the presence of the x32
482 syscall bit flag to determine compat status */
483 current_thread_info()->status
&= ~TS_COMPAT
;
485 set_thread_flag(TIF_IA32
);
486 clear_thread_flag(TIF_X32
);
488 current
->mm
->context
.ia32_compat
= TIF_IA32
;
489 current
->personality
|= force_personality32
;
490 /* Prepare the first "return" to user space */
491 current_thread_info()->status
|= TS_COMPAT
;
494 EXPORT_SYMBOL_GPL(set_personality_ia32
);
496 long do_arch_prctl(struct task_struct
*task
, int code
, unsigned long addr
)
499 int doit
= task
== current
;
504 if (addr
>= TASK_SIZE_OF(task
))
507 /* handle small bases via the GDT because that's faster to
509 if (addr
<= 0xffffffff) {
510 set_32bit_tls(task
, GS_TLS
, addr
);
512 load_TLS(&task
->thread
, cpu
);
513 load_gs_index(GS_TLS_SEL
);
515 task
->thread
.gsindex
= GS_TLS_SEL
;
518 task
->thread
.gsindex
= 0;
519 task
->thread
.gs
= addr
;
522 ret
= wrmsrl_safe(MSR_KERNEL_GS_BASE
, addr
);
528 /* Not strictly needed for fs, but do it for symmetry
530 if (addr
>= TASK_SIZE_OF(task
))
533 /* handle small bases via the GDT because that's faster to
535 if (addr
<= 0xffffffff) {
536 set_32bit_tls(task
, FS_TLS
, addr
);
538 load_TLS(&task
->thread
, cpu
);
539 loadsegment(fs
, FS_TLS_SEL
);
541 task
->thread
.fsindex
= FS_TLS_SEL
;
544 task
->thread
.fsindex
= 0;
545 task
->thread
.fs
= addr
;
547 /* set the selector to 0 to not confuse
550 ret
= wrmsrl_safe(MSR_FS_BASE
, addr
);
557 if (task
->thread
.fsindex
== FS_TLS_SEL
)
558 base
= read_32bit_tls(task
, FS_TLS
);
560 rdmsrl(MSR_FS_BASE
, base
);
562 base
= task
->thread
.fs
;
563 ret
= put_user(base
, (unsigned long __user
*)addr
);
569 if (task
->thread
.gsindex
== GS_TLS_SEL
)
570 base
= read_32bit_tls(task
, GS_TLS
);
572 savesegment(gs
, gsindex
);
574 rdmsrl(MSR_KERNEL_GS_BASE
, base
);
576 base
= task
->thread
.gs
;
578 base
= task
->thread
.gs
;
579 ret
= put_user(base
, (unsigned long __user
*)addr
);
591 long sys_arch_prctl(int code
, unsigned long addr
)
593 return do_arch_prctl(current
, code
, addr
);
596 unsigned long KSTK_ESP(struct task_struct
*task
)
598 return task_pt_regs(task
)->sp
;