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x86: cleanup PAT cpu validation
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <asm/pci-direct.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/iscsi_ibft.h>
38 #include <linux/mmzone.h>
39 #include <linux/kexec.h>
40 #include <linux/cpufreq.h>
41 #include <linux/dmi.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/ctype.h>
44 #include <linux/sort.h>
45 #include <linux/uaccess.h>
46 #include <linux/init_ohci1394_dma.h>
47 #include <linux/kvm_para.h>
48
49 #include <asm/mtrr.h>
50 #include <asm/uaccess.h>
51 #include <asm/system.h>
52 #include <asm/vsyscall.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <video/edid.h>
58 #include <asm/e820.h>
59 #include <asm/dma.h>
60 #include <asm/gart.h>
61 #include <asm/mpspec.h>
62 #include <asm/mmu_context.h>
63 #include <asm/proto.h>
64 #include <asm/setup.h>
65 #include <asm/numa.h>
66 #include <asm/sections.h>
67 #include <asm/dmi.h>
68 #include <asm/cacheflush.h>
69 #include <asm/mce.h>
70 #include <asm/ds.h>
71 #include <asm/topology.h>
72 #include <asm/trampoline.h>
73 #include <asm/pat.h>
74
75 #include <mach_apic.h>
76 #ifdef CONFIG_PARAVIRT
77 #include <asm/paravirt.h>
78 #else
79 #define ARCH_SETUP
80 #endif
81
82 /*
83 * Machine setup..
84 */
85
86 struct cpuinfo_x86 boot_cpu_data __read_mostly;
87 EXPORT_SYMBOL(boot_cpu_data);
88
89 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
90
91 unsigned long mmu_cr4_features;
92
93 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
94 int bootloader_type;
95
96 unsigned long saved_video_mode;
97
98 int force_mwait __cpuinitdata;
99
100 /*
101 * Early DMI memory
102 */
103 int dmi_alloc_index;
104 char dmi_alloc_data[DMI_MAX_DATA];
105
106 /*
107 * Setup options
108 */
109 struct screen_info screen_info;
110 EXPORT_SYMBOL(screen_info);
111 struct sys_desc_table_struct {
112 unsigned short length;
113 unsigned char table[0];
114 };
115
116 struct edid_info edid_info;
117 EXPORT_SYMBOL_GPL(edid_info);
118
119 extern int root_mountflags;
120
121 char __initdata command_line[COMMAND_LINE_SIZE];
122
123 static struct resource standard_io_resources[] = {
124 { .name = "dma1", .start = 0x00, .end = 0x1f,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "pic1", .start = 0x20, .end = 0x21,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "timer0", .start = 0x40, .end = 0x43,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "timer1", .start = 0x50, .end = 0x53,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "keyboard", .start = 0x60, .end = 0x6f,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
136 { .name = "pic2", .start = 0xa0, .end = 0xa1,
137 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
138 { .name = "dma2", .start = 0xc0, .end = 0xdf,
139 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
140 { .name = "fpu", .start = 0xf0, .end = 0xff,
141 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
142 };
143
144 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
145
146 static struct resource data_resource = {
147 .name = "Kernel data",
148 .start = 0,
149 .end = 0,
150 .flags = IORESOURCE_RAM,
151 };
152 static struct resource code_resource = {
153 .name = "Kernel code",
154 .start = 0,
155 .end = 0,
156 .flags = IORESOURCE_RAM,
157 };
158 static struct resource bss_resource = {
159 .name = "Kernel bss",
160 .start = 0,
161 .end = 0,
162 .flags = IORESOURCE_RAM,
163 };
164
165 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
166
167 #ifdef CONFIG_PROC_VMCORE
168 /* elfcorehdr= specifies the location of elf core header
169 * stored by the crashed kernel. This option will be passed
170 * by kexec loader to the capture kernel.
171 */
172 static int __init setup_elfcorehdr(char *arg)
173 {
174 char *end;
175 if (!arg)
176 return -EINVAL;
177 elfcorehdr_addr = memparse(arg, &end);
178 return end > arg ? 0 : -EINVAL;
179 }
180 early_param("elfcorehdr", setup_elfcorehdr);
181 #endif
182
183 #ifndef CONFIG_NUMA
184 static void __init
185 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
186 {
187 unsigned long bootmap_size, bootmap;
188
189 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
190 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
191 PAGE_SIZE);
192 if (bootmap == -1L)
193 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
194 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
195 e820_register_active_regions(0, start_pfn, end_pfn);
196 free_bootmem_with_active_regions(0, end_pfn);
197 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
198 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
199 }
200 #endif
201
202 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
203 struct edd edd;
204 #ifdef CONFIG_EDD_MODULE
205 EXPORT_SYMBOL(edd);
206 #endif
207 /**
208 * copy_edd() - Copy the BIOS EDD information
209 * from boot_params into a safe place.
210 *
211 */
212 static inline void copy_edd(void)
213 {
214 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
215 sizeof(edd.mbr_signature));
216 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
217 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
218 edd.edd_info_nr = boot_params.eddbuf_entries;
219 }
220 #else
221 static inline void copy_edd(void)
222 {
223 }
224 #endif
225
226 #ifdef CONFIG_KEXEC
227 static void __init reserve_crashkernel(void)
228 {
229 unsigned long long total_mem;
230 unsigned long long crash_size, crash_base;
231 int ret;
232
233 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
234
235 ret = parse_crashkernel(boot_command_line, total_mem,
236 &crash_size, &crash_base);
237 if (ret == 0 && crash_size) {
238 if (crash_base <= 0) {
239 printk(KERN_INFO "crashkernel reservation failed - "
240 "you have to specify a base address\n");
241 return;
242 }
243
244 if (reserve_bootmem(crash_base, crash_size,
245 BOOTMEM_EXCLUSIVE) < 0) {
246 printk(KERN_INFO "crashkernel reservation failed - "
247 "memory is in use\n");
248 return;
249 }
250
251 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
252 "for crashkernel (System RAM: %ldMB)\n",
253 (unsigned long)(crash_size >> 20),
254 (unsigned long)(crash_base >> 20),
255 (unsigned long)(total_mem >> 20));
256 crashk_res.start = crash_base;
257 crashk_res.end = crash_base + crash_size - 1;
258 insert_resource(&iomem_resource, &crashk_res);
259 }
260 }
261 #else
262 static inline void __init reserve_crashkernel(void)
263 {}
264 #endif
265
266 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
267 void __attribute__((weak)) __init memory_setup(void)
268 {
269 machine_specific_memory_setup();
270 }
271
272 static void __init parse_setup_data(void)
273 {
274 struct setup_data *data;
275 unsigned long pa_data;
276
277 if (boot_params.hdr.version < 0x0209)
278 return;
279 pa_data = boot_params.hdr.setup_data;
280 while (pa_data) {
281 data = early_ioremap(pa_data, PAGE_SIZE);
282 switch (data->type) {
283 default:
284 break;
285 }
286 #ifndef CONFIG_DEBUG_BOOT_PARAMS
287 free_early(pa_data, pa_data+sizeof(*data)+data->len);
288 #endif
289 pa_data = data->next;
290 early_iounmap(data, PAGE_SIZE);
291 }
292 }
293
294 #ifdef CONFIG_PCI_MMCONFIG
295 extern void __cpuinit fam10h_check_enable_mmcfg(void);
296 extern void __init check_enable_amd_mmconf_dmi(void);
297 #else
298 void __cpuinit fam10h_check_enable_mmcfg(void)
299 {
300 }
301 void __init check_enable_amd_mmconf_dmi(void)
302 {
303 }
304 #endif
305
306 /*
307 * setup_arch - architecture-specific boot-time initializations
308 *
309 * Note: On x86_64, fixmaps are ready for use even before this is called.
310 */
311 void __init setup_arch(char **cmdline_p)
312 {
313 unsigned i;
314
315 printk(KERN_INFO "Command line: %s\n", boot_command_line);
316
317 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
318 screen_info = boot_params.screen_info;
319 edid_info = boot_params.edid_info;
320 saved_video_mode = boot_params.hdr.vid_mode;
321 bootloader_type = boot_params.hdr.type_of_loader;
322
323 #ifdef CONFIG_BLK_DEV_RAM
324 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
325 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
326 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
327 #endif
328 #ifdef CONFIG_EFI
329 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
330 "EL64", 4))
331 efi_enabled = 1;
332 #endif
333
334 ARCH_SETUP
335
336 memory_setup();
337 copy_edd();
338
339 if (!boot_params.hdr.root_flags)
340 root_mountflags &= ~MS_RDONLY;
341 init_mm.start_code = (unsigned long) &_text;
342 init_mm.end_code = (unsigned long) &_etext;
343 init_mm.end_data = (unsigned long) &_edata;
344 init_mm.brk = (unsigned long) &_end;
345
346 code_resource.start = virt_to_phys(&_text);
347 code_resource.end = virt_to_phys(&_etext)-1;
348 data_resource.start = virt_to_phys(&_etext);
349 data_resource.end = virt_to_phys(&_edata)-1;
350 bss_resource.start = virt_to_phys(&__bss_start);
351 bss_resource.end = virt_to_phys(&__bss_stop)-1;
352
353 early_identify_cpu(&boot_cpu_data);
354
355 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
356 *cmdline_p = command_line;
357
358 parse_setup_data();
359
360 parse_early_param();
361
362 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
363 if (init_ohci1394_dma_early)
364 init_ohci1394_dma_on_all_controllers();
365 #endif
366
367 finish_e820_parsing();
368
369 /* after parse_early_param, so could debug it */
370 insert_resource(&iomem_resource, &code_resource);
371 insert_resource(&iomem_resource, &data_resource);
372 insert_resource(&iomem_resource, &bss_resource);
373
374 early_gart_iommu_check();
375
376 e820_register_active_regions(0, 0, -1UL);
377 /*
378 * partially used pages are not usable - thus
379 * we are rounding upwards:
380 */
381 end_pfn = e820_end_of_ram();
382 /* update e820 for memory not covered by WB MTRRs */
383 mtrr_bp_init();
384 if (mtrr_trim_uncached_memory(end_pfn)) {
385 e820_register_active_regions(0, 0, -1UL);
386 end_pfn = e820_end_of_ram();
387 }
388
389 num_physpages = end_pfn;
390
391 check_efer();
392
393 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
394 if (efi_enabled)
395 efi_init();
396
397 vsmp_init();
398
399 dmi_scan_machine();
400
401 io_delay_init();
402
403 #ifdef CONFIG_KVM_CLOCK
404 kvmclock_init();
405 #endif
406
407 #ifdef CONFIG_SMP
408 /* setup to use the early static init tables during kernel startup */
409 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
410 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
411 #ifdef CONFIG_NUMA
412 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
413 #endif
414 #endif
415
416 #ifdef CONFIG_ACPI
417 /*
418 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
419 * Call this early for SRAT node setup.
420 */
421 acpi_boot_table_init();
422 #endif
423
424 /* How many end-of-memory variables you have, grandma! */
425 max_low_pfn = end_pfn;
426 max_pfn = end_pfn;
427 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
428
429 /* Remove active ranges so rediscovery with NUMA-awareness happens */
430 remove_all_active_ranges();
431
432 #ifdef CONFIG_ACPI_NUMA
433 /*
434 * Parse SRAT to discover nodes.
435 */
436 acpi_numa_init();
437 #endif
438
439 #ifdef CONFIG_NUMA
440 numa_initmem_init(0, end_pfn);
441 #else
442 contig_initmem_init(0, end_pfn);
443 #endif
444
445 dma32_reserve_bootmem();
446
447 #ifdef CONFIG_ACPI_SLEEP
448 /*
449 * Reserve low memory region for sleep support.
450 */
451 acpi_reserve_bootmem();
452 #endif
453
454 if (efi_enabled)
455 efi_reserve_bootmem();
456
457 /*
458 * Find and reserve possible boot-time SMP configuration:
459 */
460 find_smp_config();
461 #ifdef CONFIG_BLK_DEV_INITRD
462 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
463 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
464 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
465 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
466 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
467
468 if (ramdisk_end <= end_of_mem) {
469 /*
470 * don't need to reserve again, already reserved early
471 * in x86_64_start_kernel, and early_res_to_bootmem
472 * convert that to reserved in bootmem
473 */
474 initrd_start = ramdisk_image + PAGE_OFFSET;
475 initrd_end = initrd_start+ramdisk_size;
476 } else {
477 free_bootmem(ramdisk_image, ramdisk_size);
478 printk(KERN_ERR "initrd extends beyond end of memory "
479 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
480 ramdisk_end, end_of_mem);
481 initrd_start = 0;
482 }
483 }
484 #endif
485 reserve_crashkernel();
486
487 reserve_ibft_region();
488
489 paging_init();
490 map_vsyscall();
491
492 early_quirks();
493
494 #ifdef CONFIG_ACPI
495 /*
496 * Read APIC and some other early information from ACPI tables.
497 */
498 acpi_boot_init();
499 #endif
500
501 init_cpu_to_node();
502
503 /*
504 * get boot-time SMP configuration:
505 */
506 if (smp_found_config)
507 get_smp_config();
508 init_apic_mappings();
509 ioapic_init_mappings();
510
511 kvm_guest_init();
512
513 /*
514 * We trust e820 completely. No explicit ROM probing in memory.
515 */
516 e820_reserve_resources();
517 e820_mark_nosave_regions();
518
519 /* request I/O space for devices used on all i[345]86 PCs */
520 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
521 request_resource(&ioport_resource, &standard_io_resources[i]);
522
523 e820_setup_gap();
524
525 #ifdef CONFIG_VT
526 #if defined(CONFIG_VGA_CONSOLE)
527 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
528 conswitchp = &vga_con;
529 #elif defined(CONFIG_DUMMY_CONSOLE)
530 conswitchp = &dummy_con;
531 #endif
532 #endif
533
534 /* do this before identify_cpu for boot cpu */
535 check_enable_amd_mmconf_dmi();
536 }
537
538 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
539 {
540 unsigned int *v;
541
542 if (c->extended_cpuid_level < 0x80000004)
543 return 0;
544
545 v = (unsigned int *) c->x86_model_id;
546 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
547 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
548 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
549 c->x86_model_id[48] = 0;
550 return 1;
551 }
552
553
554 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
555 {
556 unsigned int n, dummy, eax, ebx, ecx, edx;
557
558 n = c->extended_cpuid_level;
559
560 if (n >= 0x80000005) {
561 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
562 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
563 "D cache %dK (%d bytes/line)\n",
564 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
565 c->x86_cache_size = (ecx>>24) + (edx>>24);
566 /* On K8 L1 TLB is inclusive, so don't count it */
567 c->x86_tlbsize = 0;
568 }
569
570 if (n >= 0x80000006) {
571 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
572 ecx = cpuid_ecx(0x80000006);
573 c->x86_cache_size = ecx >> 16;
574 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
575
576 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
577 c->x86_cache_size, ecx & 0xFF);
578 }
579 if (n >= 0x80000008) {
580 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
581 c->x86_virt_bits = (eax >> 8) & 0xff;
582 c->x86_phys_bits = eax & 0xff;
583 }
584 }
585
586 #ifdef CONFIG_NUMA
587 static int __cpuinit nearby_node(int apicid)
588 {
589 int i, node;
590
591 for (i = apicid - 1; i >= 0; i--) {
592 node = apicid_to_node[i];
593 if (node != NUMA_NO_NODE && node_online(node))
594 return node;
595 }
596 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
597 node = apicid_to_node[i];
598 if (node != NUMA_NO_NODE && node_online(node))
599 return node;
600 }
601 return first_node(node_online_map); /* Shouldn't happen */
602 }
603 #endif
604
605 /*
606 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
607 * Assumes number of cores is a power of two.
608 */
609 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
610 {
611 #ifdef CONFIG_SMP
612 unsigned bits;
613 #ifdef CONFIG_NUMA
614 int cpu = smp_processor_id();
615 int node = 0;
616 unsigned apicid = hard_smp_processor_id();
617 #endif
618 bits = c->x86_coreid_bits;
619
620 /* Low order bits define the core id (index of core in socket) */
621 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
622 /* Convert the initial APIC ID into the socket ID */
623 c->phys_proc_id = c->initial_apicid >> bits;
624
625 #ifdef CONFIG_NUMA
626 node = c->phys_proc_id;
627 if (apicid_to_node[apicid] != NUMA_NO_NODE)
628 node = apicid_to_node[apicid];
629 if (!node_online(node)) {
630 /* Two possibilities here:
631 - The CPU is missing memory and no node was created.
632 In that case try picking one from a nearby CPU
633 - The APIC IDs differ from the HyperTransport node IDs
634 which the K8 northbridge parsing fills in.
635 Assume they are all increased by a constant offset,
636 but in the same order as the HT nodeids.
637 If that doesn't result in a usable node fall back to the
638 path for the previous case. */
639
640 int ht_nodeid = c->initial_apicid;
641
642 if (ht_nodeid >= 0 &&
643 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
644 node = apicid_to_node[ht_nodeid];
645 /* Pick a nearby node */
646 if (!node_online(node))
647 node = nearby_node(apicid);
648 }
649 numa_set_node(cpu, node);
650
651 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
652 #endif
653 #endif
654 }
655
656 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
657 {
658 #ifdef CONFIG_SMP
659 unsigned bits, ecx;
660
661 /* Multi core CPU? */
662 if (c->extended_cpuid_level < 0x80000008)
663 return;
664
665 ecx = cpuid_ecx(0x80000008);
666
667 c->x86_max_cores = (ecx & 0xff) + 1;
668
669 /* CPU telling us the core id bits shift? */
670 bits = (ecx >> 12) & 0xF;
671
672 /* Otherwise recompute */
673 if (bits == 0) {
674 while ((1 << bits) < c->x86_max_cores)
675 bits++;
676 }
677
678 c->x86_coreid_bits = bits;
679
680 #endif
681 }
682
683 #define ENABLE_C1E_MASK 0x18000000
684 #define CPUID_PROCESSOR_SIGNATURE 1
685 #define CPUID_XFAM 0x0ff00000
686 #define CPUID_XFAM_K8 0x00000000
687 #define CPUID_XFAM_10H 0x00100000
688 #define CPUID_XFAM_11H 0x00200000
689 #define CPUID_XMOD 0x000f0000
690 #define CPUID_XMOD_REV_F 0x00040000
691
692 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
693 static __cpuinit int amd_apic_timer_broken(void)
694 {
695 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
696
697 switch (eax & CPUID_XFAM) {
698 case CPUID_XFAM_K8:
699 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
700 break;
701 case CPUID_XFAM_10H:
702 case CPUID_XFAM_11H:
703 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
704 if (lo & ENABLE_C1E_MASK)
705 return 1;
706 break;
707 default:
708 /* err on the side of caution */
709 return 1;
710 }
711 return 0;
712 }
713
714 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
715 {
716 early_init_amd_mc(c);
717
718 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
719 if (c->x86_power & (1<<8))
720 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
721 }
722
723 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
724 {
725 unsigned level;
726
727 #ifdef CONFIG_SMP
728 unsigned long value;
729
730 /*
731 * Disable TLB flush filter by setting HWCR.FFDIS on K8
732 * bit 6 of msr C001_0015
733 *
734 * Errata 63 for SH-B3 steppings
735 * Errata 122 for all steppings (F+ have it disabled by default)
736 */
737 if (c->x86 == 15) {
738 rdmsrl(MSR_K8_HWCR, value);
739 value |= 1 << 6;
740 wrmsrl(MSR_K8_HWCR, value);
741 }
742 #endif
743
744 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
745 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
746 clear_cpu_cap(c, 0*32+31);
747
748 /* On C+ stepping K8 rep microcode works well for copy/memset */
749 level = cpuid_eax(1);
750 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
751 level >= 0x0f58))
752 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
753 if (c->x86 == 0x10 || c->x86 == 0x11)
754 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
755
756 /* Enable workaround for FXSAVE leak */
757 if (c->x86 >= 6)
758 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
759
760 level = get_model_name(c);
761 if (!level) {
762 switch (c->x86) {
763 case 15:
764 /* Should distinguish Models here, but this is only
765 a fallback anyways. */
766 strcpy(c->x86_model_id, "Hammer");
767 break;
768 }
769 }
770 display_cacheinfo(c);
771
772 /* Multi core CPU? */
773 if (c->extended_cpuid_level >= 0x80000008)
774 amd_detect_cmp(c);
775
776 if (c->extended_cpuid_level >= 0x80000006 &&
777 (cpuid_edx(0x80000006) & 0xf000))
778 num_cache_leaves = 4;
779 else
780 num_cache_leaves = 3;
781
782 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
783 set_cpu_cap(c, X86_FEATURE_K8);
784
785 /* MFENCE stops RDTSC speculation */
786 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
787
788 if (c->x86 == 0x10)
789 fam10h_check_enable_mmcfg();
790
791 if (amd_apic_timer_broken())
792 disable_apic_timer = 1;
793
794 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
795 unsigned long long tseg;
796
797 /*
798 * Split up direct mapping around the TSEG SMM area.
799 * Don't do it for gbpages because there seems very little
800 * benefit in doing so.
801 */
802 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
803 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
804 set_memory_4k((unsigned long)__va(tseg), 1);
805 }
806 }
807
808 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
809 {
810 #ifdef CONFIG_SMP
811 u32 eax, ebx, ecx, edx;
812 int index_msb, core_bits;
813
814 cpuid(1, &eax, &ebx, &ecx, &edx);
815
816
817 if (!cpu_has(c, X86_FEATURE_HT))
818 return;
819 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
820 goto out;
821
822 smp_num_siblings = (ebx & 0xff0000) >> 16;
823
824 if (smp_num_siblings == 1) {
825 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
826 } else if (smp_num_siblings > 1) {
827
828 if (smp_num_siblings > NR_CPUS) {
829 printk(KERN_WARNING "CPU: Unsupported number of "
830 "siblings %d", smp_num_siblings);
831 smp_num_siblings = 1;
832 return;
833 }
834
835 index_msb = get_count_order(smp_num_siblings);
836 c->phys_proc_id = phys_pkg_id(index_msb);
837
838 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
839
840 index_msb = get_count_order(smp_num_siblings);
841
842 core_bits = get_count_order(c->x86_max_cores);
843
844 c->cpu_core_id = phys_pkg_id(index_msb) &
845 ((1 << core_bits) - 1);
846 }
847 out:
848 if ((c->x86_max_cores * smp_num_siblings) > 1) {
849 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
850 c->phys_proc_id);
851 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
852 c->cpu_core_id);
853 }
854
855 #endif
856 }
857
858 /*
859 * find out the number of processor cores on the die
860 */
861 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
862 {
863 unsigned int eax, t;
864
865 if (c->cpuid_level < 4)
866 return 1;
867
868 cpuid_count(4, 0, &eax, &t, &t, &t);
869
870 if (eax & 0x1f)
871 return ((eax >> 26) + 1);
872 else
873 return 1;
874 }
875
876 static void __cpuinit srat_detect_node(void)
877 {
878 #ifdef CONFIG_NUMA
879 unsigned node;
880 int cpu = smp_processor_id();
881 int apicid = hard_smp_processor_id();
882
883 /* Don't do the funky fallback heuristics the AMD version employs
884 for now. */
885 node = apicid_to_node[apicid];
886 if (node == NUMA_NO_NODE || !node_online(node))
887 node = first_node(node_online_map);
888 numa_set_node(cpu, node);
889
890 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
891 #endif
892 }
893
894 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
895 {
896 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
897 (c->x86 == 0x6 && c->x86_model >= 0x0e))
898 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
899 }
900
901 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
902 {
903 /* Cache sizes */
904 unsigned n;
905
906 init_intel_cacheinfo(c);
907 if (c->cpuid_level > 9) {
908 unsigned eax = cpuid_eax(10);
909 /* Check for version and the number of counters */
910 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
911 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
912 }
913
914 if (cpu_has_ds) {
915 unsigned int l1, l2;
916 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
917 if (!(l1 & (1<<11)))
918 set_cpu_cap(c, X86_FEATURE_BTS);
919 if (!(l1 & (1<<12)))
920 set_cpu_cap(c, X86_FEATURE_PEBS);
921 }
922
923
924 if (cpu_has_bts)
925 ds_init_intel(c);
926
927 n = c->extended_cpuid_level;
928 if (n >= 0x80000008) {
929 unsigned eax = cpuid_eax(0x80000008);
930 c->x86_virt_bits = (eax >> 8) & 0xff;
931 c->x86_phys_bits = eax & 0xff;
932 /* CPUID workaround for Intel 0F34 CPU */
933 if (c->x86_vendor == X86_VENDOR_INTEL &&
934 c->x86 == 0xF && c->x86_model == 0x3 &&
935 c->x86_mask == 0x4)
936 c->x86_phys_bits = 36;
937 }
938
939 if (c->x86 == 15)
940 c->x86_cache_alignment = c->x86_clflush_size * 2;
941 if (c->x86 == 6)
942 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
943 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
944 c->x86_max_cores = intel_num_cpu_cores(c);
945
946 srat_detect_node();
947 }
948
949 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
950 {
951 if (c->x86 == 0x6 && c->x86_model >= 0xf)
952 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
953 }
954
955 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
956 {
957 /* Cache sizes */
958 unsigned n;
959
960 n = c->extended_cpuid_level;
961 if (n >= 0x80000008) {
962 unsigned eax = cpuid_eax(0x80000008);
963 c->x86_virt_bits = (eax >> 8) & 0xff;
964 c->x86_phys_bits = eax & 0xff;
965 }
966
967 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
968 c->x86_cache_alignment = c->x86_clflush_size * 2;
969 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
970 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
971 }
972 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
973 }
974
975 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
976 {
977 char *v = c->x86_vendor_id;
978
979 if (!strcmp(v, "AuthenticAMD"))
980 c->x86_vendor = X86_VENDOR_AMD;
981 else if (!strcmp(v, "GenuineIntel"))
982 c->x86_vendor = X86_VENDOR_INTEL;
983 else if (!strcmp(v, "CentaurHauls"))
984 c->x86_vendor = X86_VENDOR_CENTAUR;
985 else
986 c->x86_vendor = X86_VENDOR_UNKNOWN;
987 }
988
989 /* Do some early cpuid on the boot CPU to get some parameter that are
990 needed before check_bugs. Everything advanced is in identify_cpu
991 below. */
992 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
993 {
994 u32 tfms, xlvl;
995
996 c->loops_per_jiffy = loops_per_jiffy;
997 c->x86_cache_size = -1;
998 c->x86_vendor = X86_VENDOR_UNKNOWN;
999 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1000 c->x86_vendor_id[0] = '\0'; /* Unset */
1001 c->x86_model_id[0] = '\0'; /* Unset */
1002 c->x86_clflush_size = 64;
1003 c->x86_cache_alignment = c->x86_clflush_size;
1004 c->x86_max_cores = 1;
1005 c->x86_coreid_bits = 0;
1006 c->extended_cpuid_level = 0;
1007 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1008
1009 /* Get vendor name */
1010 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1011 (unsigned int *)&c->x86_vendor_id[0],
1012 (unsigned int *)&c->x86_vendor_id[8],
1013 (unsigned int *)&c->x86_vendor_id[4]);
1014
1015 get_cpu_vendor(c);
1016
1017 /* Initialize the standard set of capabilities */
1018 /* Note that the vendor-specific code below might override */
1019
1020 /* Intel-defined flags: level 0x00000001 */
1021 if (c->cpuid_level >= 0x00000001) {
1022 __u32 misc;
1023 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1024 &c->x86_capability[0]);
1025 c->x86 = (tfms >> 8) & 0xf;
1026 c->x86_model = (tfms >> 4) & 0xf;
1027 c->x86_mask = tfms & 0xf;
1028 if (c->x86 == 0xf)
1029 c->x86 += (tfms >> 20) & 0xff;
1030 if (c->x86 >= 0x6)
1031 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1032 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1033 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1034 } else {
1035 /* Have CPUID level 0 only - unheard of */
1036 c->x86 = 4;
1037 }
1038
1039 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1040 #ifdef CONFIG_SMP
1041 c->phys_proc_id = c->initial_apicid;
1042 #endif
1043 /* AMD-defined flags: level 0x80000001 */
1044 xlvl = cpuid_eax(0x80000000);
1045 c->extended_cpuid_level = xlvl;
1046 if ((xlvl & 0xffff0000) == 0x80000000) {
1047 if (xlvl >= 0x80000001) {
1048 c->x86_capability[1] = cpuid_edx(0x80000001);
1049 c->x86_capability[6] = cpuid_ecx(0x80000001);
1050 }
1051 if (xlvl >= 0x80000004)
1052 get_model_name(c); /* Default name */
1053 }
1054
1055 /* Transmeta-defined flags: level 0x80860001 */
1056 xlvl = cpuid_eax(0x80860000);
1057 if ((xlvl & 0xffff0000) == 0x80860000) {
1058 /* Don't set x86_cpuid_level here for now to not confuse. */
1059 if (xlvl >= 0x80860001)
1060 c->x86_capability[2] = cpuid_edx(0x80860001);
1061 }
1062
1063 c->extended_cpuid_level = cpuid_eax(0x80000000);
1064 if (c->extended_cpuid_level >= 0x80000007)
1065 c->x86_power = cpuid_edx(0x80000007);
1066
1067 switch (c->x86_vendor) {
1068 case X86_VENDOR_AMD:
1069 early_init_amd(c);
1070 break;
1071 case X86_VENDOR_INTEL:
1072 early_init_intel(c);
1073 break;
1074 case X86_VENDOR_CENTAUR:
1075 early_init_centaur(c);
1076 break;
1077 }
1078
1079 validate_pat_support(c);
1080 }
1081
1082 /*
1083 * This does the hard work of actually picking apart the CPU stuff...
1084 */
1085 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1086 {
1087 int i;
1088
1089 early_identify_cpu(c);
1090
1091 init_scattered_cpuid_features(c);
1092
1093 c->apicid = phys_pkg_id(0);
1094
1095 /*
1096 * Vendor-specific initialization. In this section we
1097 * canonicalize the feature flags, meaning if there are
1098 * features a certain CPU supports which CPUID doesn't
1099 * tell us, CPUID claiming incorrect flags, or other bugs,
1100 * we handle them here.
1101 *
1102 * At the end of this section, c->x86_capability better
1103 * indicate the features this CPU genuinely supports!
1104 */
1105 switch (c->x86_vendor) {
1106 case X86_VENDOR_AMD:
1107 init_amd(c);
1108 break;
1109
1110 case X86_VENDOR_INTEL:
1111 init_intel(c);
1112 break;
1113
1114 case X86_VENDOR_CENTAUR:
1115 init_centaur(c);
1116 break;
1117
1118 case X86_VENDOR_UNKNOWN:
1119 default:
1120 display_cacheinfo(c);
1121 break;
1122 }
1123
1124 detect_ht(c);
1125
1126 /*
1127 * On SMP, boot_cpu_data holds the common feature set between
1128 * all CPUs; so make sure that we indicate which features are
1129 * common between the CPUs. The first time this routine gets
1130 * executed, c == &boot_cpu_data.
1131 */
1132 if (c != &boot_cpu_data) {
1133 /* AND the already accumulated flags with these */
1134 for (i = 0; i < NCAPINTS; i++)
1135 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1136 }
1137
1138 /* Clear all flags overriden by options */
1139 for (i = 0; i < NCAPINTS; i++)
1140 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1141
1142 #ifdef CONFIG_X86_MCE
1143 mcheck_init(c);
1144 #endif
1145 select_idle_routine(c);
1146
1147 #ifdef CONFIG_NUMA
1148 numa_add_cpu(smp_processor_id());
1149 #endif
1150
1151 }
1152
1153 void __cpuinit identify_boot_cpu(void)
1154 {
1155 identify_cpu(&boot_cpu_data);
1156 }
1157
1158 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1159 {
1160 BUG_ON(c == &boot_cpu_data);
1161 identify_cpu(c);
1162 mtrr_ap_init();
1163 }
1164
1165 static __init int setup_noclflush(char *arg)
1166 {
1167 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1168 return 1;
1169 }
1170 __setup("noclflush", setup_noclflush);
1171
1172 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1173 {
1174 if (c->x86_model_id[0])
1175 printk(KERN_CONT "%s", c->x86_model_id);
1176
1177 if (c->x86_mask || c->cpuid_level >= 0)
1178 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1179 else
1180 printk(KERN_CONT "\n");
1181 }
1182
1183 static __init int setup_disablecpuid(char *arg)
1184 {
1185 int bit;
1186 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1187 setup_clear_cpu_cap(bit);
1188 else
1189 return 0;
1190 return 1;
1191 }
1192 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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