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x86, numa, 32-bit: print out debug info on all kvas
[deliverable/linux.git] / arch / x86 / kernel / setup_64.c
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <asm/pci-direct.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/iscsi_ibft.h>
38 #include <linux/mmzone.h>
39 #include <linux/kexec.h>
40 #include <linux/cpufreq.h>
41 #include <linux/dmi.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/ctype.h>
44 #include <linux/sort.h>
45 #include <linux/uaccess.h>
46 #include <linux/init_ohci1394_dma.h>
47 #include <linux/kvm_para.h>
48
49 #include <asm/mtrr.h>
50 #include <asm/uaccess.h>
51 #include <asm/system.h>
52 #include <asm/vsyscall.h>
53 #include <asm/io.h>
54 #include <asm/smp.h>
55 #include <asm/msr.h>
56 #include <asm/desc.h>
57 #include <video/edid.h>
58 #include <asm/e820.h>
59 #include <asm/dma.h>
60 #include <asm/gart.h>
61 #include <asm/mpspec.h>
62 #include <asm/mmu_context.h>
63 #include <asm/proto.h>
64 #include <asm/setup.h>
65 #include <asm/numa.h>
66 #include <asm/sections.h>
67 #include <asm/dmi.h>
68 #include <asm/cacheflush.h>
69 #include <asm/mce.h>
70 #include <asm/ds.h>
71 #include <asm/topology.h>
72 #include <asm/trampoline.h>
73 #include <asm/pat.h>
74
75 #include <mach_apic.h>
76 #ifdef CONFIG_PARAVIRT
77 #include <asm/paravirt.h>
78 #else
79 #define ARCH_SETUP
80 #endif
81
82 /*
83 * Machine setup..
84 */
85
86 struct cpuinfo_x86 boot_cpu_data __read_mostly;
87 EXPORT_SYMBOL(boot_cpu_data);
88
89 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
90
91 unsigned long mmu_cr4_features;
92
93 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
94 int bootloader_type;
95
96 unsigned long saved_video_mode;
97
98 int force_mwait __cpuinitdata;
99
100 /*
101 * Early DMI memory
102 */
103 int dmi_alloc_index;
104 char dmi_alloc_data[DMI_MAX_DATA];
105
106 /*
107 * Setup options
108 */
109 struct screen_info screen_info;
110 EXPORT_SYMBOL(screen_info);
111 struct sys_desc_table_struct {
112 unsigned short length;
113 unsigned char table[0];
114 };
115
116 struct edid_info edid_info;
117 EXPORT_SYMBOL_GPL(edid_info);
118
119 extern int root_mountflags;
120
121 char __initdata command_line[COMMAND_LINE_SIZE];
122
123 static struct resource standard_io_resources[] = {
124 { .name = "dma1", .start = 0x00, .end = 0x1f,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "pic1", .start = 0x20, .end = 0x21,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "timer0", .start = 0x40, .end = 0x43,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "timer1", .start = 0x50, .end = 0x53,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "keyboard", .start = 0x60, .end = 0x60,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "keyboard", .start = 0x64, .end = 0x64,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
136 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
137 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
138 { .name = "pic2", .start = 0xa0, .end = 0xa1,
139 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
140 { .name = "dma2", .start = 0xc0, .end = 0xdf,
141 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
142 { .name = "fpu", .start = 0xf0, .end = 0xff,
143 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
144 };
145
146 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
147
148 static struct resource data_resource = {
149 .name = "Kernel data",
150 .start = 0,
151 .end = 0,
152 .flags = IORESOURCE_RAM,
153 };
154 static struct resource code_resource = {
155 .name = "Kernel code",
156 .start = 0,
157 .end = 0,
158 .flags = IORESOURCE_RAM,
159 };
160 static struct resource bss_resource = {
161 .name = "Kernel bss",
162 .start = 0,
163 .end = 0,
164 .flags = IORESOURCE_RAM,
165 };
166
167 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
168
169 #ifdef CONFIG_PROC_VMCORE
170 /* elfcorehdr= specifies the location of elf core header
171 * stored by the crashed kernel. This option will be passed
172 * by kexec loader to the capture kernel.
173 */
174 static int __init setup_elfcorehdr(char *arg)
175 {
176 char *end;
177 if (!arg)
178 return -EINVAL;
179 elfcorehdr_addr = memparse(arg, &end);
180 return end > arg ? 0 : -EINVAL;
181 }
182 early_param("elfcorehdr", setup_elfcorehdr);
183 #endif
184
185 #ifndef CONFIG_NUMA
186 static void __init
187 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
188 {
189 unsigned long bootmap_size, bootmap;
190
191 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
192 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
193 PAGE_SIZE);
194 if (bootmap == -1L)
195 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
196 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
197 e820_register_active_regions(0, start_pfn, end_pfn);
198 free_bootmem_with_active_regions(0, end_pfn);
199 early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
200 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
201 }
202 #endif
203
204 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
205 struct edd edd;
206 #ifdef CONFIG_EDD_MODULE
207 EXPORT_SYMBOL(edd);
208 #endif
209 /**
210 * copy_edd() - Copy the BIOS EDD information
211 * from boot_params into a safe place.
212 *
213 */
214 static inline void copy_edd(void)
215 {
216 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
217 sizeof(edd.mbr_signature));
218 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
219 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
220 edd.edd_info_nr = boot_params.eddbuf_entries;
221 }
222 #else
223 static inline void copy_edd(void)
224 {
225 }
226 #endif
227
228 #ifdef CONFIG_KEXEC
229 static void __init reserve_crashkernel(void)
230 {
231 unsigned long long total_mem;
232 unsigned long long crash_size, crash_base;
233 int ret;
234
235 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
236
237 ret = parse_crashkernel(boot_command_line, total_mem,
238 &crash_size, &crash_base);
239 if (ret == 0 && crash_size) {
240 if (crash_base <= 0) {
241 printk(KERN_INFO "crashkernel reservation failed - "
242 "you have to specify a base address\n");
243 return;
244 }
245
246 if (reserve_bootmem(crash_base, crash_size,
247 BOOTMEM_EXCLUSIVE) < 0) {
248 printk(KERN_INFO "crashkernel reservation failed - "
249 "memory is in use\n");
250 return;
251 }
252
253 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
254 "for crashkernel (System RAM: %ldMB)\n",
255 (unsigned long)(crash_size >> 20),
256 (unsigned long)(crash_base >> 20),
257 (unsigned long)(total_mem >> 20));
258 crashk_res.start = crash_base;
259 crashk_res.end = crash_base + crash_size - 1;
260 insert_resource(&iomem_resource, &crashk_res);
261 }
262 }
263 #else
264 static inline void __init reserve_crashkernel(void)
265 {}
266 #endif
267
268 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
269 void __attribute__((weak)) __init memory_setup(void)
270 {
271 machine_specific_memory_setup();
272 }
273
274 static void __init parse_setup_data(void)
275 {
276 struct setup_data *data;
277 unsigned long pa_data;
278
279 if (boot_params.hdr.version < 0x0209)
280 return;
281 pa_data = boot_params.hdr.setup_data;
282 while (pa_data) {
283 data = early_ioremap(pa_data, PAGE_SIZE);
284 switch (data->type) {
285 default:
286 break;
287 }
288 #ifndef CONFIG_DEBUG_BOOT_PARAMS
289 free_early(pa_data, pa_data+sizeof(*data)+data->len);
290 #endif
291 pa_data = data->next;
292 early_iounmap(data, PAGE_SIZE);
293 }
294 }
295
296 #ifdef CONFIG_PCI_MMCONFIG
297 extern void __cpuinit fam10h_check_enable_mmcfg(void);
298 extern void __init check_enable_amd_mmconf_dmi(void);
299 #else
300 void __cpuinit fam10h_check_enable_mmcfg(void)
301 {
302 }
303 void __init check_enable_amd_mmconf_dmi(void)
304 {
305 }
306 #endif
307
308 /*
309 * setup_arch - architecture-specific boot-time initializations
310 *
311 * Note: On x86_64, fixmaps are ready for use even before this is called.
312 */
313 void __init setup_arch(char **cmdline_p)
314 {
315 unsigned i;
316
317 printk(KERN_INFO "Command line: %s\n", boot_command_line);
318
319 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
320 screen_info = boot_params.screen_info;
321 edid_info = boot_params.edid_info;
322 saved_video_mode = boot_params.hdr.vid_mode;
323 bootloader_type = boot_params.hdr.type_of_loader;
324
325 #ifdef CONFIG_BLK_DEV_RAM
326 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
327 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
328 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
329 #endif
330 #ifdef CONFIG_EFI
331 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
332 "EL64", 4))
333 efi_enabled = 1;
334 #endif
335
336 ARCH_SETUP
337
338 memory_setup();
339 copy_edd();
340
341 if (!boot_params.hdr.root_flags)
342 root_mountflags &= ~MS_RDONLY;
343 init_mm.start_code = (unsigned long) &_text;
344 init_mm.end_code = (unsigned long) &_etext;
345 init_mm.end_data = (unsigned long) &_edata;
346 init_mm.brk = (unsigned long) &_end;
347
348 code_resource.start = virt_to_phys(&_text);
349 code_resource.end = virt_to_phys(&_etext)-1;
350 data_resource.start = virt_to_phys(&_etext);
351 data_resource.end = virt_to_phys(&_edata)-1;
352 bss_resource.start = virt_to_phys(&__bss_start);
353 bss_resource.end = virt_to_phys(&__bss_stop)-1;
354
355 early_identify_cpu(&boot_cpu_data);
356
357 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
358 *cmdline_p = command_line;
359
360 parse_setup_data();
361
362 parse_early_param();
363
364 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
365 if (init_ohci1394_dma_early)
366 init_ohci1394_dma_on_all_controllers();
367 #endif
368
369 finish_e820_parsing();
370
371 /* after parse_early_param, so could debug it */
372 insert_resource(&iomem_resource, &code_resource);
373 insert_resource(&iomem_resource, &data_resource);
374 insert_resource(&iomem_resource, &bss_resource);
375
376 early_gart_iommu_check();
377
378 e820_register_active_regions(0, 0, -1UL);
379 /*
380 * partially used pages are not usable - thus
381 * we are rounding upwards:
382 */
383 end_pfn = e820_end_of_ram();
384 /* update e820 for memory not covered by WB MTRRs */
385 mtrr_bp_init();
386 if (mtrr_trim_uncached_memory(end_pfn)) {
387 e820_register_active_regions(0, 0, -1UL);
388 end_pfn = e820_end_of_ram();
389 }
390
391 num_physpages = end_pfn;
392
393 check_efer();
394
395 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
396 if (efi_enabled)
397 efi_init();
398
399 vsmp_init();
400
401 dmi_scan_machine();
402
403 io_delay_init();
404
405 #ifdef CONFIG_KVM_CLOCK
406 kvmclock_init();
407 #endif
408
409 #ifdef CONFIG_SMP
410 /* setup to use the early static init tables during kernel startup */
411 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
412 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
413 #ifdef CONFIG_NUMA
414 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
415 #endif
416 #endif
417
418 #ifdef CONFIG_ACPI
419 /*
420 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
421 * Call this early for SRAT node setup.
422 */
423 acpi_boot_table_init();
424 #endif
425
426 /* How many end-of-memory variables you have, grandma! */
427 max_low_pfn = end_pfn;
428 max_pfn = end_pfn;
429 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
430
431 /* Remove active ranges so rediscovery with NUMA-awareness happens */
432 remove_all_active_ranges();
433
434 #ifdef CONFIG_ACPI_NUMA
435 /*
436 * Parse SRAT to discover nodes.
437 */
438 acpi_numa_init();
439 #endif
440
441 #ifdef CONFIG_NUMA
442 numa_initmem_init(0, end_pfn);
443 #else
444 contig_initmem_init(0, end_pfn);
445 #endif
446
447 dma32_reserve_bootmem();
448
449 #ifdef CONFIG_ACPI_SLEEP
450 /*
451 * Reserve low memory region for sleep support.
452 */
453 acpi_reserve_bootmem();
454 #endif
455
456 if (efi_enabled)
457 efi_reserve_bootmem();
458
459 #ifdef CONFIG_X86_MPPARSE
460 /*
461 * Find and reserve possible boot-time SMP configuration:
462 */
463 find_smp_config();
464 #endif
465 #ifdef CONFIG_BLK_DEV_INITRD
466 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
467 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
468 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
469 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
470 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
471
472 if (ramdisk_end <= end_of_mem) {
473 /*
474 * don't need to reserve again, already reserved early
475 * in x86_64_start_kernel, and early_res_to_bootmem
476 * convert that to reserved in bootmem
477 */
478 initrd_start = ramdisk_image + PAGE_OFFSET;
479 initrd_end = initrd_start+ramdisk_size;
480 } else {
481 free_bootmem(ramdisk_image, ramdisk_size);
482 printk(KERN_ERR "initrd extends beyond end of memory "
483 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
484 ramdisk_end, end_of_mem);
485 initrd_start = 0;
486 }
487 }
488 #endif
489 reserve_crashkernel();
490
491 reserve_ibft_region();
492
493 paging_init();
494 map_vsyscall();
495
496 early_quirks();
497
498 #ifdef CONFIG_ACPI
499 /*
500 * Read APIC and some other early information from ACPI tables.
501 */
502 acpi_boot_init();
503 #endif
504
505 init_cpu_to_node();
506
507 #ifdef CONFIG_X86_MPPARSE
508 /*
509 * get boot-time SMP configuration:
510 */
511 if (smp_found_config)
512 get_smp_config();
513 #endif
514 init_apic_mappings();
515 ioapic_init_mappings();
516
517 kvm_guest_init();
518
519 /*
520 * We trust e820 completely. No explicit ROM probing in memory.
521 */
522 e820_reserve_resources();
523 e820_mark_nosave_regions(end_pfn);
524
525 /* request I/O space for devices used on all i[345]86 PCs */
526 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
527 request_resource(&ioport_resource, &standard_io_resources[i]);
528
529 e820_setup_gap();
530
531 #ifdef CONFIG_VT
532 #if defined(CONFIG_VGA_CONSOLE)
533 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
534 conswitchp = &vga_con;
535 #elif defined(CONFIG_DUMMY_CONSOLE)
536 conswitchp = &dummy_con;
537 #endif
538 #endif
539
540 /* do this before identify_cpu for boot cpu */
541 check_enable_amd_mmconf_dmi();
542 }
543
544 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
545 {
546 unsigned int *v;
547
548 if (c->extended_cpuid_level < 0x80000004)
549 return 0;
550
551 v = (unsigned int *) c->x86_model_id;
552 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
553 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
554 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
555 c->x86_model_id[48] = 0;
556 return 1;
557 }
558
559
560 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
561 {
562 unsigned int n, dummy, eax, ebx, ecx, edx;
563
564 n = c->extended_cpuid_level;
565
566 if (n >= 0x80000005) {
567 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
568 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
569 "D cache %dK (%d bytes/line)\n",
570 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
571 c->x86_cache_size = (ecx>>24) + (edx>>24);
572 /* On K8 L1 TLB is inclusive, so don't count it */
573 c->x86_tlbsize = 0;
574 }
575
576 if (n >= 0x80000006) {
577 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
578 ecx = cpuid_ecx(0x80000006);
579 c->x86_cache_size = ecx >> 16;
580 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
581
582 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
583 c->x86_cache_size, ecx & 0xFF);
584 }
585 if (n >= 0x80000008) {
586 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
587 c->x86_virt_bits = (eax >> 8) & 0xff;
588 c->x86_phys_bits = eax & 0xff;
589 }
590 }
591
592 #ifdef CONFIG_NUMA
593 static int __cpuinit nearby_node(int apicid)
594 {
595 int i, node;
596
597 for (i = apicid - 1; i >= 0; i--) {
598 node = apicid_to_node[i];
599 if (node != NUMA_NO_NODE && node_online(node))
600 return node;
601 }
602 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
603 node = apicid_to_node[i];
604 if (node != NUMA_NO_NODE && node_online(node))
605 return node;
606 }
607 return first_node(node_online_map); /* Shouldn't happen */
608 }
609 #endif
610
611 /*
612 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
613 * Assumes number of cores is a power of two.
614 */
615 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
616 {
617 #ifdef CONFIG_SMP
618 unsigned bits;
619 #ifdef CONFIG_NUMA
620 int cpu = smp_processor_id();
621 int node = 0;
622 unsigned apicid = hard_smp_processor_id();
623 #endif
624 bits = c->x86_coreid_bits;
625
626 /* Low order bits define the core id (index of core in socket) */
627 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
628 /* Convert the initial APIC ID into the socket ID */
629 c->phys_proc_id = c->initial_apicid >> bits;
630
631 #ifdef CONFIG_NUMA
632 node = c->phys_proc_id;
633 if (apicid_to_node[apicid] != NUMA_NO_NODE)
634 node = apicid_to_node[apicid];
635 if (!node_online(node)) {
636 /* Two possibilities here:
637 - The CPU is missing memory and no node was created.
638 In that case try picking one from a nearby CPU
639 - The APIC IDs differ from the HyperTransport node IDs
640 which the K8 northbridge parsing fills in.
641 Assume they are all increased by a constant offset,
642 but in the same order as the HT nodeids.
643 If that doesn't result in a usable node fall back to the
644 path for the previous case. */
645
646 int ht_nodeid = c->initial_apicid;
647
648 if (ht_nodeid >= 0 &&
649 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
650 node = apicid_to_node[ht_nodeid];
651 /* Pick a nearby node */
652 if (!node_online(node))
653 node = nearby_node(apicid);
654 }
655 numa_set_node(cpu, node);
656
657 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
658 #endif
659 #endif
660 }
661
662 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
663 {
664 #ifdef CONFIG_SMP
665 unsigned bits, ecx;
666
667 /* Multi core CPU? */
668 if (c->extended_cpuid_level < 0x80000008)
669 return;
670
671 ecx = cpuid_ecx(0x80000008);
672
673 c->x86_max_cores = (ecx & 0xff) + 1;
674
675 /* CPU telling us the core id bits shift? */
676 bits = (ecx >> 12) & 0xF;
677
678 /* Otherwise recompute */
679 if (bits == 0) {
680 while ((1 << bits) < c->x86_max_cores)
681 bits++;
682 }
683
684 c->x86_coreid_bits = bits;
685
686 #endif
687 }
688
689 #define ENABLE_C1E_MASK 0x18000000
690 #define CPUID_PROCESSOR_SIGNATURE 1
691 #define CPUID_XFAM 0x0ff00000
692 #define CPUID_XFAM_K8 0x00000000
693 #define CPUID_XFAM_10H 0x00100000
694 #define CPUID_XFAM_11H 0x00200000
695 #define CPUID_XMOD 0x000f0000
696 #define CPUID_XMOD_REV_F 0x00040000
697
698 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
699 static __cpuinit int amd_apic_timer_broken(void)
700 {
701 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
702
703 switch (eax & CPUID_XFAM) {
704 case CPUID_XFAM_K8:
705 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
706 break;
707 case CPUID_XFAM_10H:
708 case CPUID_XFAM_11H:
709 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
710 if (lo & ENABLE_C1E_MASK)
711 return 1;
712 break;
713 default:
714 /* err on the side of caution */
715 return 1;
716 }
717 return 0;
718 }
719
720 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
721 {
722 early_init_amd_mc(c);
723
724 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
725 if (c->x86_power & (1<<8))
726 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
727 }
728
729 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
730 {
731 unsigned level;
732
733 #ifdef CONFIG_SMP
734 unsigned long value;
735
736 /*
737 * Disable TLB flush filter by setting HWCR.FFDIS on K8
738 * bit 6 of msr C001_0015
739 *
740 * Errata 63 for SH-B3 steppings
741 * Errata 122 for all steppings (F+ have it disabled by default)
742 */
743 if (c->x86 == 15) {
744 rdmsrl(MSR_K8_HWCR, value);
745 value |= 1 << 6;
746 wrmsrl(MSR_K8_HWCR, value);
747 }
748 #endif
749
750 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
751 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
752 clear_cpu_cap(c, 0*32+31);
753
754 /* On C+ stepping K8 rep microcode works well for copy/memset */
755 level = cpuid_eax(1);
756 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
757 level >= 0x0f58))
758 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
759 if (c->x86 == 0x10 || c->x86 == 0x11)
760 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
761
762 /* Enable workaround for FXSAVE leak */
763 if (c->x86 >= 6)
764 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
765
766 level = get_model_name(c);
767 if (!level) {
768 switch (c->x86) {
769 case 15:
770 /* Should distinguish Models here, but this is only
771 a fallback anyways. */
772 strcpy(c->x86_model_id, "Hammer");
773 break;
774 }
775 }
776 display_cacheinfo(c);
777
778 /* Multi core CPU? */
779 if (c->extended_cpuid_level >= 0x80000008)
780 amd_detect_cmp(c);
781
782 if (c->extended_cpuid_level >= 0x80000006 &&
783 (cpuid_edx(0x80000006) & 0xf000))
784 num_cache_leaves = 4;
785 else
786 num_cache_leaves = 3;
787
788 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
789 set_cpu_cap(c, X86_FEATURE_K8);
790
791 /* MFENCE stops RDTSC speculation */
792 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
793
794 if (c->x86 == 0x10)
795 fam10h_check_enable_mmcfg();
796
797 if (amd_apic_timer_broken())
798 disable_apic_timer = 1;
799
800 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
801 unsigned long long tseg;
802
803 /*
804 * Split up direct mapping around the TSEG SMM area.
805 * Don't do it for gbpages because there seems very little
806 * benefit in doing so.
807 */
808 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
809 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
810 set_memory_4k((unsigned long)__va(tseg), 1);
811 }
812 }
813
814 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
815 {
816 #ifdef CONFIG_SMP
817 u32 eax, ebx, ecx, edx;
818 int index_msb, core_bits;
819
820 cpuid(1, &eax, &ebx, &ecx, &edx);
821
822
823 if (!cpu_has(c, X86_FEATURE_HT))
824 return;
825 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
826 goto out;
827
828 smp_num_siblings = (ebx & 0xff0000) >> 16;
829
830 if (smp_num_siblings == 1) {
831 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
832 } else if (smp_num_siblings > 1) {
833
834 if (smp_num_siblings > NR_CPUS) {
835 printk(KERN_WARNING "CPU: Unsupported number of "
836 "siblings %d", smp_num_siblings);
837 smp_num_siblings = 1;
838 return;
839 }
840
841 index_msb = get_count_order(smp_num_siblings);
842 c->phys_proc_id = phys_pkg_id(index_msb);
843
844 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
845
846 index_msb = get_count_order(smp_num_siblings);
847
848 core_bits = get_count_order(c->x86_max_cores);
849
850 c->cpu_core_id = phys_pkg_id(index_msb) &
851 ((1 << core_bits) - 1);
852 }
853 out:
854 if ((c->x86_max_cores * smp_num_siblings) > 1) {
855 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
856 c->phys_proc_id);
857 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
858 c->cpu_core_id);
859 }
860
861 #endif
862 }
863
864 /*
865 * find out the number of processor cores on the die
866 */
867 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
868 {
869 unsigned int eax, t;
870
871 if (c->cpuid_level < 4)
872 return 1;
873
874 cpuid_count(4, 0, &eax, &t, &t, &t);
875
876 if (eax & 0x1f)
877 return ((eax >> 26) + 1);
878 else
879 return 1;
880 }
881
882 static void __cpuinit srat_detect_node(void)
883 {
884 #ifdef CONFIG_NUMA
885 unsigned node;
886 int cpu = smp_processor_id();
887 int apicid = hard_smp_processor_id();
888
889 /* Don't do the funky fallback heuristics the AMD version employs
890 for now. */
891 node = apicid_to_node[apicid];
892 if (node == NUMA_NO_NODE || !node_online(node))
893 node = first_node(node_online_map);
894 numa_set_node(cpu, node);
895
896 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
897 #endif
898 }
899
900 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
901 {
902 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
903 (c->x86 == 0x6 && c->x86_model >= 0x0e))
904 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
905 }
906
907 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
908 {
909 /* Cache sizes */
910 unsigned n;
911
912 init_intel_cacheinfo(c);
913 if (c->cpuid_level > 9) {
914 unsigned eax = cpuid_eax(10);
915 /* Check for version and the number of counters */
916 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
917 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
918 }
919
920 if (cpu_has_ds) {
921 unsigned int l1, l2;
922 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
923 if (!(l1 & (1<<11)))
924 set_cpu_cap(c, X86_FEATURE_BTS);
925 if (!(l1 & (1<<12)))
926 set_cpu_cap(c, X86_FEATURE_PEBS);
927 }
928
929
930 if (cpu_has_bts)
931 ds_init_intel(c);
932
933 n = c->extended_cpuid_level;
934 if (n >= 0x80000008) {
935 unsigned eax = cpuid_eax(0x80000008);
936 c->x86_virt_bits = (eax >> 8) & 0xff;
937 c->x86_phys_bits = eax & 0xff;
938 /* CPUID workaround for Intel 0F34 CPU */
939 if (c->x86_vendor == X86_VENDOR_INTEL &&
940 c->x86 == 0xF && c->x86_model == 0x3 &&
941 c->x86_mask == 0x4)
942 c->x86_phys_bits = 36;
943 }
944
945 if (c->x86 == 15)
946 c->x86_cache_alignment = c->x86_clflush_size * 2;
947 if (c->x86 == 6)
948 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
949 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
950 c->x86_max_cores = intel_num_cpu_cores(c);
951
952 srat_detect_node();
953 }
954
955 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
956 {
957 if (c->x86 == 0x6 && c->x86_model >= 0xf)
958 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
959 }
960
961 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
962 {
963 /* Cache sizes */
964 unsigned n;
965
966 n = c->extended_cpuid_level;
967 if (n >= 0x80000008) {
968 unsigned eax = cpuid_eax(0x80000008);
969 c->x86_virt_bits = (eax >> 8) & 0xff;
970 c->x86_phys_bits = eax & 0xff;
971 }
972
973 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
974 c->x86_cache_alignment = c->x86_clflush_size * 2;
975 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
976 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
977 }
978 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
979 }
980
981 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
982 {
983 char *v = c->x86_vendor_id;
984
985 if (!strcmp(v, "AuthenticAMD"))
986 c->x86_vendor = X86_VENDOR_AMD;
987 else if (!strcmp(v, "GenuineIntel"))
988 c->x86_vendor = X86_VENDOR_INTEL;
989 else if (!strcmp(v, "CentaurHauls"))
990 c->x86_vendor = X86_VENDOR_CENTAUR;
991 else
992 c->x86_vendor = X86_VENDOR_UNKNOWN;
993 }
994
995 /* Do some early cpuid on the boot CPU to get some parameter that are
996 needed before check_bugs. Everything advanced is in identify_cpu
997 below. */
998 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
999 {
1000 u32 tfms, xlvl;
1001
1002 c->loops_per_jiffy = loops_per_jiffy;
1003 c->x86_cache_size = -1;
1004 c->x86_vendor = X86_VENDOR_UNKNOWN;
1005 c->x86_model = c->x86_mask = 0; /* So far unknown... */
1006 c->x86_vendor_id[0] = '\0'; /* Unset */
1007 c->x86_model_id[0] = '\0'; /* Unset */
1008 c->x86_clflush_size = 64;
1009 c->x86_cache_alignment = c->x86_clflush_size;
1010 c->x86_max_cores = 1;
1011 c->x86_coreid_bits = 0;
1012 c->extended_cpuid_level = 0;
1013 memset(&c->x86_capability, 0, sizeof c->x86_capability);
1014
1015 /* Get vendor name */
1016 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
1017 (unsigned int *)&c->x86_vendor_id[0],
1018 (unsigned int *)&c->x86_vendor_id[8],
1019 (unsigned int *)&c->x86_vendor_id[4]);
1020
1021 get_cpu_vendor(c);
1022
1023 /* Initialize the standard set of capabilities */
1024 /* Note that the vendor-specific code below might override */
1025
1026 /* Intel-defined flags: level 0x00000001 */
1027 if (c->cpuid_level >= 0x00000001) {
1028 __u32 misc;
1029 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1030 &c->x86_capability[0]);
1031 c->x86 = (tfms >> 8) & 0xf;
1032 c->x86_model = (tfms >> 4) & 0xf;
1033 c->x86_mask = tfms & 0xf;
1034 if (c->x86 == 0xf)
1035 c->x86 += (tfms >> 20) & 0xff;
1036 if (c->x86 >= 0x6)
1037 c->x86_model += ((tfms >> 16) & 0xF) << 4;
1038 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1039 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1040 } else {
1041 /* Have CPUID level 0 only - unheard of */
1042 c->x86 = 4;
1043 }
1044
1045 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1046 #ifdef CONFIG_SMP
1047 c->phys_proc_id = c->initial_apicid;
1048 #endif
1049 /* AMD-defined flags: level 0x80000001 */
1050 xlvl = cpuid_eax(0x80000000);
1051 c->extended_cpuid_level = xlvl;
1052 if ((xlvl & 0xffff0000) == 0x80000000) {
1053 if (xlvl >= 0x80000001) {
1054 c->x86_capability[1] = cpuid_edx(0x80000001);
1055 c->x86_capability[6] = cpuid_ecx(0x80000001);
1056 }
1057 if (xlvl >= 0x80000004)
1058 get_model_name(c); /* Default name */
1059 }
1060
1061 /* Transmeta-defined flags: level 0x80860001 */
1062 xlvl = cpuid_eax(0x80860000);
1063 if ((xlvl & 0xffff0000) == 0x80860000) {
1064 /* Don't set x86_cpuid_level here for now to not confuse. */
1065 if (xlvl >= 0x80860001)
1066 c->x86_capability[2] = cpuid_edx(0x80860001);
1067 }
1068
1069 c->extended_cpuid_level = cpuid_eax(0x80000000);
1070 if (c->extended_cpuid_level >= 0x80000007)
1071 c->x86_power = cpuid_edx(0x80000007);
1072
1073 switch (c->x86_vendor) {
1074 case X86_VENDOR_AMD:
1075 early_init_amd(c);
1076 break;
1077 case X86_VENDOR_INTEL:
1078 early_init_intel(c);
1079 break;
1080 case X86_VENDOR_CENTAUR:
1081 early_init_centaur(c);
1082 break;
1083 }
1084
1085 validate_pat_support(c);
1086 }
1087
1088 /*
1089 * This does the hard work of actually picking apart the CPU stuff...
1090 */
1091 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1092 {
1093 int i;
1094
1095 early_identify_cpu(c);
1096
1097 init_scattered_cpuid_features(c);
1098
1099 c->apicid = phys_pkg_id(0);
1100
1101 /*
1102 * Vendor-specific initialization. In this section we
1103 * canonicalize the feature flags, meaning if there are
1104 * features a certain CPU supports which CPUID doesn't
1105 * tell us, CPUID claiming incorrect flags, or other bugs,
1106 * we handle them here.
1107 *
1108 * At the end of this section, c->x86_capability better
1109 * indicate the features this CPU genuinely supports!
1110 */
1111 switch (c->x86_vendor) {
1112 case X86_VENDOR_AMD:
1113 init_amd(c);
1114 break;
1115
1116 case X86_VENDOR_INTEL:
1117 init_intel(c);
1118 break;
1119
1120 case X86_VENDOR_CENTAUR:
1121 init_centaur(c);
1122 break;
1123
1124 case X86_VENDOR_UNKNOWN:
1125 default:
1126 display_cacheinfo(c);
1127 break;
1128 }
1129
1130 detect_ht(c);
1131
1132 /*
1133 * On SMP, boot_cpu_data holds the common feature set between
1134 * all CPUs; so make sure that we indicate which features are
1135 * common between the CPUs. The first time this routine gets
1136 * executed, c == &boot_cpu_data.
1137 */
1138 if (c != &boot_cpu_data) {
1139 /* AND the already accumulated flags with these */
1140 for (i = 0; i < NCAPINTS; i++)
1141 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1142 }
1143
1144 /* Clear all flags overriden by options */
1145 for (i = 0; i < NCAPINTS; i++)
1146 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1147
1148 #ifdef CONFIG_X86_MCE
1149 mcheck_init(c);
1150 #endif
1151 select_idle_routine(c);
1152
1153 #ifdef CONFIG_NUMA
1154 numa_add_cpu(smp_processor_id());
1155 #endif
1156
1157 }
1158
1159 void __cpuinit identify_boot_cpu(void)
1160 {
1161 identify_cpu(&boot_cpu_data);
1162 }
1163
1164 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1165 {
1166 BUG_ON(c == &boot_cpu_data);
1167 identify_cpu(c);
1168 mtrr_ap_init();
1169 }
1170
1171 static __init int setup_noclflush(char *arg)
1172 {
1173 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1174 return 1;
1175 }
1176 __setup("noclflush", setup_noclflush);
1177
1178 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1179 {
1180 if (c->x86_model_id[0])
1181 printk(KERN_CONT "%s", c->x86_model_id);
1182
1183 if (c->x86_mask || c->cpuid_level >= 0)
1184 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1185 else
1186 printk(KERN_CONT "\n");
1187 }
1188
1189 static __init int setup_disablecpuid(char *arg)
1190 {
1191 int bit;
1192 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1193 setup_clear_cpu_cap(bit);
1194 else
1195 return 0;
1196 return 1;
1197 }
1198 __setup("clearcpuid=", setup_disablecpuid);
Linux kernel - Deliverables
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