2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
71 #include <asm/fpu/internal.h>
72 #include <asm/setup.h>
73 #include <asm/uv/uv.h>
74 #include <linux/mc146818rtc.h>
75 #include <asm/i8259.h>
76 #include <asm/realmode.h>
79 /* Number of siblings per CPU package */
80 int smp_num_siblings
= 1;
81 EXPORT_SYMBOL(smp_num_siblings
);
83 /* Last level cache ID of each logical CPU */
84 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
86 /* representing HT siblings of each logical CPU */
87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
90 /* representing HT and core siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
92 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
96 /* Per CPU bogomips and other parameters */
97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
98 EXPORT_PER_CPU_SYMBOL(cpu_info
);
100 /* Logical package management. We might want to allocate that dynamically */
101 static int *physical_to_logical_pkg __read_mostly
;
102 static unsigned long *physical_package_map __read_mostly
;;
103 static unsigned long *logical_package_map __read_mostly
;
104 static unsigned int max_physical_pkg_id __read_mostly
;
105 unsigned int __max_logical_packages __read_mostly
;
106 EXPORT_SYMBOL(__max_logical_packages
);
108 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip
)
112 spin_lock_irqsave(&rtc_lock
, flags
);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock
, flags
);
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH
)) =
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) =
125 static inline void smpboot_restore_warm_reset_vector(void)
130 * Install writable page 0 entry to set BIOS data area.
135 * Paranoid: Set warm reset code and vector here back
138 spin_lock_irqsave(&rtc_lock
, flags
);
140 spin_unlock_irqrestore(&rtc_lock
, flags
);
142 *((volatile u32
*)phys_to_virt(TRAMPOLINE_PHYS_LOW
)) = 0;
146 * Report back to the Boot Processor during boot time or to the caller processor
149 static void smp_callin(void)
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
159 cpuid
= smp_processor_id();
162 * (This works even if the APIC is not enabled.)
164 phys_id
= read_apic_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
178 smp_store_cpu_info(cpuid
);
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
187 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
188 pr_debug("Stack at about %p\n", &cpuid
);
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
194 set_cpu_sibling_map(raw_smp_processor_id());
197 notify_cpu_starting(cpuid
);
200 * Allow the master to continue.
202 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
205 static int cpu0_logical_apicid
;
206 static int enable_start_cpu0
;
208 * Activate a secondary processor.
210 static void notrace
start_secondary(void *unused
)
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
218 x86_cpuinit
.early_percpu_clock_init();
222 enable_start_cpu0
= 0;
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir
);
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
233 * Check TSC synchronization with the BP:
235 check_tsc_sync_target();
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform
.nmi_init();
250 /* enable local interrupts */
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
256 x86_cpuinit
.setup_percpu_clockev();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
262 int topology_update_package_map(unsigned int apicid
, unsigned int cpu
)
264 unsigned int new, pkg
= apicid
>> boot_cpu_data
.x86_coreid_bits
;
266 /* Called from early boot ? */
267 if (!physical_package_map
)
270 if (pkg
>= max_physical_pkg_id
)
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg
, physical_package_map
))
277 if (pkg
< __max_logical_packages
) {
278 set_bit(pkg
, logical_package_map
);
279 physical_to_logical_pkg
[pkg
] = pkg
;
282 new = find_first_zero_bit(logical_package_map
, __max_logical_packages
);
283 if (new >= __max_logical_packages
) {
284 physical_to_logical_pkg
[pkg
] = -1;
285 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
289 set_bit(new, logical_package_map
);
290 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
292 physical_to_logical_pkg
[pkg
] = new;
295 cpu_data(cpu
).logical_proc_id
= physical_to_logical_pkg
[pkg
];
300 * topology_phys_to_logical_pkg - Map a physical package id to a logical
302 * Returns logical package id or -1 if not found
304 int topology_phys_to_logical_pkg(unsigned int phys_pkg
)
306 if (phys_pkg
>= max_physical_pkg_id
)
308 return physical_to_logical_pkg
[phys_pkg
];
310 EXPORT_SYMBOL(topology_phys_to_logical_pkg
);
312 static void __init
smp_init_package_map(void)
314 unsigned int ncpus
, cpu
;
318 * Today neither Intel nor AMD support heterogenous systems. That
319 * might change in the future....
321 ncpus
= boot_cpu_data
.x86_max_cores
* smp_num_siblings
;
322 __max_logical_packages
= DIV_ROUND_UP(nr_cpu_ids
, ncpus
);
325 * Possibly larger than what we need as the number of apic ids per
326 * package can be smaller than the actual used apic ids.
328 max_physical_pkg_id
= DIV_ROUND_UP(MAX_LOCAL_APIC
, ncpus
);
329 size
= max_physical_pkg_id
* sizeof(unsigned int);
330 physical_to_logical_pkg
= kmalloc(size
, GFP_KERNEL
);
331 memset(physical_to_logical_pkg
, 0xff, size
);
332 size
= BITS_TO_LONGS(max_physical_pkg_id
) * sizeof(unsigned long);
333 physical_package_map
= kzalloc(size
, GFP_KERNEL
);
334 size
= BITS_TO_LONGS(__max_logical_packages
) * sizeof(unsigned long);
335 logical_package_map
= kzalloc(size
, GFP_KERNEL
);
337 pr_info("Max logical packages: %u\n", __max_logical_packages
);
339 for_each_present_cpu(cpu
) {
340 unsigned int apicid
= apic
->cpu_present_to_apicid(cpu
);
342 if (apicid
== BAD_APICID
|| !apic
->apic_id_valid(apicid
))
344 if (!topology_update_package_map(apicid
, cpu
))
346 pr_warn("CPU %u APICId %x disabled\n", cpu
, apicid
);
347 per_cpu(x86_bios_cpu_apicid
, cpu
) = BAD_APICID
;
348 set_cpu_possible(cpu
, false);
349 set_cpu_present(cpu
, false);
353 void __init
smp_store_boot_cpu_info(void)
355 int id
= 0; /* CPU 0 */
356 struct cpuinfo_x86
*c
= &cpu_data(id
);
360 smp_init_package_map();
364 * The bootstrap kernel entry code has set these up. Save them for
367 void smp_store_cpu_info(int id
)
369 struct cpuinfo_x86
*c
= &cpu_data(id
);
374 * During boot time, CPU0 has this setup already. Save the info when
375 * bringing up AP or offlined CPU0.
377 identify_secondary_cpu(c
);
381 topology_same_node(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
383 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
385 return (cpu_to_node(cpu1
) == cpu_to_node(cpu2
));
389 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
391 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
393 return !WARN_ONCE(!topology_same_node(c
, o
),
394 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
395 "[node: %d != %d]. Ignoring dependency.\n",
396 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
399 #define link_mask(mfunc, c1, c2) \
401 cpumask_set_cpu((c1), mfunc(c2)); \
402 cpumask_set_cpu((c2), mfunc(c1)); \
405 static bool match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
407 if (boot_cpu_has(X86_FEATURE_TOPOEXT
)) {
408 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
410 if (c
->phys_proc_id
== o
->phys_proc_id
&&
411 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
412 c
->compute_unit_id
== o
->compute_unit_id
)
413 return topology_sane(c
, o
, "smt");
415 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
416 c
->cpu_core_id
== o
->cpu_core_id
) {
417 return topology_sane(c
, o
, "smt");
423 static bool match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
425 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
427 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
428 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
429 return topology_sane(c
, o
, "llc");
435 * Unlike the other levels, we do not enforce keeping a
436 * multicore group inside a NUMA node. If this happens, we will
437 * discard the MC level of the topology later.
439 static bool match_die(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
441 if (c
->phys_proc_id
== o
->phys_proc_id
)
446 static struct sched_domain_topology_level numa_inside_package_topology
[] = {
447 #ifdef CONFIG_SCHED_SMT
448 { cpu_smt_mask
, cpu_smt_flags
, SD_INIT_NAME(SMT
) },
450 #ifdef CONFIG_SCHED_MC
451 { cpu_coregroup_mask
, cpu_core_flags
, SD_INIT_NAME(MC
) },
456 * set_sched_topology() sets the topology internal to a CPU. The
457 * NUMA topologies are layered on top of it to build the full
460 * If NUMA nodes are observed to occur within a CPU package, this
461 * function should be called. It forces the sched domain code to
462 * only use the SMT level for the CPU portion of the topology.
463 * This essentially falls back to relying on NUMA information
464 * from the SRAT table to describe the entire system topology
465 * (except for hyperthreads).
467 static void primarily_use_numa_for_topology(void)
469 set_sched_topology(numa_inside_package_topology
);
472 void set_cpu_sibling_map(int cpu
)
474 bool has_smt
= smp_num_siblings
> 1;
475 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
476 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
477 struct cpuinfo_x86
*o
;
480 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
483 cpumask_set_cpu(cpu
, topology_sibling_cpumask(cpu
));
484 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
485 cpumask_set_cpu(cpu
, topology_core_cpumask(cpu
));
490 for_each_cpu(i
, cpu_sibling_setup_mask
) {
493 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
494 link_mask(topology_sibling_cpumask
, cpu
, i
);
496 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
497 link_mask(cpu_llc_shared_mask
, cpu
, i
);
502 * This needs a separate iteration over the cpus because we rely on all
503 * topology_sibling_cpumask links to be set-up.
505 for_each_cpu(i
, cpu_sibling_setup_mask
) {
508 if ((i
== cpu
) || (has_mp
&& match_die(c
, o
))) {
509 link_mask(topology_core_cpumask
, cpu
, i
);
512 * Does this new cpu bringup a new core?
515 topology_sibling_cpumask(cpu
)) == 1) {
517 * for each core in package, increment
518 * the booted_cores for this new cpu
521 topology_sibling_cpumask(i
)) == i
)
524 * increment the core count for all
525 * the other cpus in this package
528 cpu_data(i
).booted_cores
++;
529 } else if (i
!= cpu
&& !c
->booted_cores
)
530 c
->booted_cores
= cpu_data(i
).booted_cores
;
532 if (match_die(c
, o
) && !topology_same_node(c
, o
))
533 primarily_use_numa_for_topology();
537 /* maps the cpu to the sched domain representing multi-core */
538 const struct cpumask
*cpu_coregroup_mask(int cpu
)
540 return cpu_llc_shared_mask(cpu
);
543 static void impress_friends(void)
546 unsigned long bogosum
= 0;
548 * Allow the user to impress friends.
550 pr_debug("Before bogomips\n");
551 for_each_possible_cpu(cpu
)
552 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
553 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
554 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
557 (bogosum
/(5000/HZ
))%100);
559 pr_debug("Before bogocount - setting activated=1\n");
562 void __inquire_remote_apic(int apicid
)
564 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
565 const char * const names
[] = { "ID", "VERSION", "SPIV" };
569 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
571 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
572 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
577 status
= safe_apic_wait_icr_idle();
579 pr_cont("a previous APIC delivery may have failed\n");
581 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
586 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
587 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
590 case APIC_ICR_RR_VALID
:
591 status
= apic_read(APIC_RRR
);
592 pr_cont("%08x\n", status
);
601 * The Multiprocessor Specification 1.4 (1997) example code suggests
602 * that there should be a 10ms delay between the BSP asserting INIT
603 * and de-asserting INIT, when starting a remote processor.
604 * But that slows boot and resume on modern processors, which include
605 * many cores and don't require that delay.
607 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
608 * Modern processor families are quirked to remove the delay entirely.
610 #define UDELAY_10MS_DEFAULT 10000
612 static unsigned int init_udelay
= UINT_MAX
;
614 static int __init
cpu_init_udelay(char *str
)
616 get_option(&str
, &init_udelay
);
620 early_param("cpu_init_udelay", cpu_init_udelay
);
622 static void __init
smp_quirk_init_udelay(void)
624 /* if cmdline changed it from default, leave it alone */
625 if (init_udelay
!= UINT_MAX
)
628 /* if modern processor, use no delay */
629 if (((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 6)) ||
630 ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && (boot_cpu_data
.x86
>= 0xF))) {
634 /* else, use legacy delay */
635 init_udelay
= UDELAY_10MS_DEFAULT
;
639 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
640 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
641 * won't ... remember to clear down the APIC, etc later.
644 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
646 unsigned long send_status
, accept_status
= 0;
650 /* Boot on the stack */
651 /* Kick the second */
652 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
654 pr_debug("Waiting for send to finish...\n");
655 send_status
= safe_apic_wait_icr_idle();
658 * Give the other CPU some time to accept the IPI.
661 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
662 maxlvt
= lapic_get_maxlvt();
663 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
664 apic_write(APIC_ESR
, 0);
665 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
667 pr_debug("NMI sent\n");
670 pr_err("APIC never delivered???\n");
672 pr_err("APIC delivery error (%lx)\n", accept_status
);
674 return (send_status
| accept_status
);
678 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
680 unsigned long send_status
= 0, accept_status
= 0;
681 int maxlvt
, num_starts
, j
;
683 maxlvt
= lapic_get_maxlvt();
686 * Be paranoid about clearing APIC errors.
688 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
689 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
690 apic_write(APIC_ESR
, 0);
694 pr_debug("Asserting INIT\n");
697 * Turn INIT on target chip
702 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
705 pr_debug("Waiting for send to finish...\n");
706 send_status
= safe_apic_wait_icr_idle();
710 pr_debug("Deasserting INIT\n");
714 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
716 pr_debug("Waiting for send to finish...\n");
717 send_status
= safe_apic_wait_icr_idle();
722 * Should we send STARTUP IPIs ?
724 * Determine this based on the APIC version.
725 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
727 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
733 * Run STARTUP IPI loop.
735 pr_debug("#startup loops: %d\n", num_starts
);
737 for (j
= 1; j
<= num_starts
; j
++) {
738 pr_debug("Sending STARTUP #%d\n", j
);
739 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
740 apic_write(APIC_ESR
, 0);
742 pr_debug("After apic_write\n");
749 /* Boot on the stack */
750 /* Kick the second */
751 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
755 * Give the other CPU some time to accept the IPI.
757 if (init_udelay
== 0)
762 pr_debug("Startup point 1\n");
764 pr_debug("Waiting for send to finish...\n");
765 send_status
= safe_apic_wait_icr_idle();
768 * Give the other CPU some time to accept the IPI.
770 if (init_udelay
== 0)
775 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
776 apic_write(APIC_ESR
, 0);
777 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
778 if (send_status
|| accept_status
)
781 pr_debug("After Startup\n");
784 pr_err("APIC never delivered???\n");
786 pr_err("APIC delivery error (%lx)\n", accept_status
);
788 return (send_status
| accept_status
);
791 void smp_announce(void)
793 int num_nodes
= num_online_nodes();
795 printk(KERN_INFO
"x86: Booted up %d node%s, %d CPUs\n",
796 num_nodes
, (num_nodes
> 1 ? "s" : ""), num_online_cpus());
799 /* reduce the number of lines printed when booting a large cpu count system */
800 static void announce_cpu(int cpu
, int apicid
)
802 static int current_node
= -1;
803 int node
= early_cpu_to_node(cpu
);
804 static int width
, node_width
;
807 width
= num_digits(num_possible_cpus()) + 1; /* + '#' sign */
810 node_width
= num_digits(num_possible_nodes()) + 1; /* + '#' */
813 printk(KERN_INFO
"x86: Booting SMP configuration:\n");
815 if (system_state
== SYSTEM_BOOTING
) {
816 if (node
!= current_node
) {
817 if (current_node
> (-1))
821 printk(KERN_INFO
".... node %*s#%d, CPUs: ",
822 node_width
- num_digits(node
), " ", node
);
825 /* Add padding for the BSP */
827 pr_cont("%*s", width
+ 1, " ");
829 pr_cont("%*s#%d", width
- num_digits(cpu
), " ", cpu
);
832 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
836 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
840 cpu
= smp_processor_id();
841 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
848 * Wake up AP by INIT, INIT, STARTUP sequence.
850 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
851 * boot-strap code which is not a desired behavior for waking up BSP. To
852 * void the boot-strap code, wake up CPU0 by NMI instead.
854 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
855 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
856 * We'll change this code in the future to wake up hard offlined CPU0 if
857 * real platform and request are available.
860 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
861 int *cpu0_nmi_registered
)
869 * Wake up AP by INIT, INIT, STARTUP sequence.
872 boot_error
= wakeup_secondary_cpu_via_init(apicid
, start_ip
);
877 * Wake up BSP by nmi.
879 * Register a NMI handler to help wake up CPU0.
881 boot_error
= register_nmi_handler(NMI_LOCAL
,
882 wakeup_cpu0_nmi
, 0, "wake_cpu0");
885 enable_start_cpu0
= 1;
886 *cpu0_nmi_registered
= 1;
887 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
888 id
= cpu0_logical_apicid
;
891 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
900 void common_cpu_up(unsigned int cpu
, struct task_struct
*idle
)
902 /* Just in case we booted with a single CPU. */
903 alternatives_enable_smp();
905 per_cpu(current_task
, cpu
) = idle
;
908 /* Stack for startup_32 can be just as for start_secondary onwards */
910 per_cpu(cpu_current_top_of_stack
, cpu
) =
911 (unsigned long)task_stack_page(idle
) + THREAD_SIZE
;
913 clear_tsk_thread_flag(idle
, TIF_FORK
);
914 initial_gs
= per_cpu_offset(cpu
);
919 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
920 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
921 * Returns zero if CPU booted OK, else error code from
922 * ->wakeup_secondary_cpu.
924 static int do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
926 volatile u32
*trampoline_status
=
927 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
928 /* start_ip had better be page-aligned! */
929 unsigned long start_ip
= real_mode_header
->trampoline_start
;
931 unsigned long boot_error
= 0;
932 int cpu0_nmi_registered
= 0;
933 unsigned long timeout
;
935 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
936 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
938 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
939 initial_code
= (unsigned long)start_secondary
;
940 stack_start
= idle
->thread
.sp
;
943 * Enable the espfix hack for this CPU
945 #ifdef CONFIG_X86_ESPFIX64
949 /* So we see what's up */
950 announce_cpu(cpu
, apicid
);
953 * This grunge runs the startup process for
954 * the targeted processor.
957 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
959 pr_debug("Setting warm reset code and vector.\n");
961 smpboot_setup_warm_reset_vector(start_ip
);
963 * Be paranoid about clearing APIC errors.
965 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
966 apic_write(APIC_ESR
, 0);
972 * AP might wait on cpu_callout_mask in cpu_init() with
973 * cpu_initialized_mask set if previous attempt to online
974 * it timed-out. Clear cpu_initialized_mask so that after
975 * INIT/SIPI it could start with a clean state.
977 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
981 * Wake up a CPU in difference cases:
982 * - Use the method in the APIC driver if it's defined
984 * - Use an INIT boot APIC message for APs or NMI for BSP.
986 if (apic
->wakeup_secondary_cpu
)
987 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
989 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
990 &cpu0_nmi_registered
);
994 * Wait 10s total for first sign of life from AP
997 timeout
= jiffies
+ 10*HZ
;
998 while (time_before(jiffies
, timeout
)) {
999 if (cpumask_test_cpu(cpu
, cpu_initialized_mask
)) {
1001 * Tell AP to proceed with initialization
1003 cpumask_set_cpu(cpu
, cpu_callout_mask
);
1013 * Wait till AP completes initial initialization
1015 while (!cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1017 * Allow other tasks to run while we wait for the
1018 * AP to come online. This also gives a chance
1019 * for the MTRR work(triggered by the AP coming online)
1020 * to be completed in the stop machine context.
1026 /* mark "stuck" area as not stuck */
1027 *trampoline_status
= 0;
1029 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
1031 * Cleanup possible dangling ends...
1033 smpboot_restore_warm_reset_vector();
1036 * Clean up the nmi handler. Do this after the callin and callout sync
1037 * to avoid impact of possible long unregister time.
1039 if (cpu0_nmi_registered
)
1040 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
1045 int native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1047 int apicid
= apic
->cpu_present_to_apicid(cpu
);
1048 unsigned long flags
;
1051 WARN_ON(irqs_disabled());
1053 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
1055 if (apicid
== BAD_APICID
||
1056 !physid_isset(apicid
, phys_cpu_present_map
) ||
1057 !apic
->apic_id_valid(apicid
)) {
1058 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
1063 * Already booted CPU?
1065 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
1066 pr_debug("do_boot_cpu %d Already started\n", cpu
);
1071 * Save current MTRR state in case it was changed since early boot
1072 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1076 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1077 err
= cpu_check_up_prepare(cpu
);
1078 if (err
&& err
!= -EBUSY
)
1081 /* the FPU context is blank, nobody can own it */
1082 __cpu_disable_lazy_restore(cpu
);
1084 common_cpu_up(cpu
, tidle
);
1087 * We have to walk the irq descriptors to setup the vector
1088 * space for the cpu which comes online. Prevent irq
1089 * alloc/free across the bringup.
1093 err
= do_boot_cpu(apicid
, cpu
, tidle
);
1096 irq_unlock_sparse();
1097 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err
, cpu
);
1102 * Check TSC synchronization with the AP (keep irqs disabled
1105 local_irq_save(flags
);
1106 check_tsc_sync_source(cpu
);
1107 local_irq_restore(flags
);
1109 while (!cpu_online(cpu
)) {
1111 touch_nmi_watchdog();
1114 irq_unlock_sparse();
1120 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1122 void arch_disable_smp_support(void)
1124 disable_ioapic_support();
1128 * Fall back to non SMP mode after errors.
1130 * RED-PEN audit/test this more. I bet there is more state messed up here.
1132 static __init
void disable_smp(void)
1134 pr_info("SMP disabled\n");
1136 disable_ioapic_support();
1138 init_cpu_present(cpumask_of(0));
1139 init_cpu_possible(cpumask_of(0));
1141 if (smp_found_config
)
1142 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1144 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
1145 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1146 cpumask_set_cpu(0, topology_core_cpumask(0));
1157 * Various sanity checks.
1159 static int __init
smp_sanity_check(unsigned max_cpus
)
1163 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1164 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
1168 pr_warn("More than 8 CPUs detected - skipping them\n"
1169 "Use CONFIG_X86_BIGSMP\n");
1172 for_each_present_cpu(cpu
) {
1174 set_cpu_present(cpu
, false);
1179 for_each_possible_cpu(cpu
) {
1181 set_cpu_possible(cpu
, false);
1189 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1190 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1191 hard_smp_processor_id());
1193 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1197 * If we couldn't find an SMP configuration at boot time,
1198 * get out of here now!
1200 if (!smp_found_config
&& !acpi_lapic
) {
1202 pr_notice("SMP motherboard not detected\n");
1203 return SMP_NO_CONFIG
;
1207 * Should not be necessary because the MP table should list the boot
1208 * CPU too, but we do it for the sake of robustness anyway.
1210 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1211 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1212 boot_cpu_physical_apicid
);
1213 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1218 * If we couldn't find a local APIC, then get out of here now!
1220 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1222 if (!disable_apic
) {
1223 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1224 boot_cpu_physical_apicid
);
1225 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1231 * If SMP should be disabled, then really disable it!
1234 pr_info("SMP mode deactivated\n");
1235 return SMP_FORCE_UP
;
1241 static void __init
smp_cpu_index_default(void)
1244 struct cpuinfo_x86
*c
;
1246 for_each_possible_cpu(i
) {
1248 /* mark all to hotplug */
1249 c
->cpu_index
= nr_cpu_ids
;
1254 * Prepare for SMP bootup. The MP table or ACPI has been read
1255 * earlier. Just do some sanity checking here and enable APIC mode.
1257 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1261 smp_cpu_index_default();
1264 * Setup boot CPU information
1266 smp_store_boot_cpu_info(); /* Final full version of the data */
1267 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1270 current_thread_info()->cpu
= 0; /* needed? */
1271 for_each_possible_cpu(i
) {
1272 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1273 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1274 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1276 set_cpu_sibling_map(0);
1278 switch (smp_sanity_check(max_cpus
)) {
1281 if (APIC_init_uniprocessor())
1282 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1289 apic_bsp_setup(false);
1295 default_setup_apic_routing();
1297 if (read_apic_id() != boot_cpu_physical_apicid
) {
1298 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1299 read_apic_id(), boot_cpu_physical_apicid
);
1300 /* Or can we switch back to PIC here? */
1303 cpu0_logical_apicid
= apic_bsp_setup(false);
1305 pr_info("CPU%d: ", 0);
1306 print_cpu_info(&cpu_data(0));
1311 set_mtrr_aps_delayed_init();
1313 smp_quirk_init_udelay();
1316 void arch_enable_nonboot_cpus_begin(void)
1318 set_mtrr_aps_delayed_init();
1321 void arch_enable_nonboot_cpus_end(void)
1327 * Early setup to make printk work.
1329 void __init
native_smp_prepare_boot_cpu(void)
1331 int me
= smp_processor_id();
1332 switch_to_new_gdt(me
);
1333 /* already set me in cpu_online_mask in boot_cpu_init() */
1334 cpumask_set_cpu(me
, cpu_callout_mask
);
1335 cpu_set_state_online(me
);
1338 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1340 pr_debug("Boot done\n");
1344 setup_ioapic_dest();
1348 static int __initdata setup_possible_cpus
= -1;
1349 static int __init
_setup_possible_cpus(char *str
)
1351 get_option(&str
, &setup_possible_cpus
);
1354 early_param("possible_cpus", _setup_possible_cpus
);
1358 * cpu_possible_mask should be static, it cannot change as cpu's
1359 * are onlined, or offlined. The reason is per-cpu data-structures
1360 * are allocated by some modules at init time, and dont expect to
1361 * do this dynamically on cpu arrival/departure.
1362 * cpu_present_mask on the other hand can change dynamically.
1363 * In case when cpu_hotplug is not compiled, then we resort to current
1364 * behaviour, which is cpu_possible == cpu_present.
1367 * Three ways to find out the number of additional hotplug CPUs:
1368 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1369 * - The user can overwrite it with possible_cpus=NUM
1370 * - Otherwise don't reserve additional CPUs.
1371 * We do this because additional CPUs waste a lot of memory.
1374 __init
void prefill_possible_map(void)
1378 /* no processor from mptable or madt */
1379 if (!num_processors
)
1382 i
= setup_max_cpus
?: 1;
1383 if (setup_possible_cpus
== -1) {
1384 possible
= num_processors
;
1385 #ifdef CONFIG_HOTPLUG_CPU
1387 possible
+= disabled_cpus
;
1393 possible
= setup_possible_cpus
;
1395 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1397 /* nr_cpu_ids could be reduced via nr_cpus= */
1398 if (possible
> nr_cpu_ids
) {
1399 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1400 possible
, nr_cpu_ids
);
1401 possible
= nr_cpu_ids
;
1404 #ifdef CONFIG_HOTPLUG_CPU
1405 if (!setup_max_cpus
)
1408 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1409 possible
, setup_max_cpus
);
1413 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1414 possible
, max_t(int, possible
- num_processors
, 0));
1416 for (i
= 0; i
< possible
; i
++)
1417 set_cpu_possible(i
, true);
1418 for (; i
< NR_CPUS
; i
++)
1419 set_cpu_possible(i
, false);
1421 nr_cpu_ids
= possible
;
1424 #ifdef CONFIG_HOTPLUG_CPU
1426 static void remove_siblinginfo(int cpu
)
1429 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1431 for_each_cpu(sibling
, topology_core_cpumask(cpu
)) {
1432 cpumask_clear_cpu(cpu
, topology_core_cpumask(sibling
));
1434 * last thread sibling in this cpu core going down
1436 if (cpumask_weight(topology_sibling_cpumask(cpu
)) == 1)
1437 cpu_data(sibling
).booted_cores
--;
1440 for_each_cpu(sibling
, topology_sibling_cpumask(cpu
))
1441 cpumask_clear_cpu(cpu
, topology_sibling_cpumask(sibling
));
1442 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1443 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1444 cpumask_clear(cpu_llc_shared_mask(cpu
));
1445 cpumask_clear(topology_sibling_cpumask(cpu
));
1446 cpumask_clear(topology_core_cpumask(cpu
));
1447 c
->phys_proc_id
= 0;
1449 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1452 static void remove_cpu_from_maps(int cpu
)
1454 set_cpu_online(cpu
, false);
1455 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1456 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1457 /* was set by cpu_init() */
1458 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1459 numa_remove_cpu(cpu
);
1462 void cpu_disable_common(void)
1464 int cpu
= smp_processor_id();
1466 remove_siblinginfo(cpu
);
1468 /* It's now safe to remove this processor from the online map */
1470 remove_cpu_from_maps(cpu
);
1471 unlock_vector_lock();
1475 int native_cpu_disable(void)
1479 ret
= check_irq_vectors_for_cpu_disable();
1484 cpu_disable_common();
1489 int common_cpu_die(unsigned int cpu
)
1493 /* We don't do anything here: idle task is faking death itself. */
1495 /* They ack this in play_dead() by setting CPU_DEAD */
1496 if (cpu_wait_death(cpu
, 5)) {
1497 if (system_state
== SYSTEM_RUNNING
)
1498 pr_info("CPU %u is now offline\n", cpu
);
1500 pr_err("CPU %u didn't die...\n", cpu
);
1507 void native_cpu_die(unsigned int cpu
)
1509 common_cpu_die(cpu
);
1512 void play_dead_common(void)
1515 reset_lazy_tlbstate();
1516 amd_e400_remove_cpu(raw_smp_processor_id());
1519 (void)cpu_report_death();
1522 * With physical CPU hotplug, we should halt the cpu
1524 local_irq_disable();
1527 static bool wakeup_cpu0(void)
1529 if (smp_processor_id() == 0 && enable_start_cpu0
)
1536 * We need to flush the caches before going to sleep, lest we have
1537 * dirty data in our caches when we come back up.
1539 static inline void mwait_play_dead(void)
1541 unsigned int eax
, ebx
, ecx
, edx
;
1542 unsigned int highest_cstate
= 0;
1543 unsigned int highest_subcstate
= 0;
1547 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1549 if (!this_cpu_has(X86_FEATURE_CLFLUSH
))
1551 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1554 eax
= CPUID_MWAIT_LEAF
;
1556 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1559 * eax will be 0 if EDX enumeration is not valid.
1560 * Initialized below to cstate, sub_cstate value when EDX is valid.
1562 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1565 edx
>>= MWAIT_SUBSTATE_SIZE
;
1566 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1567 if (edx
& MWAIT_SUBSTATE_MASK
) {
1569 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1572 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1573 (highest_subcstate
- 1);
1577 * This should be a memory location in a cache line which is
1578 * unlikely to be touched by other processors. The actual
1579 * content is immaterial as it is not actually modified in any way.
1581 mwait_ptr
= ¤t_thread_info()->flags
;
1587 * The CLFLUSH is a workaround for erratum AAI65 for
1588 * the Xeon 7400 series. It's not clear it is actually
1589 * needed, but it should be harmless in either case.
1590 * The WBINVD is insufficient due to the spurious-wakeup
1591 * case where we return around the loop.
1596 __monitor(mwait_ptr
, 0, 0);
1600 * If NMI wants to wake up CPU0, start CPU0.
1607 static inline void hlt_play_dead(void)
1609 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1615 * If NMI wants to wake up CPU0, start CPU0.
1622 void native_play_dead(void)
1625 tboot_shutdown(TB_SHUTDOWN_WFS
);
1627 mwait_play_dead(); /* Only returns on failure */
1628 if (cpuidle_play_dead())
1632 #else /* ... !CONFIG_HOTPLUG_CPU */
1633 int native_cpu_disable(void)
1638 void native_cpu_die(unsigned int cpu
)
1640 /* We said "no" in __cpu_disable */
1644 void native_play_dead(void)