arch/x86/kernel/smpboot_64.c

   1 /*
   2  *      x86 SMP booting functions
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   5  *      (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
   6  *      Copyright 2001 Andi Kleen, SuSE Labs.
   7  *
   8  *      Much of the core SMP work is based on previous work by Thomas Radke, to
   9  *      whom a great many thanks are extended.
  10  *
  11  *      Thanks to Intel for making available several different Pentium,
  12  *      Pentium Pro and Pentium-II/Xeon MP machines.
  13  *      Original development of Linux SMP code supported by Caldera.
  14  *
  15  *      This code is released under the GNU General Public License version 2
  16  *
  17  *      Fixes
  18  *              Felix Koop      :       NR_CPUS used properly
  19  *              Jose Renau      :       Handle single CPU case.
  20  *              Alan Cox        :       By repeated request 8) - Total BogoMIP report.
  21  *              Greg Wright     :       Fix for kernel stacks panic.
  22  *              Erich Boleyn    :       MP v1.4 and additional changes.
  23  *      Matthias Sattler        :       Changes for 2.1 kernel map.
  24  *      Michel Lespinasse       :       Changes for 2.1 kernel map.
  25  *      Michael Chastain        :       Change trampoline.S to gnu as.
  26  *              Alan Cox        :       Dumb bug: 'B' step PPro's are fine
  27  *              Ingo Molnar     :       Added APIC timers, based on code
  28  *                                      from Jose Renau
  29  *              Ingo Molnar     :       various cleanups and rewrites
  30  *              Tigran Aivazian :       fixed "0.00 in /proc/uptime on SMP" bug.
  31  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs
  32  *      Andi Kleen              :       Changed for SMP boot into long mode.
  33  *              Rusty Russell   :       Hacked into shape for new "hotplug" boot process.
  34  *      Andi Kleen              :       Converted to new state machine.
  35  *                                      Various cleanups.
  36  *                                      Probably mostly hotplug CPU ready now.
  37  *      Ashok Raj                       : CPU hotplug support
  38  */
  39
  40
  41 #include <linux/init.h>
  42
  43 #include <linux/mm.h>
  44 #include <linux/kernel_stat.h>
  45 #include <linux/bootmem.h>
  46 #include <linux/thread_info.h>
  47 #include <linux/module.h>
  48 #include <linux/delay.h>
  49 #include <linux/mc146818rtc.h>
  50 #include <linux/smp.h>
  51 #include <linux/kdebug.h>
  52
  53 #include <asm/mtrr.h>
  54 #include <asm/pgalloc.h>
  55 #include <asm/desc.h>
  56 #include <asm/tlbflush.h>
  57 #include <asm/proto.h>
  58 #include <asm/nmi.h>
  59 #include <asm/irq.h>
  60 #include <asm/hw_irq.h>
  61 #include <asm/numa.h>
  62
  63 /* Set when the idlers are all forked */
  64 int smp_threads_ready;
  65
  66 /*
  67  * Trampoline 80x86 program as an array.
  68  */
  69
  70 extern const unsigned char trampoline_data[];
  71 extern const unsigned char trampoline_end[];
  72
  73 /* State of each CPU */
  74 DEFINE_PER_CPU(int, cpu_state) = { 0 };
  75
  76 /*
  77  * Store all idle threads, this can be reused instead of creating
  78  * a new thread. Also avoids complicated thread destroy functionality
  79  * for idle threads.
  80  */
  81 #ifdef CONFIG_HOTPLUG_CPU
  82 /*
  83  * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
  84  * removed after init for !CONFIG_HOTPLUG_CPU.
  85  */
  86 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
  87 #define get_idle_for_cpu(x)     (per_cpu(idle_thread_array, x))
  88 #define set_idle_for_cpu(x,p)   (per_cpu(idle_thread_array, x) = (p))
  89 #else
  90 struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
  91 #define get_idle_for_cpu(x)     (idle_thread_array[(x)])
  92 #define set_idle_for_cpu(x,p)   (idle_thread_array[(x)] = (p))
  93 #endif
  94
  95
  96 /*
  97  * Currently trivial. Write the real->protected mode
  98  * bootstrap into the page concerned. The caller
  99  * has made sure it's suitably aligned.
 100  */
 101
 102 static unsigned long __cpuinit setup_trampoline(void)
 103 {
 104         void *tramp = __va(SMP_TRAMPOLINE_BASE);
 105         memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
 106         return virt_to_phys(tramp);
 107 }
 108
 109 /*
 110  * The bootstrap kernel entry code has set these up. Save them for
 111  * a given CPU
 112  */
 113
 114 static void __cpuinit smp_store_cpu_info(int id)
 115 {
 116         struct cpuinfo_x86 *c = &cpu_data(id);
 117
 118         *c = boot_cpu_data;
 119         c->cpu_index = id;
 120         identify_cpu(c);
 121         print_cpu_info(c);
 122 }
 123
 124 static atomic_t init_deasserted __cpuinitdata;
 125
 126 /*
 127  * Report back to the Boot Processor.
 128  * Running on AP.
 129  */
 130 void __cpuinit smp_callin(void)
 131 {
 132         int cpuid, phys_id;
 133         unsigned long timeout;
 134
 135         /*
 136          * If waken up by an INIT in an 82489DX configuration
 137          * we may get here before an INIT-deassert IPI reaches
 138          * our local APIC.  We have to wait for the IPI or we'll
 139          * lock up on an APIC access.
 140          */
 141         while (!atomic_read(&init_deasserted))
 142                 cpu_relax();
 143
 144         /*
 145          * (This works even if the APIC is not enabled.)
 146          */
 147         phys_id = GET_APIC_ID(apic_read(APIC_ID));
 148         cpuid = smp_processor_id();
 149         if (cpu_isset(cpuid, cpu_callin_map)) {
 150                 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
 151                                         phys_id, cpuid);
 152         }
 153         Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
 154
 155         /*
 156          * STARTUP IPIs are fragile beasts as they might sometimes
 157          * trigger some glue motherboard logic. Complete APIC bus
 158          * silence for 1 second, this overestimates the time the
 159          * boot CPU is spending to send the up to 2 STARTUP IPIs
 160          * by a factor of two. This should be enough.
 161          */
 162
 163         /*
 164          * Waiting 2s total for startup (udelay is not yet working)
 165          */
 166         timeout = jiffies + 2*HZ;
 167         while (time_before(jiffies, timeout)) {
 168                 /*
 169                  * Has the boot CPU finished it's STARTUP sequence?
 170                  */
 171                 if (cpu_isset(cpuid, cpu_callout_map))
 172                         break;
 173                 cpu_relax();
 174         }
 175
 176         if (!time_before(jiffies, timeout)) {
 177                 panic("smp_callin: CPU%d started up but did not get a callout!\n",
 178                         cpuid);
 179         }
 180
 181         /*
 182          * the boot CPU has finished the init stage and is spinning
 183          * on callin_map until we finish. We are free to set up this
 184          * CPU, first the APIC. (this is probably redundant on most
 185          * boards)
 186          */
 187
 188         Dprintk("CALLIN, before setup_local_APIC().\n");
 189         setup_local_APIC();
 190         end_local_APIC_setup();
 191
 192         /*
 193          * Get our bogomips.
 194          *
 195          * Need to enable IRQs because it can take longer and then
 196          * the NMI watchdog might kill us.
 197          */
 198         local_irq_enable();
 199         calibrate_delay();
 200         local_irq_disable();
 201         Dprintk("Stack at about %p\n",&cpuid);
 202
 203         /*
 204          * Save our processor parameters
 205          */
 206         smp_store_cpu_info(cpuid);
 207
 208         /*
 209          * Allow the master to continue.
 210          */
 211         cpu_set(cpuid, cpu_callin_map);
 212 }
 213
 214 /*
 215  * Setup code on secondary processor (after comming out of the trampoline)
 216  */
 217 void __cpuinit start_secondary(void)
 218 {
 219         /*
 220          * Dont put anything before smp_callin(), SMP
 221          * booting is too fragile that we want to limit the
 222          * things done here to the most necessary things.
 223          */
 224         cpu_init();
 225         preempt_disable();
 226         smp_callin();
 227
 228         /* otherwise gcc will move up the smp_processor_id before the cpu_init */
 229         barrier();
 230
 231         /*
 232          * Check TSC sync first:
 233          */
 234         check_tsc_sync_target();
 235
 236         if (nmi_watchdog == NMI_IO_APIC) {
 237                 disable_8259A_irq(0);
 238                 enable_NMI_through_LVT0();
 239                 enable_8259A_irq(0);
 240         }
 241
 242         /*
 243          * The sibling maps must be set before turing the online map on for
 244          * this cpu
 245          */
 246         set_cpu_sibling_map(smp_processor_id());
 247
 248         /*
 249          * We need to hold call_lock, so there is no inconsistency
 250          * between the time smp_call_function() determines number of
 251          * IPI recipients, and the time when the determination is made
 252          * for which cpus receive the IPI in genapic_flat.c. Holding this
 253          * lock helps us to not include this cpu in a currently in progress
 254          * smp_call_function().
 255          */
 256         lock_ipi_call_lock();
 257         spin_lock(&vector_lock);
 258
 259         /* Setup the per cpu irq handling data structures */
 260         __setup_vector_irq(smp_processor_id());
 261         /*
 262          * Allow the master to continue.
 263          */
 264         spin_unlock(&vector_lock);
 265         cpu_set(smp_processor_id(), cpu_online_map);
 266         per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
 267
 268         unlock_ipi_call_lock();
 269
 270         setup_secondary_clock();
 271
 272         cpu_idle();
 273 }
 274
 275 extern volatile unsigned long init_rsp;
 276 extern void (*initial_code)(void);
 277
 278 #ifdef APIC_DEBUG
 279 static void inquire_remote_apic(int apicid)
 280 {
 281         unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
 282         char *names[] = { "ID", "VERSION", "SPIV" };
 283         int timeout;
 284         u32 status;
 285
 286         printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
 287
 288         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 289                 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
 290
 291                 /*
 292                  * Wait for idle.
 293                  */
 294                 status = safe_apic_wait_icr_idle();
 295                 if (status)
 296                         printk(KERN_CONT
 297                                "a previous APIC delivery may have failed\n");
 298
 299                 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 300                 apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]);
 301
 302                 timeout = 0;
 303                 do {
 304                         udelay(100);
 305                         status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 306                 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 307
 308                 switch (status) {
 309                 case APIC_ICR_RR_VALID:
 310                         status = apic_read(APIC_RRR);
 311                         printk(KERN_CONT "%08x\n", status);
 312                         break;
 313                 default:
 314                         printk(KERN_CONT "failed\n");
 315                 }
 316         }
 317 }
 318 #endif
 319
 320 /*
 321  * Kick the secondary to wake up.
 322  */
 323 static int __cpuinit wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
 324 {
 325         unsigned long send_status, accept_status = 0;
 326         int maxlvt, num_starts, j;
 327
 328         Dprintk("Asserting INIT.\n");
 329
 330         /*
 331          * Turn INIT on target chip
 332          */
 333         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 334
 335         /*
 336          * Send IPI
 337          */
 338         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
 339                                 | APIC_DM_INIT);
 340
 341         Dprintk("Waiting for send to finish...\n");
 342         send_status = safe_apic_wait_icr_idle();
 343
 344         mdelay(10);
 345
 346         Dprintk("Deasserting INIT.\n");
 347
 348         /* Target chip */
 349         apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 350
 351         /* Send IPI */
 352         apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
 353
 354         Dprintk("Waiting for send to finish...\n");
 355         send_status = safe_apic_wait_icr_idle();
 356
 357         mb();
 358         atomic_set(&init_deasserted, 1);
 359
 360         num_starts = 2;
 361
 362         /*
 363          * Run STARTUP IPI loop.
 364          */
 365         Dprintk("#startup loops: %d.\n", num_starts);
 366
 367         maxlvt = lapic_get_maxlvt();
 368
 369         for (j = 1; j <= num_starts; j++) {
 370                 Dprintk("Sending STARTUP #%d.\n",j);
 371                 apic_write(APIC_ESR, 0);
 372                 apic_read(APIC_ESR);
 373                 Dprintk("After apic_write.\n");
 374
 375                 /*
 376                  * STARTUP IPI
 377                  */
 378
 379                 /* Target chip */
 380                 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 381
 382                 /* Boot on the stack */
 383                 /* Kick the second */
 384                 apic_write(APIC_ICR, APIC_DM_STARTUP | (start_rip >> 12));
 385
 386                 /*
 387                  * Give the other CPU some time to accept the IPI.
 388                  */
 389                 udelay(300);
 390
 391                 Dprintk("Startup point 1.\n");
 392
 393                 Dprintk("Waiting for send to finish...\n");
 394                 send_status = safe_apic_wait_icr_idle();
 395
 396                 /*
 397                  * Give the other CPU some time to accept the IPI.
 398                  */
 399                 udelay(200);
 400                 /*
 401                  * Due to the Pentium erratum 3AP.
 402                  */
 403                 if (maxlvt > 3) {
 404                         apic_write(APIC_ESR, 0);
 405                 }
 406                 accept_status = (apic_read(APIC_ESR) & 0xEF);
 407                 if (send_status || accept_status)
 408                         break;
 409         }
 410         Dprintk("After Startup.\n");
 411
 412         if (send_status)
 413                 printk(KERN_ERR "APIC never delivered???\n");
 414         if (accept_status)
 415                 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
 416
 417         return (send_status | accept_status);
 418 }
 419
 420 struct create_idle {
 421         struct work_struct work;
 422         struct task_struct *idle;
 423         struct completion done;
 424         int cpu;
 425 };
 426
 427 static void __cpuinit do_fork_idle(struct work_struct *work)
 428 {
 429         struct create_idle *c_idle =
 430                 container_of(work, struct create_idle, work);
 431
 432         c_idle->idle = fork_idle(c_idle->cpu);
 433         complete(&c_idle->done);
 434 }
 435
 436 /*
 437  * Boot one CPU.
 438  */
 439 static int __cpuinit do_boot_cpu(int cpu, int apicid)
 440 {
 441         unsigned long boot_error;
 442         int timeout;
 443         unsigned long start_rip;
 444         struct create_idle c_idle = {
 445                 .cpu = cpu,
 446                 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
 447         };
 448         INIT_WORK(&c_idle.work, do_fork_idle);
 449
 450         /* allocate memory for gdts of secondary cpus. Hotplug is considered */
 451         if (!cpu_gdt_descr[cpu].address &&
 452                 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
 453                 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
 454                 return -1;
 455         }
 456
 457         /* Allocate node local memory for AP pdas */
 458         if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
 459                 struct x8664_pda *newpda, *pda;
 460                 int node = cpu_to_node(cpu);
 461                 pda = cpu_pda(cpu);
 462                 newpda = kmalloc_node(sizeof (struct x8664_pda), GFP_ATOMIC,
 463                                       node);
 464                 if (newpda) {
 465                         memcpy(newpda, pda, sizeof (struct x8664_pda));
 466                         cpu_pda(cpu) = newpda;
 467                 } else
 468                         printk(KERN_ERR
 469                 "Could not allocate node local PDA for CPU %d on node %d\n",
 470                                 cpu, node);
 471         }
 472
 473         alternatives_smp_switch(1);
 474
 475         c_idle.idle = get_idle_for_cpu(cpu);
 476
 477         if (c_idle.idle) {
 478                 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
 479                         (THREAD_SIZE +  task_stack_page(c_idle.idle))) - 1);
 480                 init_idle(c_idle.idle, cpu);
 481                 goto do_rest;
 482         }
 483
 484         /*
 485          * During cold boot process, keventd thread is not spun up yet.
 486          * When we do cpu hot-add, we create idle threads on the fly, we should
 487          * not acquire any attributes from the calling context. Hence the clean
 488          * way to create kernel_threads() is to do that from keventd().
 489          * We do the current_is_keventd() due to the fact that ACPI notifier
 490          * was also queuing to keventd() and when the caller is already running
 491          * in context of keventd(), we would end up with locking up the keventd
 492          * thread.
 493          */
 494         if (!keventd_up() || current_is_keventd())
 495                 c_idle.work.func(&c_idle.work);
 496         else {
 497                 schedule_work(&c_idle.work);
 498                 wait_for_completion(&c_idle.done);
 499         }
 500
 501         if (IS_ERR(c_idle.idle)) {
 502                 printk("failed fork for CPU %d\n", cpu);
 503                 return PTR_ERR(c_idle.idle);
 504         }
 505
 506         set_idle_for_cpu(cpu, c_idle.idle);
 507
 508 do_rest:
 509
 510         cpu_pda(cpu)->pcurrent = c_idle.idle;
 511
 512         start_rip = setup_trampoline();
 513
 514         init_rsp = c_idle.idle->thread.sp;
 515         load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
 516         initial_code = start_secondary;
 517         clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
 518
 519         printk(KERN_INFO "Booting processor %d/%d APIC 0x%x\n", cpu,
 520                 cpus_weight(cpu_present_map),
 521                 apicid);
 522
 523         /*
 524          * This grunge runs the startup process for
 525          * the targeted processor.
 526          */
 527
 528         atomic_set(&init_deasserted, 0);
 529
 530         Dprintk("Setting warm reset code and vector.\n");
 531
 532         CMOS_WRITE(0xa, 0xf);
 533         local_flush_tlb();
 534         Dprintk("1.\n");
 535         *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
 536         Dprintk("2.\n");
 537         *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
 538         Dprintk("3.\n");
 539
 540         /*
 541          * Be paranoid about clearing APIC errors.
 542          */
 543         apic_write(APIC_ESR, 0);
 544         apic_read(APIC_ESR);
 545
 546         /*
 547          * Status is now clean
 548          */
 549         boot_error = 0;
 550
 551         /*
 552          * Starting actual IPI sequence...
 553          */
 554         boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
 555
 556         if (!boot_error) {
 557                 /*
 558                  * allow APs to start initializing.
 559                  */
 560                 Dprintk("Before Callout %d.\n", cpu);
 561                 cpu_set(cpu, cpu_callout_map);
 562                 Dprintk("After Callout %d.\n", cpu);
 563
 564                 /*
 565                  * Wait 5s total for a response
 566                  */
 567                 for (timeout = 0; timeout < 50000; timeout++) {
 568                         if (cpu_isset(cpu, cpu_callin_map))
 569                                 break;  /* It has booted */
 570                         udelay(100);
 571                 }
 572
 573                 if (cpu_isset(cpu, cpu_callin_map)) {
 574                         /* number CPUs logically, starting from 1 (BSP is 0) */
 575                         Dprintk("CPU has booted.\n");
 576                 } else {
 577                         boot_error = 1;
 578                         if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
 579                                         == 0xA5)
 580                                 /* trampoline started but...? */
 581                                 printk("Stuck ??\n");
 582                         else
 583                                 /* trampoline code not run */
 584                                 printk("Not responding.\n");
 585 #ifdef APIC_DEBUG
 586                         inquire_remote_apic(apicid);
 587 #endif
 588                 }
 589         }
 590         if (boot_error) {
 591                 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
 592                 clear_bit(cpu, (unsigned long *)&cpu_initialized); /* was set by cpu_init() */
 593                 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
 594                 cpu_clear(cpu, cpu_present_map);
 595                 cpu_clear(cpu, cpu_possible_map);
 596                 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
 597                 return -EIO;
 598         }
 599
 600         return 0;
 601 }
 602
 603 cycles_t cacheflush_time;
 604 unsigned long cache_decay_ticks;
 605
 606 /*
 607  * Cleanup possible dangling ends...
 608  */
 609 static __cpuinit void smp_cleanup_boot(void)
 610 {
 611         /*
 612          * Paranoid:  Set warm reset code and vector here back
 613          * to default values.
 614          */
 615         CMOS_WRITE(0, 0xf);
 616
 617         /*
 618          * Reset trampoline flag
 619          */
 620         *((volatile int *) phys_to_virt(0x467)) = 0;
 621 }
 622
 623 /*
 624  * Fall back to non SMP mode after errors.
 625  *
 626  * RED-PEN audit/test this more. I bet there is more state messed up here.
 627  */
 628 static __init void disable_smp(void)
 629 {
 630         cpu_present_map = cpumask_of_cpu(0);
 631         cpu_possible_map = cpumask_of_cpu(0);
 632         if (smp_found_config)
 633                 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
 634         else
 635                 phys_cpu_present_map = physid_mask_of_physid(0);
 636         cpu_set(0, per_cpu(cpu_sibling_map, 0));
 637         cpu_set(0, per_cpu(cpu_core_map, 0));
 638 }
 639
 640 /*
 641  * Various sanity checks.
 642  */
 643 static int __init smp_sanity_check(unsigned max_cpus)
 644 {
 645         if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
 646                 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
 647                        hard_smp_processor_id());
 648                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 649         }
 650
 651         /*
 652          * If we couldn't find an SMP configuration at boot time,
 653          * get out of here now!
 654          */
 655         if (!smp_found_config) {
 656                 printk(KERN_NOTICE "SMP motherboard not detected.\n");
 657                 disable_smp();
 658                 if (APIC_init_uniprocessor())
 659                         printk(KERN_NOTICE "Local APIC not detected."
 660                                            " Using dummy APIC emulation.\n");
 661                 return -1;
 662         }
 663
 664         /*
 665          * Should not be necessary because the MP table should list the boot
 666          * CPU too, but we do it for the sake of robustness anyway.
 667          */
 668         if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
 669                 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
 670                                                                  boot_cpu_id);
 671                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 672         }
 673
 674         /*
 675          * If we couldn't find a local APIC, then get out of here now!
 676          */
 677         if (!cpu_has_apic) {
 678                 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
 679                         boot_cpu_id);
 680                 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
 681                 nr_ioapics = 0;
 682                 return -1;
 683         }
 684
 685         /*
 686          * If SMP should be disabled, then really disable it!
 687          */
 688         if (!max_cpus) {
 689                 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
 690                 nr_ioapics = 0;
 691                 return -1;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static void __init smp_cpu_index_default(void)
 698 {
 699         int i;
 700         struct cpuinfo_x86 *c;
 701
 702         for_each_cpu_mask(i, cpu_possible_map) {
 703                 c = &cpu_data(i);
 704                 /* mark all to hotplug */
 705                 c->cpu_index = NR_CPUS;
 706         }
 707 }
 708
 709 /*
 710  * Prepare for SMP bootup.  The MP table or ACPI has been read
 711  * earlier.  Just do some sanity checking here and enable APIC mode.
 712  */
 713 void __init native_smp_prepare_cpus(unsigned int max_cpus)
 714 {
 715         nmi_watchdog_default();
 716         smp_cpu_index_default();
 717         current_cpu_data = boot_cpu_data;
 718         current_thread_info()->cpu = 0;  /* needed? */
 719         set_cpu_sibling_map(0);
 720
 721         if (smp_sanity_check(max_cpus) < 0) {
 722                 printk(KERN_INFO "SMP disabled\n");
 723                 disable_smp();
 724                 return;
 725         }
 726
 727
 728         /*
 729          * Switch from PIC to APIC mode.
 730          */
 731         setup_local_APIC();
 732
 733         /*
 734          * Enable IO APIC before setting up error vector
 735          */
 736         if (!skip_ioapic_setup && nr_ioapics)
 737                 enable_IO_APIC();
 738         end_local_APIC_setup();
 739
 740         if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id) {
 741                 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
 742                       GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_id);
 743                 /* Or can we switch back to PIC here? */
 744         }
 745
 746         /*
 747          * Now start the IO-APICs
 748          */
 749         if (!skip_ioapic_setup && nr_ioapics)
 750                 setup_IO_APIC();
 751         else
 752                 nr_ioapics = 0;
 753
 754         /*
 755          * Set up local APIC timer on boot CPU.
 756          */
 757
 758         setup_boot_clock();
 759 }
 760
 761 /*
 762  * Early setup to make printk work.
 763  */
 764 void __init native_smp_prepare_boot_cpu(void)
 765 {
 766         int me = smp_processor_id();
 767         /* already set me in cpu_online_map in boot_cpu_init() */
 768         cpu_set(me, cpu_callout_map);
 769         per_cpu(cpu_state, me) = CPU_ONLINE;
 770 }
 771
 772 /*
 773  * Entry point to boot a CPU.
 774  */
 775 int __cpuinit native_cpu_up(unsigned int cpu)
 776 {
 777         int apicid = cpu_present_to_apicid(cpu);
 778         unsigned long flags;
 779         int err;
 780
 781         WARN_ON(irqs_disabled());
 782
 783         Dprintk("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
 784
 785         if (apicid == BAD_APICID || apicid == boot_cpu_id ||
 786             !physid_isset(apicid, phys_cpu_present_map)) {
 787                 printk("__cpu_up: bad cpu %d\n", cpu);
 788                 return -EINVAL;
 789         }
 790
 791         /*
 792          * Already booted CPU?
 793          */
 794         if (cpu_isset(cpu, cpu_callin_map)) {
 795                 Dprintk("do_boot_cpu %d Already started\n", cpu);
 796                 return -ENOSYS;
 797         }
 798
 799         /*
 800          * Save current MTRR state in case it was changed since early boot
 801          * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
 802          */
 803         mtrr_save_state();
 804
 805         per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
 806         /* Boot it! */
 807         err = do_boot_cpu(cpu, apicid);
 808         if (err < 0) {
 809                 Dprintk("do_boot_cpu failed %d\n", err);
 810                 return err;
 811         }
 812
 813         /* Unleash the CPU! */
 814         Dprintk("waiting for cpu %d\n", cpu);
 815
 816         /*
 817          * Make sure and check TSC sync:
 818          */
 819         local_irq_save(flags);
 820         check_tsc_sync_source(cpu);
 821         local_irq_restore(flags);
 822
 823         while (!cpu_isset(cpu, cpu_online_map))
 824                 cpu_relax();
 825         err = 0;
 826
 827         return err;
 828 }
 829
 830 /*
 831  * Finish the SMP boot.
 832  */
 833 void __init native_smp_cpus_done(unsigned int max_cpus)
 834 {
 835         smp_cleanup_boot();
 836         setup_ioapic_dest();
 837         check_nmi_watchdog();
 838 }