1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
18 #include <asm/hypervisor.h>
20 unsigned int cpu_khz
; /* TSC clocks / usec, not used here */
21 EXPORT_SYMBOL(cpu_khz
);
23 EXPORT_SYMBOL(tsc_khz
);
26 * TSC can be unstable due to cpufreq or due to unsynced TSCs
28 static int tsc_unstable
;
30 /* native_sched_clock() is called before tsc_init(), so
31 we must start with the TSC soft disabled to prevent
32 erroneous rdtsc usage on !cpu_has_tsc processors */
33 static int tsc_disabled
= -1;
35 static int tsc_clocksource_reliable
;
37 * Scheduler clock - returns current time in nanosec units.
39 u64
native_sched_clock(void)
44 * Fall back to jiffies if there's no TSC available:
45 * ( But note that we still use it if the TSC is marked
46 * unstable. We do this because unlike Time Of Day,
47 * the scheduler clock tolerates small errors and it's
48 * very important for it to be as fast as the platform
51 if (unlikely(tsc_disabled
)) {
52 /* No locking but a rare wrong value is not a big deal: */
53 return (jiffies_64
- INITIAL_JIFFIES
) * (1000000000 / HZ
);
56 /* read the Time Stamp Counter: */
59 /* return the value in ns */
60 return __cycles_2_ns(this_offset
);
63 /* We need to define a real function for sched_clock, to override the
64 weak default version */
65 #ifdef CONFIG_PARAVIRT
66 unsigned long long sched_clock(void)
68 return paravirt_sched_clock();
72 sched_clock(void) __attribute__((alias("native_sched_clock")));
75 int check_tsc_unstable(void)
79 EXPORT_SYMBOL_GPL(check_tsc_unstable
);
82 int __init
notsc_setup(char *str
)
84 printk(KERN_WARNING
"notsc: Kernel compiled with CONFIG_X86_TSC, "
85 "cannot disable TSC completely.\n");
91 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
94 int __init
notsc_setup(char *str
)
96 setup_clear_cpu_cap(X86_FEATURE_TSC
);
101 __setup("notsc", notsc_setup
);
103 static int __init
tsc_setup(char *str
)
105 if (!strcmp(str
, "reliable"))
106 tsc_clocksource_reliable
= 1;
110 __setup("tsc=", tsc_setup
);
112 #define MAX_RETRIES 5
113 #define SMI_TRESHOLD 50000
116 * Read TSC and the reference counters. Take care of SMI disturbance
118 static u64
tsc_read_refs(u64
*p
, int hpet
)
123 for (i
= 0; i
< MAX_RETRIES
; i
++) {
126 *p
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
128 *p
= acpi_pm_read_early();
130 if ((t2
- t1
) < SMI_TRESHOLD
)
137 * Calculate the TSC frequency from HPET reference
139 static unsigned long calc_hpet_ref(u64 deltatsc
, u64 hpet1
, u64 hpet2
)
144 hpet2
+= 0x100000000ULL
;
146 tmp
= ((u64
)hpet2
* hpet_readl(HPET_PERIOD
));
147 do_div(tmp
, 1000000);
148 do_div(deltatsc
, tmp
);
150 return (unsigned long) deltatsc
;
154 * Calculate the TSC frequency from PMTimer reference
156 static unsigned long calc_pmtimer_ref(u64 deltatsc
, u64 pm1
, u64 pm2
)
164 pm2
+= (u64
)ACPI_PM_OVRRUN
;
166 tmp
= pm2
* 1000000000LL;
167 do_div(tmp
, PMTMR_TICKS_PER_SEC
);
168 do_div(deltatsc
, tmp
);
170 return (unsigned long) deltatsc
;
174 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
175 #define CAL_PIT_LOOPS 1000
178 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
179 #define CAL2_PIT_LOOPS 5000
183 * Try to calibrate the TSC against the Programmable
184 * Interrupt Timer and return the frequency of the TSC
187 * Return ULONG_MAX on failure to calibrate.
189 static unsigned long pit_calibrate_tsc(u32 latch
, unsigned long ms
, int loopmin
)
191 u64 tsc
, t1
, t2
, delta
;
192 unsigned long tscmin
, tscmax
;
195 /* Set the Gate high, disable speaker */
196 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
199 * Setup CTC channel 2* for mode 0, (interrupt on terminal
200 * count mode), binary count. Set the latch register to 50ms
201 * (LSB then MSB) to begin countdown.
204 outb(latch
& 0xff, 0x42);
205 outb(latch
>> 8, 0x42);
207 tsc
= t1
= t2
= get_cycles();
212 while ((inb(0x61) & 0x20) == 0) {
216 if ((unsigned long) delta
< tscmin
)
217 tscmin
= (unsigned int) delta
;
218 if ((unsigned long) delta
> tscmax
)
219 tscmax
= (unsigned int) delta
;
226 * If we were not able to read the PIT more than loopmin
227 * times, then we have been hit by a massive SMI
229 * If the maximum is 10 times larger than the minimum,
230 * then we got hit by an SMI as well.
232 if (pitcnt
< loopmin
|| tscmax
> 10 * tscmin
)
235 /* Calculate the PIT value */
242 * This reads the current MSB of the PIT counter, and
243 * checks if we are running on sufficiently fast and
244 * non-virtualized hardware.
246 * Our expectations are:
248 * - the PIT is running at roughly 1.19MHz
250 * - each IO is going to take about 1us on real hardware,
251 * but we allow it to be much faster (by a factor of 10) or
252 * _slightly_ slower (ie we allow up to a 2us read+counter
253 * update - anything else implies a unacceptably slow CPU
254 * or PIT for the fast calibration to work.
256 * - with 256 PIT ticks to read the value, we have 214us to
257 * see the same MSB (and overhead like doing a single TSC
258 * read per MSB value etc).
260 * - We're doing 2 reads per loop (LSB, MSB), and we expect
261 * them each to take about a microsecond on real hardware.
262 * So we expect a count value of around 100. But we'll be
263 * generous, and accept anything over 50.
265 * - if the PIT is stuck, and we see *many* more reads, we
266 * return early (and the next caller of pit_expect_msb()
267 * then consider it a failure when they don't see the
268 * next expected value).
270 * These expectations mean that we know that we have seen the
271 * transition from one expected value to another with a fairly
272 * high accuracy, and we didn't miss any events. We can thus
273 * use the TSC value at the transitions to calculate a pretty
274 * good value for the TSC frequencty.
276 static inline int pit_expect_msb(unsigned char val
, u64
*tscp
, unsigned long *deltap
)
281 for (count
= 0; count
< 50000; count
++) {
284 if (inb(0x42) != val
)
288 *deltap
= get_cycles() - tsc
;
292 * We require _some_ success, but the quality control
293 * will be based on the error terms on the TSC values.
299 * How many MSB values do we want to see? We aim for
300 * a maximum error rate of 500ppm (in practice the
301 * real error is much smaller), but refuse to spend
302 * more than 25ms on it.
304 #define MAX_QUICK_PIT_MS 25
305 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
307 static unsigned long quick_pit_calibrate(void)
311 unsigned long d1
, d2
;
313 /* Set the Gate high, disable speaker */
314 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
317 * Counter 2, mode 0 (one-shot), binary count
319 * NOTE! Mode 2 decrements by two (and then the
320 * output is flipped each time, giving the same
321 * final output frequency as a decrement-by-one),
322 * so mode 0 is much better when looking at the
327 /* Start at 0xffff */
332 * The PIT starts counting at the next edge, so we
333 * need to delay for a microsecond. The easiest way
334 * to do that is to just read back the 16-bit counter
340 if (pit_expect_msb(0xff, &tsc
, &d1
)) {
341 for (i
= 1; i
<= MAX_QUICK_PIT_ITERATIONS
; i
++) {
342 if (!pit_expect_msb(0xff-i
, &delta
, &d2
))
346 * Iterate until the error is less than 500 ppm
349 if (d1
+d2
< delta
>> 11)
353 printk("Fast TSC calibration failed\n");
358 * Ok, if we get here, then we've seen the
359 * MSB of the PIT decrement 'i' times, and the
360 * error has shrunk to less than 500 ppm.
362 * As a result, we can depend on there not being
363 * any odd delays anywhere, and the TSC reads are
364 * reliable (within the error). We also adjust the
365 * delta to the middle of the error bars, just
366 * because it looks nicer.
368 * kHz = ticks / time-in-seconds / 1000;
369 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
370 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
372 delta
+= (long)(d2
- d1
)/2;
373 delta
*= PIT_TICK_RATE
;
374 do_div(delta
, i
*256*1000);
375 printk("Fast TSC calibration using PIT\n");
380 * native_calibrate_tsc - calibrate the tsc on boot
382 unsigned long native_calibrate_tsc(void)
384 u64 tsc1
, tsc2
, delta
, ref1
, ref2
;
385 unsigned long tsc_pit_min
= ULONG_MAX
, tsc_ref_min
= ULONG_MAX
;
386 unsigned long flags
, latch
, ms
, fast_calibrate
, tsc_khz
;
387 int hpet
= is_hpet_enabled(), i
, loopmin
;
389 tsc_khz
= get_hypervisor_tsc_freq();
391 printk(KERN_INFO
"TSC: Frequency read from the hypervisor\n");
395 local_irq_save(flags
);
396 fast_calibrate
= quick_pit_calibrate();
397 local_irq_restore(flags
);
399 return fast_calibrate
;
402 * Run 5 calibration loops to get the lowest frequency value
403 * (the best estimate). We use two different calibration modes
406 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
407 * load a timeout of 50ms. We read the time right after we
408 * started the timer and wait until the PIT count down reaches
409 * zero. In each wait loop iteration we read the TSC and check
410 * the delta to the previous read. We keep track of the min
411 * and max values of that delta. The delta is mostly defined
412 * by the IO time of the PIT access, so we can detect when a
413 * SMI/SMM disturbance happend between the two reads. If the
414 * maximum time is significantly larger than the minimum time,
415 * then we discard the result and have another try.
417 * 2) Reference counter. If available we use the HPET or the
418 * PMTIMER as a reference to check the sanity of that value.
419 * We use separate TSC readouts and check inside of the
420 * reference read for a SMI/SMM disturbance. We dicard
421 * disturbed values here as well. We do that around the PIT
422 * calibration delay loop as we have to wait for a certain
423 * amount of time anyway.
426 /* Preset PIT loop values */
429 loopmin
= CAL_PIT_LOOPS
;
431 for (i
= 0; i
< 3; i
++) {
432 unsigned long tsc_pit_khz
;
435 * Read the start value and the reference count of
436 * hpet/pmtimer when available. Then do the PIT
437 * calibration, which will take at least 50ms, and
438 * read the end value.
440 local_irq_save(flags
);
441 tsc1
= tsc_read_refs(&ref1
, hpet
);
442 tsc_pit_khz
= pit_calibrate_tsc(latch
, ms
, loopmin
);
443 tsc2
= tsc_read_refs(&ref2
, hpet
);
444 local_irq_restore(flags
);
446 /* Pick the lowest PIT TSC calibration so far */
447 tsc_pit_min
= min(tsc_pit_min
, tsc_pit_khz
);
449 /* hpet or pmtimer available ? */
450 if (!hpet
&& !ref1
&& !ref2
)
453 /* Check, whether the sampling was disturbed by an SMI */
454 if (tsc1
== ULLONG_MAX
|| tsc2
== ULLONG_MAX
)
457 tsc2
= (tsc2
- tsc1
) * 1000000LL;
459 tsc2
= calc_hpet_ref(tsc2
, ref1
, ref2
);
461 tsc2
= calc_pmtimer_ref(tsc2
, ref1
, ref2
);
463 tsc_ref_min
= min(tsc_ref_min
, (unsigned long) tsc2
);
465 /* Check the reference deviation */
466 delta
= ((u64
) tsc_pit_min
) * 100;
467 do_div(delta
, tsc_ref_min
);
470 * If both calibration results are inside a 10% window
471 * then we can be sure, that the calibration
472 * succeeded. We break out of the loop right away. We
473 * use the reference value, as it is more precise.
475 if (delta
>= 90 && delta
<= 110) {
477 "TSC: PIT calibration matches %s. %d loops\n",
478 hpet
? "HPET" : "PMTIMER", i
+ 1);
483 * Check whether PIT failed more than once. This
484 * happens in virtualized environments. We need to
485 * give the virtual PC a slightly longer timeframe for
486 * the HPET/PMTIMER to make the result precise.
488 if (i
== 1 && tsc_pit_min
== ULONG_MAX
) {
491 loopmin
= CAL2_PIT_LOOPS
;
496 * Now check the results.
498 if (tsc_pit_min
== ULONG_MAX
) {
499 /* PIT gave no useful value */
500 printk(KERN_WARNING
"TSC: Unable to calibrate against PIT\n");
502 /* We don't have an alternative source, disable TSC */
503 if (!hpet
&& !ref1
&& !ref2
) {
504 printk("TSC: No reference (HPET/PMTIMER) available\n");
508 /* The alternative source failed as well, disable TSC */
509 if (tsc_ref_min
== ULONG_MAX
) {
510 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration "
515 /* Use the alternative source */
516 printk(KERN_INFO
"TSC: using %s reference calibration\n",
517 hpet
? "HPET" : "PMTIMER");
522 /* We don't have an alternative source, use the PIT calibration value */
523 if (!hpet
&& !ref1
&& !ref2
) {
524 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
528 /* The alternative source failed, use the PIT calibration value */
529 if (tsc_ref_min
== ULONG_MAX
) {
530 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration failed. "
531 "Using PIT calibration\n");
536 * The calibration values differ too much. In doubt, we use
537 * the PIT value as we know that there are PMTIMERs around
538 * running at double speed. At least we let the user know:
540 printk(KERN_WARNING
"TSC: PIT calibration deviates from %s: %lu %lu.\n",
541 hpet
? "HPET" : "PMTIMER", tsc_pit_min
, tsc_ref_min
);
542 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
547 /* Only called from the Powernow K7 cpu freq driver */
548 int recalibrate_cpu_khz(void)
551 unsigned long cpu_khz_old
= cpu_khz
;
554 tsc_khz
= calibrate_tsc();
556 cpu_data(0).loops_per_jiffy
=
557 cpufreq_scale(cpu_data(0).loops_per_jiffy
,
558 cpu_khz_old
, cpu_khz
);
567 EXPORT_SYMBOL(recalibrate_cpu_khz
);
569 #endif /* CONFIG_X86_32 */
571 /* Accelerators for sched_clock()
572 * convert from cycles(64bits) => nanoseconds (64bits)
574 * ns = cycles / (freq / ns_per_sec)
575 * ns = cycles * (ns_per_sec / freq)
576 * ns = cycles * (10^9 / (cpu_khz * 10^3))
577 * ns = cycles * (10^6 / cpu_khz)
579 * Then we use scaling math (suggested by george@mvista.com) to get:
580 * ns = cycles * (10^6 * SC / cpu_khz) / SC
581 * ns = cycles * cyc2ns_scale / SC
583 * And since SC is a constant power of two, we can convert the div
586 * We can use khz divisor instead of mhz to keep a better precision, since
587 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
588 * (mathieu.desnoyers@polymtl.ca)
590 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
593 DEFINE_PER_CPU(unsigned long, cyc2ns
);
595 static void set_cyc2ns_scale(unsigned long cpu_khz
, int cpu
)
597 unsigned long long tsc_now
, ns_now
;
598 unsigned long flags
, *scale
;
600 local_irq_save(flags
);
601 sched_clock_idle_sleep_event();
603 scale
= &per_cpu(cyc2ns
, cpu
);
606 ns_now
= __cycles_2_ns(tsc_now
);
609 *scale
= (NSEC_PER_MSEC
<< CYC2NS_SCALE_FACTOR
)/cpu_khz
;
611 sched_clock_idle_wakeup_event(0);
612 local_irq_restore(flags
);
615 #ifdef CONFIG_CPU_FREQ
617 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
620 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
621 * not that important because current Opteron setups do not support
622 * scaling on SMP anyroads.
624 * Should fix up last_tsc too. Currently gettimeofday in the
625 * first tick after the change will be slightly wrong.
628 static unsigned int ref_freq
;
629 static unsigned long loops_per_jiffy_ref
;
630 static unsigned long tsc_khz_ref
;
632 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
635 struct cpufreq_freqs
*freq
= data
;
636 unsigned long *lpj
, dummy
;
638 if (cpu_has(&cpu_data(freq
->cpu
), X86_FEATURE_CONSTANT_TSC
))
642 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
644 lpj
= &cpu_data(freq
->cpu
).loops_per_jiffy
;
646 lpj
= &boot_cpu_data
.loops_per_jiffy
;
650 ref_freq
= freq
->old
;
651 loops_per_jiffy_ref
= *lpj
;
652 tsc_khz_ref
= tsc_khz
;
654 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
655 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new) ||
656 (val
== CPUFREQ_RESUMECHANGE
)) {
657 *lpj
= cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
659 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
660 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
661 mark_tsc_unstable("cpufreq changes");
664 set_cyc2ns_scale(tsc_khz
, freq
->cpu
);
669 static struct notifier_block time_cpufreq_notifier_block
= {
670 .notifier_call
= time_cpufreq_notifier
673 static int __init
cpufreq_tsc(void)
677 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
679 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
680 CPUFREQ_TRANSITION_NOTIFIER
);
684 core_initcall(cpufreq_tsc
);
686 #endif /* CONFIG_CPU_FREQ */
688 /* clocksource code */
690 static struct clocksource clocksource_tsc
;
693 * We compare the TSC to the cycle_last value in the clocksource
694 * structure to avoid a nasty time-warp. This can be observed in a
695 * very small window right after one CPU updated cycle_last under
696 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
697 * is smaller than the cycle_last reference value due to a TSC which
698 * is slighty behind. This delta is nowhere else observable, but in
699 * that case it results in a forward time jump in the range of hours
700 * due to the unsigned delta calculation of the time keeping core
701 * code, which is necessary to support wrapping clocksources like pm
704 static cycle_t
read_tsc(void)
706 cycle_t ret
= (cycle_t
)get_cycles();
708 return ret
>= clocksource_tsc
.cycle_last
?
709 ret
: clocksource_tsc
.cycle_last
;
713 static cycle_t __vsyscall_fn
vread_tsc(void)
715 cycle_t ret
= (cycle_t
)vget_cycles();
717 return ret
>= __vsyscall_gtod_data
.clock
.cycle_last
?
718 ret
: __vsyscall_gtod_data
.clock
.cycle_last
;
722 static struct clocksource clocksource_tsc
= {
726 .mask
= CLOCKSOURCE_MASK(64),
728 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
729 CLOCK_SOURCE_MUST_VERIFY
,
735 void mark_tsc_unstable(char *reason
)
739 printk("Marking TSC unstable due to %s\n", reason
);
740 /* Change only the rating, when not registered */
741 if (clocksource_tsc
.mult
)
742 clocksource_change_rating(&clocksource_tsc
, 0);
744 clocksource_tsc
.rating
= 0;
748 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
750 static int __init
dmi_mark_tsc_unstable(const struct dmi_system_id
*d
)
752 printk(KERN_NOTICE
"%s detected: marking TSC unstable.\n",
758 /* List of systems that have known TSC problems */
759 static struct dmi_system_id __initdata bad_tsc_dmi_table
[] = {
761 .callback
= dmi_mark_tsc_unstable
,
762 .ident
= "IBM Thinkpad 380XD",
764 DMI_MATCH(DMI_BOARD_VENDOR
, "IBM"),
765 DMI_MATCH(DMI_BOARD_NAME
, "2635FA0"),
771 static void __init
check_system_tsc_reliable(void)
773 #ifdef CONFIG_MGEODE_LX
774 /* RTSC counts during suspend */
775 #define RTSC_SUSP 0x100
776 unsigned long res_low
, res_high
;
778 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0
, &res_low
, &res_high
);
779 /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */
780 if (res_low
& RTSC_SUSP
)
781 tsc_clocksource_reliable
= 1;
783 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE
))
784 tsc_clocksource_reliable
= 1;
788 * Make an educated guess if the TSC is trustworthy and synchronized
791 __cpuinit
int unsynchronized_tsc(void)
793 if (!cpu_has_tsc
|| tsc_unstable
)
796 #ifdef CONFIG_X86_SMP
797 if (apic_is_clustered_box())
801 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
804 * Intel systems are normally all synchronized.
805 * Exceptions must mark TSC as unstable:
807 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
) {
808 /* assume multi socket systems are not synchronized: */
809 if (num_possible_cpus() > 1)
816 static void __init
init_tsc_clocksource(void)
818 clocksource_tsc
.mult
= clocksource_khz2mult(tsc_khz
,
819 clocksource_tsc
.shift
);
820 if (tsc_clocksource_reliable
)
821 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_MUST_VERIFY
;
822 /* lower the rating if we already know its unstable: */
823 if (check_tsc_unstable()) {
824 clocksource_tsc
.rating
= 0;
825 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_IS_CONTINUOUS
;
827 clocksource_register(&clocksource_tsc
);
830 void __init
tsc_init(void)
838 tsc_khz
= calibrate_tsc();
842 mark_tsc_unstable("could not calculate TSC khz");
847 if (cpu_has(&boot_cpu_data
, X86_FEATURE_CONSTANT_TSC
) &&
848 (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
))
849 cpu_khz
= calibrate_cpu();
852 printk("Detected %lu.%03lu MHz processor.\n",
853 (unsigned long)cpu_khz
/ 1000,
854 (unsigned long)cpu_khz
% 1000);
857 * Secondary CPUs do not run through tsc_init(), so set up
858 * all the scale factors for all CPUs, assuming the same
859 * speed as the bootup CPU. (cpufreq notifiers will fix this
860 * up if their speed diverges)
862 for_each_possible_cpu(cpu
)
863 set_cyc2ns_scale(cpu_khz
, cpu
);
865 if (tsc_disabled
> 0)
868 /* now allow native_sched_clock() to use rdtsc */
871 lpj
= ((u64
)tsc_khz
* 1000);
876 /* Check and install the TSC clocksource */
877 dmi_check_system(bad_tsc_dmi_table
);
879 if (unsynchronized_tsc())
880 mark_tsc_unstable("TSCs unsynchronized");
882 check_system_tsc_reliable();
883 init_tsc_clocksource();