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[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27 #include <linux/stringify.h>
28
29 #include "x86.h"
30 #include "tss.h"
31
32 /*
33 * Operand types
34 */
35 #define OpNone 0ull
36 #define OpImplicit 1ull /* No generic decode */
37 #define OpReg 2ull /* Register */
38 #define OpMem 3ull /* Memory */
39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
40 #define OpDI 5ull /* ES:DI/EDI/RDI */
41 #define OpMem64 6ull /* Memory, 64-bit */
42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
43 #define OpDX 8ull /* DX register */
44 #define OpCL 9ull /* CL register (for shifts) */
45 #define OpImmByte 10ull /* 8-bit sign extended immediate */
46 #define OpOne 11ull /* Implied 1 */
47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
48 #define OpMem16 13ull /* Memory operand (16-bit). */
49 #define OpMem32 14ull /* Memory operand (32-bit). */
50 #define OpImmU 15ull /* Immediate operand, zero extended */
51 #define OpSI 16ull /* SI/ESI/RSI */
52 #define OpImmFAddr 17ull /* Immediate far address */
53 #define OpMemFAddr 18ull /* Far address in memory */
54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
55 #define OpES 20ull /* ES */
56 #define OpCS 21ull /* CS */
57 #define OpSS 22ull /* SS */
58 #define OpDS 23ull /* DS */
59 #define OpFS 24ull /* FS */
60 #define OpGS 25ull /* GS */
61 #define OpMem8 26ull /* 8-bit zero extended memory operand */
62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
64 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
65 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
66
67 #define OpBits 5 /* Width of operand field */
68 #define OpMask ((1ull << OpBits) - 1)
69
70 /*
71 * Opcode effective-address decode tables.
72 * Note that we only emulate instructions that have at least one memory
73 * operand (excluding implicit stack references). We assume that stack
74 * references and instruction fetches will never occur in special memory
75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
76 * not be handled.
77 */
78
79 /* Operand sizes: 8-bit operands or specified/overridden size. */
80 #define ByteOp (1<<0) /* 8-bit operands. */
81 /* Destination operand type. */
82 #define DstShift 1
83 #define ImplicitOps (OpImplicit << DstShift)
84 #define DstReg (OpReg << DstShift)
85 #define DstMem (OpMem << DstShift)
86 #define DstAcc (OpAcc << DstShift)
87 #define DstDI (OpDI << DstShift)
88 #define DstMem64 (OpMem64 << DstShift)
89 #define DstImmUByte (OpImmUByte << DstShift)
90 #define DstDX (OpDX << DstShift)
91 #define DstAccLo (OpAccLo << DstShift)
92 #define DstMask (OpMask << DstShift)
93 /* Source operand type. */
94 #define SrcShift 6
95 #define SrcNone (OpNone << SrcShift)
96 #define SrcReg (OpReg << SrcShift)
97 #define SrcMem (OpMem << SrcShift)
98 #define SrcMem16 (OpMem16 << SrcShift)
99 #define SrcMem32 (OpMem32 << SrcShift)
100 #define SrcImm (OpImm << SrcShift)
101 #define SrcImmByte (OpImmByte << SrcShift)
102 #define SrcOne (OpOne << SrcShift)
103 #define SrcImmUByte (OpImmUByte << SrcShift)
104 #define SrcImmU (OpImmU << SrcShift)
105 #define SrcSI (OpSI << SrcShift)
106 #define SrcXLat (OpXLat << SrcShift)
107 #define SrcImmFAddr (OpImmFAddr << SrcShift)
108 #define SrcMemFAddr (OpMemFAddr << SrcShift)
109 #define SrcAcc (OpAcc << SrcShift)
110 #define SrcImmU16 (OpImmU16 << SrcShift)
111 #define SrcImm64 (OpImm64 << SrcShift)
112 #define SrcDX (OpDX << SrcShift)
113 #define SrcMem8 (OpMem8 << SrcShift)
114 #define SrcAccHi (OpAccHi << SrcShift)
115 #define SrcMask (OpMask << SrcShift)
116 #define BitOp (1<<11)
117 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
118 #define String (1<<13) /* String instruction (rep capable) */
119 #define Stack (1<<14) /* Stack instruction (push/pop) */
120 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
121 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
122 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
123 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
124 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
125 #define Escape (5<<15) /* Escape to coprocessor instruction */
126 #define Sse (1<<18) /* SSE Vector instruction */
127 /* Generic ModRM decode. */
128 #define ModRM (1<<19)
129 /* Destination is only written; never read. */
130 #define Mov (1<<20)
131 /* Misc flags */
132 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
133 #define VendorSpecific (1<<22) /* Vendor specific instruction */
134 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
135 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
136 #define Undefined (1<<25) /* No Such Instruction */
137 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
138 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
139 #define No64 (1<<28)
140 #define PageTable (1 << 29) /* instruction used to write page table */
141 #define NotImpl (1 << 30) /* instruction is not implemented */
142 /* Source 2 operand type */
143 #define Src2Shift (31)
144 #define Src2None (OpNone << Src2Shift)
145 #define Src2Mem (OpMem << Src2Shift)
146 #define Src2CL (OpCL << Src2Shift)
147 #define Src2ImmByte (OpImmByte << Src2Shift)
148 #define Src2One (OpOne << Src2Shift)
149 #define Src2Imm (OpImm << Src2Shift)
150 #define Src2ES (OpES << Src2Shift)
151 #define Src2CS (OpCS << Src2Shift)
152 #define Src2SS (OpSS << Src2Shift)
153 #define Src2DS (OpDS << Src2Shift)
154 #define Src2FS (OpFS << Src2Shift)
155 #define Src2GS (OpGS << Src2Shift)
156 #define Src2Mask (OpMask << Src2Shift)
157 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
158 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
159 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
160 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
161 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
162 #define NoWrite ((u64)1 << 45) /* No writeback */
163 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
164
165 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
166
167 #define X2(x...) x, x
168 #define X3(x...) X2(x), x
169 #define X4(x...) X2(x), X2(x)
170 #define X5(x...) X4(x), x
171 #define X6(x...) X4(x), X2(x)
172 #define X7(x...) X4(x), X3(x)
173 #define X8(x...) X4(x), X4(x)
174 #define X16(x...) X8(x), X8(x)
175
176 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
177 #define FASTOP_SIZE 8
178
179 /*
180 * fastop functions have a special calling convention:
181 *
182 * dst: rax (in/out)
183 * src: rdx (in/out)
184 * src2: rcx (in)
185 * flags: rflags (in/out)
186 * ex: rsi (in:fastop pointer, out:zero if exception)
187 *
188 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
189 * different operand sizes can be reached by calculation, rather than a jump
190 * table (which would be bigger than the code).
191 *
192 * fastop functions are declared as taking a never-defined fastop parameter,
193 * so they can't be called from C directly.
194 */
195
196 struct fastop;
197
198 struct opcode {
199 u64 flags : 56;
200 u64 intercept : 8;
201 union {
202 int (*execute)(struct x86_emulate_ctxt *ctxt);
203 const struct opcode *group;
204 const struct group_dual *gdual;
205 const struct gprefix *gprefix;
206 const struct escape *esc;
207 void (*fastop)(struct fastop *fake);
208 } u;
209 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
210 };
211
212 struct group_dual {
213 struct opcode mod012[8];
214 struct opcode mod3[8];
215 };
216
217 struct gprefix {
218 struct opcode pfx_no;
219 struct opcode pfx_66;
220 struct opcode pfx_f2;
221 struct opcode pfx_f3;
222 };
223
224 struct escape {
225 struct opcode op[8];
226 struct opcode high[64];
227 };
228
229 /* EFLAGS bit definitions. */
230 #define EFLG_ID (1<<21)
231 #define EFLG_VIP (1<<20)
232 #define EFLG_VIF (1<<19)
233 #define EFLG_AC (1<<18)
234 #define EFLG_VM (1<<17)
235 #define EFLG_RF (1<<16)
236 #define EFLG_IOPL (3<<12)
237 #define EFLG_NT (1<<14)
238 #define EFLG_OF (1<<11)
239 #define EFLG_DF (1<<10)
240 #define EFLG_IF (1<<9)
241 #define EFLG_TF (1<<8)
242 #define EFLG_SF (1<<7)
243 #define EFLG_ZF (1<<6)
244 #define EFLG_AF (1<<4)
245 #define EFLG_PF (1<<2)
246 #define EFLG_CF (1<<0)
247
248 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
249 #define EFLG_RESERVED_ONE_MASK 2
250
251 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
252 {
253 if (!(ctxt->regs_valid & (1 << nr))) {
254 ctxt->regs_valid |= 1 << nr;
255 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
256 }
257 return ctxt->_regs[nr];
258 }
259
260 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
261 {
262 ctxt->regs_valid |= 1 << nr;
263 ctxt->regs_dirty |= 1 << nr;
264 return &ctxt->_regs[nr];
265 }
266
267 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
268 {
269 reg_read(ctxt, nr);
270 return reg_write(ctxt, nr);
271 }
272
273 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
274 {
275 unsigned reg;
276
277 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
278 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
279 }
280
281 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
282 {
283 ctxt->regs_dirty = 0;
284 ctxt->regs_valid = 0;
285 }
286
287 /*
288 * Instruction emulation:
289 * Most instructions are emulated directly via a fragment of inline assembly
290 * code. This allows us to save/restore EFLAGS and thus very easily pick up
291 * any modified flags.
292 */
293
294 #if defined(CONFIG_X86_64)
295 #define _LO32 "k" /* force 32-bit operand */
296 #define _STK "%%rsp" /* stack pointer */
297 #elif defined(__i386__)
298 #define _LO32 "" /* force 32-bit operand */
299 #define _STK "%%esp" /* stack pointer */
300 #endif
301
302 /*
303 * These EFLAGS bits are restored from saved value during emulation, and
304 * any changes are written back to the saved value after emulation.
305 */
306 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
307
308 /* Before executing instruction: restore necessary bits in EFLAGS. */
309 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
310 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
311 "movl %"_sav",%"_LO32 _tmp"; " \
312 "push %"_tmp"; " \
313 "push %"_tmp"; " \
314 "movl %"_msk",%"_LO32 _tmp"; " \
315 "andl %"_LO32 _tmp",("_STK"); " \
316 "pushf; " \
317 "notl %"_LO32 _tmp"; " \
318 "andl %"_LO32 _tmp",("_STK"); " \
319 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
320 "pop %"_tmp"; " \
321 "orl %"_LO32 _tmp",("_STK"); " \
322 "popf; " \
323 "pop %"_sav"; "
324
325 /* After executing instruction: write-back necessary bits in EFLAGS. */
326 #define _POST_EFLAGS(_sav, _msk, _tmp) \
327 /* _sav |= EFLAGS & _msk; */ \
328 "pushf; " \
329 "pop %"_tmp"; " \
330 "andl %"_msk",%"_LO32 _tmp"; " \
331 "orl %"_LO32 _tmp",%"_sav"; "
332
333 #ifdef CONFIG_X86_64
334 #define ON64(x) x
335 #else
336 #define ON64(x)
337 #endif
338
339 #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \
340 do { \
341 __asm__ __volatile__ ( \
342 _PRE_EFLAGS("0", "4", "2") \
343 _op _suffix " %"_x"3,%1; " \
344 _POST_EFLAGS("0", "4", "2") \
345 : "=m" ((ctxt)->eflags), \
346 "+q" (*(_dsttype*)&(ctxt)->dst.val), \
347 "=&r" (_tmp) \
348 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \
349 } while (0)
350
351
352 /* Raw emulation: instruction has two explicit operands. */
353 #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \
354 do { \
355 unsigned long _tmp; \
356 \
357 switch ((ctxt)->dst.bytes) { \
358 case 2: \
359 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \
360 break; \
361 case 4: \
362 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \
363 break; \
364 case 8: \
365 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
366 break; \
367 } \
368 } while (0)
369
370 #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
371 do { \
372 unsigned long _tmp; \
373 switch ((ctxt)->dst.bytes) { \
374 case 1: \
375 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \
376 break; \
377 default: \
378 __emulate_2op_nobyte(ctxt, _op, \
379 _wx, _wy, _lx, _ly, _qx, _qy); \
380 break; \
381 } \
382 } while (0)
383
384 /* Source operand is byte-sized and may be restricted to just %cl. */
385 #define emulate_2op_SrcB(ctxt, _op) \
386 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
387
388 /* Source operand is byte, word, long or quad sized. */
389 #define emulate_2op_SrcV(ctxt, _op) \
390 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
391
392 /* Source operand is word, long or quad sized. */
393 #define emulate_2op_SrcV_nobyte(ctxt, _op) \
394 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
395
396 /* Instruction has three operands and one operand is stored in ECX register */
397 #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \
398 do { \
399 unsigned long _tmp; \
400 _type _clv = (ctxt)->src2.val; \
401 _type _srcv = (ctxt)->src.val; \
402 _type _dstv = (ctxt)->dst.val; \
403 \
404 __asm__ __volatile__ ( \
405 _PRE_EFLAGS("0", "5", "2") \
406 _op _suffix " %4,%1 \n" \
407 _POST_EFLAGS("0", "5", "2") \
408 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
409 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
410 ); \
411 \
412 (ctxt)->src2.val = (unsigned long) _clv; \
413 (ctxt)->src2.val = (unsigned long) _srcv; \
414 (ctxt)->dst.val = (unsigned long) _dstv; \
415 } while (0)
416
417 #define emulate_2op_cl(ctxt, _op) \
418 do { \
419 switch ((ctxt)->dst.bytes) { \
420 case 2: \
421 __emulate_2op_cl(ctxt, _op, "w", u16); \
422 break; \
423 case 4: \
424 __emulate_2op_cl(ctxt, _op, "l", u32); \
425 break; \
426 case 8: \
427 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \
428 break; \
429 } \
430 } while (0)
431
432 #define __emulate_1op(ctxt, _op, _suffix) \
433 do { \
434 unsigned long _tmp; \
435 \
436 __asm__ __volatile__ ( \
437 _PRE_EFLAGS("0", "3", "2") \
438 _op _suffix " %1; " \
439 _POST_EFLAGS("0", "3", "2") \
440 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
441 "=&r" (_tmp) \
442 : "i" (EFLAGS_MASK)); \
443 } while (0)
444
445 /* Instruction has only one explicit operand (no source operand). */
446 #define emulate_1op(ctxt, _op) \
447 do { \
448 switch ((ctxt)->dst.bytes) { \
449 case 1: __emulate_1op(ctxt, _op, "b"); break; \
450 case 2: __emulate_1op(ctxt, _op, "w"); break; \
451 case 4: __emulate_1op(ctxt, _op, "l"); break; \
452 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \
453 } \
454 } while (0)
455
456 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
457
458 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
459 #define FOP_RET "ret \n\t"
460
461 #define FOP_START(op) \
462 extern void em_##op(struct fastop *fake); \
463 asm(".pushsection .text, \"ax\" \n\t" \
464 ".global em_" #op " \n\t" \
465 FOP_ALIGN \
466 "em_" #op ": \n\t"
467
468 #define FOP_END \
469 ".popsection")
470
471 #define FOPNOP() FOP_ALIGN FOP_RET
472
473 #define FOP1E(op, dst) \
474 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
475
476 #define FOP1EEX(op, dst) \
477 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
478
479 #define FASTOP1(op) \
480 FOP_START(op) \
481 FOP1E(op##b, al) \
482 FOP1E(op##w, ax) \
483 FOP1E(op##l, eax) \
484 ON64(FOP1E(op##q, rax)) \
485 FOP_END
486
487 /* 1-operand, using src2 (for MUL/DIV r/m) */
488 #define FASTOP1SRC2(op, name) \
489 FOP_START(name) \
490 FOP1E(op, cl) \
491 FOP1E(op, cx) \
492 FOP1E(op, ecx) \
493 ON64(FOP1E(op, rcx)) \
494 FOP_END
495
496 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
497 #define FASTOP1SRC2EX(op, name) \
498 FOP_START(name) \
499 FOP1EEX(op, cl) \
500 FOP1EEX(op, cx) \
501 FOP1EEX(op, ecx) \
502 ON64(FOP1EEX(op, rcx)) \
503 FOP_END
504
505 #define FOP2E(op, dst, src) \
506 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
507
508 #define FASTOP2(op) \
509 FOP_START(op) \
510 FOP2E(op##b, al, dl) \
511 FOP2E(op##w, ax, dx) \
512 FOP2E(op##l, eax, edx) \
513 ON64(FOP2E(op##q, rax, rdx)) \
514 FOP_END
515
516 /* 2 operand, word only */
517 #define FASTOP2W(op) \
518 FOP_START(op) \
519 FOPNOP() \
520 FOP2E(op##w, ax, dx) \
521 FOP2E(op##l, eax, edx) \
522 ON64(FOP2E(op##q, rax, rdx)) \
523 FOP_END
524
525 /* 2 operand, src is CL */
526 #define FASTOP2CL(op) \
527 FOP_START(op) \
528 FOP2E(op##b, al, cl) \
529 FOP2E(op##w, ax, cl) \
530 FOP2E(op##l, eax, cl) \
531 ON64(FOP2E(op##q, rax, cl)) \
532 FOP_END
533
534 #define FOP3E(op, dst, src, src2) \
535 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
536
537 /* 3-operand, word-only, src2=cl */
538 #define FASTOP3WCL(op) \
539 FOP_START(op) \
540 FOPNOP() \
541 FOP3E(op##w, ax, dx, cl) \
542 FOP3E(op##l, eax, edx, cl) \
543 ON64(FOP3E(op##q, rax, rdx, cl)) \
544 FOP_END
545
546 /* Special case for SETcc - 1 instruction per cc */
547 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
548
549 asm(".global kvm_fastop_exception \n"
550 "kvm_fastop_exception: xor %esi, %esi; ret");
551
552 FOP_START(setcc)
553 FOP_SETCC(seto)
554 FOP_SETCC(setno)
555 FOP_SETCC(setc)
556 FOP_SETCC(setnc)
557 FOP_SETCC(setz)
558 FOP_SETCC(setnz)
559 FOP_SETCC(setbe)
560 FOP_SETCC(setnbe)
561 FOP_SETCC(sets)
562 FOP_SETCC(setns)
563 FOP_SETCC(setp)
564 FOP_SETCC(setnp)
565 FOP_SETCC(setl)
566 FOP_SETCC(setnl)
567 FOP_SETCC(setle)
568 FOP_SETCC(setnle)
569 FOP_END;
570
571 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
572 FOP_END;
573
574 #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
575 do { \
576 unsigned long _tmp; \
577 ulong *rax = &ctxt->dst.val; \
578 ulong *rdx = &ctxt->src.val; \
579 \
580 __asm__ __volatile__ ( \
581 _PRE_EFLAGS("0", "5", "1") \
582 "1: \n\t" \
583 _op _suffix " %6; " \
584 "2: \n\t" \
585 _POST_EFLAGS("0", "5", "1") \
586 ".pushsection .fixup,\"ax\" \n\t" \
587 "3: movb $1, %4 \n\t" \
588 "jmp 2b \n\t" \
589 ".popsection \n\t" \
590 _ASM_EXTABLE(1b, 3b) \
591 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
592 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
593 : "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
594 } while (0)
595
596 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
597 #define emulate_1op_rax_rdx(ctxt, _op, _ex) \
598 do { \
599 switch((ctxt)->src.bytes) { \
600 case 1: \
601 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \
602 break; \
603 case 2: \
604 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \
605 break; \
606 case 4: \
607 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \
608 break; \
609 case 8: ON64( \
610 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \
611 break; \
612 } \
613 } while (0)
614
615 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
616 enum x86_intercept intercept,
617 enum x86_intercept_stage stage)
618 {
619 struct x86_instruction_info info = {
620 .intercept = intercept,
621 .rep_prefix = ctxt->rep_prefix,
622 .modrm_mod = ctxt->modrm_mod,
623 .modrm_reg = ctxt->modrm_reg,
624 .modrm_rm = ctxt->modrm_rm,
625 .src_val = ctxt->src.val64,
626 .src_bytes = ctxt->src.bytes,
627 .dst_bytes = ctxt->dst.bytes,
628 .ad_bytes = ctxt->ad_bytes,
629 .next_rip = ctxt->eip,
630 };
631
632 return ctxt->ops->intercept(ctxt, &info, stage);
633 }
634
635 static void assign_masked(ulong *dest, ulong src, ulong mask)
636 {
637 *dest = (*dest & ~mask) | (src & mask);
638 }
639
640 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
641 {
642 return (1UL << (ctxt->ad_bytes << 3)) - 1;
643 }
644
645 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
646 {
647 u16 sel;
648 struct desc_struct ss;
649
650 if (ctxt->mode == X86EMUL_MODE_PROT64)
651 return ~0UL;
652 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
653 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
654 }
655
656 static int stack_size(struct x86_emulate_ctxt *ctxt)
657 {
658 return (__fls(stack_mask(ctxt)) + 1) >> 3;
659 }
660
661 /* Access/update address held in a register, based on addressing mode. */
662 static inline unsigned long
663 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
664 {
665 if (ctxt->ad_bytes == sizeof(unsigned long))
666 return reg;
667 else
668 return reg & ad_mask(ctxt);
669 }
670
671 static inline unsigned long
672 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
673 {
674 return address_mask(ctxt, reg);
675 }
676
677 static void masked_increment(ulong *reg, ulong mask, int inc)
678 {
679 assign_masked(reg, *reg + inc, mask);
680 }
681
682 static inline void
683 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
684 {
685 ulong mask;
686
687 if (ctxt->ad_bytes == sizeof(unsigned long))
688 mask = ~0UL;
689 else
690 mask = ad_mask(ctxt);
691 masked_increment(reg, mask, inc);
692 }
693
694 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
695 {
696 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
697 }
698
699 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
700 {
701 register_address_increment(ctxt, &ctxt->_eip, rel);
702 }
703
704 static u32 desc_limit_scaled(struct desc_struct *desc)
705 {
706 u32 limit = get_desc_limit(desc);
707
708 return desc->g ? (limit << 12) | 0xfff : limit;
709 }
710
711 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
712 {
713 ctxt->has_seg_override = true;
714 ctxt->seg_override = seg;
715 }
716
717 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
718 {
719 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
720 return 0;
721
722 return ctxt->ops->get_cached_segment_base(ctxt, seg);
723 }
724
725 static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
726 {
727 if (!ctxt->has_seg_override)
728 return 0;
729
730 return ctxt->seg_override;
731 }
732
733 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
734 u32 error, bool valid)
735 {
736 ctxt->exception.vector = vec;
737 ctxt->exception.error_code = error;
738 ctxt->exception.error_code_valid = valid;
739 return X86EMUL_PROPAGATE_FAULT;
740 }
741
742 static int emulate_db(struct x86_emulate_ctxt *ctxt)
743 {
744 return emulate_exception(ctxt, DB_VECTOR, 0, false);
745 }
746
747 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
748 {
749 return emulate_exception(ctxt, GP_VECTOR, err, true);
750 }
751
752 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
753 {
754 return emulate_exception(ctxt, SS_VECTOR, err, true);
755 }
756
757 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
758 {
759 return emulate_exception(ctxt, UD_VECTOR, 0, false);
760 }
761
762 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
763 {
764 return emulate_exception(ctxt, TS_VECTOR, err, true);
765 }
766
767 static int emulate_de(struct x86_emulate_ctxt *ctxt)
768 {
769 return emulate_exception(ctxt, DE_VECTOR, 0, false);
770 }
771
772 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
773 {
774 return emulate_exception(ctxt, NM_VECTOR, 0, false);
775 }
776
777 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
778 {
779 u16 selector;
780 struct desc_struct desc;
781
782 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
783 return selector;
784 }
785
786 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
787 unsigned seg)
788 {
789 u16 dummy;
790 u32 base3;
791 struct desc_struct desc;
792
793 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
794 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
795 }
796
797 /*
798 * x86 defines three classes of vector instructions: explicitly
799 * aligned, explicitly unaligned, and the rest, which change behaviour
800 * depending on whether they're AVX encoded or not.
801 *
802 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
803 * subject to the same check.
804 */
805 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
806 {
807 if (likely(size < 16))
808 return false;
809
810 if (ctxt->d & Aligned)
811 return true;
812 else if (ctxt->d & Unaligned)
813 return false;
814 else if (ctxt->d & Avx)
815 return false;
816 else
817 return true;
818 }
819
820 static int __linearize(struct x86_emulate_ctxt *ctxt,
821 struct segmented_address addr,
822 unsigned size, bool write, bool fetch,
823 ulong *linear)
824 {
825 struct desc_struct desc;
826 bool usable;
827 ulong la;
828 u32 lim;
829 u16 sel;
830 unsigned cpl;
831
832 la = seg_base(ctxt, addr.seg) + addr.ea;
833 switch (ctxt->mode) {
834 case X86EMUL_MODE_PROT64:
835 if (((signed long)la << 16) >> 16 != la)
836 return emulate_gp(ctxt, 0);
837 break;
838 default:
839 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
840 addr.seg);
841 if (!usable)
842 goto bad;
843 /* code segment in protected mode or read-only data segment */
844 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
845 || !(desc.type & 2)) && write)
846 goto bad;
847 /* unreadable code segment */
848 if (!fetch && (desc.type & 8) && !(desc.type & 2))
849 goto bad;
850 lim = desc_limit_scaled(&desc);
851 if ((desc.type & 8) || !(desc.type & 4)) {
852 /* expand-up segment */
853 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
854 goto bad;
855 } else {
856 /* expand-down segment */
857 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
858 goto bad;
859 lim = desc.d ? 0xffffffff : 0xffff;
860 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
861 goto bad;
862 }
863 cpl = ctxt->ops->cpl(ctxt);
864 if (!(desc.type & 8)) {
865 /* data segment */
866 if (cpl > desc.dpl)
867 goto bad;
868 } else if ((desc.type & 8) && !(desc.type & 4)) {
869 /* nonconforming code segment */
870 if (cpl != desc.dpl)
871 goto bad;
872 } else if ((desc.type & 8) && (desc.type & 4)) {
873 /* conforming code segment */
874 if (cpl < desc.dpl)
875 goto bad;
876 }
877 break;
878 }
879 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
880 la &= (u32)-1;
881 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
882 return emulate_gp(ctxt, 0);
883 *linear = la;
884 return X86EMUL_CONTINUE;
885 bad:
886 if (addr.seg == VCPU_SREG_SS)
887 return emulate_ss(ctxt, sel);
888 else
889 return emulate_gp(ctxt, sel);
890 }
891
892 static int linearize(struct x86_emulate_ctxt *ctxt,
893 struct segmented_address addr,
894 unsigned size, bool write,
895 ulong *linear)
896 {
897 return __linearize(ctxt, addr, size, write, false, linear);
898 }
899
900
901 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
902 struct segmented_address addr,
903 void *data,
904 unsigned size)
905 {
906 int rc;
907 ulong linear;
908
909 rc = linearize(ctxt, addr, size, false, &linear);
910 if (rc != X86EMUL_CONTINUE)
911 return rc;
912 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
913 }
914
915 /*
916 * Fetch the next byte of the instruction being emulated which is pointed to
917 * by ctxt->_eip, then increment ctxt->_eip.
918 *
919 * Also prefetch the remaining bytes of the instruction without crossing page
920 * boundary if they are not in fetch_cache yet.
921 */
922 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
923 {
924 struct fetch_cache *fc = &ctxt->fetch;
925 int rc;
926 int size, cur_size;
927
928 if (ctxt->_eip == fc->end) {
929 unsigned long linear;
930 struct segmented_address addr = { .seg = VCPU_SREG_CS,
931 .ea = ctxt->_eip };
932 cur_size = fc->end - fc->start;
933 size = min(15UL - cur_size,
934 PAGE_SIZE - offset_in_page(ctxt->_eip));
935 rc = __linearize(ctxt, addr, size, false, true, &linear);
936 if (unlikely(rc != X86EMUL_CONTINUE))
937 return rc;
938 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
939 size, &ctxt->exception);
940 if (unlikely(rc != X86EMUL_CONTINUE))
941 return rc;
942 fc->end += size;
943 }
944 *dest = fc->data[ctxt->_eip - fc->start];
945 ctxt->_eip++;
946 return X86EMUL_CONTINUE;
947 }
948
949 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
950 void *dest, unsigned size)
951 {
952 int rc;
953
954 /* x86 instructions are limited to 15 bytes. */
955 if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
956 return X86EMUL_UNHANDLEABLE;
957 while (size--) {
958 rc = do_insn_fetch_byte(ctxt, dest++);
959 if (rc != X86EMUL_CONTINUE)
960 return rc;
961 }
962 return X86EMUL_CONTINUE;
963 }
964
965 /* Fetch next part of the instruction being emulated. */
966 #define insn_fetch(_type, _ctxt) \
967 ({ unsigned long _x; \
968 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \
969 if (rc != X86EMUL_CONTINUE) \
970 goto done; \
971 (_type)_x; \
972 })
973
974 #define insn_fetch_arr(_arr, _size, _ctxt) \
975 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \
976 if (rc != X86EMUL_CONTINUE) \
977 goto done; \
978 })
979
980 /*
981 * Given the 'reg' portion of a ModRM byte, and a register block, return a
982 * pointer into the block that addresses the relevant register.
983 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
984 */
985 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
986 int highbyte_regs)
987 {
988 void *p;
989
990 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
991 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
992 else
993 p = reg_rmw(ctxt, modrm_reg);
994 return p;
995 }
996
997 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
998 struct segmented_address addr,
999 u16 *size, unsigned long *address, int op_bytes)
1000 {
1001 int rc;
1002
1003 if (op_bytes == 2)
1004 op_bytes = 3;
1005 *address = 0;
1006 rc = segmented_read_std(ctxt, addr, size, 2);
1007 if (rc != X86EMUL_CONTINUE)
1008 return rc;
1009 addr.ea += 2;
1010 rc = segmented_read_std(ctxt, addr, address, op_bytes);
1011 return rc;
1012 }
1013
1014 FASTOP2(add);
1015 FASTOP2(or);
1016 FASTOP2(adc);
1017 FASTOP2(sbb);
1018 FASTOP2(and);
1019 FASTOP2(sub);
1020 FASTOP2(xor);
1021 FASTOP2(cmp);
1022 FASTOP2(test);
1023
1024 FASTOP1SRC2(mul, mul_ex);
1025 FASTOP1SRC2(imul, imul_ex);
1026 FASTOP1SRC2EX(div, div_ex);
1027 FASTOP1SRC2EX(idiv, idiv_ex);
1028
1029 FASTOP3WCL(shld);
1030 FASTOP3WCL(shrd);
1031
1032 FASTOP2W(imul);
1033
1034 FASTOP1(not);
1035 FASTOP1(neg);
1036 FASTOP1(inc);
1037 FASTOP1(dec);
1038
1039 FASTOP2CL(rol);
1040 FASTOP2CL(ror);
1041 FASTOP2CL(rcl);
1042 FASTOP2CL(rcr);
1043 FASTOP2CL(shl);
1044 FASTOP2CL(shr);
1045 FASTOP2CL(sar);
1046
1047 FASTOP2W(bsf);
1048 FASTOP2W(bsr);
1049 FASTOP2W(bt);
1050 FASTOP2W(bts);
1051 FASTOP2W(btr);
1052 FASTOP2W(btc);
1053
1054 static u8 test_cc(unsigned int condition, unsigned long flags)
1055 {
1056 u8 rc;
1057 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1058
1059 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1060 asm("push %[flags]; popf; call *%[fastop]"
1061 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
1062 return rc;
1063 }
1064
1065 static void fetch_register_operand(struct operand *op)
1066 {
1067 switch (op->bytes) {
1068 case 1:
1069 op->val = *(u8 *)op->addr.reg;
1070 break;
1071 case 2:
1072 op->val = *(u16 *)op->addr.reg;
1073 break;
1074 case 4:
1075 op->val = *(u32 *)op->addr.reg;
1076 break;
1077 case 8:
1078 op->val = *(u64 *)op->addr.reg;
1079 break;
1080 }
1081 }
1082
1083 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1084 {
1085 ctxt->ops->get_fpu(ctxt);
1086 switch (reg) {
1087 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1088 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1089 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1090 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1091 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1092 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1093 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1094 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1095 #ifdef CONFIG_X86_64
1096 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1097 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1098 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1099 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1100 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1101 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1102 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1103 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1104 #endif
1105 default: BUG();
1106 }
1107 ctxt->ops->put_fpu(ctxt);
1108 }
1109
1110 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1111 int reg)
1112 {
1113 ctxt->ops->get_fpu(ctxt);
1114 switch (reg) {
1115 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1116 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1117 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1118 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1119 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1120 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1121 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1122 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1123 #ifdef CONFIG_X86_64
1124 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1125 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1126 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1127 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1128 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1129 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1130 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1131 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1132 #endif
1133 default: BUG();
1134 }
1135 ctxt->ops->put_fpu(ctxt);
1136 }
1137
1138 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1139 {
1140 ctxt->ops->get_fpu(ctxt);
1141 switch (reg) {
1142 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1143 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1144 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1145 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1146 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1147 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1148 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1149 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1150 default: BUG();
1151 }
1152 ctxt->ops->put_fpu(ctxt);
1153 }
1154
1155 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1156 {
1157 ctxt->ops->get_fpu(ctxt);
1158 switch (reg) {
1159 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1160 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1161 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1162 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1163 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1164 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1165 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1166 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1167 default: BUG();
1168 }
1169 ctxt->ops->put_fpu(ctxt);
1170 }
1171
1172 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1173 {
1174 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1175 return emulate_nm(ctxt);
1176
1177 ctxt->ops->get_fpu(ctxt);
1178 asm volatile("fninit");
1179 ctxt->ops->put_fpu(ctxt);
1180 return X86EMUL_CONTINUE;
1181 }
1182
1183 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1184 {
1185 u16 fcw;
1186
1187 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1188 return emulate_nm(ctxt);
1189
1190 ctxt->ops->get_fpu(ctxt);
1191 asm volatile("fnstcw %0": "+m"(fcw));
1192 ctxt->ops->put_fpu(ctxt);
1193
1194 /* force 2 byte destination */
1195 ctxt->dst.bytes = 2;
1196 ctxt->dst.val = fcw;
1197
1198 return X86EMUL_CONTINUE;
1199 }
1200
1201 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1202 {
1203 u16 fsw;
1204
1205 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1206 return emulate_nm(ctxt);
1207
1208 ctxt->ops->get_fpu(ctxt);
1209 asm volatile("fnstsw %0": "+m"(fsw));
1210 ctxt->ops->put_fpu(ctxt);
1211
1212 /* force 2 byte destination */
1213 ctxt->dst.bytes = 2;
1214 ctxt->dst.val = fsw;
1215
1216 return X86EMUL_CONTINUE;
1217 }
1218
1219 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1220 struct operand *op)
1221 {
1222 unsigned reg = ctxt->modrm_reg;
1223 int highbyte_regs = ctxt->rex_prefix == 0;
1224
1225 if (!(ctxt->d & ModRM))
1226 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1227
1228 if (ctxt->d & Sse) {
1229 op->type = OP_XMM;
1230 op->bytes = 16;
1231 op->addr.xmm = reg;
1232 read_sse_reg(ctxt, &op->vec_val, reg);
1233 return;
1234 }
1235 if (ctxt->d & Mmx) {
1236 reg &= 7;
1237 op->type = OP_MM;
1238 op->bytes = 8;
1239 op->addr.mm = reg;
1240 return;
1241 }
1242
1243 op->type = OP_REG;
1244 if (ctxt->d & ByteOp) {
1245 op->addr.reg = decode_register(ctxt, reg, highbyte_regs);
1246 op->bytes = 1;
1247 } else {
1248 op->addr.reg = decode_register(ctxt, reg, 0);
1249 op->bytes = ctxt->op_bytes;
1250 }
1251 fetch_register_operand(op);
1252 op->orig_val = op->val;
1253 }
1254
1255 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1256 {
1257 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1258 ctxt->modrm_seg = VCPU_SREG_SS;
1259 }
1260
1261 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1262 struct operand *op)
1263 {
1264 u8 sib;
1265 int index_reg = 0, base_reg = 0, scale;
1266 int rc = X86EMUL_CONTINUE;
1267 ulong modrm_ea = 0;
1268
1269 if (ctxt->rex_prefix) {
1270 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */
1271 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
1272 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
1273 }
1274
1275 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
1276 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1277 ctxt->modrm_rm |= (ctxt->modrm & 0x07);
1278 ctxt->modrm_seg = VCPU_SREG_DS;
1279
1280 if (ctxt->modrm_mod == 3) {
1281 op->type = OP_REG;
1282 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1283 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp);
1284 if (ctxt->d & Sse) {
1285 op->type = OP_XMM;
1286 op->bytes = 16;
1287 op->addr.xmm = ctxt->modrm_rm;
1288 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1289 return rc;
1290 }
1291 if (ctxt->d & Mmx) {
1292 op->type = OP_MM;
1293 op->bytes = 8;
1294 op->addr.xmm = ctxt->modrm_rm & 7;
1295 return rc;
1296 }
1297 fetch_register_operand(op);
1298 return rc;
1299 }
1300
1301 op->type = OP_MEM;
1302
1303 if (ctxt->ad_bytes == 2) {
1304 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1305 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1306 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1307 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1308
1309 /* 16-bit ModR/M decode. */
1310 switch (ctxt->modrm_mod) {
1311 case 0:
1312 if (ctxt->modrm_rm == 6)
1313 modrm_ea += insn_fetch(u16, ctxt);
1314 break;
1315 case 1:
1316 modrm_ea += insn_fetch(s8, ctxt);
1317 break;
1318 case 2:
1319 modrm_ea += insn_fetch(u16, ctxt);
1320 break;
1321 }
1322 switch (ctxt->modrm_rm) {
1323 case 0:
1324 modrm_ea += bx + si;
1325 break;
1326 case 1:
1327 modrm_ea += bx + di;
1328 break;
1329 case 2:
1330 modrm_ea += bp + si;
1331 break;
1332 case 3:
1333 modrm_ea += bp + di;
1334 break;
1335 case 4:
1336 modrm_ea += si;
1337 break;
1338 case 5:
1339 modrm_ea += di;
1340 break;
1341 case 6:
1342 if (ctxt->modrm_mod != 0)
1343 modrm_ea += bp;
1344 break;
1345 case 7:
1346 modrm_ea += bx;
1347 break;
1348 }
1349 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1350 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1351 ctxt->modrm_seg = VCPU_SREG_SS;
1352 modrm_ea = (u16)modrm_ea;
1353 } else {
1354 /* 32/64-bit ModR/M decode. */
1355 if ((ctxt->modrm_rm & 7) == 4) {
1356 sib = insn_fetch(u8, ctxt);
1357 index_reg |= (sib >> 3) & 7;
1358 base_reg |= sib & 7;
1359 scale = sib >> 6;
1360
1361 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1362 modrm_ea += insn_fetch(s32, ctxt);
1363 else {
1364 modrm_ea += reg_read(ctxt, base_reg);
1365 adjust_modrm_seg(ctxt, base_reg);
1366 }
1367 if (index_reg != 4)
1368 modrm_ea += reg_read(ctxt, index_reg) << scale;
1369 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1370 if (ctxt->mode == X86EMUL_MODE_PROT64)
1371 ctxt->rip_relative = 1;
1372 } else {
1373 base_reg = ctxt->modrm_rm;
1374 modrm_ea += reg_read(ctxt, base_reg);
1375 adjust_modrm_seg(ctxt, base_reg);
1376 }
1377 switch (ctxt->modrm_mod) {
1378 case 0:
1379 if (ctxt->modrm_rm == 5)
1380 modrm_ea += insn_fetch(s32, ctxt);
1381 break;
1382 case 1:
1383 modrm_ea += insn_fetch(s8, ctxt);
1384 break;
1385 case 2:
1386 modrm_ea += insn_fetch(s32, ctxt);
1387 break;
1388 }
1389 }
1390 op->addr.mem.ea = modrm_ea;
1391 done:
1392 return rc;
1393 }
1394
1395 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1396 struct operand *op)
1397 {
1398 int rc = X86EMUL_CONTINUE;
1399
1400 op->type = OP_MEM;
1401 switch (ctxt->ad_bytes) {
1402 case 2:
1403 op->addr.mem.ea = insn_fetch(u16, ctxt);
1404 break;
1405 case 4:
1406 op->addr.mem.ea = insn_fetch(u32, ctxt);
1407 break;
1408 case 8:
1409 op->addr.mem.ea = insn_fetch(u64, ctxt);
1410 break;
1411 }
1412 done:
1413 return rc;
1414 }
1415
1416 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1417 {
1418 long sv = 0, mask;
1419
1420 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1421 mask = ~(ctxt->dst.bytes * 8 - 1);
1422
1423 if (ctxt->src.bytes == 2)
1424 sv = (s16)ctxt->src.val & (s16)mask;
1425 else if (ctxt->src.bytes == 4)
1426 sv = (s32)ctxt->src.val & (s32)mask;
1427
1428 ctxt->dst.addr.mem.ea += (sv >> 3);
1429 }
1430
1431 /* only subword offset */
1432 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1433 }
1434
1435 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1436 unsigned long addr, void *dest, unsigned size)
1437 {
1438 int rc;
1439 struct read_cache *mc = &ctxt->mem_read;
1440
1441 if (mc->pos < mc->end)
1442 goto read_cached;
1443
1444 WARN_ON((mc->end + size) >= sizeof(mc->data));
1445
1446 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1447 &ctxt->exception);
1448 if (rc != X86EMUL_CONTINUE)
1449 return rc;
1450
1451 mc->end += size;
1452
1453 read_cached:
1454 memcpy(dest, mc->data + mc->pos, size);
1455 mc->pos += size;
1456 return X86EMUL_CONTINUE;
1457 }
1458
1459 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1460 struct segmented_address addr,
1461 void *data,
1462 unsigned size)
1463 {
1464 int rc;
1465 ulong linear;
1466
1467 rc = linearize(ctxt, addr, size, false, &linear);
1468 if (rc != X86EMUL_CONTINUE)
1469 return rc;
1470 return read_emulated(ctxt, linear, data, size);
1471 }
1472
1473 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1474 struct segmented_address addr,
1475 const void *data,
1476 unsigned size)
1477 {
1478 int rc;
1479 ulong linear;
1480
1481 rc = linearize(ctxt, addr, size, true, &linear);
1482 if (rc != X86EMUL_CONTINUE)
1483 return rc;
1484 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1485 &ctxt->exception);
1486 }
1487
1488 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1489 struct segmented_address addr,
1490 const void *orig_data, const void *data,
1491 unsigned size)
1492 {
1493 int rc;
1494 ulong linear;
1495
1496 rc = linearize(ctxt, addr, size, true, &linear);
1497 if (rc != X86EMUL_CONTINUE)
1498 return rc;
1499 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1500 size, &ctxt->exception);
1501 }
1502
1503 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1504 unsigned int size, unsigned short port,
1505 void *dest)
1506 {
1507 struct read_cache *rc = &ctxt->io_read;
1508
1509 if (rc->pos == rc->end) { /* refill pio read ahead */
1510 unsigned int in_page, n;
1511 unsigned int count = ctxt->rep_prefix ?
1512 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1513 in_page = (ctxt->eflags & EFLG_DF) ?
1514 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1515 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1516 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1517 count);
1518 if (n == 0)
1519 n = 1;
1520 rc->pos = rc->end = 0;
1521 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1522 return 0;
1523 rc->end = n * size;
1524 }
1525
1526 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) {
1527 ctxt->dst.data = rc->data + rc->pos;
1528 ctxt->dst.type = OP_MEM_STR;
1529 ctxt->dst.count = (rc->end - rc->pos) / size;
1530 rc->pos = rc->end;
1531 } else {
1532 memcpy(dest, rc->data + rc->pos, size);
1533 rc->pos += size;
1534 }
1535 return 1;
1536 }
1537
1538 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1539 u16 index, struct desc_struct *desc)
1540 {
1541 struct desc_ptr dt;
1542 ulong addr;
1543
1544 ctxt->ops->get_idt(ctxt, &dt);
1545
1546 if (dt.size < index * 8 + 7)
1547 return emulate_gp(ctxt, index << 3 | 0x2);
1548
1549 addr = dt.address + index * 8;
1550 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1551 &ctxt->exception);
1552 }
1553
1554 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1555 u16 selector, struct desc_ptr *dt)
1556 {
1557 const struct x86_emulate_ops *ops = ctxt->ops;
1558
1559 if (selector & 1 << 2) {
1560 struct desc_struct desc;
1561 u16 sel;
1562
1563 memset (dt, 0, sizeof *dt);
1564 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1565 return;
1566
1567 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1568 dt->address = get_desc_base(&desc);
1569 } else
1570 ops->get_gdt(ctxt, dt);
1571 }
1572
1573 /* allowed just for 8 bytes segments */
1574 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1575 u16 selector, struct desc_struct *desc,
1576 ulong *desc_addr_p)
1577 {
1578 struct desc_ptr dt;
1579 u16 index = selector >> 3;
1580 ulong addr;
1581
1582 get_descriptor_table_ptr(ctxt, selector, &dt);
1583
1584 if (dt.size < index * 8 + 7)
1585 return emulate_gp(ctxt, selector & 0xfffc);
1586
1587 *desc_addr_p = addr = dt.address + index * 8;
1588 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1589 &ctxt->exception);
1590 }
1591
1592 /* allowed just for 8 bytes segments */
1593 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1594 u16 selector, struct desc_struct *desc)
1595 {
1596 struct desc_ptr dt;
1597 u16 index = selector >> 3;
1598 ulong addr;
1599
1600 get_descriptor_table_ptr(ctxt, selector, &dt);
1601
1602 if (dt.size < index * 8 + 7)
1603 return emulate_gp(ctxt, selector & 0xfffc);
1604
1605 addr = dt.address + index * 8;
1606 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1607 &ctxt->exception);
1608 }
1609
1610 /* Does not support long mode */
1611 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1612 u16 selector, int seg)
1613 {
1614 struct desc_struct seg_desc, old_desc;
1615 u8 dpl, rpl, cpl;
1616 unsigned err_vec = GP_VECTOR;
1617 u32 err_code = 0;
1618 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1619 ulong desc_addr;
1620 int ret;
1621 u16 dummy;
1622
1623 memset(&seg_desc, 0, sizeof seg_desc);
1624
1625 if (ctxt->mode == X86EMUL_MODE_REAL) {
1626 /* set real mode segment descriptor (keep limit etc. for
1627 * unreal mode) */
1628 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1629 set_desc_base(&seg_desc, selector << 4);
1630 goto load;
1631 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1632 /* VM86 needs a clean new segment descriptor */
1633 set_desc_base(&seg_desc, selector << 4);
1634 set_desc_limit(&seg_desc, 0xffff);
1635 seg_desc.type = 3;
1636 seg_desc.p = 1;
1637 seg_desc.s = 1;
1638 seg_desc.dpl = 3;
1639 goto load;
1640 }
1641
1642 rpl = selector & 3;
1643 cpl = ctxt->ops->cpl(ctxt);
1644
1645 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1646 if ((seg == VCPU_SREG_CS
1647 || (seg == VCPU_SREG_SS
1648 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1649 || seg == VCPU_SREG_TR)
1650 && null_selector)
1651 goto exception;
1652
1653 /* TR should be in GDT only */
1654 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1655 goto exception;
1656
1657 if (null_selector) /* for NULL selector skip all following checks */
1658 goto load;
1659
1660 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1661 if (ret != X86EMUL_CONTINUE)
1662 return ret;
1663
1664 err_code = selector & 0xfffc;
1665 err_vec = GP_VECTOR;
1666
1667 /* can't load system descriptor into segment selector */
1668 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1669 goto exception;
1670
1671 if (!seg_desc.p) {
1672 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1673 goto exception;
1674 }
1675
1676 dpl = seg_desc.dpl;
1677
1678 switch (seg) {
1679 case VCPU_SREG_SS:
1680 /*
1681 * segment is not a writable data segment or segment
1682 * selector's RPL != CPL or segment selector's RPL != CPL
1683 */
1684 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1685 goto exception;
1686 break;
1687 case VCPU_SREG_CS:
1688 if (!(seg_desc.type & 8))
1689 goto exception;
1690
1691 if (seg_desc.type & 4) {
1692 /* conforming */
1693 if (dpl > cpl)
1694 goto exception;
1695 } else {
1696 /* nonconforming */
1697 if (rpl > cpl || dpl != cpl)
1698 goto exception;
1699 }
1700 /* CS(RPL) <- CPL */
1701 selector = (selector & 0xfffc) | cpl;
1702 break;
1703 case VCPU_SREG_TR:
1704 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1705 goto exception;
1706 old_desc = seg_desc;
1707 seg_desc.type |= 2; /* busy */
1708 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1709 sizeof(seg_desc), &ctxt->exception);
1710 if (ret != X86EMUL_CONTINUE)
1711 return ret;
1712 break;
1713 case VCPU_SREG_LDTR:
1714 if (seg_desc.s || seg_desc.type != 2)
1715 goto exception;
1716 break;
1717 default: /* DS, ES, FS, or GS */
1718 /*
1719 * segment is not a data or readable code segment or
1720 * ((segment is a data or nonconforming code segment)
1721 * and (both RPL and CPL > DPL))
1722 */
1723 if ((seg_desc.type & 0xa) == 0x8 ||
1724 (((seg_desc.type & 0xc) != 0xc) &&
1725 (rpl > dpl && cpl > dpl)))
1726 goto exception;
1727 break;
1728 }
1729
1730 if (seg_desc.s) {
1731 /* mark segment as accessed */
1732 seg_desc.type |= 1;
1733 ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1734 if (ret != X86EMUL_CONTINUE)
1735 return ret;
1736 }
1737 load:
1738 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1739 return X86EMUL_CONTINUE;
1740 exception:
1741 emulate_exception(ctxt, err_vec, err_code, true);
1742 return X86EMUL_PROPAGATE_FAULT;
1743 }
1744
1745 static void write_register_operand(struct operand *op)
1746 {
1747 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1748 switch (op->bytes) {
1749 case 1:
1750 *(u8 *)op->addr.reg = (u8)op->val;
1751 break;
1752 case 2:
1753 *(u16 *)op->addr.reg = (u16)op->val;
1754 break;
1755 case 4:
1756 *op->addr.reg = (u32)op->val;
1757 break; /* 64b: zero-extend */
1758 case 8:
1759 *op->addr.reg = op->val;
1760 break;
1761 }
1762 }
1763
1764 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1765 {
1766 int rc;
1767
1768 switch (op->type) {
1769 case OP_REG:
1770 write_register_operand(op);
1771 break;
1772 case OP_MEM:
1773 if (ctxt->lock_prefix)
1774 rc = segmented_cmpxchg(ctxt,
1775 op->addr.mem,
1776 &op->orig_val,
1777 &op->val,
1778 op->bytes);
1779 else
1780 rc = segmented_write(ctxt,
1781 op->addr.mem,
1782 &op->val,
1783 op->bytes);
1784 if (rc != X86EMUL_CONTINUE)
1785 return rc;
1786 break;
1787 case OP_MEM_STR:
1788 rc = segmented_write(ctxt,
1789 op->addr.mem,
1790 op->data,
1791 op->bytes * op->count);
1792 if (rc != X86EMUL_CONTINUE)
1793 return rc;
1794 break;
1795 case OP_XMM:
1796 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1797 break;
1798 case OP_MM:
1799 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1800 break;
1801 case OP_NONE:
1802 /* no writeback */
1803 break;
1804 default:
1805 break;
1806 }
1807 return X86EMUL_CONTINUE;
1808 }
1809
1810 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1811 {
1812 struct segmented_address addr;
1813
1814 rsp_increment(ctxt, -bytes);
1815 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1816 addr.seg = VCPU_SREG_SS;
1817
1818 return segmented_write(ctxt, addr, data, bytes);
1819 }
1820
1821 static int em_push(struct x86_emulate_ctxt *ctxt)
1822 {
1823 /* Disable writeback. */
1824 ctxt->dst.type = OP_NONE;
1825 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1826 }
1827
1828 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1829 void *dest, int len)
1830 {
1831 int rc;
1832 struct segmented_address addr;
1833
1834 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1835 addr.seg = VCPU_SREG_SS;
1836 rc = segmented_read(ctxt, addr, dest, len);
1837 if (rc != X86EMUL_CONTINUE)
1838 return rc;
1839
1840 rsp_increment(ctxt, len);
1841 return rc;
1842 }
1843
1844 static int em_pop(struct x86_emulate_ctxt *ctxt)
1845 {
1846 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1847 }
1848
1849 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1850 void *dest, int len)
1851 {
1852 int rc;
1853 unsigned long val, change_mask;
1854 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1855 int cpl = ctxt->ops->cpl(ctxt);
1856
1857 rc = emulate_pop(ctxt, &val, len);
1858 if (rc != X86EMUL_CONTINUE)
1859 return rc;
1860
1861 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1862 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1863
1864 switch(ctxt->mode) {
1865 case X86EMUL_MODE_PROT64:
1866 case X86EMUL_MODE_PROT32:
1867 case X86EMUL_MODE_PROT16:
1868 if (cpl == 0)
1869 change_mask |= EFLG_IOPL;
1870 if (cpl <= iopl)
1871 change_mask |= EFLG_IF;
1872 break;
1873 case X86EMUL_MODE_VM86:
1874 if (iopl < 3)
1875 return emulate_gp(ctxt, 0);
1876 change_mask |= EFLG_IF;
1877 break;
1878 default: /* real mode */
1879 change_mask |= (EFLG_IOPL | EFLG_IF);
1880 break;
1881 }
1882
1883 *(unsigned long *)dest =
1884 (ctxt->eflags & ~change_mask) | (val & change_mask);
1885
1886 return rc;
1887 }
1888
1889 static int em_popf(struct x86_emulate_ctxt *ctxt)
1890 {
1891 ctxt->dst.type = OP_REG;
1892 ctxt->dst.addr.reg = &ctxt->eflags;
1893 ctxt->dst.bytes = ctxt->op_bytes;
1894 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1895 }
1896
1897 static int em_enter(struct x86_emulate_ctxt *ctxt)
1898 {
1899 int rc;
1900 unsigned frame_size = ctxt->src.val;
1901 unsigned nesting_level = ctxt->src2.val & 31;
1902 ulong rbp;
1903
1904 if (nesting_level)
1905 return X86EMUL_UNHANDLEABLE;
1906
1907 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1908 rc = push(ctxt, &rbp, stack_size(ctxt));
1909 if (rc != X86EMUL_CONTINUE)
1910 return rc;
1911 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1912 stack_mask(ctxt));
1913 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1914 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1915 stack_mask(ctxt));
1916 return X86EMUL_CONTINUE;
1917 }
1918
1919 static int em_leave(struct x86_emulate_ctxt *ctxt)
1920 {
1921 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1922 stack_mask(ctxt));
1923 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1924 }
1925
1926 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1927 {
1928 int seg = ctxt->src2.val;
1929
1930 ctxt->src.val = get_segment_selector(ctxt, seg);
1931
1932 return em_push(ctxt);
1933 }
1934
1935 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1936 {
1937 int seg = ctxt->src2.val;
1938 unsigned long selector;
1939 int rc;
1940
1941 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1942 if (rc != X86EMUL_CONTINUE)
1943 return rc;
1944
1945 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1946 return rc;
1947 }
1948
1949 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1950 {
1951 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1952 int rc = X86EMUL_CONTINUE;
1953 int reg = VCPU_REGS_RAX;
1954
1955 while (reg <= VCPU_REGS_RDI) {
1956 (reg == VCPU_REGS_RSP) ?
1957 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1958
1959 rc = em_push(ctxt);
1960 if (rc != X86EMUL_CONTINUE)
1961 return rc;
1962
1963 ++reg;
1964 }
1965
1966 return rc;
1967 }
1968
1969 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1970 {
1971 ctxt->src.val = (unsigned long)ctxt->eflags;
1972 return em_push(ctxt);
1973 }
1974
1975 static int em_popa(struct x86_emulate_ctxt *ctxt)
1976 {
1977 int rc = X86EMUL_CONTINUE;
1978 int reg = VCPU_REGS_RDI;
1979
1980 while (reg >= VCPU_REGS_RAX) {
1981 if (reg == VCPU_REGS_RSP) {
1982 rsp_increment(ctxt, ctxt->op_bytes);
1983 --reg;
1984 }
1985
1986 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1987 if (rc != X86EMUL_CONTINUE)
1988 break;
1989 --reg;
1990 }
1991 return rc;
1992 }
1993
1994 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1995 {
1996 const struct x86_emulate_ops *ops = ctxt->ops;
1997 int rc;
1998 struct desc_ptr dt;
1999 gva_t cs_addr;
2000 gva_t eip_addr;
2001 u16 cs, eip;
2002
2003 /* TODO: Add limit checks */
2004 ctxt->src.val = ctxt->eflags;
2005 rc = em_push(ctxt);
2006 if (rc != X86EMUL_CONTINUE)
2007 return rc;
2008
2009 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
2010
2011 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2012 rc = em_push(ctxt);
2013 if (rc != X86EMUL_CONTINUE)
2014 return rc;
2015
2016 ctxt->src.val = ctxt->_eip;
2017 rc = em_push(ctxt);
2018 if (rc != X86EMUL_CONTINUE)
2019 return rc;
2020
2021 ops->get_idt(ctxt, &dt);
2022
2023 eip_addr = dt.address + (irq << 2);
2024 cs_addr = dt.address + (irq << 2) + 2;
2025
2026 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
2027 if (rc != X86EMUL_CONTINUE)
2028 return rc;
2029
2030 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
2031 if (rc != X86EMUL_CONTINUE)
2032 return rc;
2033
2034 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2035 if (rc != X86EMUL_CONTINUE)
2036 return rc;
2037
2038 ctxt->_eip = eip;
2039
2040 return rc;
2041 }
2042
2043 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2044 {
2045 int rc;
2046
2047 invalidate_registers(ctxt);
2048 rc = __emulate_int_real(ctxt, irq);
2049 if (rc == X86EMUL_CONTINUE)
2050 writeback_registers(ctxt);
2051 return rc;
2052 }
2053
2054 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2055 {
2056 switch(ctxt->mode) {
2057 case X86EMUL_MODE_REAL:
2058 return __emulate_int_real(ctxt, irq);
2059 case X86EMUL_MODE_VM86:
2060 case X86EMUL_MODE_PROT16:
2061 case X86EMUL_MODE_PROT32:
2062 case X86EMUL_MODE_PROT64:
2063 default:
2064 /* Protected mode interrupts unimplemented yet */
2065 return X86EMUL_UNHANDLEABLE;
2066 }
2067 }
2068
2069 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2070 {
2071 int rc = X86EMUL_CONTINUE;
2072 unsigned long temp_eip = 0;
2073 unsigned long temp_eflags = 0;
2074 unsigned long cs = 0;
2075 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
2076 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
2077 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
2078 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
2079
2080 /* TODO: Add stack limit check */
2081
2082 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2083
2084 if (rc != X86EMUL_CONTINUE)
2085 return rc;
2086
2087 if (temp_eip & ~0xffff)
2088 return emulate_gp(ctxt, 0);
2089
2090 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2091
2092 if (rc != X86EMUL_CONTINUE)
2093 return rc;
2094
2095 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2096
2097 if (rc != X86EMUL_CONTINUE)
2098 return rc;
2099
2100 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2101
2102 if (rc != X86EMUL_CONTINUE)
2103 return rc;
2104
2105 ctxt->_eip = temp_eip;
2106
2107
2108 if (ctxt->op_bytes == 4)
2109 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2110 else if (ctxt->op_bytes == 2) {
2111 ctxt->eflags &= ~0xffff;
2112 ctxt->eflags |= temp_eflags;
2113 }
2114
2115 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2116 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
2117
2118 return rc;
2119 }
2120
2121 static int em_iret(struct x86_emulate_ctxt *ctxt)
2122 {
2123 switch(ctxt->mode) {
2124 case X86EMUL_MODE_REAL:
2125 return emulate_iret_real(ctxt);
2126 case X86EMUL_MODE_VM86:
2127 case X86EMUL_MODE_PROT16:
2128 case X86EMUL_MODE_PROT32:
2129 case X86EMUL_MODE_PROT64:
2130 default:
2131 /* iret from protected mode unimplemented yet */
2132 return X86EMUL_UNHANDLEABLE;
2133 }
2134 }
2135
2136 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2137 {
2138 int rc;
2139 unsigned short sel;
2140
2141 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2142
2143 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
2144 if (rc != X86EMUL_CONTINUE)
2145 return rc;
2146
2147 ctxt->_eip = 0;
2148 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2149 return X86EMUL_CONTINUE;
2150 }
2151
2152 static int em_grp45(struct x86_emulate_ctxt *ctxt)
2153 {
2154 int rc = X86EMUL_CONTINUE;
2155
2156 switch (ctxt->modrm_reg) {
2157 case 2: /* call near abs */ {
2158 long int old_eip;
2159 old_eip = ctxt->_eip;
2160 ctxt->_eip = ctxt->src.val;
2161 ctxt->src.val = old_eip;
2162 rc = em_push(ctxt);
2163 break;
2164 }
2165 case 4: /* jmp abs */
2166 ctxt->_eip = ctxt->src.val;
2167 break;
2168 case 5: /* jmp far */
2169 rc = em_jmp_far(ctxt);
2170 break;
2171 case 6: /* push */
2172 rc = em_push(ctxt);
2173 break;
2174 }
2175 return rc;
2176 }
2177
2178 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2179 {
2180 u64 old = ctxt->dst.orig_val64;
2181
2182 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2183 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2184 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2185 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2186 ctxt->eflags &= ~EFLG_ZF;
2187 } else {
2188 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2189 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2190
2191 ctxt->eflags |= EFLG_ZF;
2192 }
2193 return X86EMUL_CONTINUE;
2194 }
2195
2196 static int em_ret(struct x86_emulate_ctxt *ctxt)
2197 {
2198 ctxt->dst.type = OP_REG;
2199 ctxt->dst.addr.reg = &ctxt->_eip;
2200 ctxt->dst.bytes = ctxt->op_bytes;
2201 return em_pop(ctxt);
2202 }
2203
2204 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2205 {
2206 int rc;
2207 unsigned long cs;
2208
2209 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
2210 if (rc != X86EMUL_CONTINUE)
2211 return rc;
2212 if (ctxt->op_bytes == 4)
2213 ctxt->_eip = (u32)ctxt->_eip;
2214 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2215 if (rc != X86EMUL_CONTINUE)
2216 return rc;
2217 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2218 return rc;
2219 }
2220
2221 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2222 {
2223 /* Save real source value, then compare EAX against destination. */
2224 ctxt->src.orig_val = ctxt->src.val;
2225 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX);
2226 fastop(ctxt, em_cmp);
2227
2228 if (ctxt->eflags & EFLG_ZF) {
2229 /* Success: write back to memory. */
2230 ctxt->dst.val = ctxt->src.orig_val;
2231 } else {
2232 /* Failure: write the value we saw to EAX. */
2233 ctxt->dst.type = OP_REG;
2234 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2235 }
2236 return X86EMUL_CONTINUE;
2237 }
2238
2239 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2240 {
2241 int seg = ctxt->src2.val;
2242 unsigned short sel;
2243 int rc;
2244
2245 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2246
2247 rc = load_segment_descriptor(ctxt, sel, seg);
2248 if (rc != X86EMUL_CONTINUE)
2249 return rc;
2250
2251 ctxt->dst.val = ctxt->src.val;
2252 return rc;
2253 }
2254
2255 static void
2256 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2257 struct desc_struct *cs, struct desc_struct *ss)
2258 {
2259 cs->l = 0; /* will be adjusted later */
2260 set_desc_base(cs, 0); /* flat segment */
2261 cs->g = 1; /* 4kb granularity */
2262 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2263 cs->type = 0x0b; /* Read, Execute, Accessed */
2264 cs->s = 1;
2265 cs->dpl = 0; /* will be adjusted later */
2266 cs->p = 1;
2267 cs->d = 1;
2268 cs->avl = 0;
2269
2270 set_desc_base(ss, 0); /* flat segment */
2271 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2272 ss->g = 1; /* 4kb granularity */
2273 ss->s = 1;
2274 ss->type = 0x03; /* Read/Write, Accessed */
2275 ss->d = 1; /* 32bit stack segment */
2276 ss->dpl = 0;
2277 ss->p = 1;
2278 ss->l = 0;
2279 ss->avl = 0;
2280 }
2281
2282 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2283 {
2284 u32 eax, ebx, ecx, edx;
2285
2286 eax = ecx = 0;
2287 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2288 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2289 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2290 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2291 }
2292
2293 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2294 {
2295 const struct x86_emulate_ops *ops = ctxt->ops;
2296 u32 eax, ebx, ecx, edx;
2297
2298 /*
2299 * syscall should always be enabled in longmode - so only become
2300 * vendor specific (cpuid) if other modes are active...
2301 */
2302 if (ctxt->mode == X86EMUL_MODE_PROT64)
2303 return true;
2304
2305 eax = 0x00000000;
2306 ecx = 0x00000000;
2307 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2308 /*
2309 * Intel ("GenuineIntel")
2310 * remark: Intel CPUs only support "syscall" in 64bit
2311 * longmode. Also an 64bit guest with a
2312 * 32bit compat-app running will #UD !! While this
2313 * behaviour can be fixed (by emulating) into AMD
2314 * response - CPUs of AMD can't behave like Intel.
2315 */
2316 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2317 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2318 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2319 return false;
2320
2321 /* AMD ("AuthenticAMD") */
2322 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2323 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2324 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2325 return true;
2326
2327 /* AMD ("AMDisbetter!") */
2328 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2329 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2330 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2331 return true;
2332
2333 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2334 return false;
2335 }
2336
2337 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2338 {
2339 const struct x86_emulate_ops *ops = ctxt->ops;
2340 struct desc_struct cs, ss;
2341 u64 msr_data;
2342 u16 cs_sel, ss_sel;
2343 u64 efer = 0;
2344
2345 /* syscall is not available in real mode */
2346 if (ctxt->mode == X86EMUL_MODE_REAL ||
2347 ctxt->mode == X86EMUL_MODE_VM86)
2348 return emulate_ud(ctxt);
2349
2350 if (!(em_syscall_is_enabled(ctxt)))
2351 return emulate_ud(ctxt);
2352
2353 ops->get_msr(ctxt, MSR_EFER, &efer);
2354 setup_syscalls_segments(ctxt, &cs, &ss);
2355
2356 if (!(efer & EFER_SCE))
2357 return emulate_ud(ctxt);
2358
2359 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2360 msr_data >>= 32;
2361 cs_sel = (u16)(msr_data & 0xfffc);
2362 ss_sel = (u16)(msr_data + 8);
2363
2364 if (efer & EFER_LMA) {
2365 cs.d = 0;
2366 cs.l = 1;
2367 }
2368 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2369 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2370
2371 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2372 if (efer & EFER_LMA) {
2373 #ifdef CONFIG_X86_64
2374 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
2375
2376 ops->get_msr(ctxt,
2377 ctxt->mode == X86EMUL_MODE_PROT64 ?
2378 MSR_LSTAR : MSR_CSTAR, &msr_data);
2379 ctxt->_eip = msr_data;
2380
2381 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2382 ctxt->eflags &= ~(msr_data | EFLG_RF);
2383 #endif
2384 } else {
2385 /* legacy mode */
2386 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2387 ctxt->_eip = (u32)msr_data;
2388
2389 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2390 }
2391
2392 return X86EMUL_CONTINUE;
2393 }
2394
2395 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2396 {
2397 const struct x86_emulate_ops *ops = ctxt->ops;
2398 struct desc_struct cs, ss;
2399 u64 msr_data;
2400 u16 cs_sel, ss_sel;
2401 u64 efer = 0;
2402
2403 ops->get_msr(ctxt, MSR_EFER, &efer);
2404 /* inject #GP if in real mode */
2405 if (ctxt->mode == X86EMUL_MODE_REAL)
2406 return emulate_gp(ctxt, 0);
2407
2408 /*
2409 * Not recognized on AMD in compat mode (but is recognized in legacy
2410 * mode).
2411 */
2412 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
2413 && !vendor_intel(ctxt))
2414 return emulate_ud(ctxt);
2415
2416 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2417 * Therefore, we inject an #UD.
2418 */
2419 if (ctxt->mode == X86EMUL_MODE_PROT64)
2420 return emulate_ud(ctxt);
2421
2422 setup_syscalls_segments(ctxt, &cs, &ss);
2423
2424 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2425 switch (ctxt->mode) {
2426 case X86EMUL_MODE_PROT32:
2427 if ((msr_data & 0xfffc) == 0x0)
2428 return emulate_gp(ctxt, 0);
2429 break;
2430 case X86EMUL_MODE_PROT64:
2431 if (msr_data == 0x0)
2432 return emulate_gp(ctxt, 0);
2433 break;
2434 default:
2435 break;
2436 }
2437
2438 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2439 cs_sel = (u16)msr_data;
2440 cs_sel &= ~SELECTOR_RPL_MASK;
2441 ss_sel = cs_sel + 8;
2442 ss_sel &= ~SELECTOR_RPL_MASK;
2443 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2444 cs.d = 0;
2445 cs.l = 1;
2446 }
2447
2448 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2449 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2450
2451 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2452 ctxt->_eip = msr_data;
2453
2454 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2455 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2456
2457 return X86EMUL_CONTINUE;
2458 }
2459
2460 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2461 {
2462 const struct x86_emulate_ops *ops = ctxt->ops;
2463 struct desc_struct cs, ss;
2464 u64 msr_data;
2465 int usermode;
2466 u16 cs_sel = 0, ss_sel = 0;
2467
2468 /* inject #GP if in real mode or Virtual 8086 mode */
2469 if (ctxt->mode == X86EMUL_MODE_REAL ||
2470 ctxt->mode == X86EMUL_MODE_VM86)
2471 return emulate_gp(ctxt, 0);
2472
2473 setup_syscalls_segments(ctxt, &cs, &ss);
2474
2475 if ((ctxt->rex_prefix & 0x8) != 0x0)
2476 usermode = X86EMUL_MODE_PROT64;
2477 else
2478 usermode = X86EMUL_MODE_PROT32;
2479
2480 cs.dpl = 3;
2481 ss.dpl = 3;
2482 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2483 switch (usermode) {
2484 case X86EMUL_MODE_PROT32:
2485 cs_sel = (u16)(msr_data + 16);
2486 if ((msr_data & 0xfffc) == 0x0)
2487 return emulate_gp(ctxt, 0);
2488 ss_sel = (u16)(msr_data + 24);
2489 break;
2490 case X86EMUL_MODE_PROT64:
2491 cs_sel = (u16)(msr_data + 32);
2492 if (msr_data == 0x0)
2493 return emulate_gp(ctxt, 0);
2494 ss_sel = cs_sel + 8;
2495 cs.d = 0;
2496 cs.l = 1;
2497 break;
2498 }
2499 cs_sel |= SELECTOR_RPL_MASK;
2500 ss_sel |= SELECTOR_RPL_MASK;
2501
2502 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2503 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2504
2505 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
2506 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
2507
2508 return X86EMUL_CONTINUE;
2509 }
2510
2511 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2512 {
2513 int iopl;
2514 if (ctxt->mode == X86EMUL_MODE_REAL)
2515 return false;
2516 if (ctxt->mode == X86EMUL_MODE_VM86)
2517 return true;
2518 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2519 return ctxt->ops->cpl(ctxt) > iopl;
2520 }
2521
2522 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2523 u16 port, u16 len)
2524 {
2525 const struct x86_emulate_ops *ops = ctxt->ops;
2526 struct desc_struct tr_seg;
2527 u32 base3;
2528 int r;
2529 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2530 unsigned mask = (1 << len) - 1;
2531 unsigned long base;
2532
2533 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2534 if (!tr_seg.p)
2535 return false;
2536 if (desc_limit_scaled(&tr_seg) < 103)
2537 return false;
2538 base = get_desc_base(&tr_seg);
2539 #ifdef CONFIG_X86_64
2540 base |= ((u64)base3) << 32;
2541 #endif
2542 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2543 if (r != X86EMUL_CONTINUE)
2544 return false;
2545 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2546 return false;
2547 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2548 if (r != X86EMUL_CONTINUE)
2549 return false;
2550 if ((perm >> bit_idx) & mask)
2551 return false;
2552 return true;
2553 }
2554
2555 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2556 u16 port, u16 len)
2557 {
2558 if (ctxt->perm_ok)
2559 return true;
2560
2561 if (emulator_bad_iopl(ctxt))
2562 if (!emulator_io_port_access_allowed(ctxt, port, len))
2563 return false;
2564
2565 ctxt->perm_ok = true;
2566
2567 return true;
2568 }
2569
2570 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2571 struct tss_segment_16 *tss)
2572 {
2573 tss->ip = ctxt->_eip;
2574 tss->flag = ctxt->eflags;
2575 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2576 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2577 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2578 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2579 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2580 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2581 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2582 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2583
2584 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2585 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2586 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2587 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2588 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2589 }
2590
2591 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2592 struct tss_segment_16 *tss)
2593 {
2594 int ret;
2595
2596 ctxt->_eip = tss->ip;
2597 ctxt->eflags = tss->flag | 2;
2598 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2599 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2600 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2601 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2602 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2603 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2604 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2605 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2606
2607 /*
2608 * SDM says that segment selectors are loaded before segment
2609 * descriptors
2610 */
2611 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2612 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2613 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2614 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2615 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2616
2617 /*
2618 * Now load segment descriptors. If fault happens at this stage
2619 * it is handled in a context of new task
2620 */
2621 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2622 if (ret != X86EMUL_CONTINUE)
2623 return ret;
2624 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2625 if (ret != X86EMUL_CONTINUE)
2626 return ret;
2627 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2628 if (ret != X86EMUL_CONTINUE)
2629 return ret;
2630 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2631 if (ret != X86EMUL_CONTINUE)
2632 return ret;
2633 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2634 if (ret != X86EMUL_CONTINUE)
2635 return ret;
2636
2637 return X86EMUL_CONTINUE;
2638 }
2639
2640 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2641 u16 tss_selector, u16 old_tss_sel,
2642 ulong old_tss_base, struct desc_struct *new_desc)
2643 {
2644 const struct x86_emulate_ops *ops = ctxt->ops;
2645 struct tss_segment_16 tss_seg;
2646 int ret;
2647 u32 new_tss_base = get_desc_base(new_desc);
2648
2649 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2650 &ctxt->exception);
2651 if (ret != X86EMUL_CONTINUE)
2652 /* FIXME: need to provide precise fault address */
2653 return ret;
2654
2655 save_state_to_tss16(ctxt, &tss_seg);
2656
2657 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2658 &ctxt->exception);
2659 if (ret != X86EMUL_CONTINUE)
2660 /* FIXME: need to provide precise fault address */
2661 return ret;
2662
2663 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2664 &ctxt->exception);
2665 if (ret != X86EMUL_CONTINUE)
2666 /* FIXME: need to provide precise fault address */
2667 return ret;
2668
2669 if (old_tss_sel != 0xffff) {
2670 tss_seg.prev_task_link = old_tss_sel;
2671
2672 ret = ops->write_std(ctxt, new_tss_base,
2673 &tss_seg.prev_task_link,
2674 sizeof tss_seg.prev_task_link,
2675 &ctxt->exception);
2676 if (ret != X86EMUL_CONTINUE)
2677 /* FIXME: need to provide precise fault address */
2678 return ret;
2679 }
2680
2681 return load_state_from_tss16(ctxt, &tss_seg);
2682 }
2683
2684 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2685 struct tss_segment_32 *tss)
2686 {
2687 tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2688 tss->eip = ctxt->_eip;
2689 tss->eflags = ctxt->eflags;
2690 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2691 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2692 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2693 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2694 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2695 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2696 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2697 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2698
2699 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2700 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2701 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2702 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2703 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2704 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2705 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2706 }
2707
2708 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2709 struct tss_segment_32 *tss)
2710 {
2711 int ret;
2712
2713 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2714 return emulate_gp(ctxt, 0);
2715 ctxt->_eip = tss->eip;
2716 ctxt->eflags = tss->eflags | 2;
2717
2718 /* General purpose registers */
2719 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2720 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2721 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2722 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2723 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2724 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2725 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2726 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2727
2728 /*
2729 * SDM says that segment selectors are loaded before segment
2730 * descriptors
2731 */
2732 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2733 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2734 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2735 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2736 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2737 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2738 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2739
2740 /*
2741 * If we're switching between Protected Mode and VM86, we need to make
2742 * sure to update the mode before loading the segment descriptors so
2743 * that the selectors are interpreted correctly.
2744 *
2745 * Need to get rflags to the vcpu struct immediately because it
2746 * influences the CPL which is checked at least when loading the segment
2747 * descriptors and when pushing an error code to the new kernel stack.
2748 *
2749 * TODO Introduce a separate ctxt->ops->set_cpl callback
2750 */
2751 if (ctxt->eflags & X86_EFLAGS_VM)
2752 ctxt->mode = X86EMUL_MODE_VM86;
2753 else
2754 ctxt->mode = X86EMUL_MODE_PROT32;
2755
2756 ctxt->ops->set_rflags(ctxt, ctxt->eflags);
2757
2758 /*
2759 * Now load segment descriptors. If fault happenes at this stage
2760 * it is handled in a context of new task
2761 */
2762 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2763 if (ret != X86EMUL_CONTINUE)
2764 return ret;
2765 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2766 if (ret != X86EMUL_CONTINUE)
2767 return ret;
2768 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2769 if (ret != X86EMUL_CONTINUE)
2770 return ret;
2771 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2772 if (ret != X86EMUL_CONTINUE)
2773 return ret;
2774 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2775 if (ret != X86EMUL_CONTINUE)
2776 return ret;
2777 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2778 if (ret != X86EMUL_CONTINUE)
2779 return ret;
2780 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2781 if (ret != X86EMUL_CONTINUE)
2782 return ret;
2783
2784 return X86EMUL_CONTINUE;
2785 }
2786
2787 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2788 u16 tss_selector, u16 old_tss_sel,
2789 ulong old_tss_base, struct desc_struct *new_desc)
2790 {
2791 const struct x86_emulate_ops *ops = ctxt->ops;
2792 struct tss_segment_32 tss_seg;
2793 int ret;
2794 u32 new_tss_base = get_desc_base(new_desc);
2795
2796 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2797 &ctxt->exception);
2798 if (ret != X86EMUL_CONTINUE)
2799 /* FIXME: need to provide precise fault address */
2800 return ret;
2801
2802 save_state_to_tss32(ctxt, &tss_seg);
2803
2804 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2805 &ctxt->exception);
2806 if (ret != X86EMUL_CONTINUE)
2807 /* FIXME: need to provide precise fault address */
2808 return ret;
2809
2810 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2811 &ctxt->exception);
2812 if (ret != X86EMUL_CONTINUE)
2813 /* FIXME: need to provide precise fault address */
2814 return ret;
2815
2816 if (old_tss_sel != 0xffff) {
2817 tss_seg.prev_task_link = old_tss_sel;
2818
2819 ret = ops->write_std(ctxt, new_tss_base,
2820 &tss_seg.prev_task_link,
2821 sizeof tss_seg.prev_task_link,
2822 &ctxt->exception);
2823 if (ret != X86EMUL_CONTINUE)
2824 /* FIXME: need to provide precise fault address */
2825 return ret;
2826 }
2827
2828 return load_state_from_tss32(ctxt, &tss_seg);
2829 }
2830
2831 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2832 u16 tss_selector, int idt_index, int reason,
2833 bool has_error_code, u32 error_code)
2834 {
2835 const struct x86_emulate_ops *ops = ctxt->ops;
2836 struct desc_struct curr_tss_desc, next_tss_desc;
2837 int ret;
2838 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2839 ulong old_tss_base =
2840 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2841 u32 desc_limit;
2842 ulong desc_addr;
2843
2844 /* FIXME: old_tss_base == ~0 ? */
2845
2846 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2847 if (ret != X86EMUL_CONTINUE)
2848 return ret;
2849 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2850 if (ret != X86EMUL_CONTINUE)
2851 return ret;
2852
2853 /* FIXME: check that next_tss_desc is tss */
2854
2855 /*
2856 * Check privileges. The three cases are task switch caused by...
2857 *
2858 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2859 * 2. Exception/IRQ/iret: No check is performed
2860 * 3. jmp/call to TSS: Check against DPL of the TSS
2861 */
2862 if (reason == TASK_SWITCH_GATE) {
2863 if (idt_index != -1) {
2864 /* Software interrupts */
2865 struct desc_struct task_gate_desc;
2866 int dpl;
2867
2868 ret = read_interrupt_descriptor(ctxt, idt_index,
2869 &task_gate_desc);
2870 if (ret != X86EMUL_CONTINUE)
2871 return ret;
2872
2873 dpl = task_gate_desc.dpl;
2874 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2875 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2876 }
2877 } else if (reason != TASK_SWITCH_IRET) {
2878 int dpl = next_tss_desc.dpl;
2879 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2880 return emulate_gp(ctxt, tss_selector);
2881 }
2882
2883
2884 desc_limit = desc_limit_scaled(&next_tss_desc);
2885 if (!next_tss_desc.p ||
2886 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2887 desc_limit < 0x2b)) {
2888 emulate_ts(ctxt, tss_selector & 0xfffc);
2889 return X86EMUL_PROPAGATE_FAULT;
2890 }
2891
2892 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2893 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2894 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2895 }
2896
2897 if (reason == TASK_SWITCH_IRET)
2898 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2899
2900 /* set back link to prev task only if NT bit is set in eflags
2901 note that old_tss_sel is not used after this point */
2902 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2903 old_tss_sel = 0xffff;
2904
2905 if (next_tss_desc.type & 8)
2906 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2907 old_tss_base, &next_tss_desc);
2908 else
2909 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2910 old_tss_base, &next_tss_desc);
2911 if (ret != X86EMUL_CONTINUE)
2912 return ret;
2913
2914 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2915 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2916
2917 if (reason != TASK_SWITCH_IRET) {
2918 next_tss_desc.type |= (1 << 1); /* set busy flag */
2919 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2920 }
2921
2922 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2923 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2924
2925 if (has_error_code) {
2926 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2927 ctxt->lock_prefix = 0;
2928 ctxt->src.val = (unsigned long) error_code;
2929 ret = em_push(ctxt);
2930 }
2931
2932 return ret;
2933 }
2934
2935 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2936 u16 tss_selector, int idt_index, int reason,
2937 bool has_error_code, u32 error_code)
2938 {
2939 int rc;
2940
2941 invalidate_registers(ctxt);
2942 ctxt->_eip = ctxt->eip;
2943 ctxt->dst.type = OP_NONE;
2944
2945 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2946 has_error_code, error_code);
2947
2948 if (rc == X86EMUL_CONTINUE) {
2949 ctxt->eip = ctxt->_eip;
2950 writeback_registers(ctxt);
2951 }
2952
2953 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2954 }
2955
2956 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2957 struct operand *op)
2958 {
2959 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2960
2961 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
2962 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2963 }
2964
2965 static int em_das(struct x86_emulate_ctxt *ctxt)
2966 {
2967 u8 al, old_al;
2968 bool af, cf, old_cf;
2969
2970 cf = ctxt->eflags & X86_EFLAGS_CF;
2971 al = ctxt->dst.val;
2972
2973 old_al = al;
2974 old_cf = cf;
2975 cf = false;
2976 af = ctxt->eflags & X86_EFLAGS_AF;
2977 if ((al & 0x0f) > 9 || af) {
2978 al -= 6;
2979 cf = old_cf | (al >= 250);
2980 af = true;
2981 } else {
2982 af = false;
2983 }
2984 if (old_al > 0x99 || old_cf) {
2985 al -= 0x60;
2986 cf = true;
2987 }
2988
2989 ctxt->dst.val = al;
2990 /* Set PF, ZF, SF */
2991 ctxt->src.type = OP_IMM;
2992 ctxt->src.val = 0;
2993 ctxt->src.bytes = 1;
2994 fastop(ctxt, em_or);
2995 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2996 if (cf)
2997 ctxt->eflags |= X86_EFLAGS_CF;
2998 if (af)
2999 ctxt->eflags |= X86_EFLAGS_AF;
3000 return X86EMUL_CONTINUE;
3001 }
3002
3003 static int em_aam(struct x86_emulate_ctxt *ctxt)
3004 {
3005 u8 al, ah;
3006
3007 if (ctxt->src.val == 0)
3008 return emulate_de(ctxt);
3009
3010 al = ctxt->dst.val & 0xff;
3011 ah = al / ctxt->src.val;
3012 al %= ctxt->src.val;
3013
3014 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3015
3016 /* Set PF, ZF, SF */
3017 ctxt->src.type = OP_IMM;
3018 ctxt->src.val = 0;
3019 ctxt->src.bytes = 1;
3020 fastop(ctxt, em_or);
3021
3022 return X86EMUL_CONTINUE;
3023 }
3024
3025 static int em_aad(struct x86_emulate_ctxt *ctxt)
3026 {
3027 u8 al = ctxt->dst.val & 0xff;
3028 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3029
3030 al = (al + (ah * ctxt->src.val)) & 0xff;
3031
3032 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3033
3034 /* Set PF, ZF, SF */
3035 ctxt->src.type = OP_IMM;
3036 ctxt->src.val = 0;
3037 ctxt->src.bytes = 1;
3038 fastop(ctxt, em_or);
3039
3040 return X86EMUL_CONTINUE;
3041 }
3042
3043 static int em_call(struct x86_emulate_ctxt *ctxt)
3044 {
3045 long rel = ctxt->src.val;
3046
3047 ctxt->src.val = (unsigned long)ctxt->_eip;
3048 jmp_rel(ctxt, rel);
3049 return em_push(ctxt);
3050 }
3051
3052 static int em_call_far(struct x86_emulate_ctxt *ctxt)
3053 {
3054 u16 sel, old_cs;
3055 ulong old_eip;
3056 int rc;
3057
3058 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3059 old_eip = ctxt->_eip;
3060
3061 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3062 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
3063 return X86EMUL_CONTINUE;
3064
3065 ctxt->_eip = 0;
3066 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
3067
3068 ctxt->src.val = old_cs;
3069 rc = em_push(ctxt);
3070 if (rc != X86EMUL_CONTINUE)
3071 return rc;
3072
3073 ctxt->src.val = old_eip;
3074 return em_push(ctxt);
3075 }
3076
3077 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3078 {
3079 int rc;
3080
3081 ctxt->dst.type = OP_REG;
3082 ctxt->dst.addr.reg = &ctxt->_eip;
3083 ctxt->dst.bytes = ctxt->op_bytes;
3084 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
3085 if (rc != X86EMUL_CONTINUE)
3086 return rc;
3087 rsp_increment(ctxt, ctxt->src.val);
3088 return X86EMUL_CONTINUE;
3089 }
3090
3091 static int em_xchg(struct x86_emulate_ctxt *ctxt)
3092 {
3093 /* Write back the register source. */
3094 ctxt->src.val = ctxt->dst.val;
3095 write_register_operand(&ctxt->src);
3096
3097 /* Write back the memory destination with implicit LOCK prefix. */
3098 ctxt->dst.val = ctxt->src.orig_val;
3099 ctxt->lock_prefix = 1;
3100 return X86EMUL_CONTINUE;
3101 }
3102
3103 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3104 {
3105 ctxt->dst.val = ctxt->src2.val;
3106 return fastop(ctxt, em_imul);
3107 }
3108
3109 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3110 {
3111 ctxt->dst.type = OP_REG;
3112 ctxt->dst.bytes = ctxt->src.bytes;
3113 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3114 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3115
3116 return X86EMUL_CONTINUE;
3117 }
3118
3119 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3120 {
3121 u64 tsc = 0;
3122
3123 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3124 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3125 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3126 return X86EMUL_CONTINUE;
3127 }
3128
3129 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3130 {
3131 u64 pmc;
3132
3133 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3134 return emulate_gp(ctxt, 0);
3135 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3136 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3137 return X86EMUL_CONTINUE;
3138 }
3139
3140 static int em_mov(struct x86_emulate_ctxt *ctxt)
3141 {
3142 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
3143 return X86EMUL_CONTINUE;
3144 }
3145
3146 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3147 {
3148 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3149 return emulate_gp(ctxt, 0);
3150
3151 /* Disable writeback. */
3152 ctxt->dst.type = OP_NONE;
3153 return X86EMUL_CONTINUE;
3154 }
3155
3156 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3157 {
3158 unsigned long val;
3159
3160 if (ctxt->mode == X86EMUL_MODE_PROT64)
3161 val = ctxt->src.val & ~0ULL;
3162 else
3163 val = ctxt->src.val & ~0U;
3164
3165 /* #UD condition is already handled. */
3166 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3167 return emulate_gp(ctxt, 0);
3168
3169 /* Disable writeback. */
3170 ctxt->dst.type = OP_NONE;
3171 return X86EMUL_CONTINUE;
3172 }
3173
3174 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3175 {
3176 u64 msr_data;
3177
3178 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3179 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3180 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3181 return emulate_gp(ctxt, 0);
3182
3183 return X86EMUL_CONTINUE;
3184 }
3185
3186 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3187 {
3188 u64 msr_data;
3189
3190 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3191 return emulate_gp(ctxt, 0);
3192
3193 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3194 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3195 return X86EMUL_CONTINUE;
3196 }
3197
3198 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3199 {
3200 if (ctxt->modrm_reg > VCPU_SREG_GS)
3201 return emulate_ud(ctxt);
3202
3203 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3204 return X86EMUL_CONTINUE;
3205 }
3206
3207 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3208 {
3209 u16 sel = ctxt->src.val;
3210
3211 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3212 return emulate_ud(ctxt);
3213
3214 if (ctxt->modrm_reg == VCPU_SREG_SS)
3215 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3216
3217 /* Disable writeback. */
3218 ctxt->dst.type = OP_NONE;
3219 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3220 }
3221
3222 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3223 {
3224 u16 sel = ctxt->src.val;
3225
3226 /* Disable writeback. */
3227 ctxt->dst.type = OP_NONE;
3228 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3229 }
3230
3231 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3232 {
3233 u16 sel = ctxt->src.val;
3234
3235 /* Disable writeback. */
3236 ctxt->dst.type = OP_NONE;
3237 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3238 }
3239
3240 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3241 {
3242 int rc;
3243 ulong linear;
3244
3245 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3246 if (rc == X86EMUL_CONTINUE)
3247 ctxt->ops->invlpg(ctxt, linear);
3248 /* Disable writeback. */
3249 ctxt->dst.type = OP_NONE;
3250 return X86EMUL_CONTINUE;
3251 }
3252
3253 static int em_clts(struct x86_emulate_ctxt *ctxt)
3254 {
3255 ulong cr0;
3256
3257 cr0 = ctxt->ops->get_cr(ctxt, 0);
3258 cr0 &= ~X86_CR0_TS;
3259 ctxt->ops->set_cr(ctxt, 0, cr0);
3260 return X86EMUL_CONTINUE;
3261 }
3262
3263 static int em_vmcall(struct x86_emulate_ctxt *ctxt)
3264 {
3265 int rc;
3266
3267 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3268 return X86EMUL_UNHANDLEABLE;
3269
3270 rc = ctxt->ops->fix_hypercall(ctxt);
3271 if (rc != X86EMUL_CONTINUE)
3272 return rc;
3273
3274 /* Let the processor re-execute the fixed hypercall */
3275 ctxt->_eip = ctxt->eip;
3276 /* Disable writeback. */
3277 ctxt->dst.type = OP_NONE;
3278 return X86EMUL_CONTINUE;
3279 }
3280
3281 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3282 void (*get)(struct x86_emulate_ctxt *ctxt,
3283 struct desc_ptr *ptr))
3284 {
3285 struct desc_ptr desc_ptr;
3286
3287 if (ctxt->mode == X86EMUL_MODE_PROT64)
3288 ctxt->op_bytes = 8;
3289 get(ctxt, &desc_ptr);
3290 if (ctxt->op_bytes == 2) {
3291 ctxt->op_bytes = 4;
3292 desc_ptr.address &= 0x00ffffff;
3293 }
3294 /* Disable writeback. */
3295 ctxt->dst.type = OP_NONE;
3296 return segmented_write(ctxt, ctxt->dst.addr.mem,
3297 &desc_ptr, 2 + ctxt->op_bytes);
3298 }
3299
3300 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3301 {
3302 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3303 }
3304
3305 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3306 {
3307 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3308 }
3309
3310 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3311 {
3312 struct desc_ptr desc_ptr;
3313 int rc;
3314
3315 if (ctxt->mode == X86EMUL_MODE_PROT64)
3316 ctxt->op_bytes = 8;
3317 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3318 &desc_ptr.size, &desc_ptr.address,
3319 ctxt->op_bytes);
3320 if (rc != X86EMUL_CONTINUE)
3321 return rc;
3322 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3323 /* Disable writeback. */
3324 ctxt->dst.type = OP_NONE;
3325 return X86EMUL_CONTINUE;
3326 }
3327
3328 static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3329 {
3330 int rc;
3331
3332 rc = ctxt->ops->fix_hypercall(ctxt);
3333
3334 /* Disable writeback. */
3335 ctxt->dst.type = OP_NONE;
3336 return rc;
3337 }
3338
3339 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3340 {
3341 struct desc_ptr desc_ptr;
3342 int rc;
3343
3344 if (ctxt->mode == X86EMUL_MODE_PROT64)
3345 ctxt->op_bytes = 8;
3346 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3347 &desc_ptr.size, &desc_ptr.address,
3348 ctxt->op_bytes);
3349 if (rc != X86EMUL_CONTINUE)
3350 return rc;
3351 ctxt->ops->set_idt(ctxt, &desc_ptr);
3352 /* Disable writeback. */
3353 ctxt->dst.type = OP_NONE;
3354 return X86EMUL_CONTINUE;
3355 }
3356
3357 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3358 {
3359 ctxt->dst.bytes = 2;
3360 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3361 return X86EMUL_CONTINUE;
3362 }
3363
3364 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3365 {
3366 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3367 | (ctxt->src.val & 0x0f));
3368 ctxt->dst.type = OP_NONE;
3369 return X86EMUL_CONTINUE;
3370 }
3371
3372 static int em_loop(struct x86_emulate_ctxt *ctxt)
3373 {
3374 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
3375 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3376 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3377 jmp_rel(ctxt, ctxt->src.val);
3378
3379 return X86EMUL_CONTINUE;
3380 }
3381
3382 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3383 {
3384 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3385 jmp_rel(ctxt, ctxt->src.val);
3386
3387 return X86EMUL_CONTINUE;
3388 }
3389
3390 static int em_in(struct x86_emulate_ctxt *ctxt)
3391 {
3392 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3393 &ctxt->dst.val))
3394 return X86EMUL_IO_NEEDED;
3395
3396 return X86EMUL_CONTINUE;
3397 }
3398
3399 static int em_out(struct x86_emulate_ctxt *ctxt)
3400 {
3401 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3402 &ctxt->src.val, 1);
3403 /* Disable writeback. */
3404 ctxt->dst.type = OP_NONE;
3405 return X86EMUL_CONTINUE;
3406 }
3407
3408 static int em_cli(struct x86_emulate_ctxt *ctxt)
3409 {
3410 if (emulator_bad_iopl(ctxt))
3411 return emulate_gp(ctxt, 0);
3412
3413 ctxt->eflags &= ~X86_EFLAGS_IF;
3414 return X86EMUL_CONTINUE;
3415 }
3416
3417 static int em_sti(struct x86_emulate_ctxt *ctxt)
3418 {
3419 if (emulator_bad_iopl(ctxt))
3420 return emulate_gp(ctxt, 0);
3421
3422 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3423 ctxt->eflags |= X86_EFLAGS_IF;
3424 return X86EMUL_CONTINUE;
3425 }
3426
3427 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3428 {
3429 u32 eax, ebx, ecx, edx;
3430
3431 eax = reg_read(ctxt, VCPU_REGS_RAX);
3432 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3433 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3434 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3435 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3436 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3437 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3438 return X86EMUL_CONTINUE;
3439 }
3440
3441 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3442 {
3443 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3444 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3445 return X86EMUL_CONTINUE;
3446 }
3447
3448 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3449 {
3450 switch (ctxt->op_bytes) {
3451 #ifdef CONFIG_X86_64
3452 case 8:
3453 asm("bswap %0" : "+r"(ctxt->dst.val));
3454 break;
3455 #endif
3456 default:
3457 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3458 break;
3459 }
3460 return X86EMUL_CONTINUE;
3461 }
3462
3463 static bool valid_cr(int nr)
3464 {
3465 switch (nr) {
3466 case 0:
3467 case 2 ... 4:
3468 case 8:
3469 return true;
3470 default:
3471 return false;
3472 }
3473 }
3474
3475 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3476 {
3477 if (!valid_cr(ctxt->modrm_reg))
3478 return emulate_ud(ctxt);
3479
3480 return X86EMUL_CONTINUE;
3481 }
3482
3483 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3484 {
3485 u64 new_val = ctxt->src.val64;
3486 int cr = ctxt->modrm_reg;
3487 u64 efer = 0;
3488
3489 static u64 cr_reserved_bits[] = {
3490 0xffffffff00000000ULL,
3491 0, 0, 0, /* CR3 checked later */
3492 CR4_RESERVED_BITS,
3493 0, 0, 0,
3494 CR8_RESERVED_BITS,
3495 };
3496
3497 if (!valid_cr(cr))
3498 return emulate_ud(ctxt);
3499
3500 if (new_val & cr_reserved_bits[cr])
3501 return emulate_gp(ctxt, 0);
3502
3503 switch (cr) {
3504 case 0: {
3505 u64 cr4;
3506 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3507 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3508 return emulate_gp(ctxt, 0);
3509
3510 cr4 = ctxt->ops->get_cr(ctxt, 4);
3511 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3512
3513 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3514 !(cr4 & X86_CR4_PAE))
3515 return emulate_gp(ctxt, 0);
3516
3517 break;
3518 }
3519 case 3: {
3520 u64 rsvd = 0;
3521
3522 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3523 if (efer & EFER_LMA)
3524 rsvd = CR3_L_MODE_RESERVED_BITS;
3525 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
3526 rsvd = CR3_PAE_RESERVED_BITS;
3527 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
3528 rsvd = CR3_NONPAE_RESERVED_BITS;
3529
3530 if (new_val & rsvd)
3531 return emulate_gp(ctxt, 0);
3532
3533 break;
3534 }
3535 case 4: {
3536 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3537
3538 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3539 return emulate_gp(ctxt, 0);
3540
3541 break;
3542 }
3543 }
3544
3545 return X86EMUL_CONTINUE;
3546 }
3547
3548 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3549 {
3550 unsigned long dr7;
3551
3552 ctxt->ops->get_dr(ctxt, 7, &dr7);
3553
3554 /* Check if DR7.Global_Enable is set */
3555 return dr7 & (1 << 13);
3556 }
3557
3558 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3559 {
3560 int dr = ctxt->modrm_reg;
3561 u64 cr4;
3562
3563 if (dr > 7)
3564 return emulate_ud(ctxt);
3565
3566 cr4 = ctxt->ops->get_cr(ctxt, 4);
3567 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3568 return emulate_ud(ctxt);
3569
3570 if (check_dr7_gd(ctxt))
3571 return emulate_db(ctxt);
3572
3573 return X86EMUL_CONTINUE;
3574 }
3575
3576 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3577 {
3578 u64 new_val = ctxt->src.val64;
3579 int dr = ctxt->modrm_reg;
3580
3581 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3582 return emulate_gp(ctxt, 0);
3583
3584 return check_dr_read(ctxt);
3585 }
3586
3587 static int check_svme(struct x86_emulate_ctxt *ctxt)
3588 {
3589 u64 efer;
3590
3591 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3592
3593 if (!(efer & EFER_SVME))
3594 return emulate_ud(ctxt);
3595
3596 return X86EMUL_CONTINUE;
3597 }
3598
3599 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3600 {
3601 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3602
3603 /* Valid physical address? */
3604 if (rax & 0xffff000000000000ULL)
3605 return emulate_gp(ctxt, 0);
3606
3607 return check_svme(ctxt);
3608 }
3609
3610 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3611 {
3612 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3613
3614 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3615 return emulate_ud(ctxt);
3616
3617 return X86EMUL_CONTINUE;
3618 }
3619
3620 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3621 {
3622 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3623 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3624
3625 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3626 (rcx > 3))
3627 return emulate_gp(ctxt, 0);
3628
3629 return X86EMUL_CONTINUE;
3630 }
3631
3632 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3633 {
3634 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3635 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3636 return emulate_gp(ctxt, 0);
3637
3638 return X86EMUL_CONTINUE;
3639 }
3640
3641 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3642 {
3643 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3644 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3645 return emulate_gp(ctxt, 0);
3646
3647 return X86EMUL_CONTINUE;
3648 }
3649
3650 #define D(_y) { .flags = (_y) }
3651 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
3652 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
3653 .check_perm = (_p) }
3654 #define N D(NotImpl)
3655 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3656 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3657 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3658 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3659 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3660 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3661 #define II(_f, _e, _i) \
3662 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3663 #define IIP(_f, _e, _i, _p) \
3664 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
3665 .check_perm = (_p) }
3666 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3667
3668 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3669 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3670 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3671 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3672 #define I2bvIP(_f, _e, _i, _p) \
3673 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3674
3675 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3676 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3677 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3678
3679 static const struct opcode group7_rm1[] = {
3680 DI(SrcNone | Priv, monitor),
3681 DI(SrcNone | Priv, mwait),
3682 N, N, N, N, N, N,
3683 };
3684
3685 static const struct opcode group7_rm3[] = {
3686 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3687 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall),
3688 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3689 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3690 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3691 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3692 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3693 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3694 };
3695
3696 static const struct opcode group7_rm7[] = {
3697 N,
3698 DIP(SrcNone, rdtscp, check_rdtsc),
3699 N, N, N, N, N, N,
3700 };
3701
3702 static const struct opcode group1[] = {
3703 F(Lock, em_add),
3704 F(Lock | PageTable, em_or),
3705 F(Lock, em_adc),
3706 F(Lock, em_sbb),
3707 F(Lock | PageTable, em_and),
3708 F(Lock, em_sub),
3709 F(Lock, em_xor),
3710 F(NoWrite, em_cmp),
3711 };
3712
3713 static const struct opcode group1A[] = {
3714 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3715 };
3716
3717 static const struct opcode group2[] = {
3718 F(DstMem | ModRM, em_rol),
3719 F(DstMem | ModRM, em_ror),
3720 F(DstMem | ModRM, em_rcl),
3721 F(DstMem | ModRM, em_rcr),
3722 F(DstMem | ModRM, em_shl),
3723 F(DstMem | ModRM, em_shr),
3724 F(DstMem | ModRM, em_shl),
3725 F(DstMem | ModRM, em_sar),
3726 };
3727
3728 static const struct opcode group3[] = {
3729 F(DstMem | SrcImm | NoWrite, em_test),
3730 F(DstMem | SrcImm | NoWrite, em_test),
3731 F(DstMem | SrcNone | Lock, em_not),
3732 F(DstMem | SrcNone | Lock, em_neg),
3733 F(DstXacc | Src2Mem, em_mul_ex),
3734 F(DstXacc | Src2Mem, em_imul_ex),
3735 F(DstXacc | Src2Mem, em_div_ex),
3736 F(DstXacc | Src2Mem, em_idiv_ex),
3737 };
3738
3739 static const struct opcode group4[] = {
3740 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3741 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3742 N, N, N, N, N, N,
3743 };
3744
3745 static const struct opcode group5[] = {
3746 F(DstMem | SrcNone | Lock, em_inc),
3747 F(DstMem | SrcNone | Lock, em_dec),
3748 I(SrcMem | Stack, em_grp45),
3749 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far),
3750 I(SrcMem | Stack, em_grp45),
3751 I(SrcMemFAddr | ImplicitOps, em_grp45),
3752 I(SrcMem | Stack, em_grp45), D(Undefined),
3753 };
3754
3755 static const struct opcode group6[] = {
3756 DI(Prot, sldt),
3757 DI(Prot, str),
3758 II(Prot | Priv | SrcMem16, em_lldt, lldt),
3759 II(Prot | Priv | SrcMem16, em_ltr, ltr),
3760 N, N, N, N,
3761 };
3762
3763 static const struct group_dual group7 = { {
3764 II(Mov | DstMem | Priv, em_sgdt, sgdt),
3765 II(Mov | DstMem | Priv, em_sidt, sidt),
3766 II(SrcMem | Priv, em_lgdt, lgdt),
3767 II(SrcMem | Priv, em_lidt, lidt),
3768 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3769 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3770 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3771 }, {
3772 I(SrcNone | Priv | VendorSpecific, em_vmcall),
3773 EXT(0, group7_rm1),
3774 N, EXT(0, group7_rm3),
3775 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3776 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3777 EXT(0, group7_rm7),
3778 } };
3779
3780 static const struct opcode group8[] = {
3781 N, N, N, N,
3782 F(DstMem | SrcImmByte | NoWrite, em_bt),
3783 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3784 F(DstMem | SrcImmByte | Lock, em_btr),
3785 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3786 };
3787
3788 static const struct group_dual group9 = { {
3789 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3790 }, {
3791 N, N, N, N, N, N, N, N,
3792 } };
3793
3794 static const struct opcode group11[] = {
3795 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3796 X7(D(Undefined)),
3797 };
3798
3799 static const struct gprefix pfx_0f_6f_0f_7f = {
3800 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3801 };
3802
3803 static const struct gprefix pfx_vmovntpx = {
3804 I(0, em_mov), N, N, N,
3805 };
3806
3807 static const struct escape escape_d9 = { {
3808 N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
3809 }, {
3810 /* 0xC0 - 0xC7 */
3811 N, N, N, N, N, N, N, N,
3812 /* 0xC8 - 0xCF */
3813 N, N, N, N, N, N, N, N,
3814 /* 0xD0 - 0xC7 */
3815 N, N, N, N, N, N, N, N,
3816 /* 0xD8 - 0xDF */
3817 N, N, N, N, N, N, N, N,
3818 /* 0xE0 - 0xE7 */
3819 N, N, N, N, N, N, N, N,
3820 /* 0xE8 - 0xEF */
3821 N, N, N, N, N, N, N, N,
3822 /* 0xF0 - 0xF7 */
3823 N, N, N, N, N, N, N, N,
3824 /* 0xF8 - 0xFF */
3825 N, N, N, N, N, N, N, N,
3826 } };
3827
3828 static const struct escape escape_db = { {
3829 N, N, N, N, N, N, N, N,
3830 }, {
3831 /* 0xC0 - 0xC7 */
3832 N, N, N, N, N, N, N, N,
3833 /* 0xC8 - 0xCF */
3834 N, N, N, N, N, N, N, N,
3835 /* 0xD0 - 0xC7 */
3836 N, N, N, N, N, N, N, N,
3837 /* 0xD8 - 0xDF */
3838 N, N, N, N, N, N, N, N,
3839 /* 0xE0 - 0xE7 */
3840 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3841 /* 0xE8 - 0xEF */
3842 N, N, N, N, N, N, N, N,
3843 /* 0xF0 - 0xF7 */
3844 N, N, N, N, N, N, N, N,
3845 /* 0xF8 - 0xFF */
3846 N, N, N, N, N, N, N, N,
3847 } };
3848
3849 static const struct escape escape_dd = { {
3850 N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
3851 }, {
3852 /* 0xC0 - 0xC7 */
3853 N, N, N, N, N, N, N, N,
3854 /* 0xC8 - 0xCF */
3855 N, N, N, N, N, N, N, N,
3856 /* 0xD0 - 0xC7 */
3857 N, N, N, N, N, N, N, N,
3858 /* 0xD8 - 0xDF */
3859 N, N, N, N, N, N, N, N,
3860 /* 0xE0 - 0xE7 */
3861 N, N, N, N, N, N, N, N,
3862 /* 0xE8 - 0xEF */
3863 N, N, N, N, N, N, N, N,
3864 /* 0xF0 - 0xF7 */
3865 N, N, N, N, N, N, N, N,
3866 /* 0xF8 - 0xFF */
3867 N, N, N, N, N, N, N, N,
3868 } };
3869
3870 static const struct opcode opcode_table[256] = {
3871 /* 0x00 - 0x07 */
3872 F6ALU(Lock, em_add),
3873 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
3874 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3875 /* 0x08 - 0x0F */
3876 F6ALU(Lock | PageTable, em_or),
3877 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
3878 N,
3879 /* 0x10 - 0x17 */
3880 F6ALU(Lock, em_adc),
3881 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
3882 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3883 /* 0x18 - 0x1F */
3884 F6ALU(Lock, em_sbb),
3885 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
3886 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3887 /* 0x20 - 0x27 */
3888 F6ALU(Lock | PageTable, em_and), N, N,
3889 /* 0x28 - 0x2F */
3890 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3891 /* 0x30 - 0x37 */
3892 F6ALU(Lock, em_xor), N, N,
3893 /* 0x38 - 0x3F */
3894 F6ALU(NoWrite, em_cmp), N, N,
3895 /* 0x40 - 0x4F */
3896 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3897 /* 0x50 - 0x57 */
3898 X8(I(SrcReg | Stack, em_push)),
3899 /* 0x58 - 0x5F */
3900 X8(I(DstReg | Stack, em_pop)),
3901 /* 0x60 - 0x67 */
3902 I(ImplicitOps | Stack | No64, em_pusha),
3903 I(ImplicitOps | Stack | No64, em_popa),
3904 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
3905 N, N, N, N,
3906 /* 0x68 - 0x6F */
3907 I(SrcImm | Mov | Stack, em_push),
3908 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3909 I(SrcImmByte | Mov | Stack, em_push),
3910 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3911 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3912 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3913 /* 0x70 - 0x7F */
3914 X16(D(SrcImmByte)),
3915 /* 0x80 - 0x87 */
3916 G(ByteOp | DstMem | SrcImm, group1),
3917 G(DstMem | SrcImm, group1),
3918 G(ByteOp | DstMem | SrcImm | No64, group1),
3919 G(DstMem | SrcImmByte, group1),
3920 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3921 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3922 /* 0x88 - 0x8F */
3923 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3924 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3925 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3926 D(ModRM | SrcMem | NoAccess | DstReg),
3927 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
3928 G(0, group1A),
3929 /* 0x90 - 0x97 */
3930 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3931 /* 0x98 - 0x9F */
3932 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3933 I(SrcImmFAddr | No64, em_call_far), N,
3934 II(ImplicitOps | Stack, em_pushf, pushf),
3935 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
3936 /* 0xA0 - 0xA7 */
3937 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3938 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3939 I2bv(SrcSI | DstDI | Mov | String, em_mov),
3940 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3941 /* 0xA8 - 0xAF */
3942 F2bv(DstAcc | SrcImm | NoWrite, em_test),
3943 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
3944 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3945 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3946 /* 0xB0 - 0xB7 */
3947 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3948 /* 0xB8 - 0xBF */
3949 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3950 /* 0xC0 - 0xC7 */
3951 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3952 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3953 I(ImplicitOps | Stack, em_ret),
3954 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
3955 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3956 G(ByteOp, group11), G(0, group11),
3957 /* 0xC8 - 0xCF */
3958 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3959 N, I(ImplicitOps | Stack, em_ret_far),
3960 D(ImplicitOps), DI(SrcImmByte, intn),
3961 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3962 /* 0xD0 - 0xD7 */
3963 G(Src2One | ByteOp, group2), G(Src2One, group2),
3964 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
3965 I(DstAcc | SrcImmUByte | No64, em_aam),
3966 I(DstAcc | SrcImmUByte | No64, em_aad),
3967 F(DstAcc | ByteOp | No64, em_salc),
3968 I(DstAcc | SrcXLat | ByteOp, em_mov),
3969 /* 0xD8 - 0xDF */
3970 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
3971 /* 0xE0 - 0xE7 */
3972 X3(I(SrcImmByte, em_loop)),
3973 I(SrcImmByte, em_jcxz),
3974 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
3975 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3976 /* 0xE8 - 0xEF */
3977 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
3978 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3979 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
3980 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3981 /* 0xF0 - 0xF7 */
3982 N, DI(ImplicitOps, icebp), N, N,
3983 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
3984 G(ByteOp, group3), G(0, group3),
3985 /* 0xF8 - 0xFF */
3986 D(ImplicitOps), D(ImplicitOps),
3987 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3988 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
3989 };
3990
3991 static const struct opcode twobyte_table[256] = {
3992 /* 0x00 - 0x0F */
3993 G(0, group6), GD(0, &group7), N, N,
3994 N, I(ImplicitOps | VendorSpecific, em_syscall),
3995 II(ImplicitOps | Priv, em_clts, clts), N,
3996 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3997 N, D(ImplicitOps | ModRM), N, N,
3998 /* 0x10 - 0x1F */
3999 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
4000 /* 0x20 - 0x2F */
4001 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
4002 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
4003 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
4004 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
4005 N, N, N, N,
4006 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
4007 N, N, N, N,
4008 /* 0x30 - 0x3F */
4009 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4010 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4011 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4012 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4013 I(ImplicitOps | VendorSpecific, em_sysenter),
4014 I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
4015 N, N,
4016 N, N, N, N, N, N, N, N,
4017 /* 0x40 - 0x4F */
4018 X16(D(DstReg | SrcMem | ModRM | Mov)),
4019 /* 0x50 - 0x5F */
4020 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4021 /* 0x60 - 0x6F */
4022 N, N, N, N,
4023 N, N, N, N,
4024 N, N, N, N,
4025 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4026 /* 0x70 - 0x7F */
4027 N, N, N, N,
4028 N, N, N, N,
4029 N, N, N, N,
4030 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4031 /* 0x80 - 0x8F */
4032 X16(D(SrcImm)),
4033 /* 0x90 - 0x9F */
4034 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4035 /* 0xA0 - 0xA7 */
4036 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4037 II(ImplicitOps, em_cpuid, cpuid),
4038 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4039 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4040 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4041 /* 0xA8 - 0xAF */
4042 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4043 DI(ImplicitOps, rsm),
4044 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4045 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4046 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4047 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
4048 /* 0xB0 - 0xB7 */
4049 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
4050 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4051 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4052 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4053 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4054 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4055 /* 0xB8 - 0xBF */
4056 N, N,
4057 G(BitOp, group8),
4058 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4059 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
4060 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4061 /* 0xC0 - 0xC7 */
4062 D2bv(DstMem | SrcReg | ModRM | Lock),
4063 N, D(DstMem | SrcReg | ModRM | Mov),
4064 N, N, N, GD(0, &group9),
4065 /* 0xC8 - 0xCF */
4066 X8(I(DstReg, em_bswap)),
4067 /* 0xD0 - 0xDF */
4068 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4069 /* 0xE0 - 0xEF */
4070 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4071 /* 0xF0 - 0xFF */
4072 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4073 };
4074
4075 #undef D
4076 #undef N
4077 #undef G
4078 #undef GD
4079 #undef I
4080 #undef GP
4081 #undef EXT
4082
4083 #undef D2bv
4084 #undef D2bvIP
4085 #undef I2bv
4086 #undef I2bvIP
4087 #undef I6ALU
4088
4089 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4090 {
4091 unsigned size;
4092
4093 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4094 if (size == 8)
4095 size = 4;
4096 return size;
4097 }
4098
4099 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4100 unsigned size, bool sign_extension)
4101 {
4102 int rc = X86EMUL_CONTINUE;
4103
4104 op->type = OP_IMM;
4105 op->bytes = size;
4106 op->addr.mem.ea = ctxt->_eip;
4107 /* NB. Immediates are sign-extended as necessary. */
4108 switch (op->bytes) {
4109 case 1:
4110 op->val = insn_fetch(s8, ctxt);
4111 break;
4112 case 2:
4113 op->val = insn_fetch(s16, ctxt);
4114 break;
4115 case 4:
4116 op->val = insn_fetch(s32, ctxt);
4117 break;
4118 case 8:
4119 op->val = insn_fetch(s64, ctxt);
4120 break;
4121 }
4122 if (!sign_extension) {
4123 switch (op->bytes) {
4124 case 1:
4125 op->val &= 0xff;
4126 break;
4127 case 2:
4128 op->val &= 0xffff;
4129 break;
4130 case 4:
4131 op->val &= 0xffffffff;
4132 break;
4133 }
4134 }
4135 done:
4136 return rc;
4137 }
4138
4139 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4140 unsigned d)
4141 {
4142 int rc = X86EMUL_CONTINUE;
4143
4144 switch (d) {
4145 case OpReg:
4146 decode_register_operand(ctxt, op);
4147 break;
4148 case OpImmUByte:
4149 rc = decode_imm(ctxt, op, 1, false);
4150 break;
4151 case OpMem:
4152 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4153 mem_common:
4154 *op = ctxt->memop;
4155 ctxt->memopp = op;
4156 if ((ctxt->d & BitOp) && op == &ctxt->dst)
4157 fetch_bit_operand(ctxt);
4158 op->orig_val = op->val;
4159 break;
4160 case OpMem64:
4161 ctxt->memop.bytes = 8;
4162 goto mem_common;
4163 case OpAcc:
4164 op->type = OP_REG;
4165 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4166 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4167 fetch_register_operand(op);
4168 op->orig_val = op->val;
4169 break;
4170 case OpAccLo:
4171 op->type = OP_REG;
4172 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4173 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4174 fetch_register_operand(op);
4175 op->orig_val = op->val;
4176 break;
4177 case OpAccHi:
4178 if (ctxt->d & ByteOp) {
4179 op->type = OP_NONE;
4180 break;
4181 }
4182 op->type = OP_REG;
4183 op->bytes = ctxt->op_bytes;
4184 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4185 fetch_register_operand(op);
4186 op->orig_val = op->val;
4187 break;
4188 case OpDI:
4189 op->type = OP_MEM;
4190 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4191 op->addr.mem.ea =
4192 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4193 op->addr.mem.seg = VCPU_SREG_ES;
4194 op->val = 0;
4195 op->count = 1;
4196 break;
4197 case OpDX:
4198 op->type = OP_REG;
4199 op->bytes = 2;
4200 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4201 fetch_register_operand(op);
4202 break;
4203 case OpCL:
4204 op->bytes = 1;
4205 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4206 break;
4207 case OpImmByte:
4208 rc = decode_imm(ctxt, op, 1, true);
4209 break;
4210 case OpOne:
4211 op->bytes = 1;
4212 op->val = 1;
4213 break;
4214 case OpImm:
4215 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4216 break;
4217 case OpImm64:
4218 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4219 break;
4220 case OpMem8:
4221 ctxt->memop.bytes = 1;
4222 if (ctxt->memop.type == OP_REG) {
4223 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
4224 fetch_register_operand(&ctxt->memop);
4225 }
4226 goto mem_common;
4227 case OpMem16:
4228 ctxt->memop.bytes = 2;
4229 goto mem_common;
4230 case OpMem32:
4231 ctxt->memop.bytes = 4;
4232 goto mem_common;
4233 case OpImmU16:
4234 rc = decode_imm(ctxt, op, 2, false);
4235 break;
4236 case OpImmU:
4237 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4238 break;
4239 case OpSI:
4240 op->type = OP_MEM;
4241 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4242 op->addr.mem.ea =
4243 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
4244 op->addr.mem.seg = seg_override(ctxt);
4245 op->val = 0;
4246 op->count = 1;
4247 break;
4248 case OpXLat:
4249 op->type = OP_MEM;
4250 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4251 op->addr.mem.ea =
4252 register_address(ctxt,
4253 reg_read(ctxt, VCPU_REGS_RBX) +
4254 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4255 op->addr.mem.seg = seg_override(ctxt);
4256 op->val = 0;
4257 break;
4258 case OpImmFAddr:
4259 op->type = OP_IMM;
4260 op->addr.mem.ea = ctxt->_eip;
4261 op->bytes = ctxt->op_bytes + 2;
4262 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4263 break;
4264 case OpMemFAddr:
4265 ctxt->memop.bytes = ctxt->op_bytes + 2;
4266 goto mem_common;
4267 case OpES:
4268 op->val = VCPU_SREG_ES;
4269 break;
4270 case OpCS:
4271 op->val = VCPU_SREG_CS;
4272 break;
4273 case OpSS:
4274 op->val = VCPU_SREG_SS;
4275 break;
4276 case OpDS:
4277 op->val = VCPU_SREG_DS;
4278 break;
4279 case OpFS:
4280 op->val = VCPU_SREG_FS;
4281 break;
4282 case OpGS:
4283 op->val = VCPU_SREG_GS;
4284 break;
4285 case OpImplicit:
4286 /* Special instructions do their own operand decoding. */
4287 default:
4288 op->type = OP_NONE; /* Disable writeback. */
4289 break;
4290 }
4291
4292 done:
4293 return rc;
4294 }
4295
4296 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4297 {
4298 int rc = X86EMUL_CONTINUE;
4299 int mode = ctxt->mode;
4300 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4301 bool op_prefix = false;
4302 struct opcode opcode;
4303
4304 ctxt->memop.type = OP_NONE;
4305 ctxt->memopp = NULL;
4306 ctxt->_eip = ctxt->eip;
4307 ctxt->fetch.start = ctxt->_eip;
4308 ctxt->fetch.end = ctxt->fetch.start + insn_len;
4309 if (insn_len > 0)
4310 memcpy(ctxt->fetch.data, insn, insn_len);
4311
4312 switch (mode) {
4313 case X86EMUL_MODE_REAL:
4314 case X86EMUL_MODE_VM86:
4315 case X86EMUL_MODE_PROT16:
4316 def_op_bytes = def_ad_bytes = 2;
4317 break;
4318 case X86EMUL_MODE_PROT32:
4319 def_op_bytes = def_ad_bytes = 4;
4320 break;
4321 #ifdef CONFIG_X86_64
4322 case X86EMUL_MODE_PROT64:
4323 def_op_bytes = 4;
4324 def_ad_bytes = 8;
4325 break;
4326 #endif
4327 default:
4328 return EMULATION_FAILED;
4329 }
4330
4331 ctxt->op_bytes = def_op_bytes;
4332 ctxt->ad_bytes = def_ad_bytes;
4333
4334 /* Legacy prefixes. */
4335 for (;;) {
4336 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4337 case 0x66: /* operand-size override */
4338 op_prefix = true;
4339 /* switch between 2/4 bytes */
4340 ctxt->op_bytes = def_op_bytes ^ 6;
4341 break;
4342 case 0x67: /* address-size override */
4343 if (mode == X86EMUL_MODE_PROT64)
4344 /* switch between 4/8 bytes */
4345 ctxt->ad_bytes = def_ad_bytes ^ 12;
4346 else
4347 /* switch between 2/4 bytes */
4348 ctxt->ad_bytes = def_ad_bytes ^ 6;
4349 break;
4350 case 0x26: /* ES override */
4351 case 0x2e: /* CS override */
4352 case 0x36: /* SS override */
4353 case 0x3e: /* DS override */
4354 set_seg_override(ctxt, (ctxt->b >> 3) & 3);
4355 break;
4356 case 0x64: /* FS override */
4357 case 0x65: /* GS override */
4358 set_seg_override(ctxt, ctxt->b & 7);
4359 break;
4360 case 0x40 ... 0x4f: /* REX */
4361 if (mode != X86EMUL_MODE_PROT64)
4362 goto done_prefixes;
4363 ctxt->rex_prefix = ctxt->b;
4364 continue;
4365 case 0xf0: /* LOCK */
4366 ctxt->lock_prefix = 1;
4367 break;
4368 case 0xf2: /* REPNE/REPNZ */
4369 case 0xf3: /* REP/REPE/REPZ */
4370 ctxt->rep_prefix = ctxt->b;
4371 break;
4372 default:
4373 goto done_prefixes;
4374 }
4375
4376 /* Any legacy prefix after a REX prefix nullifies its effect. */
4377
4378 ctxt->rex_prefix = 0;
4379 }
4380
4381 done_prefixes:
4382
4383 /* REX prefix. */
4384 if (ctxt->rex_prefix & 8)
4385 ctxt->op_bytes = 8; /* REX.W */
4386
4387 /* Opcode byte(s). */
4388 opcode = opcode_table[ctxt->b];
4389 /* Two-byte opcode? */
4390 if (ctxt->b == 0x0f) {
4391 ctxt->twobyte = 1;
4392 ctxt->b = insn_fetch(u8, ctxt);
4393 opcode = twobyte_table[ctxt->b];
4394 }
4395 ctxt->d = opcode.flags;
4396
4397 if (ctxt->d & ModRM)
4398 ctxt->modrm = insn_fetch(u8, ctxt);
4399
4400 while (ctxt->d & GroupMask) {
4401 switch (ctxt->d & GroupMask) {
4402 case Group:
4403 goffset = (ctxt->modrm >> 3) & 7;
4404 opcode = opcode.u.group[goffset];
4405 break;
4406 case GroupDual:
4407 goffset = (ctxt->modrm >> 3) & 7;
4408 if ((ctxt->modrm >> 6) == 3)
4409 opcode = opcode.u.gdual->mod3[goffset];
4410 else
4411 opcode = opcode.u.gdual->mod012[goffset];
4412 break;
4413 case RMExt:
4414 goffset = ctxt->modrm & 7;
4415 opcode = opcode.u.group[goffset];
4416 break;
4417 case Prefix:
4418 if (ctxt->rep_prefix && op_prefix)
4419 return EMULATION_FAILED;
4420 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4421 switch (simd_prefix) {
4422 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4423 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4424 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4425 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4426 }
4427 break;
4428 case Escape:
4429 if (ctxt->modrm > 0xbf)
4430 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4431 else
4432 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4433 break;
4434 default:
4435 return EMULATION_FAILED;
4436 }
4437
4438 ctxt->d &= ~(u64)GroupMask;
4439 ctxt->d |= opcode.flags;
4440 }
4441
4442 ctxt->execute = opcode.u.execute;
4443 ctxt->check_perm = opcode.check_perm;
4444 ctxt->intercept = opcode.intercept;
4445
4446 /* Unrecognised? */
4447 if (ctxt->d == 0 || (ctxt->d & NotImpl))
4448 return EMULATION_FAILED;
4449
4450 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
4451 return EMULATION_FAILED;
4452
4453 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4454 ctxt->op_bytes = 8;
4455
4456 if (ctxt->d & Op3264) {
4457 if (mode == X86EMUL_MODE_PROT64)
4458 ctxt->op_bytes = 8;
4459 else
4460 ctxt->op_bytes = 4;
4461 }
4462
4463 if (ctxt->d & Sse)
4464 ctxt->op_bytes = 16;
4465 else if (ctxt->d & Mmx)
4466 ctxt->op_bytes = 8;
4467
4468 /* ModRM and SIB bytes. */
4469 if (ctxt->d & ModRM) {
4470 rc = decode_modrm(ctxt, &ctxt->memop);
4471 if (!ctxt->has_seg_override)
4472 set_seg_override(ctxt, ctxt->modrm_seg);
4473 } else if (ctxt->d & MemAbs)
4474 rc = decode_abs(ctxt, &ctxt->memop);
4475 if (rc != X86EMUL_CONTINUE)
4476 goto done;
4477
4478 if (!ctxt->has_seg_override)
4479 set_seg_override(ctxt, VCPU_SREG_DS);
4480
4481 ctxt->memop.addr.mem.seg = seg_override(ctxt);
4482
4483 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
4484 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
4485
4486 /*
4487 * Decode and fetch the source operand: register, memory
4488 * or immediate.
4489 */
4490 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4491 if (rc != X86EMUL_CONTINUE)
4492 goto done;
4493
4494 /*
4495 * Decode and fetch the second source operand: register, memory
4496 * or immediate.
4497 */
4498 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4499 if (rc != X86EMUL_CONTINUE)
4500 goto done;
4501
4502 /* Decode and fetch the destination operand: register or memory. */
4503 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4504
4505 done:
4506 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
4507 ctxt->memopp->addr.mem.ea += ctxt->_eip;
4508
4509 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4510 }
4511
4512 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4513 {
4514 return ctxt->d & PageTable;
4515 }
4516
4517 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4518 {
4519 /* The second termination condition only applies for REPE
4520 * and REPNE. Test if the repeat string operation prefix is
4521 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4522 * corresponding termination condition according to:
4523 * - if REPE/REPZ and ZF = 0 then done
4524 * - if REPNE/REPNZ and ZF = 1 then done
4525 */
4526 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4527 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4528 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4529 ((ctxt->eflags & EFLG_ZF) == 0))
4530 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4531 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
4532 return true;
4533
4534 return false;
4535 }
4536
4537 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4538 {
4539 bool fault = false;
4540
4541 ctxt->ops->get_fpu(ctxt);
4542 asm volatile("1: fwait \n\t"
4543 "2: \n\t"
4544 ".pushsection .fixup,\"ax\" \n\t"
4545 "3: \n\t"
4546 "movb $1, %[fault] \n\t"
4547 "jmp 2b \n\t"
4548 ".popsection \n\t"
4549 _ASM_EXTABLE(1b, 3b)
4550 : [fault]"+qm"(fault));
4551 ctxt->ops->put_fpu(ctxt);
4552
4553 if (unlikely(fault))
4554 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4555
4556 return X86EMUL_CONTINUE;
4557 }
4558
4559 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4560 struct operand *op)
4561 {
4562 if (op->type == OP_MM)
4563 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4564 }
4565
4566 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4567 {
4568 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4569 if (!(ctxt->d & ByteOp))
4570 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4571 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4572 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4573 [fastop]"+S"(fop)
4574 : "c"(ctxt->src2.val));
4575 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4576 if (!fop) /* exception is returned in fop variable */
4577 return emulate_de(ctxt);
4578 return X86EMUL_CONTINUE;
4579 }
4580
4581 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4582 {
4583 const struct x86_emulate_ops *ops = ctxt->ops;
4584 int rc = X86EMUL_CONTINUE;
4585 int saved_dst_type = ctxt->dst.type;
4586
4587 ctxt->mem_read.pos = 0;
4588
4589 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4590 (ctxt->d & Undefined)) {
4591 rc = emulate_ud(ctxt);
4592 goto done;
4593 }
4594
4595 /* LOCK prefix is allowed only with some instructions */
4596 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4597 rc = emulate_ud(ctxt);
4598 goto done;
4599 }
4600
4601 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4602 rc = emulate_ud(ctxt);
4603 goto done;
4604 }
4605
4606 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4607 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4608 rc = emulate_ud(ctxt);
4609 goto done;
4610 }
4611
4612 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4613 rc = emulate_nm(ctxt);
4614 goto done;
4615 }
4616
4617 if (ctxt->d & Mmx) {
4618 rc = flush_pending_x87_faults(ctxt);
4619 if (rc != X86EMUL_CONTINUE)
4620 goto done;
4621 /*
4622 * Now that we know the fpu is exception safe, we can fetch
4623 * operands from it.
4624 */
4625 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4626 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4627 if (!(ctxt->d & Mov))
4628 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4629 }
4630
4631 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4632 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4633 X86_ICPT_PRE_EXCEPT);
4634 if (rc != X86EMUL_CONTINUE)
4635 goto done;
4636 }
4637
4638 /* Privileged instruction can be executed only in CPL=0 */
4639 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4640 rc = emulate_gp(ctxt, 0);
4641 goto done;
4642 }
4643
4644 /* Instruction can only be executed in protected mode */
4645 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4646 rc = emulate_ud(ctxt);
4647 goto done;
4648 }
4649
4650 /* Do instruction specific permission checks */
4651 if (ctxt->check_perm) {
4652 rc = ctxt->check_perm(ctxt);
4653 if (rc != X86EMUL_CONTINUE)
4654 goto done;
4655 }
4656
4657 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4658 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4659 X86_ICPT_POST_EXCEPT);
4660 if (rc != X86EMUL_CONTINUE)
4661 goto done;
4662 }
4663
4664 if (ctxt->rep_prefix && (ctxt->d & String)) {
4665 /* All REP prefixes have the same first termination condition */
4666 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4667 ctxt->eip = ctxt->_eip;
4668 goto done;
4669 }
4670 }
4671
4672 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4673 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4674 ctxt->src.valptr, ctxt->src.bytes);
4675 if (rc != X86EMUL_CONTINUE)
4676 goto done;
4677 ctxt->src.orig_val64 = ctxt->src.val64;
4678 }
4679
4680 if (ctxt->src2.type == OP_MEM) {
4681 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4682 &ctxt->src2.val, ctxt->src2.bytes);
4683 if (rc != X86EMUL_CONTINUE)
4684 goto done;
4685 }
4686
4687 if ((ctxt->d & DstMask) == ImplicitOps)
4688 goto special_insn;
4689
4690
4691 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4692 /* optimisation - avoid slow emulated read if Mov */
4693 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4694 &ctxt->dst.val, ctxt->dst.bytes);
4695 if (rc != X86EMUL_CONTINUE)
4696 goto done;
4697 }
4698 ctxt->dst.orig_val = ctxt->dst.val;
4699
4700 special_insn:
4701
4702 if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
4703 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4704 X86_ICPT_POST_MEMACCESS);
4705 if (rc != X86EMUL_CONTINUE)
4706 goto done;
4707 }
4708
4709 if (ctxt->execute) {
4710 if (ctxt->d & Fastop) {
4711 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4712 rc = fastop(ctxt, fop);
4713 if (rc != X86EMUL_CONTINUE)
4714 goto done;
4715 goto writeback;
4716 }
4717 rc = ctxt->execute(ctxt);
4718 if (rc != X86EMUL_CONTINUE)
4719 goto done;
4720 goto writeback;
4721 }
4722
4723 if (ctxt->twobyte)
4724 goto twobyte_insn;
4725
4726 switch (ctxt->b) {
4727 case 0x63: /* movsxd */
4728 if (ctxt->mode != X86EMUL_MODE_PROT64)
4729 goto cannot_emulate;
4730 ctxt->dst.val = (s32) ctxt->src.val;
4731 break;
4732 case 0x70 ... 0x7f: /* jcc (short) */
4733 if (test_cc(ctxt->b, ctxt->eflags))
4734 jmp_rel(ctxt, ctxt->src.val);
4735 break;
4736 case 0x8d: /* lea r16/r32, m */
4737 ctxt->dst.val = ctxt->src.addr.mem.ea;
4738 break;
4739 case 0x90 ... 0x97: /* nop / xchg reg, rax */
4740 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4741 break;
4742 rc = em_xchg(ctxt);
4743 break;
4744 case 0x98: /* cbw/cwde/cdqe */
4745 switch (ctxt->op_bytes) {
4746 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
4747 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
4748 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4749 }
4750 break;
4751 case 0xcc: /* int3 */
4752 rc = emulate_int(ctxt, 3);
4753 break;
4754 case 0xcd: /* int n */
4755 rc = emulate_int(ctxt, ctxt->src.val);
4756 break;
4757 case 0xce: /* into */
4758 if (ctxt->eflags & EFLG_OF)
4759 rc = emulate_int(ctxt, 4);
4760 break;
4761 case 0xe9: /* jmp rel */
4762 case 0xeb: /* jmp rel short */
4763 jmp_rel(ctxt, ctxt->src.val);
4764 ctxt->dst.type = OP_NONE; /* Disable writeback. */
4765 break;
4766 case 0xf4: /* hlt */
4767 ctxt->ops->halt(ctxt);
4768 break;
4769 case 0xf5: /* cmc */
4770 /* complement carry flag from eflags reg */
4771 ctxt->eflags ^= EFLG_CF;
4772 break;
4773 case 0xf8: /* clc */
4774 ctxt->eflags &= ~EFLG_CF;
4775 break;
4776 case 0xf9: /* stc */
4777 ctxt->eflags |= EFLG_CF;
4778 break;
4779 case 0xfc: /* cld */
4780 ctxt->eflags &= ~EFLG_DF;
4781 break;
4782 case 0xfd: /* std */
4783 ctxt->eflags |= EFLG_DF;
4784 break;
4785 default:
4786 goto cannot_emulate;
4787 }
4788
4789 if (rc != X86EMUL_CONTINUE)
4790 goto done;
4791
4792 writeback:
4793 if (!(ctxt->d & NoWrite)) {
4794 rc = writeback(ctxt, &ctxt->dst);
4795 if (rc != X86EMUL_CONTINUE)
4796 goto done;
4797 }
4798 if (ctxt->d & SrcWrite) {
4799 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
4800 rc = writeback(ctxt, &ctxt->src);
4801 if (rc != X86EMUL_CONTINUE)
4802 goto done;
4803 }
4804
4805 /*
4806 * restore dst type in case the decoding will be reused
4807 * (happens for string instruction )
4808 */
4809 ctxt->dst.type = saved_dst_type;
4810
4811 if ((ctxt->d & SrcMask) == SrcSI)
4812 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4813
4814 if ((ctxt->d & DstMask) == DstDI)
4815 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4816
4817 if (ctxt->rep_prefix && (ctxt->d & String)) {
4818 unsigned int count;
4819 struct read_cache *r = &ctxt->io_read;
4820 if ((ctxt->d & SrcMask) == SrcSI)
4821 count = ctxt->src.count;
4822 else
4823 count = ctxt->dst.count;
4824 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
4825 -count);
4826
4827 if (!string_insn_completed(ctxt)) {
4828 /*
4829 * Re-enter guest when pio read ahead buffer is empty
4830 * or, if it is not used, after each 1024 iteration.
4831 */
4832 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4833 (r->end == 0 || r->end != r->pos)) {
4834 /*
4835 * Reset read cache. Usually happens before
4836 * decode, but since instruction is restarted
4837 * we have to do it here.
4838 */
4839 ctxt->mem_read.end = 0;
4840 writeback_registers(ctxt);
4841 return EMULATION_RESTART;
4842 }
4843 goto done; /* skip rip writeback */
4844 }
4845 }
4846
4847 ctxt->eip = ctxt->_eip;
4848
4849 done:
4850 if (rc == X86EMUL_PROPAGATE_FAULT)
4851 ctxt->have_exception = true;
4852 if (rc == X86EMUL_INTERCEPTED)
4853 return EMULATION_INTERCEPTED;
4854
4855 if (rc == X86EMUL_CONTINUE)
4856 writeback_registers(ctxt);
4857
4858 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
4859
4860 twobyte_insn:
4861 switch (ctxt->b) {
4862 case 0x09: /* wbinvd */
4863 (ctxt->ops->wbinvd)(ctxt);
4864 break;
4865 case 0x08: /* invd */
4866 case 0x0d: /* GrpP (prefetch) */
4867 case 0x18: /* Grp16 (prefetch/nop) */
4868 break;
4869 case 0x20: /* mov cr, reg */
4870 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4871 break;
4872 case 0x21: /* mov from dr to reg */
4873 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
4874 break;
4875 case 0x40 ... 0x4f: /* cmov */
4876 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
4877 if (!test_cc(ctxt->b, ctxt->eflags))
4878 ctxt->dst.type = OP_NONE; /* no writeback */
4879 break;
4880 case 0x80 ... 0x8f: /* jnz rel, etc*/
4881 if (test_cc(ctxt->b, ctxt->eflags))
4882 jmp_rel(ctxt, ctxt->src.val);
4883 break;
4884 case 0x90 ... 0x9f: /* setcc r/m8 */
4885 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4886 break;
4887 case 0xae: /* clflush */
4888 break;
4889 case 0xb6 ... 0xb7: /* movzx */
4890 ctxt->dst.bytes = ctxt->op_bytes;
4891 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
4892 : (u16) ctxt->src.val;
4893 break;
4894 case 0xbe ... 0xbf: /* movsx */
4895 ctxt->dst.bytes = ctxt->op_bytes;
4896 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
4897 (s16) ctxt->src.val;
4898 break;
4899 case 0xc0 ... 0xc1: /* xadd */
4900 fastop(ctxt, em_add);
4901 /* Write back the register source. */
4902 ctxt->src.val = ctxt->dst.orig_val;
4903 write_register_operand(&ctxt->src);
4904 break;
4905 case 0xc3: /* movnti */
4906 ctxt->dst.bytes = ctxt->op_bytes;
4907 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
4908 (u64) ctxt->src.val;
4909 break;
4910 default:
4911 goto cannot_emulate;
4912 }
4913
4914 if (rc != X86EMUL_CONTINUE)
4915 goto done;
4916
4917 goto writeback;
4918
4919 cannot_emulate:
4920 return EMULATION_FAILED;
4921 }
4922
4923 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
4924 {
4925 invalidate_registers(ctxt);
4926 }
4927
4928 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
4929 {
4930 writeback_registers(ctxt);
4931 }
Linux kernel - Deliverables
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