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KVM: x86 emulator: convert group 5 to new style
[deliverable/linux.git] / arch / x86 / kvm / emulate.c
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #ifndef __KERNEL__
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #else
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
32 #endif
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
35
36 #include "x86.h"
37 #include "tss.h"
38
39 /*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<16) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<17) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<17) /* Register operand. */
53 #define DstMem (3<<17) /* Memory operand. */
54 #define DstAcc (4<<17) /* Destination Accumulator */
55 #define DstDI (5<<17) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<17) /* 64bit memory operand */
57 #define DstMask (7<<17)
58 /* Source operand type. */
59 #define SrcNone (0<<4) /* No source operand. */
60 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcMask (0xf<<4)
75 /* Generic ModRM decode. */
76 #define ModRM (1<<8)
77 /* Destination is only written; never read. */
78 #define Mov (1<<9)
79 #define BitOp (1<<10)
80 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
81 #define String (1<<12) /* String instruction (rep capable) */
82 #define Stack (1<<13) /* Stack instruction (push/pop) */
83 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
85 #define GroupMask 0x0f /* Group number stored in bits 0:3 */
86 /* Misc flags */
87 #define Undefined (1<<25) /* No Such Instruction */
88 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
89 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
90 #define No64 (1<<28)
91 /* Source 2 operand type */
92 #define Src2None (0<<29)
93 #define Src2CL (1<<29)
94 #define Src2ImmByte (2<<29)
95 #define Src2One (3<<29)
96 #define Src2Mask (7<<29)
97
98 #define X2(x) x, x
99 #define X3(x) X2(x), x
100 #define X4(x) X2(x), X2(x)
101 #define X5(x) X4(x), x
102 #define X6(x) X4(x), X2(x)
103 #define X7(x) X4(x), X3(x)
104 #define X8(x) X4(x), X4(x)
105 #define X16(x) X8(x), X8(x)
106
107 enum {
108 NoGrp, Group7, Group8, Group9,
109 };
110
111 struct opcode {
112 u32 flags;
113 union {
114 struct opcode *group;
115 struct group_dual *gdual;
116 } u;
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 #define D(_y) { .flags = (_y) }
125 #define N D(0)
126 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
127 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
128
129 static struct opcode group1[] = {
130 X7(D(Lock)), N
131 };
132
133 static struct opcode group1A[] = {
134 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
135 };
136
137 static struct opcode group3[] = {
138 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
139 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
140 X4(D(Undefined)),
141 };
142
143 static struct opcode group4[] = {
144 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
145 N, N, N, N, N, N,
146 };
147
148 static struct opcode group5[] = {
149 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
150 D(SrcMem | ModRM | Stack), N,
151 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
152 D(SrcMem | ModRM | Stack), N,
153 };
154
155 static struct opcode group_table[] = {
156 [Group7*8] =
157 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
158 D(SrcNone | ModRM | DstMem | Mov), N,
159 D(SrcMem16 | ModRM | Mov | Priv), D(SrcMem | ModRM | ByteOp | Priv),
160 [Group8*8] =
161 N, N, N, N,
162 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
163 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
164 [Group9*8] =
165 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
166 };
167
168 static struct opcode group2_table[] = {
169 [Group7*8] =
170 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
171 D(SrcNone | ModRM | DstMem | Mov), N,
172 D(SrcMem16 | ModRM | Mov | Priv), N,
173 [Group9*8] =
174 N, N, N, N, N, N, N, N,
175 };
176
177 static struct opcode opcode_table[256] = {
178 /* 0x00 - 0x07 */
179 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
180 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
181 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
182 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
183 /* 0x08 - 0x0F */
184 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
185 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
186 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
187 D(ImplicitOps | Stack | No64), N,
188 /* 0x10 - 0x17 */
189 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
190 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
191 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
192 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
193 /* 0x18 - 0x1F */
194 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
195 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
196 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
197 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
198 /* 0x20 - 0x27 */
199 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
200 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
201 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
202 /* 0x28 - 0x2F */
203 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
204 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
205 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
206 /* 0x30 - 0x37 */
207 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
208 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
209 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
210 /* 0x38 - 0x3F */
211 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
212 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
213 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
214 N, N,
215 /* 0x40 - 0x4F */
216 X16(D(DstReg)),
217 /* 0x50 - 0x57 */
218 X8(D(SrcReg | Stack)),
219 /* 0x58 - 0x5F */
220 X8(D(DstReg | Stack)),
221 /* 0x60 - 0x67 */
222 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
223 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
224 N, N, N, N,
225 /* 0x68 - 0x6F */
226 D(SrcImm | Mov | Stack), N, D(SrcImmByte | Mov | Stack), N,
227 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
228 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
229 /* 0x70 - 0x7F */
230 X16(D(SrcImmByte)),
231 /* 0x80 - 0x87 */
232 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
233 G(DstMem | SrcImm | ModRM | Group, group1),
234 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
235 G(DstMem | SrcImmByte | ModRM | Group, group1),
236 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
237 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
238 /* 0x88 - 0x8F */
239 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
240 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
241 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | DstReg),
242 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
243 /* 0x90 - 0x97 */
244 D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg), D(DstReg),
245 /* 0x98 - 0x9F */
246 N, N, D(SrcImmFAddr | No64), N,
247 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
248 /* 0xA0 - 0xA7 */
249 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
250 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
251 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
252 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
253 /* 0xA8 - 0xAF */
254 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm), D(ByteOp | DstDI | Mov | String), D(DstDI | Mov | String),
255 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
256 D(ByteOp | DstDI | String), D(DstDI | String),
257 /* 0xB0 - 0xB7 */
258 X8(D(ByteOp | DstReg | SrcImm | Mov)),
259 /* 0xB8 - 0xBF */
260 X8(D(DstReg | SrcImm | Mov)),
261 /* 0xC0 - 0xC7 */
262 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
263 N, D(ImplicitOps | Stack), N, N,
264 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
265 /* 0xC8 - 0xCF */
266 N, N, N, D(ImplicitOps | Stack),
267 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
268 /* 0xD0 - 0xD7 */
269 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
270 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
271 N, N, N, N,
272 /* 0xD8 - 0xDF */
273 N, N, N, N, N, N, N, N,
274 /* 0xE0 - 0xE7 */
275 N, N, N, N,
276 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
277 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
278 /* 0xE8 - 0xEF */
279 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
280 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
281 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
282 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
283 /* 0xF0 - 0xF7 */
284 N, N, N, N,
285 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
286 /* 0xF8 - 0xFF */
287 D(ImplicitOps), N, D(ImplicitOps), D(ImplicitOps),
288 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
289 };
290
291 static struct opcode twobyte_table[256] = {
292 /* 0x00 - 0x0F */
293 N, D(Group | GroupDual | Group7), N, N,
294 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
295 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
296 N, D(ImplicitOps | ModRM), N, N,
297 /* 0x10 - 0x1F */
298 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
299 /* 0x20 - 0x2F */
300 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
301 D(ModRM | ImplicitOps | Priv), D(ModRM | Priv),
302 N, N, N, N,
303 N, N, N, N, N, N, N, N,
304 /* 0x30 - 0x3F */
305 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
306 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
307 N, N, N, N, N, N, N, N,
308 /* 0x40 - 0x4F */
309 X16(D(DstReg | SrcMem | ModRM | Mov)),
310 /* 0x50 - 0x5F */
311 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
312 /* 0x60 - 0x6F */
313 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
314 /* 0x70 - 0x7F */
315 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
316 /* 0x80 - 0x8F */
317 X16(D(SrcImm)),
318 /* 0x90 - 0x9F */
319 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
320 /* 0xA0 - 0xA7 */
321 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
322 N, D(DstMem | SrcReg | ModRM | BitOp),
323 D(DstMem | SrcReg | Src2ImmByte | ModRM),
324 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
325 /* 0xA8 - 0xAF */
326 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
327 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
328 D(DstMem | SrcReg | Src2ImmByte | ModRM),
329 D(DstMem | SrcReg | Src2CL | ModRM),
330 D(ModRM), N,
331 /* 0xB0 - 0xB7 */
332 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
333 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
334 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
335 D(DstReg | SrcMem16 | ModRM | Mov),
336 /* 0xB8 - 0xBF */
337 N, N,
338 D(Group | Group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
339 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
340 D(DstReg | SrcMem16 | ModRM | Mov),
341 /* 0xC0 - 0xCF */
342 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
343 N, N, N, D(Group | GroupDual | Group9),
344 N, N, N, N, N, N, N, N,
345 /* 0xD0 - 0xDF */
346 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
347 /* 0xE0 - 0xEF */
348 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
349 /* 0xF0 - 0xFF */
350 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
351 };
352
353 #undef D
354 #undef N
355 #undef G
356 #undef GD
357
358 /* EFLAGS bit definitions. */
359 #define EFLG_ID (1<<21)
360 #define EFLG_VIP (1<<20)
361 #define EFLG_VIF (1<<19)
362 #define EFLG_AC (1<<18)
363 #define EFLG_VM (1<<17)
364 #define EFLG_RF (1<<16)
365 #define EFLG_IOPL (3<<12)
366 #define EFLG_NT (1<<14)
367 #define EFLG_OF (1<<11)
368 #define EFLG_DF (1<<10)
369 #define EFLG_IF (1<<9)
370 #define EFLG_TF (1<<8)
371 #define EFLG_SF (1<<7)
372 #define EFLG_ZF (1<<6)
373 #define EFLG_AF (1<<4)
374 #define EFLG_PF (1<<2)
375 #define EFLG_CF (1<<0)
376
377 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
378 #define EFLG_RESERVED_ONE_MASK 2
379
380 /*
381 * Instruction emulation:
382 * Most instructions are emulated directly via a fragment of inline assembly
383 * code. This allows us to save/restore EFLAGS and thus very easily pick up
384 * any modified flags.
385 */
386
387 #if defined(CONFIG_X86_64)
388 #define _LO32 "k" /* force 32-bit operand */
389 #define _STK "%%rsp" /* stack pointer */
390 #elif defined(__i386__)
391 #define _LO32 "" /* force 32-bit operand */
392 #define _STK "%%esp" /* stack pointer */
393 #endif
394
395 /*
396 * These EFLAGS bits are restored from saved value during emulation, and
397 * any changes are written back to the saved value after emulation.
398 */
399 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
400
401 /* Before executing instruction: restore necessary bits in EFLAGS. */
402 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
403 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
404 "movl %"_sav",%"_LO32 _tmp"; " \
405 "push %"_tmp"; " \
406 "push %"_tmp"; " \
407 "movl %"_msk",%"_LO32 _tmp"; " \
408 "andl %"_LO32 _tmp",("_STK"); " \
409 "pushf; " \
410 "notl %"_LO32 _tmp"; " \
411 "andl %"_LO32 _tmp",("_STK"); " \
412 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
413 "pop %"_tmp"; " \
414 "orl %"_LO32 _tmp",("_STK"); " \
415 "popf; " \
416 "pop %"_sav"; "
417
418 /* After executing instruction: write-back necessary bits in EFLAGS. */
419 #define _POST_EFLAGS(_sav, _msk, _tmp) \
420 /* _sav |= EFLAGS & _msk; */ \
421 "pushf; " \
422 "pop %"_tmp"; " \
423 "andl %"_msk",%"_LO32 _tmp"; " \
424 "orl %"_LO32 _tmp",%"_sav"; "
425
426 #ifdef CONFIG_X86_64
427 #define ON64(x) x
428 #else
429 #define ON64(x)
430 #endif
431
432 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
433 do { \
434 __asm__ __volatile__ ( \
435 _PRE_EFLAGS("0", "4", "2") \
436 _op _suffix " %"_x"3,%1; " \
437 _POST_EFLAGS("0", "4", "2") \
438 : "=m" (_eflags), "=m" ((_dst).val), \
439 "=&r" (_tmp) \
440 : _y ((_src).val), "i" (EFLAGS_MASK)); \
441 } while (0)
442
443
444 /* Raw emulation: instruction has two explicit operands. */
445 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
446 do { \
447 unsigned long _tmp; \
448 \
449 switch ((_dst).bytes) { \
450 case 2: \
451 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
452 break; \
453 case 4: \
454 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
455 break; \
456 case 8: \
457 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
458 break; \
459 } \
460 } while (0)
461
462 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
463 do { \
464 unsigned long _tmp; \
465 switch ((_dst).bytes) { \
466 case 1: \
467 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
468 break; \
469 default: \
470 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
471 _wx, _wy, _lx, _ly, _qx, _qy); \
472 break; \
473 } \
474 } while (0)
475
476 /* Source operand is byte-sized and may be restricted to just %cl. */
477 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
478 __emulate_2op(_op, _src, _dst, _eflags, \
479 "b", "c", "b", "c", "b", "c", "b", "c")
480
481 /* Source operand is byte, word, long or quad sized. */
482 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
483 __emulate_2op(_op, _src, _dst, _eflags, \
484 "b", "q", "w", "r", _LO32, "r", "", "r")
485
486 /* Source operand is word, long or quad sized. */
487 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
488 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
489 "w", "r", _LO32, "r", "", "r")
490
491 /* Instruction has three operands and one operand is stored in ECX register */
492 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
493 do { \
494 unsigned long _tmp; \
495 _type _clv = (_cl).val; \
496 _type _srcv = (_src).val; \
497 _type _dstv = (_dst).val; \
498 \
499 __asm__ __volatile__ ( \
500 _PRE_EFLAGS("0", "5", "2") \
501 _op _suffix " %4,%1 \n" \
502 _POST_EFLAGS("0", "5", "2") \
503 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
504 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
505 ); \
506 \
507 (_cl).val = (unsigned long) _clv; \
508 (_src).val = (unsigned long) _srcv; \
509 (_dst).val = (unsigned long) _dstv; \
510 } while (0)
511
512 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
513 do { \
514 switch ((_dst).bytes) { \
515 case 2: \
516 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
517 "w", unsigned short); \
518 break; \
519 case 4: \
520 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
521 "l", unsigned int); \
522 break; \
523 case 8: \
524 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
525 "q", unsigned long)); \
526 break; \
527 } \
528 } while (0)
529
530 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
531 do { \
532 unsigned long _tmp; \
533 \
534 __asm__ __volatile__ ( \
535 _PRE_EFLAGS("0", "3", "2") \
536 _op _suffix " %1; " \
537 _POST_EFLAGS("0", "3", "2") \
538 : "=m" (_eflags), "+m" ((_dst).val), \
539 "=&r" (_tmp) \
540 : "i" (EFLAGS_MASK)); \
541 } while (0)
542
543 /* Instruction has only one explicit operand (no source operand). */
544 #define emulate_1op(_op, _dst, _eflags) \
545 do { \
546 switch ((_dst).bytes) { \
547 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
548 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
549 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
550 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
551 } \
552 } while (0)
553
554 /* Fetch next part of the instruction being emulated. */
555 #define insn_fetch(_type, _size, _eip) \
556 ({ unsigned long _x; \
557 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
558 if (rc != X86EMUL_CONTINUE) \
559 goto done; \
560 (_eip) += (_size); \
561 (_type)_x; \
562 })
563
564 #define insn_fetch_arr(_arr, _size, _eip) \
565 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
566 if (rc != X86EMUL_CONTINUE) \
567 goto done; \
568 (_eip) += (_size); \
569 })
570
571 static inline unsigned long ad_mask(struct decode_cache *c)
572 {
573 return (1UL << (c->ad_bytes << 3)) - 1;
574 }
575
576 /* Access/update address held in a register, based on addressing mode. */
577 static inline unsigned long
578 address_mask(struct decode_cache *c, unsigned long reg)
579 {
580 if (c->ad_bytes == sizeof(unsigned long))
581 return reg;
582 else
583 return reg & ad_mask(c);
584 }
585
586 static inline unsigned long
587 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
588 {
589 return base + address_mask(c, reg);
590 }
591
592 static inline void
593 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
594 {
595 if (c->ad_bytes == sizeof(unsigned long))
596 *reg += inc;
597 else
598 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
599 }
600
601 static inline void jmp_rel(struct decode_cache *c, int rel)
602 {
603 register_address_increment(c, &c->eip, rel);
604 }
605
606 static void set_seg_override(struct decode_cache *c, int seg)
607 {
608 c->has_seg_override = true;
609 c->seg_override = seg;
610 }
611
612 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
613 struct x86_emulate_ops *ops, int seg)
614 {
615 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
616 return 0;
617
618 return ops->get_cached_segment_base(seg, ctxt->vcpu);
619 }
620
621 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
622 struct x86_emulate_ops *ops,
623 struct decode_cache *c)
624 {
625 if (!c->has_seg_override)
626 return 0;
627
628 return seg_base(ctxt, ops, c->seg_override);
629 }
630
631 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops)
633 {
634 return seg_base(ctxt, ops, VCPU_SREG_ES);
635 }
636
637 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
638 struct x86_emulate_ops *ops)
639 {
640 return seg_base(ctxt, ops, VCPU_SREG_SS);
641 }
642
643 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
644 u32 error, bool valid)
645 {
646 ctxt->exception = vec;
647 ctxt->error_code = error;
648 ctxt->error_code_valid = valid;
649 ctxt->restart = false;
650 }
651
652 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
653 {
654 emulate_exception(ctxt, GP_VECTOR, err, true);
655 }
656
657 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
658 int err)
659 {
660 ctxt->cr2 = addr;
661 emulate_exception(ctxt, PF_VECTOR, err, true);
662 }
663
664 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
665 {
666 emulate_exception(ctxt, UD_VECTOR, 0, false);
667 }
668
669 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
670 {
671 emulate_exception(ctxt, TS_VECTOR, err, true);
672 }
673
674 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
675 struct x86_emulate_ops *ops,
676 unsigned long eip, u8 *dest)
677 {
678 struct fetch_cache *fc = &ctxt->decode.fetch;
679 int rc;
680 int size, cur_size;
681
682 if (eip == fc->end) {
683 cur_size = fc->end - fc->start;
684 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
685 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
686 size, ctxt->vcpu, NULL);
687 if (rc != X86EMUL_CONTINUE)
688 return rc;
689 fc->end += size;
690 }
691 *dest = fc->data[eip - fc->start];
692 return X86EMUL_CONTINUE;
693 }
694
695 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
696 struct x86_emulate_ops *ops,
697 unsigned long eip, void *dest, unsigned size)
698 {
699 int rc;
700
701 /* x86 instructions are limited to 15 bytes. */
702 if (eip + size - ctxt->eip > 15)
703 return X86EMUL_UNHANDLEABLE;
704 while (size--) {
705 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
706 if (rc != X86EMUL_CONTINUE)
707 return rc;
708 }
709 return X86EMUL_CONTINUE;
710 }
711
712 /*
713 * Given the 'reg' portion of a ModRM byte, and a register block, return a
714 * pointer into the block that addresses the relevant register.
715 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
716 */
717 static void *decode_register(u8 modrm_reg, unsigned long *regs,
718 int highbyte_regs)
719 {
720 void *p;
721
722 p = &regs[modrm_reg];
723 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
724 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
725 return p;
726 }
727
728 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
729 struct x86_emulate_ops *ops,
730 void *ptr,
731 u16 *size, unsigned long *address, int op_bytes)
732 {
733 int rc;
734
735 if (op_bytes == 2)
736 op_bytes = 3;
737 *address = 0;
738 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
739 ctxt->vcpu, NULL);
740 if (rc != X86EMUL_CONTINUE)
741 return rc;
742 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
743 ctxt->vcpu, NULL);
744 return rc;
745 }
746
747 static int test_cc(unsigned int condition, unsigned int flags)
748 {
749 int rc = 0;
750
751 switch ((condition & 15) >> 1) {
752 case 0: /* o */
753 rc |= (flags & EFLG_OF);
754 break;
755 case 1: /* b/c/nae */
756 rc |= (flags & EFLG_CF);
757 break;
758 case 2: /* z/e */
759 rc |= (flags & EFLG_ZF);
760 break;
761 case 3: /* be/na */
762 rc |= (flags & (EFLG_CF|EFLG_ZF));
763 break;
764 case 4: /* s */
765 rc |= (flags & EFLG_SF);
766 break;
767 case 5: /* p/pe */
768 rc |= (flags & EFLG_PF);
769 break;
770 case 7: /* le/ng */
771 rc |= (flags & EFLG_ZF);
772 /* fall through */
773 case 6: /* l/nge */
774 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
775 break;
776 }
777
778 /* Odd condition identifiers (lsb == 1) have inverted sense. */
779 return (!!rc ^ (condition & 1));
780 }
781
782 static void decode_register_operand(struct operand *op,
783 struct decode_cache *c,
784 int inhibit_bytereg)
785 {
786 unsigned reg = c->modrm_reg;
787 int highbyte_regs = c->rex_prefix == 0;
788
789 if (!(c->d & ModRM))
790 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
791 op->type = OP_REG;
792 if ((c->d & ByteOp) && !inhibit_bytereg) {
793 op->ptr = decode_register(reg, c->regs, highbyte_regs);
794 op->val = *(u8 *)op->ptr;
795 op->bytes = 1;
796 } else {
797 op->ptr = decode_register(reg, c->regs, 0);
798 op->bytes = c->op_bytes;
799 switch (op->bytes) {
800 case 2:
801 op->val = *(u16 *)op->ptr;
802 break;
803 case 4:
804 op->val = *(u32 *)op->ptr;
805 break;
806 case 8:
807 op->val = *(u64 *) op->ptr;
808 break;
809 }
810 }
811 op->orig_val = op->val;
812 }
813
814 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
815 struct x86_emulate_ops *ops)
816 {
817 struct decode_cache *c = &ctxt->decode;
818 u8 sib;
819 int index_reg = 0, base_reg = 0, scale;
820 int rc = X86EMUL_CONTINUE;
821
822 if (c->rex_prefix) {
823 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
824 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
825 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
826 }
827
828 c->modrm = insn_fetch(u8, 1, c->eip);
829 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
830 c->modrm_reg |= (c->modrm & 0x38) >> 3;
831 c->modrm_rm |= (c->modrm & 0x07);
832 c->modrm_ea = 0;
833 c->use_modrm_ea = 1;
834
835 if (c->modrm_mod == 3) {
836 c->modrm_ptr = decode_register(c->modrm_rm,
837 c->regs, c->d & ByteOp);
838 c->modrm_val = *(unsigned long *)c->modrm_ptr;
839 return rc;
840 }
841
842 if (c->ad_bytes == 2) {
843 unsigned bx = c->regs[VCPU_REGS_RBX];
844 unsigned bp = c->regs[VCPU_REGS_RBP];
845 unsigned si = c->regs[VCPU_REGS_RSI];
846 unsigned di = c->regs[VCPU_REGS_RDI];
847
848 /* 16-bit ModR/M decode. */
849 switch (c->modrm_mod) {
850 case 0:
851 if (c->modrm_rm == 6)
852 c->modrm_ea += insn_fetch(u16, 2, c->eip);
853 break;
854 case 1:
855 c->modrm_ea += insn_fetch(s8, 1, c->eip);
856 break;
857 case 2:
858 c->modrm_ea += insn_fetch(u16, 2, c->eip);
859 break;
860 }
861 switch (c->modrm_rm) {
862 case 0:
863 c->modrm_ea += bx + si;
864 break;
865 case 1:
866 c->modrm_ea += bx + di;
867 break;
868 case 2:
869 c->modrm_ea += bp + si;
870 break;
871 case 3:
872 c->modrm_ea += bp + di;
873 break;
874 case 4:
875 c->modrm_ea += si;
876 break;
877 case 5:
878 c->modrm_ea += di;
879 break;
880 case 6:
881 if (c->modrm_mod != 0)
882 c->modrm_ea += bp;
883 break;
884 case 7:
885 c->modrm_ea += bx;
886 break;
887 }
888 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
889 (c->modrm_rm == 6 && c->modrm_mod != 0))
890 if (!c->has_seg_override)
891 set_seg_override(c, VCPU_SREG_SS);
892 c->modrm_ea = (u16)c->modrm_ea;
893 } else {
894 /* 32/64-bit ModR/M decode. */
895 if ((c->modrm_rm & 7) == 4) {
896 sib = insn_fetch(u8, 1, c->eip);
897 index_reg |= (sib >> 3) & 7;
898 base_reg |= sib & 7;
899 scale = sib >> 6;
900
901 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
902 c->modrm_ea += insn_fetch(s32, 4, c->eip);
903 else
904 c->modrm_ea += c->regs[base_reg];
905 if (index_reg != 4)
906 c->modrm_ea += c->regs[index_reg] << scale;
907 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
908 if (ctxt->mode == X86EMUL_MODE_PROT64)
909 c->rip_relative = 1;
910 } else
911 c->modrm_ea += c->regs[c->modrm_rm];
912 switch (c->modrm_mod) {
913 case 0:
914 if (c->modrm_rm == 5)
915 c->modrm_ea += insn_fetch(s32, 4, c->eip);
916 break;
917 case 1:
918 c->modrm_ea += insn_fetch(s8, 1, c->eip);
919 break;
920 case 2:
921 c->modrm_ea += insn_fetch(s32, 4, c->eip);
922 break;
923 }
924 }
925 done:
926 return rc;
927 }
928
929 static int decode_abs(struct x86_emulate_ctxt *ctxt,
930 struct x86_emulate_ops *ops)
931 {
932 struct decode_cache *c = &ctxt->decode;
933 int rc = X86EMUL_CONTINUE;
934
935 switch (c->ad_bytes) {
936 case 2:
937 c->modrm_ea = insn_fetch(u16, 2, c->eip);
938 break;
939 case 4:
940 c->modrm_ea = insn_fetch(u32, 4, c->eip);
941 break;
942 case 8:
943 c->modrm_ea = insn_fetch(u64, 8, c->eip);
944 break;
945 }
946 done:
947 return rc;
948 }
949
950 int
951 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
952 {
953 struct decode_cache *c = &ctxt->decode;
954 int rc = X86EMUL_CONTINUE;
955 int mode = ctxt->mode;
956 int def_op_bytes, def_ad_bytes, group, dual, goffset;
957 struct opcode opcode, *g_mod012, *g_mod3;
958
959 /* we cannot decode insn before we complete previous rep insn */
960 WARN_ON(ctxt->restart);
961
962 c->eip = ctxt->eip;
963 c->fetch.start = c->fetch.end = c->eip;
964 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
965
966 switch (mode) {
967 case X86EMUL_MODE_REAL:
968 case X86EMUL_MODE_VM86:
969 case X86EMUL_MODE_PROT16:
970 def_op_bytes = def_ad_bytes = 2;
971 break;
972 case X86EMUL_MODE_PROT32:
973 def_op_bytes = def_ad_bytes = 4;
974 break;
975 #ifdef CONFIG_X86_64
976 case X86EMUL_MODE_PROT64:
977 def_op_bytes = 4;
978 def_ad_bytes = 8;
979 break;
980 #endif
981 default:
982 return -1;
983 }
984
985 c->op_bytes = def_op_bytes;
986 c->ad_bytes = def_ad_bytes;
987
988 /* Legacy prefixes. */
989 for (;;) {
990 switch (c->b = insn_fetch(u8, 1, c->eip)) {
991 case 0x66: /* operand-size override */
992 /* switch between 2/4 bytes */
993 c->op_bytes = def_op_bytes ^ 6;
994 break;
995 case 0x67: /* address-size override */
996 if (mode == X86EMUL_MODE_PROT64)
997 /* switch between 4/8 bytes */
998 c->ad_bytes = def_ad_bytes ^ 12;
999 else
1000 /* switch between 2/4 bytes */
1001 c->ad_bytes = def_ad_bytes ^ 6;
1002 break;
1003 case 0x26: /* ES override */
1004 case 0x2e: /* CS override */
1005 case 0x36: /* SS override */
1006 case 0x3e: /* DS override */
1007 set_seg_override(c, (c->b >> 3) & 3);
1008 break;
1009 case 0x64: /* FS override */
1010 case 0x65: /* GS override */
1011 set_seg_override(c, c->b & 7);
1012 break;
1013 case 0x40 ... 0x4f: /* REX */
1014 if (mode != X86EMUL_MODE_PROT64)
1015 goto done_prefixes;
1016 c->rex_prefix = c->b;
1017 continue;
1018 case 0xf0: /* LOCK */
1019 c->lock_prefix = 1;
1020 break;
1021 case 0xf2: /* REPNE/REPNZ */
1022 c->rep_prefix = REPNE_PREFIX;
1023 break;
1024 case 0xf3: /* REP/REPE/REPZ */
1025 c->rep_prefix = REPE_PREFIX;
1026 break;
1027 default:
1028 goto done_prefixes;
1029 }
1030
1031 /* Any legacy prefix after a REX prefix nullifies its effect. */
1032
1033 c->rex_prefix = 0;
1034 }
1035
1036 done_prefixes:
1037
1038 /* REX prefix. */
1039 if (c->rex_prefix)
1040 if (c->rex_prefix & 8)
1041 c->op_bytes = 8; /* REX.W */
1042
1043 /* Opcode byte(s). */
1044 opcode = opcode_table[c->b];
1045 if (opcode.flags == 0) {
1046 /* Two-byte opcode? */
1047 if (c->b == 0x0f) {
1048 c->twobyte = 1;
1049 c->b = insn_fetch(u8, 1, c->eip);
1050 opcode = twobyte_table[c->b];
1051 }
1052 }
1053 c->d = opcode.flags;
1054
1055 if (c->d & Group) {
1056 group = c->d & GroupMask;
1057 dual = c->d & GroupDual;
1058 c->modrm = insn_fetch(u8, 1, c->eip);
1059 --c->eip;
1060
1061 if (group) {
1062 g_mod012 = g_mod3 = &group_table[group * 8];
1063 if (c->d & GroupDual)
1064 g_mod3 = &group2_table[group * 8];
1065 } else {
1066 if (c->d & GroupDual) {
1067 g_mod012 = opcode.u.gdual->mod012;
1068 g_mod3 = opcode.u.gdual->mod3;
1069 } else
1070 g_mod012 = g_mod3 = opcode.u.group;
1071 }
1072
1073 c->d &= ~(Group | GroupDual | GroupMask);
1074
1075 goffset = (c->modrm >> 3) & 7;
1076
1077 if ((c->modrm >> 6) == 3)
1078 opcode = g_mod3[goffset];
1079 else
1080 opcode = g_mod012[goffset];
1081 c->d |= opcode.flags;
1082 }
1083
1084 /* Unrecognised? */
1085 if (c->d == 0 || (c->d & Undefined)) {
1086 DPRINTF("Cannot emulate %02x\n", c->b);
1087 return -1;
1088 }
1089
1090 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
1091 c->op_bytes = 8;
1092
1093 /* ModRM and SIB bytes. */
1094 if (c->d & ModRM)
1095 rc = decode_modrm(ctxt, ops);
1096 else if (c->d & MemAbs)
1097 rc = decode_abs(ctxt, ops);
1098 if (rc != X86EMUL_CONTINUE)
1099 goto done;
1100
1101 if (!c->has_seg_override)
1102 set_seg_override(c, VCPU_SREG_DS);
1103
1104 if (!(!c->twobyte && c->b == 0x8d))
1105 c->modrm_ea += seg_override_base(ctxt, ops, c);
1106
1107 if (c->ad_bytes != 8)
1108 c->modrm_ea = (u32)c->modrm_ea;
1109
1110 if (c->rip_relative)
1111 c->modrm_ea += c->eip;
1112
1113 /*
1114 * Decode and fetch the source operand: register, memory
1115 * or immediate.
1116 */
1117 switch (c->d & SrcMask) {
1118 case SrcNone:
1119 break;
1120 case SrcReg:
1121 decode_register_operand(&c->src, c, 0);
1122 break;
1123 case SrcMem16:
1124 c->src.bytes = 2;
1125 goto srcmem_common;
1126 case SrcMem32:
1127 c->src.bytes = 4;
1128 goto srcmem_common;
1129 case SrcMem:
1130 c->src.bytes = (c->d & ByteOp) ? 1 :
1131 c->op_bytes;
1132 /* Don't fetch the address for invlpg: it could be unmapped. */
1133 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1134 break;
1135 srcmem_common:
1136 /*
1137 * For instructions with a ModR/M byte, switch to register
1138 * access if Mod = 3.
1139 */
1140 if ((c->d & ModRM) && c->modrm_mod == 3) {
1141 c->src.type = OP_REG;
1142 c->src.val = c->modrm_val;
1143 c->src.ptr = c->modrm_ptr;
1144 break;
1145 }
1146 c->src.type = OP_MEM;
1147 c->src.ptr = (unsigned long *)c->modrm_ea;
1148 c->src.val = 0;
1149 break;
1150 case SrcImm:
1151 case SrcImmU:
1152 c->src.type = OP_IMM;
1153 c->src.ptr = (unsigned long *)c->eip;
1154 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1155 if (c->src.bytes == 8)
1156 c->src.bytes = 4;
1157 /* NB. Immediates are sign-extended as necessary. */
1158 switch (c->src.bytes) {
1159 case 1:
1160 c->src.val = insn_fetch(s8, 1, c->eip);
1161 break;
1162 case 2:
1163 c->src.val = insn_fetch(s16, 2, c->eip);
1164 break;
1165 case 4:
1166 c->src.val = insn_fetch(s32, 4, c->eip);
1167 break;
1168 }
1169 if ((c->d & SrcMask) == SrcImmU) {
1170 switch (c->src.bytes) {
1171 case 1:
1172 c->src.val &= 0xff;
1173 break;
1174 case 2:
1175 c->src.val &= 0xffff;
1176 break;
1177 case 4:
1178 c->src.val &= 0xffffffff;
1179 break;
1180 }
1181 }
1182 break;
1183 case SrcImmByte:
1184 case SrcImmUByte:
1185 c->src.type = OP_IMM;
1186 c->src.ptr = (unsigned long *)c->eip;
1187 c->src.bytes = 1;
1188 if ((c->d & SrcMask) == SrcImmByte)
1189 c->src.val = insn_fetch(s8, 1, c->eip);
1190 else
1191 c->src.val = insn_fetch(u8, 1, c->eip);
1192 break;
1193 case SrcAcc:
1194 c->src.type = OP_REG;
1195 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1196 c->src.ptr = &c->regs[VCPU_REGS_RAX];
1197 switch (c->src.bytes) {
1198 case 1:
1199 c->src.val = *(u8 *)c->src.ptr;
1200 break;
1201 case 2:
1202 c->src.val = *(u16 *)c->src.ptr;
1203 break;
1204 case 4:
1205 c->src.val = *(u32 *)c->src.ptr;
1206 break;
1207 case 8:
1208 c->src.val = *(u64 *)c->src.ptr;
1209 break;
1210 }
1211 break;
1212 case SrcOne:
1213 c->src.bytes = 1;
1214 c->src.val = 1;
1215 break;
1216 case SrcSI:
1217 c->src.type = OP_MEM;
1218 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1219 c->src.ptr = (unsigned long *)
1220 register_address(c, seg_override_base(ctxt, ops, c),
1221 c->regs[VCPU_REGS_RSI]);
1222 c->src.val = 0;
1223 break;
1224 case SrcImmFAddr:
1225 c->src.type = OP_IMM;
1226 c->src.ptr = (unsigned long *)c->eip;
1227 c->src.bytes = c->op_bytes + 2;
1228 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
1229 break;
1230 case SrcMemFAddr:
1231 c->src.type = OP_MEM;
1232 c->src.ptr = (unsigned long *)c->modrm_ea;
1233 c->src.bytes = c->op_bytes + 2;
1234 break;
1235 }
1236
1237 /*
1238 * Decode and fetch the second source operand: register, memory
1239 * or immediate.
1240 */
1241 switch (c->d & Src2Mask) {
1242 case Src2None:
1243 break;
1244 case Src2CL:
1245 c->src2.bytes = 1;
1246 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1247 break;
1248 case Src2ImmByte:
1249 c->src2.type = OP_IMM;
1250 c->src2.ptr = (unsigned long *)c->eip;
1251 c->src2.bytes = 1;
1252 c->src2.val = insn_fetch(u8, 1, c->eip);
1253 break;
1254 case Src2One:
1255 c->src2.bytes = 1;
1256 c->src2.val = 1;
1257 break;
1258 }
1259
1260 /* Decode and fetch the destination operand: register or memory. */
1261 switch (c->d & DstMask) {
1262 case ImplicitOps:
1263 /* Special instructions do their own operand decoding. */
1264 return 0;
1265 case DstReg:
1266 decode_register_operand(&c->dst, c,
1267 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1268 break;
1269 case DstMem:
1270 case DstMem64:
1271 if ((c->d & ModRM) && c->modrm_mod == 3) {
1272 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1273 c->dst.type = OP_REG;
1274 c->dst.val = c->dst.orig_val = c->modrm_val;
1275 c->dst.ptr = c->modrm_ptr;
1276 break;
1277 }
1278 c->dst.type = OP_MEM;
1279 c->dst.ptr = (unsigned long *)c->modrm_ea;
1280 if ((c->d & DstMask) == DstMem64)
1281 c->dst.bytes = 8;
1282 else
1283 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1284 c->dst.val = 0;
1285 if (c->d & BitOp) {
1286 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1287
1288 c->dst.ptr = (void *)c->dst.ptr +
1289 (c->src.val & mask) / 8;
1290 }
1291 break;
1292 case DstAcc:
1293 c->dst.type = OP_REG;
1294 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1295 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1296 switch (c->dst.bytes) {
1297 case 1:
1298 c->dst.val = *(u8 *)c->dst.ptr;
1299 break;
1300 case 2:
1301 c->dst.val = *(u16 *)c->dst.ptr;
1302 break;
1303 case 4:
1304 c->dst.val = *(u32 *)c->dst.ptr;
1305 break;
1306 case 8:
1307 c->dst.val = *(u64 *)c->dst.ptr;
1308 break;
1309 }
1310 c->dst.orig_val = c->dst.val;
1311 break;
1312 case DstDI:
1313 c->dst.type = OP_MEM;
1314 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1315 c->dst.ptr = (unsigned long *)
1316 register_address(c, es_base(ctxt, ops),
1317 c->regs[VCPU_REGS_RDI]);
1318 c->dst.val = 0;
1319 break;
1320 }
1321
1322 done:
1323 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1324 }
1325
1326 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1327 struct x86_emulate_ops *ops,
1328 unsigned long addr, void *dest, unsigned size)
1329 {
1330 int rc;
1331 struct read_cache *mc = &ctxt->decode.mem_read;
1332 u32 err;
1333
1334 while (size) {
1335 int n = min(size, 8u);
1336 size -= n;
1337 if (mc->pos < mc->end)
1338 goto read_cached;
1339
1340 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
1341 ctxt->vcpu);
1342 if (rc == X86EMUL_PROPAGATE_FAULT)
1343 emulate_pf(ctxt, addr, err);
1344 if (rc != X86EMUL_CONTINUE)
1345 return rc;
1346 mc->end += n;
1347
1348 read_cached:
1349 memcpy(dest, mc->data + mc->pos, n);
1350 mc->pos += n;
1351 dest += n;
1352 addr += n;
1353 }
1354 return X86EMUL_CONTINUE;
1355 }
1356
1357 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1358 struct x86_emulate_ops *ops,
1359 unsigned int size, unsigned short port,
1360 void *dest)
1361 {
1362 struct read_cache *rc = &ctxt->decode.io_read;
1363
1364 if (rc->pos == rc->end) { /* refill pio read ahead */
1365 struct decode_cache *c = &ctxt->decode;
1366 unsigned int in_page, n;
1367 unsigned int count = c->rep_prefix ?
1368 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
1369 in_page = (ctxt->eflags & EFLG_DF) ?
1370 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1371 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1372 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1373 count);
1374 if (n == 0)
1375 n = 1;
1376 rc->pos = rc->end = 0;
1377 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1378 return 0;
1379 rc->end = n * size;
1380 }
1381
1382 memcpy(dest, rc->data + rc->pos, size);
1383 rc->pos += size;
1384 return 1;
1385 }
1386
1387 static u32 desc_limit_scaled(struct desc_struct *desc)
1388 {
1389 u32 limit = get_desc_limit(desc);
1390
1391 return desc->g ? (limit << 12) | 0xfff : limit;
1392 }
1393
1394 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1395 struct x86_emulate_ops *ops,
1396 u16 selector, struct desc_ptr *dt)
1397 {
1398 if (selector & 1 << 2) {
1399 struct desc_struct desc;
1400 memset (dt, 0, sizeof *dt);
1401 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
1402 return;
1403
1404 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1405 dt->address = get_desc_base(&desc);
1406 } else
1407 ops->get_gdt(dt, ctxt->vcpu);
1408 }
1409
1410 /* allowed just for 8 bytes segments */
1411 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1412 struct x86_emulate_ops *ops,
1413 u16 selector, struct desc_struct *desc)
1414 {
1415 struct desc_ptr dt;
1416 u16 index = selector >> 3;
1417 int ret;
1418 u32 err;
1419 ulong addr;
1420
1421 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1422
1423 if (dt.size < index * 8 + 7) {
1424 emulate_gp(ctxt, selector & 0xfffc);
1425 return X86EMUL_PROPAGATE_FAULT;
1426 }
1427 addr = dt.address + index * 8;
1428 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1429 if (ret == X86EMUL_PROPAGATE_FAULT)
1430 emulate_pf(ctxt, addr, err);
1431
1432 return ret;
1433 }
1434
1435 /* allowed just for 8 bytes segments */
1436 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1437 struct x86_emulate_ops *ops,
1438 u16 selector, struct desc_struct *desc)
1439 {
1440 struct desc_ptr dt;
1441 u16 index = selector >> 3;
1442 u32 err;
1443 ulong addr;
1444 int ret;
1445
1446 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1447
1448 if (dt.size < index * 8 + 7) {
1449 emulate_gp(ctxt, selector & 0xfffc);
1450 return X86EMUL_PROPAGATE_FAULT;
1451 }
1452
1453 addr = dt.address + index * 8;
1454 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
1455 if (ret == X86EMUL_PROPAGATE_FAULT)
1456 emulate_pf(ctxt, addr, err);
1457
1458 return ret;
1459 }
1460
1461 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1462 struct x86_emulate_ops *ops,
1463 u16 selector, int seg)
1464 {
1465 struct desc_struct seg_desc;
1466 u8 dpl, rpl, cpl;
1467 unsigned err_vec = GP_VECTOR;
1468 u32 err_code = 0;
1469 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1470 int ret;
1471
1472 memset(&seg_desc, 0, sizeof seg_desc);
1473
1474 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1475 || ctxt->mode == X86EMUL_MODE_REAL) {
1476 /* set real mode segment descriptor */
1477 set_desc_base(&seg_desc, selector << 4);
1478 set_desc_limit(&seg_desc, 0xffff);
1479 seg_desc.type = 3;
1480 seg_desc.p = 1;
1481 seg_desc.s = 1;
1482 goto load;
1483 }
1484
1485 /* NULL selector is not valid for TR, CS and SS */
1486 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1487 && null_selector)
1488 goto exception;
1489
1490 /* TR should be in GDT only */
1491 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1492 goto exception;
1493
1494 if (null_selector) /* for NULL selector skip all following checks */
1495 goto load;
1496
1497 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1498 if (ret != X86EMUL_CONTINUE)
1499 return ret;
1500
1501 err_code = selector & 0xfffc;
1502 err_vec = GP_VECTOR;
1503
1504 /* can't load system descriptor into segment selecor */
1505 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1506 goto exception;
1507
1508 if (!seg_desc.p) {
1509 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1510 goto exception;
1511 }
1512
1513 rpl = selector & 3;
1514 dpl = seg_desc.dpl;
1515 cpl = ops->cpl(ctxt->vcpu);
1516
1517 switch (seg) {
1518 case VCPU_SREG_SS:
1519 /*
1520 * segment is not a writable data segment or segment
1521 * selector's RPL != CPL or segment selector's RPL != CPL
1522 */
1523 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1524 goto exception;
1525 break;
1526 case VCPU_SREG_CS:
1527 if (!(seg_desc.type & 8))
1528 goto exception;
1529
1530 if (seg_desc.type & 4) {
1531 /* conforming */
1532 if (dpl > cpl)
1533 goto exception;
1534 } else {
1535 /* nonconforming */
1536 if (rpl > cpl || dpl != cpl)
1537 goto exception;
1538 }
1539 /* CS(RPL) <- CPL */
1540 selector = (selector & 0xfffc) | cpl;
1541 break;
1542 case VCPU_SREG_TR:
1543 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1544 goto exception;
1545 break;
1546 case VCPU_SREG_LDTR:
1547 if (seg_desc.s || seg_desc.type != 2)
1548 goto exception;
1549 break;
1550 default: /* DS, ES, FS, or GS */
1551 /*
1552 * segment is not a data or readable code segment or
1553 * ((segment is a data or nonconforming code segment)
1554 * and (both RPL and CPL > DPL))
1555 */
1556 if ((seg_desc.type & 0xa) == 0x8 ||
1557 (((seg_desc.type & 0xc) != 0xc) &&
1558 (rpl > dpl && cpl > dpl)))
1559 goto exception;
1560 break;
1561 }
1562
1563 if (seg_desc.s) {
1564 /* mark segment as accessed */
1565 seg_desc.type |= 1;
1566 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1567 if (ret != X86EMUL_CONTINUE)
1568 return ret;
1569 }
1570 load:
1571 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1572 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1573 return X86EMUL_CONTINUE;
1574 exception:
1575 emulate_exception(ctxt, err_vec, err_code, true);
1576 return X86EMUL_PROPAGATE_FAULT;
1577 }
1578
1579 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1580 struct x86_emulate_ops *ops)
1581 {
1582 int rc;
1583 struct decode_cache *c = &ctxt->decode;
1584 u32 err;
1585
1586 switch (c->dst.type) {
1587 case OP_REG:
1588 /* The 4-byte case *is* correct:
1589 * in 64-bit mode we zero-extend.
1590 */
1591 switch (c->dst.bytes) {
1592 case 1:
1593 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1594 break;
1595 case 2:
1596 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1597 break;
1598 case 4:
1599 *c->dst.ptr = (u32)c->dst.val;
1600 break; /* 64b: zero-ext */
1601 case 8:
1602 *c->dst.ptr = c->dst.val;
1603 break;
1604 }
1605 break;
1606 case OP_MEM:
1607 if (c->lock_prefix)
1608 rc = ops->cmpxchg_emulated(
1609 (unsigned long)c->dst.ptr,
1610 &c->dst.orig_val,
1611 &c->dst.val,
1612 c->dst.bytes,
1613 &err,
1614 ctxt->vcpu);
1615 else
1616 rc = ops->write_emulated(
1617 (unsigned long)c->dst.ptr,
1618 &c->dst.val,
1619 c->dst.bytes,
1620 &err,
1621 ctxt->vcpu);
1622 if (rc == X86EMUL_PROPAGATE_FAULT)
1623 emulate_pf(ctxt,
1624 (unsigned long)c->dst.ptr, err);
1625 if (rc != X86EMUL_CONTINUE)
1626 return rc;
1627 break;
1628 case OP_NONE:
1629 /* no writeback */
1630 break;
1631 default:
1632 break;
1633 }
1634 return X86EMUL_CONTINUE;
1635 }
1636
1637 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1638 struct x86_emulate_ops *ops)
1639 {
1640 struct decode_cache *c = &ctxt->decode;
1641
1642 c->dst.type = OP_MEM;
1643 c->dst.bytes = c->op_bytes;
1644 c->dst.val = c->src.val;
1645 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1646 c->dst.ptr = (void *) register_address(c, ss_base(ctxt, ops),
1647 c->regs[VCPU_REGS_RSP]);
1648 }
1649
1650 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1651 struct x86_emulate_ops *ops,
1652 void *dest, int len)
1653 {
1654 struct decode_cache *c = &ctxt->decode;
1655 int rc;
1656
1657 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1658 c->regs[VCPU_REGS_RSP]),
1659 dest, len);
1660 if (rc != X86EMUL_CONTINUE)
1661 return rc;
1662
1663 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1664 return rc;
1665 }
1666
1667 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1668 struct x86_emulate_ops *ops,
1669 void *dest, int len)
1670 {
1671 int rc;
1672 unsigned long val, change_mask;
1673 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1674 int cpl = ops->cpl(ctxt->vcpu);
1675
1676 rc = emulate_pop(ctxt, ops, &val, len);
1677 if (rc != X86EMUL_CONTINUE)
1678 return rc;
1679
1680 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1681 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1682
1683 switch(ctxt->mode) {
1684 case X86EMUL_MODE_PROT64:
1685 case X86EMUL_MODE_PROT32:
1686 case X86EMUL_MODE_PROT16:
1687 if (cpl == 0)
1688 change_mask |= EFLG_IOPL;
1689 if (cpl <= iopl)
1690 change_mask |= EFLG_IF;
1691 break;
1692 case X86EMUL_MODE_VM86:
1693 if (iopl < 3) {
1694 emulate_gp(ctxt, 0);
1695 return X86EMUL_PROPAGATE_FAULT;
1696 }
1697 change_mask |= EFLG_IF;
1698 break;
1699 default: /* real mode */
1700 change_mask |= (EFLG_IOPL | EFLG_IF);
1701 break;
1702 }
1703
1704 *(unsigned long *)dest =
1705 (ctxt->eflags & ~change_mask) | (val & change_mask);
1706
1707 return rc;
1708 }
1709
1710 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1711 struct x86_emulate_ops *ops, int seg)
1712 {
1713 struct decode_cache *c = &ctxt->decode;
1714
1715 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1716
1717 emulate_push(ctxt, ops);
1718 }
1719
1720 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1721 struct x86_emulate_ops *ops, int seg)
1722 {
1723 struct decode_cache *c = &ctxt->decode;
1724 unsigned long selector;
1725 int rc;
1726
1727 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1728 if (rc != X86EMUL_CONTINUE)
1729 return rc;
1730
1731 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1732 return rc;
1733 }
1734
1735 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1736 struct x86_emulate_ops *ops)
1737 {
1738 struct decode_cache *c = &ctxt->decode;
1739 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1740 int rc = X86EMUL_CONTINUE;
1741 int reg = VCPU_REGS_RAX;
1742
1743 while (reg <= VCPU_REGS_RDI) {
1744 (reg == VCPU_REGS_RSP) ?
1745 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1746
1747 emulate_push(ctxt, ops);
1748
1749 rc = writeback(ctxt, ops);
1750 if (rc != X86EMUL_CONTINUE)
1751 return rc;
1752
1753 ++reg;
1754 }
1755
1756 /* Disable writeback. */
1757 c->dst.type = OP_NONE;
1758
1759 return rc;
1760 }
1761
1762 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1763 struct x86_emulate_ops *ops)
1764 {
1765 struct decode_cache *c = &ctxt->decode;
1766 int rc = X86EMUL_CONTINUE;
1767 int reg = VCPU_REGS_RDI;
1768
1769 while (reg >= VCPU_REGS_RAX) {
1770 if (reg == VCPU_REGS_RSP) {
1771 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1772 c->op_bytes);
1773 --reg;
1774 }
1775
1776 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1777 if (rc != X86EMUL_CONTINUE)
1778 break;
1779 --reg;
1780 }
1781 return rc;
1782 }
1783
1784 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1785 struct x86_emulate_ops *ops)
1786 {
1787 struct decode_cache *c = &ctxt->decode;
1788 int rc = X86EMUL_CONTINUE;
1789 unsigned long temp_eip = 0;
1790 unsigned long temp_eflags = 0;
1791 unsigned long cs = 0;
1792 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1793 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1794 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1795 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1796
1797 /* TODO: Add stack limit check */
1798
1799 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1800
1801 if (rc != X86EMUL_CONTINUE)
1802 return rc;
1803
1804 if (temp_eip & ~0xffff) {
1805 emulate_gp(ctxt, 0);
1806 return X86EMUL_PROPAGATE_FAULT;
1807 }
1808
1809 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1810
1811 if (rc != X86EMUL_CONTINUE)
1812 return rc;
1813
1814 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1815
1816 if (rc != X86EMUL_CONTINUE)
1817 return rc;
1818
1819 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1820
1821 if (rc != X86EMUL_CONTINUE)
1822 return rc;
1823
1824 c->eip = temp_eip;
1825
1826
1827 if (c->op_bytes == 4)
1828 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1829 else if (c->op_bytes == 2) {
1830 ctxt->eflags &= ~0xffff;
1831 ctxt->eflags |= temp_eflags;
1832 }
1833
1834 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1835 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1836
1837 return rc;
1838 }
1839
1840 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1841 struct x86_emulate_ops* ops)
1842 {
1843 switch(ctxt->mode) {
1844 case X86EMUL_MODE_REAL:
1845 return emulate_iret_real(ctxt, ops);
1846 case X86EMUL_MODE_VM86:
1847 case X86EMUL_MODE_PROT16:
1848 case X86EMUL_MODE_PROT32:
1849 case X86EMUL_MODE_PROT64:
1850 default:
1851 /* iret from protected mode unimplemented yet */
1852 return X86EMUL_UNHANDLEABLE;
1853 }
1854 }
1855
1856 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1857 struct x86_emulate_ops *ops)
1858 {
1859 struct decode_cache *c = &ctxt->decode;
1860
1861 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1862 }
1863
1864 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1865 {
1866 struct decode_cache *c = &ctxt->decode;
1867 switch (c->modrm_reg) {
1868 case 0: /* rol */
1869 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1870 break;
1871 case 1: /* ror */
1872 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1873 break;
1874 case 2: /* rcl */
1875 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1876 break;
1877 case 3: /* rcr */
1878 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1879 break;
1880 case 4: /* sal/shl */
1881 case 6: /* sal/shl */
1882 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1883 break;
1884 case 5: /* shr */
1885 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1886 break;
1887 case 7: /* sar */
1888 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1889 break;
1890 }
1891 }
1892
1893 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1894 struct x86_emulate_ops *ops)
1895 {
1896 struct decode_cache *c = &ctxt->decode;
1897
1898 switch (c->modrm_reg) {
1899 case 0 ... 1: /* test */
1900 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1901 break;
1902 case 2: /* not */
1903 c->dst.val = ~c->dst.val;
1904 break;
1905 case 3: /* neg */
1906 emulate_1op("neg", c->dst, ctxt->eflags);
1907 break;
1908 default:
1909 return 0;
1910 }
1911 return 1;
1912 }
1913
1914 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1915 struct x86_emulate_ops *ops)
1916 {
1917 struct decode_cache *c = &ctxt->decode;
1918
1919 switch (c->modrm_reg) {
1920 case 0: /* inc */
1921 emulate_1op("inc", c->dst, ctxt->eflags);
1922 break;
1923 case 1: /* dec */
1924 emulate_1op("dec", c->dst, ctxt->eflags);
1925 break;
1926 case 2: /* call near abs */ {
1927 long int old_eip;
1928 old_eip = c->eip;
1929 c->eip = c->src.val;
1930 c->src.val = old_eip;
1931 emulate_push(ctxt, ops);
1932 break;
1933 }
1934 case 4: /* jmp abs */
1935 c->eip = c->src.val;
1936 break;
1937 case 6: /* push */
1938 emulate_push(ctxt, ops);
1939 break;
1940 }
1941 return X86EMUL_CONTINUE;
1942 }
1943
1944 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1945 struct x86_emulate_ops *ops)
1946 {
1947 struct decode_cache *c = &ctxt->decode;
1948 u64 old = c->dst.orig_val64;
1949
1950 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1951 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1952 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1953 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1954 ctxt->eflags &= ~EFLG_ZF;
1955 } else {
1956 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1957 (u32) c->regs[VCPU_REGS_RBX];
1958
1959 ctxt->eflags |= EFLG_ZF;
1960 }
1961 return X86EMUL_CONTINUE;
1962 }
1963
1964 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1965 struct x86_emulate_ops *ops)
1966 {
1967 struct decode_cache *c = &ctxt->decode;
1968 int rc;
1969 unsigned long cs;
1970
1971 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1972 if (rc != X86EMUL_CONTINUE)
1973 return rc;
1974 if (c->op_bytes == 4)
1975 c->eip = (u32)c->eip;
1976 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1977 if (rc != X86EMUL_CONTINUE)
1978 return rc;
1979 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1980 return rc;
1981 }
1982
1983 static inline void
1984 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1985 struct x86_emulate_ops *ops, struct desc_struct *cs,
1986 struct desc_struct *ss)
1987 {
1988 memset(cs, 0, sizeof(struct desc_struct));
1989 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1990 memset(ss, 0, sizeof(struct desc_struct));
1991
1992 cs->l = 0; /* will be adjusted later */
1993 set_desc_base(cs, 0); /* flat segment */
1994 cs->g = 1; /* 4kb granularity */
1995 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1996 cs->type = 0x0b; /* Read, Execute, Accessed */
1997 cs->s = 1;
1998 cs->dpl = 0; /* will be adjusted later */
1999 cs->p = 1;
2000 cs->d = 1;
2001
2002 set_desc_base(ss, 0); /* flat segment */
2003 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2004 ss->g = 1; /* 4kb granularity */
2005 ss->s = 1;
2006 ss->type = 0x03; /* Read/Write, Accessed */
2007 ss->d = 1; /* 32bit stack segment */
2008 ss->dpl = 0;
2009 ss->p = 1;
2010 }
2011
2012 static int
2013 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2014 {
2015 struct decode_cache *c = &ctxt->decode;
2016 struct desc_struct cs, ss;
2017 u64 msr_data;
2018 u16 cs_sel, ss_sel;
2019
2020 /* syscall is not available in real mode */
2021 if (ctxt->mode == X86EMUL_MODE_REAL ||
2022 ctxt->mode == X86EMUL_MODE_VM86) {
2023 emulate_ud(ctxt);
2024 return X86EMUL_PROPAGATE_FAULT;
2025 }
2026
2027 setup_syscalls_segments(ctxt, ops, &cs, &ss);
2028
2029 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
2030 msr_data >>= 32;
2031 cs_sel = (u16)(msr_data & 0xfffc);
2032 ss_sel = (u16)(msr_data + 8);
2033
2034 if (is_long_mode(ctxt->vcpu)) {
2035 cs.d = 0;
2036 cs.l = 1;
2037 }
2038 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2039 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2040 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2041 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
2042
2043 c->regs[VCPU_REGS_RCX] = c->eip;
2044 if (is_long_mode(ctxt->vcpu)) {
2045 #ifdef CONFIG_X86_64
2046 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2047
2048 ops->get_msr(ctxt->vcpu,
2049 ctxt->mode == X86EMUL_MODE_PROT64 ?
2050 MSR_LSTAR : MSR_CSTAR, &msr_data);
2051 c->eip = msr_data;
2052
2053 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
2054 ctxt->eflags &= ~(msr_data | EFLG_RF);
2055 #endif
2056 } else {
2057 /* legacy mode */
2058 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
2059 c->eip = (u32)msr_data;
2060
2061 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2062 }
2063
2064 return X86EMUL_CONTINUE;
2065 }
2066
2067 static int
2068 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2069 {
2070 struct decode_cache *c = &ctxt->decode;
2071 struct desc_struct cs, ss;
2072 u64 msr_data;
2073 u16 cs_sel, ss_sel;
2074
2075 /* inject #GP if in real mode */
2076 if (ctxt->mode == X86EMUL_MODE_REAL) {
2077 emulate_gp(ctxt, 0);
2078 return X86EMUL_PROPAGATE_FAULT;
2079 }
2080
2081 /* XXX sysenter/sysexit have not been tested in 64bit mode.
2082 * Therefore, we inject an #UD.
2083 */
2084 if (ctxt->mode == X86EMUL_MODE_PROT64) {
2085 emulate_ud(ctxt);
2086 return X86EMUL_PROPAGATE_FAULT;
2087 }
2088
2089 setup_syscalls_segments(ctxt, ops, &cs, &ss);
2090
2091 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
2092 switch (ctxt->mode) {
2093 case X86EMUL_MODE_PROT32:
2094 if ((msr_data & 0xfffc) == 0x0) {
2095 emulate_gp(ctxt, 0);
2096 return X86EMUL_PROPAGATE_FAULT;
2097 }
2098 break;
2099 case X86EMUL_MODE_PROT64:
2100 if (msr_data == 0x0) {
2101 emulate_gp(ctxt, 0);
2102 return X86EMUL_PROPAGATE_FAULT;
2103 }
2104 break;
2105 }
2106
2107 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2108 cs_sel = (u16)msr_data;
2109 cs_sel &= ~SELECTOR_RPL_MASK;
2110 ss_sel = cs_sel + 8;
2111 ss_sel &= ~SELECTOR_RPL_MASK;
2112 if (ctxt->mode == X86EMUL_MODE_PROT64
2113 || is_long_mode(ctxt->vcpu)) {
2114 cs.d = 0;
2115 cs.l = 1;
2116 }
2117
2118 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2119 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2120 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2121 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
2122
2123 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
2124 c->eip = msr_data;
2125
2126 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
2127 c->regs[VCPU_REGS_RSP] = msr_data;
2128
2129 return X86EMUL_CONTINUE;
2130 }
2131
2132 static int
2133 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2134 {
2135 struct decode_cache *c = &ctxt->decode;
2136 struct desc_struct cs, ss;
2137 u64 msr_data;
2138 int usermode;
2139 u16 cs_sel, ss_sel;
2140
2141 /* inject #GP if in real mode or Virtual 8086 mode */
2142 if (ctxt->mode == X86EMUL_MODE_REAL ||
2143 ctxt->mode == X86EMUL_MODE_VM86) {
2144 emulate_gp(ctxt, 0);
2145 return X86EMUL_PROPAGATE_FAULT;
2146 }
2147
2148 setup_syscalls_segments(ctxt, ops, &cs, &ss);
2149
2150 if ((c->rex_prefix & 0x8) != 0x0)
2151 usermode = X86EMUL_MODE_PROT64;
2152 else
2153 usermode = X86EMUL_MODE_PROT32;
2154
2155 cs.dpl = 3;
2156 ss.dpl = 3;
2157 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
2158 switch (usermode) {
2159 case X86EMUL_MODE_PROT32:
2160 cs_sel = (u16)(msr_data + 16);
2161 if ((msr_data & 0xfffc) == 0x0) {
2162 emulate_gp(ctxt, 0);
2163 return X86EMUL_PROPAGATE_FAULT;
2164 }
2165 ss_sel = (u16)(msr_data + 24);
2166 break;
2167 case X86EMUL_MODE_PROT64:
2168 cs_sel = (u16)(msr_data + 32);
2169 if (msr_data == 0x0) {
2170 emulate_gp(ctxt, 0);
2171 return X86EMUL_PROPAGATE_FAULT;
2172 }
2173 ss_sel = cs_sel + 8;
2174 cs.d = 0;
2175 cs.l = 1;
2176 break;
2177 }
2178 cs_sel |= SELECTOR_RPL_MASK;
2179 ss_sel |= SELECTOR_RPL_MASK;
2180
2181 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
2182 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
2183 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
2184 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
2185
2186 c->eip = c->regs[VCPU_REGS_RDX];
2187 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2188
2189 return X86EMUL_CONTINUE;
2190 }
2191
2192 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
2193 struct x86_emulate_ops *ops)
2194 {
2195 int iopl;
2196 if (ctxt->mode == X86EMUL_MODE_REAL)
2197 return false;
2198 if (ctxt->mode == X86EMUL_MODE_VM86)
2199 return true;
2200 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2201 return ops->cpl(ctxt->vcpu) > iopl;
2202 }
2203
2204 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2205 struct x86_emulate_ops *ops,
2206 u16 port, u16 len)
2207 {
2208 struct desc_struct tr_seg;
2209 int r;
2210 u16 io_bitmap_ptr;
2211 u8 perm, bit_idx = port & 0x7;
2212 unsigned mask = (1 << len) - 1;
2213
2214 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
2215 if (!tr_seg.p)
2216 return false;
2217 if (desc_limit_scaled(&tr_seg) < 103)
2218 return false;
2219 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
2220 ctxt->vcpu, NULL);
2221 if (r != X86EMUL_CONTINUE)
2222 return false;
2223 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2224 return false;
2225 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
2226 &perm, 1, ctxt->vcpu, NULL);
2227 if (r != X86EMUL_CONTINUE)
2228 return false;
2229 if ((perm >> bit_idx) & mask)
2230 return false;
2231 return true;
2232 }
2233
2234 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2235 struct x86_emulate_ops *ops,
2236 u16 port, u16 len)
2237 {
2238 if (emulator_bad_iopl(ctxt, ops))
2239 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
2240 return false;
2241 return true;
2242 }
2243
2244 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2245 struct x86_emulate_ops *ops,
2246 struct tss_segment_16 *tss)
2247 {
2248 struct decode_cache *c = &ctxt->decode;
2249
2250 tss->ip = c->eip;
2251 tss->flag = ctxt->eflags;
2252 tss->ax = c->regs[VCPU_REGS_RAX];
2253 tss->cx = c->regs[VCPU_REGS_RCX];
2254 tss->dx = c->regs[VCPU_REGS_RDX];
2255 tss->bx = c->regs[VCPU_REGS_RBX];
2256 tss->sp = c->regs[VCPU_REGS_RSP];
2257 tss->bp = c->regs[VCPU_REGS_RBP];
2258 tss->si = c->regs[VCPU_REGS_RSI];
2259 tss->di = c->regs[VCPU_REGS_RDI];
2260
2261 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2262 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2263 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2264 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2265 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2266 }
2267
2268 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2269 struct x86_emulate_ops *ops,
2270 struct tss_segment_16 *tss)
2271 {
2272 struct decode_cache *c = &ctxt->decode;
2273 int ret;
2274
2275 c->eip = tss->ip;
2276 ctxt->eflags = tss->flag | 2;
2277 c->regs[VCPU_REGS_RAX] = tss->ax;
2278 c->regs[VCPU_REGS_RCX] = tss->cx;
2279 c->regs[VCPU_REGS_RDX] = tss->dx;
2280 c->regs[VCPU_REGS_RBX] = tss->bx;
2281 c->regs[VCPU_REGS_RSP] = tss->sp;
2282 c->regs[VCPU_REGS_RBP] = tss->bp;
2283 c->regs[VCPU_REGS_RSI] = tss->si;
2284 c->regs[VCPU_REGS_RDI] = tss->di;
2285
2286 /*
2287 * SDM says that segment selectors are loaded before segment
2288 * descriptors
2289 */
2290 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2291 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2292 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2293 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2294 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2295
2296 /*
2297 * Now load segment descriptors. If fault happenes at this stage
2298 * it is handled in a context of new task
2299 */
2300 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2301 if (ret != X86EMUL_CONTINUE)
2302 return ret;
2303 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2304 if (ret != X86EMUL_CONTINUE)
2305 return ret;
2306 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2307 if (ret != X86EMUL_CONTINUE)
2308 return ret;
2309 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2310 if (ret != X86EMUL_CONTINUE)
2311 return ret;
2312 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2313 if (ret != X86EMUL_CONTINUE)
2314 return ret;
2315
2316 return X86EMUL_CONTINUE;
2317 }
2318
2319 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2320 struct x86_emulate_ops *ops,
2321 u16 tss_selector, u16 old_tss_sel,
2322 ulong old_tss_base, struct desc_struct *new_desc)
2323 {
2324 struct tss_segment_16 tss_seg;
2325 int ret;
2326 u32 err, new_tss_base = get_desc_base(new_desc);
2327
2328 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2329 &err);
2330 if (ret == X86EMUL_PROPAGATE_FAULT) {
2331 /* FIXME: need to provide precise fault address */
2332 emulate_pf(ctxt, old_tss_base, err);
2333 return ret;
2334 }
2335
2336 save_state_to_tss16(ctxt, ops, &tss_seg);
2337
2338 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2339 &err);
2340 if (ret == X86EMUL_PROPAGATE_FAULT) {
2341 /* FIXME: need to provide precise fault address */
2342 emulate_pf(ctxt, old_tss_base, err);
2343 return ret;
2344 }
2345
2346 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2347 &err);
2348 if (ret == X86EMUL_PROPAGATE_FAULT) {
2349 /* FIXME: need to provide precise fault address */
2350 emulate_pf(ctxt, new_tss_base, err);
2351 return ret;
2352 }
2353
2354 if (old_tss_sel != 0xffff) {
2355 tss_seg.prev_task_link = old_tss_sel;
2356
2357 ret = ops->write_std(new_tss_base,
2358 &tss_seg.prev_task_link,
2359 sizeof tss_seg.prev_task_link,
2360 ctxt->vcpu, &err);
2361 if (ret == X86EMUL_PROPAGATE_FAULT) {
2362 /* FIXME: need to provide precise fault address */
2363 emulate_pf(ctxt, new_tss_base, err);
2364 return ret;
2365 }
2366 }
2367
2368 return load_state_from_tss16(ctxt, ops, &tss_seg);
2369 }
2370
2371 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2372 struct x86_emulate_ops *ops,
2373 struct tss_segment_32 *tss)
2374 {
2375 struct decode_cache *c = &ctxt->decode;
2376
2377 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2378 tss->eip = c->eip;
2379 tss->eflags = ctxt->eflags;
2380 tss->eax = c->regs[VCPU_REGS_RAX];
2381 tss->ecx = c->regs[VCPU_REGS_RCX];
2382 tss->edx = c->regs[VCPU_REGS_RDX];
2383 tss->ebx = c->regs[VCPU_REGS_RBX];
2384 tss->esp = c->regs[VCPU_REGS_RSP];
2385 tss->ebp = c->regs[VCPU_REGS_RBP];
2386 tss->esi = c->regs[VCPU_REGS_RSI];
2387 tss->edi = c->regs[VCPU_REGS_RDI];
2388
2389 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2390 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2391 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2392 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2393 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2394 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2395 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2396 }
2397
2398 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2399 struct x86_emulate_ops *ops,
2400 struct tss_segment_32 *tss)
2401 {
2402 struct decode_cache *c = &ctxt->decode;
2403 int ret;
2404
2405 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
2406 emulate_gp(ctxt, 0);
2407 return X86EMUL_PROPAGATE_FAULT;
2408 }
2409 c->eip = tss->eip;
2410 ctxt->eflags = tss->eflags | 2;
2411 c->regs[VCPU_REGS_RAX] = tss->eax;
2412 c->regs[VCPU_REGS_RCX] = tss->ecx;
2413 c->regs[VCPU_REGS_RDX] = tss->edx;
2414 c->regs[VCPU_REGS_RBX] = tss->ebx;
2415 c->regs[VCPU_REGS_RSP] = tss->esp;
2416 c->regs[VCPU_REGS_RBP] = tss->ebp;
2417 c->regs[VCPU_REGS_RSI] = tss->esi;
2418 c->regs[VCPU_REGS_RDI] = tss->edi;
2419
2420 /*
2421 * SDM says that segment selectors are loaded before segment
2422 * descriptors
2423 */
2424 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2425 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2426 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2427 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2428 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2429 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2430 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2431
2432 /*
2433 * Now load segment descriptors. If fault happenes at this stage
2434 * it is handled in a context of new task
2435 */
2436 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2437 if (ret != X86EMUL_CONTINUE)
2438 return ret;
2439 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2440 if (ret != X86EMUL_CONTINUE)
2441 return ret;
2442 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2443 if (ret != X86EMUL_CONTINUE)
2444 return ret;
2445 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2446 if (ret != X86EMUL_CONTINUE)
2447 return ret;
2448 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2449 if (ret != X86EMUL_CONTINUE)
2450 return ret;
2451 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2452 if (ret != X86EMUL_CONTINUE)
2453 return ret;
2454 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2455 if (ret != X86EMUL_CONTINUE)
2456 return ret;
2457
2458 return X86EMUL_CONTINUE;
2459 }
2460
2461 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2462 struct x86_emulate_ops *ops,
2463 u16 tss_selector, u16 old_tss_sel,
2464 ulong old_tss_base, struct desc_struct *new_desc)
2465 {
2466 struct tss_segment_32 tss_seg;
2467 int ret;
2468 u32 err, new_tss_base = get_desc_base(new_desc);
2469
2470 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2471 &err);
2472 if (ret == X86EMUL_PROPAGATE_FAULT) {
2473 /* FIXME: need to provide precise fault address */
2474 emulate_pf(ctxt, old_tss_base, err);
2475 return ret;
2476 }
2477
2478 save_state_to_tss32(ctxt, ops, &tss_seg);
2479
2480 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2481 &err);
2482 if (ret == X86EMUL_PROPAGATE_FAULT) {
2483 /* FIXME: need to provide precise fault address */
2484 emulate_pf(ctxt, old_tss_base, err);
2485 return ret;
2486 }
2487
2488 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2489 &err);
2490 if (ret == X86EMUL_PROPAGATE_FAULT) {
2491 /* FIXME: need to provide precise fault address */
2492 emulate_pf(ctxt, new_tss_base, err);
2493 return ret;
2494 }
2495
2496 if (old_tss_sel != 0xffff) {
2497 tss_seg.prev_task_link = old_tss_sel;
2498
2499 ret = ops->write_std(new_tss_base,
2500 &tss_seg.prev_task_link,
2501 sizeof tss_seg.prev_task_link,
2502 ctxt->vcpu, &err);
2503 if (ret == X86EMUL_PROPAGATE_FAULT) {
2504 /* FIXME: need to provide precise fault address */
2505 emulate_pf(ctxt, new_tss_base, err);
2506 return ret;
2507 }
2508 }
2509
2510 return load_state_from_tss32(ctxt, ops, &tss_seg);
2511 }
2512
2513 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2514 struct x86_emulate_ops *ops,
2515 u16 tss_selector, int reason,
2516 bool has_error_code, u32 error_code)
2517 {
2518 struct desc_struct curr_tss_desc, next_tss_desc;
2519 int ret;
2520 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2521 ulong old_tss_base =
2522 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2523 u32 desc_limit;
2524
2525 /* FIXME: old_tss_base == ~0 ? */
2526
2527 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2528 if (ret != X86EMUL_CONTINUE)
2529 return ret;
2530 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2531 if (ret != X86EMUL_CONTINUE)
2532 return ret;
2533
2534 /* FIXME: check that next_tss_desc is tss */
2535
2536 if (reason != TASK_SWITCH_IRET) {
2537 if ((tss_selector & 3) > next_tss_desc.dpl ||
2538 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2539 emulate_gp(ctxt, 0);
2540 return X86EMUL_PROPAGATE_FAULT;
2541 }
2542 }
2543
2544 desc_limit = desc_limit_scaled(&next_tss_desc);
2545 if (!next_tss_desc.p ||
2546 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2547 desc_limit < 0x2b)) {
2548 emulate_ts(ctxt, tss_selector & 0xfffc);
2549 return X86EMUL_PROPAGATE_FAULT;
2550 }
2551
2552 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2553 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2554 write_segment_descriptor(ctxt, ops, old_tss_sel,
2555 &curr_tss_desc);
2556 }
2557
2558 if (reason == TASK_SWITCH_IRET)
2559 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2560
2561 /* set back link to prev task only if NT bit is set in eflags
2562 note that old_tss_sel is not used afetr this point */
2563 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2564 old_tss_sel = 0xffff;
2565
2566 if (next_tss_desc.type & 8)
2567 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2568 old_tss_base, &next_tss_desc);
2569 else
2570 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2571 old_tss_base, &next_tss_desc);
2572 if (ret != X86EMUL_CONTINUE)
2573 return ret;
2574
2575 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2576 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2577
2578 if (reason != TASK_SWITCH_IRET) {
2579 next_tss_desc.type |= (1 << 1); /* set busy flag */
2580 write_segment_descriptor(ctxt, ops, tss_selector,
2581 &next_tss_desc);
2582 }
2583
2584 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2585 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2586 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2587
2588 if (has_error_code) {
2589 struct decode_cache *c = &ctxt->decode;
2590
2591 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2592 c->lock_prefix = 0;
2593 c->src.val = (unsigned long) error_code;
2594 emulate_push(ctxt, ops);
2595 }
2596
2597 return ret;
2598 }
2599
2600 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2601 struct x86_emulate_ops *ops,
2602 u16 tss_selector, int reason,
2603 bool has_error_code, u32 error_code)
2604 {
2605 struct decode_cache *c = &ctxt->decode;
2606 int rc;
2607
2608 c->eip = ctxt->eip;
2609 c->dst.type = OP_NONE;
2610
2611 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2612 has_error_code, error_code);
2613
2614 if (rc == X86EMUL_CONTINUE) {
2615 rc = writeback(ctxt, ops);
2616 if (rc == X86EMUL_CONTINUE)
2617 ctxt->eip = c->eip;
2618 }
2619
2620 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2621 }
2622
2623 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2624 int reg, struct operand *op)
2625 {
2626 struct decode_cache *c = &ctxt->decode;
2627 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2628
2629 register_address_increment(c, &c->regs[reg], df * op->bytes);
2630 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]);
2631 }
2632
2633 int
2634 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2635 {
2636 u64 msr_data;
2637 struct decode_cache *c = &ctxt->decode;
2638 int rc = X86EMUL_CONTINUE;
2639 int saved_dst_type = c->dst.type;
2640
2641 ctxt->decode.mem_read.pos = 0;
2642
2643 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2644 emulate_ud(ctxt);
2645 goto done;
2646 }
2647
2648 /* LOCK prefix is allowed only with some instructions */
2649 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2650 emulate_ud(ctxt);
2651 goto done;
2652 }
2653
2654 /* Privileged instruction can be executed only in CPL=0 */
2655 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2656 emulate_gp(ctxt, 0);
2657 goto done;
2658 }
2659
2660 if (c->rep_prefix && (c->d & String)) {
2661 ctxt->restart = true;
2662 /* All REP prefixes have the same first termination condition */
2663 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2664 string_done:
2665 ctxt->restart = false;
2666 ctxt->eip = c->eip;
2667 goto done;
2668 }
2669 /* The second termination condition only applies for REPE
2670 * and REPNE. Test if the repeat string operation prefix is
2671 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2672 * corresponding termination condition according to:
2673 * - if REPE/REPZ and ZF = 0 then done
2674 * - if REPNE/REPNZ and ZF = 1 then done
2675 */
2676 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2677 (c->b == 0xae) || (c->b == 0xaf)) {
2678 if ((c->rep_prefix == REPE_PREFIX) &&
2679 ((ctxt->eflags & EFLG_ZF) == 0))
2680 goto string_done;
2681 if ((c->rep_prefix == REPNE_PREFIX) &&
2682 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2683 goto string_done;
2684 }
2685 c->eip = ctxt->eip;
2686 }
2687
2688 if (c->src.type == OP_MEM) {
2689 rc = read_emulated(ctxt, ops, (unsigned long)c->src.ptr,
2690 c->src.valptr, c->src.bytes);
2691 if (rc != X86EMUL_CONTINUE)
2692 goto done;
2693 c->src.orig_val64 = c->src.val64;
2694 }
2695
2696 if (c->src2.type == OP_MEM) {
2697 rc = read_emulated(ctxt, ops, (unsigned long)c->src2.ptr,
2698 &c->src2.val, c->src2.bytes);
2699 if (rc != X86EMUL_CONTINUE)
2700 goto done;
2701 }
2702
2703 if ((c->d & DstMask) == ImplicitOps)
2704 goto special_insn;
2705
2706
2707 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2708 /* optimisation - avoid slow emulated read if Mov */
2709 rc = read_emulated(ctxt, ops, (unsigned long)c->dst.ptr,
2710 &c->dst.val, c->dst.bytes);
2711 if (rc != X86EMUL_CONTINUE)
2712 goto done;
2713 }
2714 c->dst.orig_val = c->dst.val;
2715
2716 special_insn:
2717
2718 if (c->twobyte)
2719 goto twobyte_insn;
2720
2721 switch (c->b) {
2722 case 0x00 ... 0x05:
2723 add: /* add */
2724 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2725 break;
2726 case 0x06: /* push es */
2727 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
2728 break;
2729 case 0x07: /* pop es */
2730 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2731 if (rc != X86EMUL_CONTINUE)
2732 goto done;
2733 break;
2734 case 0x08 ... 0x0d:
2735 or: /* or */
2736 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2737 break;
2738 case 0x0e: /* push cs */
2739 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
2740 break;
2741 case 0x10 ... 0x15:
2742 adc: /* adc */
2743 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2744 break;
2745 case 0x16: /* push ss */
2746 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
2747 break;
2748 case 0x17: /* pop ss */
2749 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2750 if (rc != X86EMUL_CONTINUE)
2751 goto done;
2752 break;
2753 case 0x18 ... 0x1d:
2754 sbb: /* sbb */
2755 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2756 break;
2757 case 0x1e: /* push ds */
2758 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
2759 break;
2760 case 0x1f: /* pop ds */
2761 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2762 if (rc != X86EMUL_CONTINUE)
2763 goto done;
2764 break;
2765 case 0x20 ... 0x25:
2766 and: /* and */
2767 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2768 break;
2769 case 0x28 ... 0x2d:
2770 sub: /* sub */
2771 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2772 break;
2773 case 0x30 ... 0x35:
2774 xor: /* xor */
2775 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2776 break;
2777 case 0x38 ... 0x3d:
2778 cmp: /* cmp */
2779 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2780 break;
2781 case 0x40 ... 0x47: /* inc r16/r32 */
2782 emulate_1op("inc", c->dst, ctxt->eflags);
2783 break;
2784 case 0x48 ... 0x4f: /* dec r16/r32 */
2785 emulate_1op("dec", c->dst, ctxt->eflags);
2786 break;
2787 case 0x50 ... 0x57: /* push reg */
2788 emulate_push(ctxt, ops);
2789 break;
2790 case 0x58 ... 0x5f: /* pop reg */
2791 pop_instruction:
2792 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2793 if (rc != X86EMUL_CONTINUE)
2794 goto done;
2795 break;
2796 case 0x60: /* pusha */
2797 rc = emulate_pusha(ctxt, ops);
2798 if (rc != X86EMUL_CONTINUE)
2799 goto done;
2800 break;
2801 case 0x61: /* popa */
2802 rc = emulate_popa(ctxt, ops);
2803 if (rc != X86EMUL_CONTINUE)
2804 goto done;
2805 break;
2806 case 0x63: /* movsxd */
2807 if (ctxt->mode != X86EMUL_MODE_PROT64)
2808 goto cannot_emulate;
2809 c->dst.val = (s32) c->src.val;
2810 break;
2811 case 0x68: /* push imm */
2812 case 0x6a: /* push imm8 */
2813 emulate_push(ctxt, ops);
2814 break;
2815 case 0x6c: /* insb */
2816 case 0x6d: /* insw/insd */
2817 c->dst.bytes = min(c->dst.bytes, 4u);
2818 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2819 c->dst.bytes)) {
2820 emulate_gp(ctxt, 0);
2821 goto done;
2822 }
2823 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2824 c->regs[VCPU_REGS_RDX], &c->dst.val))
2825 goto done; /* IO is needed, skip writeback */
2826 break;
2827 case 0x6e: /* outsb */
2828 case 0x6f: /* outsw/outsd */
2829 c->src.bytes = min(c->src.bytes, 4u);
2830 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2831 c->src.bytes)) {
2832 emulate_gp(ctxt, 0);
2833 goto done;
2834 }
2835 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2836 &c->src.val, 1, ctxt->vcpu);
2837
2838 c->dst.type = OP_NONE; /* nothing to writeback */
2839 break;
2840 case 0x70 ... 0x7f: /* jcc (short) */
2841 if (test_cc(c->b, ctxt->eflags))
2842 jmp_rel(c, c->src.val);
2843 break;
2844 case 0x80 ... 0x83: /* Grp1 */
2845 switch (c->modrm_reg) {
2846 case 0:
2847 goto add;
2848 case 1:
2849 goto or;
2850 case 2:
2851 goto adc;
2852 case 3:
2853 goto sbb;
2854 case 4:
2855 goto and;
2856 case 5:
2857 goto sub;
2858 case 6:
2859 goto xor;
2860 case 7:
2861 goto cmp;
2862 }
2863 break;
2864 case 0x84 ... 0x85:
2865 test:
2866 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2867 break;
2868 case 0x86 ... 0x87: /* xchg */
2869 xchg:
2870 /* Write back the register source. */
2871 switch (c->dst.bytes) {
2872 case 1:
2873 *(u8 *) c->src.ptr = (u8) c->dst.val;
2874 break;
2875 case 2:
2876 *(u16 *) c->src.ptr = (u16) c->dst.val;
2877 break;
2878 case 4:
2879 *c->src.ptr = (u32) c->dst.val;
2880 break; /* 64b reg: zero-extend */
2881 case 8:
2882 *c->src.ptr = c->dst.val;
2883 break;
2884 }
2885 /*
2886 * Write back the memory destination with implicit LOCK
2887 * prefix.
2888 */
2889 c->dst.val = c->src.val;
2890 c->lock_prefix = 1;
2891 break;
2892 case 0x88 ... 0x8b: /* mov */
2893 goto mov;
2894 case 0x8c: /* mov r/m, sreg */
2895 if (c->modrm_reg > VCPU_SREG_GS) {
2896 emulate_ud(ctxt);
2897 goto done;
2898 }
2899 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
2900 break;
2901 case 0x8d: /* lea r16/r32, m */
2902 c->dst.val = c->modrm_ea;
2903 break;
2904 case 0x8e: { /* mov seg, r/m16 */
2905 uint16_t sel;
2906
2907 sel = c->src.val;
2908
2909 if (c->modrm_reg == VCPU_SREG_CS ||
2910 c->modrm_reg > VCPU_SREG_GS) {
2911 emulate_ud(ctxt);
2912 goto done;
2913 }
2914
2915 if (c->modrm_reg == VCPU_SREG_SS)
2916 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
2917
2918 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
2919
2920 c->dst.type = OP_NONE; /* Disable writeback. */
2921 break;
2922 }
2923 case 0x8f: /* pop (sole member of Grp1a) */
2924 rc = emulate_grp1a(ctxt, ops);
2925 if (rc != X86EMUL_CONTINUE)
2926 goto done;
2927 break;
2928 case 0x90: /* nop / xchg r8,rax */
2929 if (c->dst.ptr == (unsigned long *)&c->regs[VCPU_REGS_RAX]) {
2930 c->dst.type = OP_NONE; /* nop */
2931 break;
2932 }
2933 case 0x91 ... 0x97: /* xchg reg,rax */
2934 c->src.type = OP_REG;
2935 c->src.bytes = c->op_bytes;
2936 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
2937 c->src.val = *(c->src.ptr);
2938 goto xchg;
2939 case 0x9c: /* pushf */
2940 c->src.val = (unsigned long) ctxt->eflags;
2941 emulate_push(ctxt, ops);
2942 break;
2943 case 0x9d: /* popf */
2944 c->dst.type = OP_REG;
2945 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2946 c->dst.bytes = c->op_bytes;
2947 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
2948 if (rc != X86EMUL_CONTINUE)
2949 goto done;
2950 break;
2951 case 0xa0 ... 0xa3: /* mov */
2952 case 0xa4 ... 0xa5: /* movs */
2953 goto mov;
2954 case 0xa6 ... 0xa7: /* cmps */
2955 c->dst.type = OP_NONE; /* Disable writeback. */
2956 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
2957 goto cmp;
2958 case 0xa8 ... 0xa9: /* test ax, imm */
2959 goto test;
2960 case 0xaa ... 0xab: /* stos */
2961 c->dst.val = c->regs[VCPU_REGS_RAX];
2962 break;
2963 case 0xac ... 0xad: /* lods */
2964 goto mov;
2965 case 0xae ... 0xaf: /* scas */
2966 DPRINTF("Urk! I don't handle SCAS.\n");
2967 goto cannot_emulate;
2968 case 0xb0 ... 0xbf: /* mov r, imm */
2969 goto mov;
2970 case 0xc0 ... 0xc1:
2971 emulate_grp2(ctxt);
2972 break;
2973 case 0xc3: /* ret */
2974 c->dst.type = OP_REG;
2975 c->dst.ptr = &c->eip;
2976 c->dst.bytes = c->op_bytes;
2977 goto pop_instruction;
2978 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
2979 mov:
2980 c->dst.val = c->src.val;
2981 break;
2982 case 0xcb: /* ret far */
2983 rc = emulate_ret_far(ctxt, ops);
2984 if (rc != X86EMUL_CONTINUE)
2985 goto done;
2986 break;
2987 case 0xcf: /* iret */
2988 rc = emulate_iret(ctxt, ops);
2989
2990 if (rc != X86EMUL_CONTINUE)
2991 goto done;
2992 break;
2993 case 0xd0 ... 0xd1: /* Grp2 */
2994 c->src.val = 1;
2995 emulate_grp2(ctxt);
2996 break;
2997 case 0xd2 ... 0xd3: /* Grp2 */
2998 c->src.val = c->regs[VCPU_REGS_RCX];
2999 emulate_grp2(ctxt);
3000 break;
3001 case 0xe4: /* inb */
3002 case 0xe5: /* in */
3003 goto do_io_in;
3004 case 0xe6: /* outb */
3005 case 0xe7: /* out */
3006 goto do_io_out;
3007 case 0xe8: /* call (near) */ {
3008 long int rel = c->src.val;
3009 c->src.val = (unsigned long) c->eip;
3010 jmp_rel(c, rel);
3011 emulate_push(ctxt, ops);
3012 break;
3013 }
3014 case 0xe9: /* jmp rel */
3015 goto jmp;
3016 case 0xea: { /* jmp far */
3017 unsigned short sel;
3018 jump_far:
3019 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3020
3021 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3022 goto done;
3023
3024 c->eip = 0;
3025 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3026 break;
3027 }
3028 case 0xeb:
3029 jmp: /* jmp rel short */
3030 jmp_rel(c, c->src.val);
3031 c->dst.type = OP_NONE; /* Disable writeback. */
3032 break;
3033 case 0xec: /* in al,dx */
3034 case 0xed: /* in (e/r)ax,dx */
3035 c->src.val = c->regs[VCPU_REGS_RDX];
3036 do_io_in:
3037 c->dst.bytes = min(c->dst.bytes, 4u);
3038 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3039 emulate_gp(ctxt, 0);
3040 goto done;
3041 }
3042 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3043 &c->dst.val))
3044 goto done; /* IO is needed */
3045 break;
3046 case 0xee: /* out dx,al */
3047 case 0xef: /* out dx,(e/r)ax */
3048 c->src.val = c->regs[VCPU_REGS_RDX];
3049 do_io_out:
3050 c->dst.bytes = min(c->dst.bytes, 4u);
3051 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3052 emulate_gp(ctxt, 0);
3053 goto done;
3054 }
3055 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3056 ctxt->vcpu);
3057 c->dst.type = OP_NONE; /* Disable writeback. */
3058 break;
3059 case 0xf4: /* hlt */
3060 ctxt->vcpu->arch.halt_request = 1;
3061 break;
3062 case 0xf5: /* cmc */
3063 /* complement carry flag from eflags reg */
3064 ctxt->eflags ^= EFLG_CF;
3065 c->dst.type = OP_NONE; /* Disable writeback. */
3066 break;
3067 case 0xf6 ... 0xf7: /* Grp3 */
3068 if (!emulate_grp3(ctxt, ops))
3069 goto cannot_emulate;
3070 break;
3071 case 0xf8: /* clc */
3072 ctxt->eflags &= ~EFLG_CF;
3073 c->dst.type = OP_NONE; /* Disable writeback. */
3074 break;
3075 case 0xfa: /* cli */
3076 if (emulator_bad_iopl(ctxt, ops)) {
3077 emulate_gp(ctxt, 0);
3078 goto done;
3079 } else {
3080 ctxt->eflags &= ~X86_EFLAGS_IF;
3081 c->dst.type = OP_NONE; /* Disable writeback. */
3082 }
3083 break;
3084 case 0xfb: /* sti */
3085 if (emulator_bad_iopl(ctxt, ops)) {
3086 emulate_gp(ctxt, 0);
3087 goto done;
3088 } else {
3089 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3090 ctxt->eflags |= X86_EFLAGS_IF;
3091 c->dst.type = OP_NONE; /* Disable writeback. */
3092 }
3093 break;
3094 case 0xfc: /* cld */
3095 ctxt->eflags &= ~EFLG_DF;
3096 c->dst.type = OP_NONE; /* Disable writeback. */
3097 break;
3098 case 0xfd: /* std */
3099 ctxt->eflags |= EFLG_DF;
3100 c->dst.type = OP_NONE; /* Disable writeback. */
3101 break;
3102 case 0xfe: /* Grp4 */
3103 grp45:
3104 rc = emulate_grp45(ctxt, ops);
3105 if (rc != X86EMUL_CONTINUE)
3106 goto done;
3107 break;
3108 case 0xff: /* Grp5 */
3109 if (c->modrm_reg == 5)
3110 goto jump_far;
3111 goto grp45;
3112 default:
3113 goto cannot_emulate;
3114 }
3115
3116 writeback:
3117 rc = writeback(ctxt, ops);
3118 if (rc != X86EMUL_CONTINUE)
3119 goto done;
3120
3121 /*
3122 * restore dst type in case the decoding will be reused
3123 * (happens for string instruction )
3124 */
3125 c->dst.type = saved_dst_type;
3126
3127 if ((c->d & SrcMask) == SrcSI)
3128 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3129 VCPU_REGS_RSI, &c->src);
3130
3131 if ((c->d & DstMask) == DstDI)
3132 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3133 &c->dst);
3134
3135 if (c->rep_prefix && (c->d & String)) {
3136 struct read_cache *rc = &ctxt->decode.io_read;
3137 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3138 /*
3139 * Re-enter guest when pio read ahead buffer is empty or,
3140 * if it is not used, after each 1024 iteration.
3141 */
3142 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3143 (rc->end != 0 && rc->end == rc->pos))
3144 ctxt->restart = false;
3145 }
3146 /*
3147 * reset read cache here in case string instruction is restared
3148 * without decoding
3149 */
3150 ctxt->decode.mem_read.end = 0;
3151 ctxt->eip = c->eip;
3152
3153 done:
3154 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3155
3156 twobyte_insn:
3157 switch (c->b) {
3158 case 0x01: /* lgdt, lidt, lmsw */
3159 switch (c->modrm_reg) {
3160 u16 size;
3161 unsigned long address;
3162
3163 case 0: /* vmcall */
3164 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3165 goto cannot_emulate;
3166
3167 rc = kvm_fix_hypercall(ctxt->vcpu);
3168 if (rc != X86EMUL_CONTINUE)
3169 goto done;
3170
3171 /* Let the processor re-execute the fixed hypercall */
3172 c->eip = ctxt->eip;
3173 /* Disable writeback. */
3174 c->dst.type = OP_NONE;
3175 break;
3176 case 2: /* lgdt */
3177 rc = read_descriptor(ctxt, ops, c->src.ptr,
3178 &size, &address, c->op_bytes);
3179 if (rc != X86EMUL_CONTINUE)
3180 goto done;
3181 realmode_lgdt(ctxt->vcpu, size, address);
3182 /* Disable writeback. */
3183 c->dst.type = OP_NONE;
3184 break;
3185 case 3: /* lidt/vmmcall */
3186 if (c->modrm_mod == 3) {
3187 switch (c->modrm_rm) {
3188 case 1:
3189 rc = kvm_fix_hypercall(ctxt->vcpu);
3190 if (rc != X86EMUL_CONTINUE)
3191 goto done;
3192 break;
3193 default:
3194 goto cannot_emulate;
3195 }
3196 } else {
3197 rc = read_descriptor(ctxt, ops, c->src.ptr,
3198 &size, &address,
3199 c->op_bytes);
3200 if (rc != X86EMUL_CONTINUE)
3201 goto done;
3202 realmode_lidt(ctxt->vcpu, size, address);
3203 }
3204 /* Disable writeback. */
3205 c->dst.type = OP_NONE;
3206 break;
3207 case 4: /* smsw */
3208 c->dst.bytes = 2;
3209 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3210 break;
3211 case 6: /* lmsw */
3212 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) |
3213 (c->src.val & 0x0f), ctxt->vcpu);
3214 c->dst.type = OP_NONE;
3215 break;
3216 case 5: /* not defined */
3217 emulate_ud(ctxt);
3218 goto done;
3219 case 7: /* invlpg*/
3220 emulate_invlpg(ctxt->vcpu, c->modrm_ea);
3221 /* Disable writeback. */
3222 c->dst.type = OP_NONE;
3223 break;
3224 default:
3225 goto cannot_emulate;
3226 }
3227 break;
3228 case 0x05: /* syscall */
3229 rc = emulate_syscall(ctxt, ops);
3230 if (rc != X86EMUL_CONTINUE)
3231 goto done;
3232 else
3233 goto writeback;
3234 break;
3235 case 0x06:
3236 emulate_clts(ctxt->vcpu);
3237 c->dst.type = OP_NONE;
3238 break;
3239 case 0x09: /* wbinvd */
3240 kvm_emulate_wbinvd(ctxt->vcpu);
3241 c->dst.type = OP_NONE;
3242 break;
3243 case 0x08: /* invd */
3244 case 0x0d: /* GrpP (prefetch) */
3245 case 0x18: /* Grp16 (prefetch/nop) */
3246 c->dst.type = OP_NONE;
3247 break;
3248 case 0x20: /* mov cr, reg */
3249 switch (c->modrm_reg) {
3250 case 1:
3251 case 5 ... 7:
3252 case 9 ... 15:
3253 emulate_ud(ctxt);
3254 goto done;
3255 }
3256 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3257 c->dst.type = OP_NONE; /* no writeback */
3258 break;
3259 case 0x21: /* mov from dr to reg */
3260 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3261 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3262 emulate_ud(ctxt);
3263 goto done;
3264 }
3265 ops->get_dr(c->modrm_reg, &c->regs[c->modrm_rm], ctxt->vcpu);
3266 c->dst.type = OP_NONE; /* no writeback */
3267 break;
3268 case 0x22: /* mov reg, cr */
3269 if (ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu)) {
3270 emulate_gp(ctxt, 0);
3271 goto done;
3272 }
3273 c->dst.type = OP_NONE;
3274 break;
3275 case 0x23: /* mov from reg to dr */
3276 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3277 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3278 emulate_ud(ctxt);
3279 goto done;
3280 }
3281
3282 if (ops->set_dr(c->modrm_reg, c->regs[c->modrm_rm] &
3283 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3284 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3285 /* #UD condition is already handled by the code above */
3286 emulate_gp(ctxt, 0);
3287 goto done;
3288 }
3289
3290 c->dst.type = OP_NONE; /* no writeback */
3291 break;
3292 case 0x30:
3293 /* wrmsr */
3294 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3295 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3296 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3297 emulate_gp(ctxt, 0);
3298 goto done;
3299 }
3300 rc = X86EMUL_CONTINUE;
3301 c->dst.type = OP_NONE;
3302 break;
3303 case 0x32:
3304 /* rdmsr */
3305 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3306 emulate_gp(ctxt, 0);
3307 goto done;
3308 } else {
3309 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3310 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3311 }
3312 rc = X86EMUL_CONTINUE;
3313 c->dst.type = OP_NONE;
3314 break;
3315 case 0x34: /* sysenter */
3316 rc = emulate_sysenter(ctxt, ops);
3317 if (rc != X86EMUL_CONTINUE)
3318 goto done;
3319 else
3320 goto writeback;
3321 break;
3322 case 0x35: /* sysexit */
3323 rc = emulate_sysexit(ctxt, ops);
3324 if (rc != X86EMUL_CONTINUE)
3325 goto done;
3326 else
3327 goto writeback;
3328 break;
3329 case 0x40 ... 0x4f: /* cmov */
3330 c->dst.val = c->dst.orig_val = c->src.val;
3331 if (!test_cc(c->b, ctxt->eflags))
3332 c->dst.type = OP_NONE; /* no writeback */
3333 break;
3334 case 0x80 ... 0x8f: /* jnz rel, etc*/
3335 if (test_cc(c->b, ctxt->eflags))
3336 jmp_rel(c, c->src.val);
3337 c->dst.type = OP_NONE;
3338 break;
3339 case 0xa0: /* push fs */
3340 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3341 break;
3342 case 0xa1: /* pop fs */
3343 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3344 if (rc != X86EMUL_CONTINUE)
3345 goto done;
3346 break;
3347 case 0xa3:
3348 bt: /* bt */
3349 c->dst.type = OP_NONE;
3350 /* only subword offset */
3351 c->src.val &= (c->dst.bytes << 3) - 1;
3352 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3353 break;
3354 case 0xa4: /* shld imm8, r, r/m */
3355 case 0xa5: /* shld cl, r, r/m */
3356 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3357 break;
3358 case 0xa8: /* push gs */
3359 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3360 break;
3361 case 0xa9: /* pop gs */
3362 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3363 if (rc != X86EMUL_CONTINUE)
3364 goto done;
3365 break;
3366 case 0xab:
3367 bts: /* bts */
3368 /* only subword offset */
3369 c->src.val &= (c->dst.bytes << 3) - 1;
3370 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3371 break;
3372 case 0xac: /* shrd imm8, r, r/m */
3373 case 0xad: /* shrd cl, r, r/m */
3374 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3375 break;
3376 case 0xae: /* clflush */
3377 break;
3378 case 0xb0 ... 0xb1: /* cmpxchg */
3379 /*
3380 * Save real source value, then compare EAX against
3381 * destination.
3382 */
3383 c->src.orig_val = c->src.val;
3384 c->src.val = c->regs[VCPU_REGS_RAX];
3385 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3386 if (ctxt->eflags & EFLG_ZF) {
3387 /* Success: write back to memory. */
3388 c->dst.val = c->src.orig_val;
3389 } else {
3390 /* Failure: write the value we saw to EAX. */
3391 c->dst.type = OP_REG;
3392 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3393 }
3394 break;
3395 case 0xb3:
3396 btr: /* btr */
3397 /* only subword offset */
3398 c->src.val &= (c->dst.bytes << 3) - 1;
3399 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3400 break;
3401 case 0xb6 ... 0xb7: /* movzx */
3402 c->dst.bytes = c->op_bytes;
3403 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3404 : (u16) c->src.val;
3405 break;
3406 case 0xba: /* Grp8 */
3407 switch (c->modrm_reg & 3) {
3408 case 0:
3409 goto bt;
3410 case 1:
3411 goto bts;
3412 case 2:
3413 goto btr;
3414 case 3:
3415 goto btc;
3416 }
3417 break;
3418 case 0xbb:
3419 btc: /* btc */
3420 /* only subword offset */
3421 c->src.val &= (c->dst.bytes << 3) - 1;
3422 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3423 break;
3424 case 0xbe ... 0xbf: /* movsx */
3425 c->dst.bytes = c->op_bytes;
3426 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3427 (s16) c->src.val;
3428 break;
3429 case 0xc3: /* movnti */
3430 c->dst.bytes = c->op_bytes;
3431 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3432 (u64) c->src.val;
3433 break;
3434 case 0xc7: /* Grp9 (cmpxchg8b) */
3435 rc = emulate_grp9(ctxt, ops);
3436 if (rc != X86EMUL_CONTINUE)
3437 goto done;
3438 break;
3439 default:
3440 goto cannot_emulate;
3441 }
3442 goto writeback;
3443
3444 cannot_emulate:
3445 DPRINTF("Cannot emulate %02x\n", c->b);
3446 return -1;
3447 }
Linux kernel - Deliverables
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