1 /******************************************************************************
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 * Copyright (c) 2005 Keir Fraser
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 /* Operand sizes: 8-bit operands or specified/overridden size. */
41 #define ByteOp (1<<0) /* 8-bit operands. */
42 /* Destination operand type. */
43 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44 #define DstReg (2<<1) /* Register operand. */
45 #define DstMem (3<<1) /* Memory operand. */
46 #define DstAcc (4<<1) /* Destination Accumulator */
47 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
48 #define DstMem64 (6<<1) /* 64bit memory operand */
49 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50 #define DstMask (7<<1)
51 /* Source operand type. */
52 #define SrcNone (0<<4) /* No source operand. */
53 #define SrcReg (1<<4) /* Register operand. */
54 #define SrcMem (2<<4) /* Memory operand. */
55 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57 #define SrcImm (5<<4) /* Immediate operand. */
58 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59 #define SrcOne (7<<4) /* Implied '1' */
60 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
62 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65 #define SrcAcc (0xd<<4) /* Source Accumulator */
66 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
70 /* Destination is only written; never read. */
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79 #define Sse (1<<17) /* SSE Vector instruction */
81 #define VendorSpecific (1<<22) /* Vendor specific instruction */
82 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
83 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
84 #define Undefined (1<<25) /* No Such Instruction */
85 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
86 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
88 /* Source 2 operand type */
89 #define Src2None (0<<29)
90 #define Src2CL (1<<29)
91 #define Src2ImmByte (2<<29)
92 #define Src2One (3<<29)
93 #define Src2Imm (4<<29)
94 #define Src2Mask (7<<29)
97 #define X3(x...) X2(x), x
98 #define X4(x...) X2(x), X2(x)
99 #define X5(x...) X4(x), x
100 #define X6(x...) X4(x), X2(x)
101 #define X7(x...) X4(x), X3(x)
102 #define X8(x...) X4(x), X4(x)
103 #define X16(x...) X8(x), X8(x)
109 int (*execute
)(struct x86_emulate_ctxt
*ctxt
);
110 struct opcode
*group
;
111 struct group_dual
*gdual
;
112 struct gprefix
*gprefix
;
114 int (*check_perm
)(struct x86_emulate_ctxt
*ctxt
);
118 struct opcode mod012
[8];
119 struct opcode mod3
[8];
123 struct opcode pfx_no
;
124 struct opcode pfx_66
;
125 struct opcode pfx_f2
;
126 struct opcode pfx_f3
;
129 /* EFLAGS bit definitions. */
130 #define EFLG_ID (1<<21)
131 #define EFLG_VIP (1<<20)
132 #define EFLG_VIF (1<<19)
133 #define EFLG_AC (1<<18)
134 #define EFLG_VM (1<<17)
135 #define EFLG_RF (1<<16)
136 #define EFLG_IOPL (3<<12)
137 #define EFLG_NT (1<<14)
138 #define EFLG_OF (1<<11)
139 #define EFLG_DF (1<<10)
140 #define EFLG_IF (1<<9)
141 #define EFLG_TF (1<<8)
142 #define EFLG_SF (1<<7)
143 #define EFLG_ZF (1<<6)
144 #define EFLG_AF (1<<4)
145 #define EFLG_PF (1<<2)
146 #define EFLG_CF (1<<0)
148 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
149 #define EFLG_RESERVED_ONE_MASK 2
152 * Instruction emulation:
153 * Most instructions are emulated directly via a fragment of inline assembly
154 * code. This allows us to save/restore EFLAGS and thus very easily pick up
155 * any modified flags.
158 #if defined(CONFIG_X86_64)
159 #define _LO32 "k" /* force 32-bit operand */
160 #define _STK "%%rsp" /* stack pointer */
161 #elif defined(__i386__)
162 #define _LO32 "" /* force 32-bit operand */
163 #define _STK "%%esp" /* stack pointer */
167 * These EFLAGS bits are restored from saved value during emulation, and
168 * any changes are written back to the saved value after emulation.
170 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
172 /* Before executing instruction: restore necessary bits in EFLAGS. */
173 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
174 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
175 "movl %"_sav",%"_LO32 _tmp"; " \
178 "movl %"_msk",%"_LO32 _tmp"; " \
179 "andl %"_LO32 _tmp",("_STK"); " \
181 "notl %"_LO32 _tmp"; " \
182 "andl %"_LO32 _tmp",("_STK"); " \
183 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
185 "orl %"_LO32 _tmp",("_STK"); " \
189 /* After executing instruction: write-back necessary bits in EFLAGS. */
190 #define _POST_EFLAGS(_sav, _msk, _tmp) \
191 /* _sav |= EFLAGS & _msk; */ \
194 "andl %"_msk",%"_LO32 _tmp"; " \
195 "orl %"_LO32 _tmp",%"_sav"; "
203 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
205 __asm__ __volatile__ ( \
206 _PRE_EFLAGS("0", "4", "2") \
207 _op _suffix " %"_x"3,%1; " \
208 _POST_EFLAGS("0", "4", "2") \
209 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
211 : _y ((_src).val), "i" (EFLAGS_MASK)); \
215 /* Raw emulation: instruction has two explicit operands. */
216 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
218 unsigned long _tmp; \
220 switch ((_dst).bytes) { \
222 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
233 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
235 unsigned long _tmp; \
236 switch ((_dst).bytes) { \
238 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
242 _wx, _wy, _lx, _ly, _qx, _qy); \
247 /* Source operand is byte-sized and may be restricted to just %cl. */
248 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
249 __emulate_2op(_op, _src, _dst, _eflags, \
250 "b", "c", "b", "c", "b", "c", "b", "c")
252 /* Source operand is byte, word, long or quad sized. */
253 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
254 __emulate_2op(_op, _src, _dst, _eflags, \
255 "b", "q", "w", "r", _LO32, "r", "", "r")
257 /* Source operand is word, long or quad sized. */
258 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
259 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
260 "w", "r", _LO32, "r", "", "r")
262 /* Instruction has three operands and one operand is stored in ECX register */
263 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
265 unsigned long _tmp; \
266 _type _clv = (_cl).val; \
267 _type _srcv = (_src).val; \
268 _type _dstv = (_dst).val; \
270 __asm__ __volatile__ ( \
271 _PRE_EFLAGS("0", "5", "2") \
272 _op _suffix " %4,%1 \n" \
273 _POST_EFLAGS("0", "5", "2") \
274 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
275 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 (_cl).val = (unsigned long) _clv; \
279 (_src).val = (unsigned long) _srcv; \
280 (_dst).val = (unsigned long) _dstv; \
283 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
285 switch ((_dst).bytes) { \
287 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
288 "w", unsigned short); \
291 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
292 "l", unsigned int); \
295 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
296 "q", unsigned long)); \
301 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
303 unsigned long _tmp; \
305 __asm__ __volatile__ ( \
306 _PRE_EFLAGS("0", "3", "2") \
307 _op _suffix " %1; " \
308 _POST_EFLAGS("0", "3", "2") \
309 : "=m" (_eflags), "+m" ((_dst).val), \
311 : "i" (EFLAGS_MASK)); \
314 /* Instruction has only one explicit operand (no source operand). */
315 #define emulate_1op(_op, _dst, _eflags) \
317 switch ((_dst).bytes) { \
318 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
319 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
320 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
321 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
325 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
327 unsigned long _tmp; \
329 __asm__ __volatile__ ( \
330 _PRE_EFLAGS("0", "4", "1") \
331 _op _suffix " %5; " \
332 _POST_EFLAGS("0", "4", "1") \
333 : "=m" (_eflags), "=&r" (_tmp), \
334 "+a" (_rax), "+d" (_rdx) \
335 : "i" (EFLAGS_MASK), "m" ((_src).val), \
336 "a" (_rax), "d" (_rdx)); \
339 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
341 unsigned long _tmp; \
343 __asm__ __volatile__ ( \
344 _PRE_EFLAGS("0", "5", "1") \
346 _op _suffix " %6; " \
348 _POST_EFLAGS("0", "5", "1") \
349 ".pushsection .fixup,\"ax\" \n\t" \
350 "3: movb $1, %4 \n\t" \
353 _ASM_EXTABLE(1b, 3b) \
354 : "=m" (_eflags), "=&r" (_tmp), \
355 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
356 : "i" (EFLAGS_MASK), "m" ((_src).val), \
357 "a" (_rax), "d" (_rdx)); \
360 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
361 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
363 switch((_src).bytes) { \
364 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
365 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
366 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
367 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
371 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
373 switch((_src).bytes) { \
375 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
376 _eflags, "b", _ex); \
379 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
380 _eflags, "w", _ex); \
383 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
384 _eflags, "l", _ex); \
387 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
388 _eflags, "q", _ex)); \
393 /* Fetch next part of the instruction being emulated. */
394 #define insn_fetch(_type, _size, _eip) \
395 ({ unsigned long _x; \
396 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
397 if (rc != X86EMUL_CONTINUE) \
403 #define insn_fetch_arr(_arr, _size, _eip) \
404 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
405 if (rc != X86EMUL_CONTINUE) \
410 static inline unsigned long ad_mask(struct decode_cache
*c
)
412 return (1UL << (c
->ad_bytes
<< 3)) - 1;
415 /* Access/update address held in a register, based on addressing mode. */
416 static inline unsigned long
417 address_mask(struct decode_cache
*c
, unsigned long reg
)
419 if (c
->ad_bytes
== sizeof(unsigned long))
422 return reg
& ad_mask(c
);
425 static inline unsigned long
426 register_address(struct decode_cache
*c
, unsigned long reg
)
428 return address_mask(c
, reg
);
432 register_address_increment(struct decode_cache
*c
, unsigned long *reg
, int inc
)
434 if (c
->ad_bytes
== sizeof(unsigned long))
437 *reg
= (*reg
& ~ad_mask(c
)) | ((*reg
+ inc
) & ad_mask(c
));
440 static inline void jmp_rel(struct decode_cache
*c
, int rel
)
442 register_address_increment(c
, &c
->eip
, rel
);
445 static void set_seg_override(struct decode_cache
*c
, int seg
)
447 c
->has_seg_override
= true;
448 c
->seg_override
= seg
;
451 static unsigned long seg_base(struct x86_emulate_ctxt
*ctxt
,
452 struct x86_emulate_ops
*ops
, int seg
)
454 if (ctxt
->mode
== X86EMUL_MODE_PROT64
&& seg
< VCPU_SREG_FS
)
457 return ops
->get_cached_segment_base(seg
, ctxt
->vcpu
);
460 static unsigned seg_override(struct x86_emulate_ctxt
*ctxt
,
461 struct x86_emulate_ops
*ops
,
462 struct decode_cache
*c
)
464 if (!c
->has_seg_override
)
467 return c
->seg_override
;
470 static ulong
linear(struct x86_emulate_ctxt
*ctxt
,
471 struct segmented_address addr
)
473 struct decode_cache
*c
= &ctxt
->decode
;
476 la
= seg_base(ctxt
, ctxt
->ops
, addr
.seg
) + addr
.ea
;
477 if (c
->ad_bytes
!= 8)
482 static int emulate_exception(struct x86_emulate_ctxt
*ctxt
, int vec
,
483 u32 error
, bool valid
)
485 ctxt
->exception
.vector
= vec
;
486 ctxt
->exception
.error_code
= error
;
487 ctxt
->exception
.error_code_valid
= valid
;
488 return X86EMUL_PROPAGATE_FAULT
;
491 static int emulate_gp(struct x86_emulate_ctxt
*ctxt
, int err
)
493 return emulate_exception(ctxt
, GP_VECTOR
, err
, true);
496 static int emulate_ud(struct x86_emulate_ctxt
*ctxt
)
498 return emulate_exception(ctxt
, UD_VECTOR
, 0, false);
501 static int emulate_ts(struct x86_emulate_ctxt
*ctxt
, int err
)
503 return emulate_exception(ctxt
, TS_VECTOR
, err
, true);
506 static int emulate_de(struct x86_emulate_ctxt
*ctxt
)
508 return emulate_exception(ctxt
, DE_VECTOR
, 0, false);
511 static int emulate_nm(struct x86_emulate_ctxt
*ctxt
)
513 return emulate_exception(ctxt
, NM_VECTOR
, 0, false);
516 static int do_fetch_insn_byte(struct x86_emulate_ctxt
*ctxt
,
517 struct x86_emulate_ops
*ops
,
518 unsigned long eip
, u8
*dest
)
520 struct fetch_cache
*fc
= &ctxt
->decode
.fetch
;
524 if (eip
== fc
->end
) {
525 cur_size
= fc
->end
- fc
->start
;
526 size
= min(15UL - cur_size
, PAGE_SIZE
- offset_in_page(eip
));
527 rc
= ops
->fetch(ctxt
->cs_base
+ eip
, fc
->data
+ cur_size
,
528 size
, ctxt
->vcpu
, &ctxt
->exception
);
529 if (rc
!= X86EMUL_CONTINUE
)
533 *dest
= fc
->data
[eip
- fc
->start
];
534 return X86EMUL_CONTINUE
;
537 static int do_insn_fetch(struct x86_emulate_ctxt
*ctxt
,
538 struct x86_emulate_ops
*ops
,
539 unsigned long eip
, void *dest
, unsigned size
)
543 /* x86 instructions are limited to 15 bytes. */
544 if (eip
+ size
- ctxt
->eip
> 15)
545 return X86EMUL_UNHANDLEABLE
;
547 rc
= do_fetch_insn_byte(ctxt
, ops
, eip
++, dest
++);
548 if (rc
!= X86EMUL_CONTINUE
)
551 return X86EMUL_CONTINUE
;
555 * Given the 'reg' portion of a ModRM byte, and a register block, return a
556 * pointer into the block that addresses the relevant register.
557 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
559 static void *decode_register(u8 modrm_reg
, unsigned long *regs
,
564 p
= ®s
[modrm_reg
];
565 if (highbyte_regs
&& modrm_reg
>= 4 && modrm_reg
< 8)
566 p
= (unsigned char *)®s
[modrm_reg
& 3] + 1;
570 static int read_descriptor(struct x86_emulate_ctxt
*ctxt
,
571 struct x86_emulate_ops
*ops
,
572 struct segmented_address addr
,
573 u16
*size
, unsigned long *address
, int op_bytes
)
580 rc
= ops
->read_std(linear(ctxt
, addr
), (unsigned long *)size
, 2,
581 ctxt
->vcpu
, &ctxt
->exception
);
582 if (rc
!= X86EMUL_CONTINUE
)
585 rc
= ops
->read_std(linear(ctxt
, addr
), address
, op_bytes
,
586 ctxt
->vcpu
, &ctxt
->exception
);
590 static int test_cc(unsigned int condition
, unsigned int flags
)
594 switch ((condition
& 15) >> 1) {
596 rc
|= (flags
& EFLG_OF
);
598 case 1: /* b/c/nae */
599 rc
|= (flags
& EFLG_CF
);
602 rc
|= (flags
& EFLG_ZF
);
605 rc
|= (flags
& (EFLG_CF
|EFLG_ZF
));
608 rc
|= (flags
& EFLG_SF
);
611 rc
|= (flags
& EFLG_PF
);
614 rc
|= (flags
& EFLG_ZF
);
617 rc
|= (!(flags
& EFLG_SF
) != !(flags
& EFLG_OF
));
621 /* Odd condition identifiers (lsb == 1) have inverted sense. */
622 return (!!rc
^ (condition
& 1));
625 static void fetch_register_operand(struct operand
*op
)
629 op
->val
= *(u8
*)op
->addr
.reg
;
632 op
->val
= *(u16
*)op
->addr
.reg
;
635 op
->val
= *(u32
*)op
->addr
.reg
;
638 op
->val
= *(u64
*)op
->addr
.reg
;
643 static void read_sse_reg(struct x86_emulate_ctxt
*ctxt
, sse128_t
*data
, int reg
)
645 ctxt
->ops
->get_fpu(ctxt
);
647 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data
)); break;
648 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data
)); break;
649 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data
)); break;
650 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data
)); break;
651 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data
)); break;
652 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data
)); break;
653 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data
)); break;
654 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data
)); break;
656 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data
)); break;
657 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data
)); break;
658 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data
)); break;
659 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data
)); break;
660 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data
)); break;
661 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data
)); break;
662 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data
)); break;
663 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data
)); break;
667 ctxt
->ops
->put_fpu(ctxt
);
670 static void write_sse_reg(struct x86_emulate_ctxt
*ctxt
, sse128_t
*data
,
673 ctxt
->ops
->get_fpu(ctxt
);
675 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data
)); break;
676 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data
)); break;
677 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data
)); break;
678 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data
)); break;
679 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data
)); break;
680 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data
)); break;
681 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data
)); break;
682 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data
)); break;
684 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data
)); break;
685 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data
)); break;
686 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data
)); break;
687 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data
)); break;
688 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data
)); break;
689 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data
)); break;
690 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data
)); break;
691 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data
)); break;
695 ctxt
->ops
->put_fpu(ctxt
);
698 static void decode_register_operand(struct x86_emulate_ctxt
*ctxt
,
700 struct decode_cache
*c
,
703 unsigned reg
= c
->modrm_reg
;
704 int highbyte_regs
= c
->rex_prefix
== 0;
707 reg
= (c
->b
& 7) | ((c
->rex_prefix
& 1) << 3);
713 read_sse_reg(ctxt
, &op
->vec_val
, reg
);
718 if ((c
->d
& ByteOp
) && !inhibit_bytereg
) {
719 op
->addr
.reg
= decode_register(reg
, c
->regs
, highbyte_regs
);
722 op
->addr
.reg
= decode_register(reg
, c
->regs
, 0);
723 op
->bytes
= c
->op_bytes
;
725 fetch_register_operand(op
);
726 op
->orig_val
= op
->val
;
729 static int decode_modrm(struct x86_emulate_ctxt
*ctxt
,
730 struct x86_emulate_ops
*ops
,
733 struct decode_cache
*c
= &ctxt
->decode
;
735 int index_reg
= 0, base_reg
= 0, scale
;
736 int rc
= X86EMUL_CONTINUE
;
740 c
->modrm_reg
= (c
->rex_prefix
& 4) << 1; /* REX.R */
741 index_reg
= (c
->rex_prefix
& 2) << 2; /* REX.X */
742 c
->modrm_rm
= base_reg
= (c
->rex_prefix
& 1) << 3; /* REG.B */
745 c
->modrm
= insn_fetch(u8
, 1, c
->eip
);
746 c
->modrm_mod
|= (c
->modrm
& 0xc0) >> 6;
747 c
->modrm_reg
|= (c
->modrm
& 0x38) >> 3;
748 c
->modrm_rm
|= (c
->modrm
& 0x07);
749 c
->modrm_seg
= VCPU_SREG_DS
;
751 if (c
->modrm_mod
== 3) {
753 op
->bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
754 op
->addr
.reg
= decode_register(c
->modrm_rm
,
755 c
->regs
, c
->d
& ByteOp
);
759 op
->addr
.xmm
= c
->modrm_rm
;
760 read_sse_reg(ctxt
, &op
->vec_val
, c
->modrm_rm
);
763 fetch_register_operand(op
);
769 if (c
->ad_bytes
== 2) {
770 unsigned bx
= c
->regs
[VCPU_REGS_RBX
];
771 unsigned bp
= c
->regs
[VCPU_REGS_RBP
];
772 unsigned si
= c
->regs
[VCPU_REGS_RSI
];
773 unsigned di
= c
->regs
[VCPU_REGS_RDI
];
775 /* 16-bit ModR/M decode. */
776 switch (c
->modrm_mod
) {
778 if (c
->modrm_rm
== 6)
779 modrm_ea
+= insn_fetch(u16
, 2, c
->eip
);
782 modrm_ea
+= insn_fetch(s8
, 1, c
->eip
);
785 modrm_ea
+= insn_fetch(u16
, 2, c
->eip
);
788 switch (c
->modrm_rm
) {
808 if (c
->modrm_mod
!= 0)
815 if (c
->modrm_rm
== 2 || c
->modrm_rm
== 3 ||
816 (c
->modrm_rm
== 6 && c
->modrm_mod
!= 0))
817 c
->modrm_seg
= VCPU_SREG_SS
;
818 modrm_ea
= (u16
)modrm_ea
;
820 /* 32/64-bit ModR/M decode. */
821 if ((c
->modrm_rm
& 7) == 4) {
822 sib
= insn_fetch(u8
, 1, c
->eip
);
823 index_reg
|= (sib
>> 3) & 7;
827 if ((base_reg
& 7) == 5 && c
->modrm_mod
== 0)
828 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
830 modrm_ea
+= c
->regs
[base_reg
];
832 modrm_ea
+= c
->regs
[index_reg
] << scale
;
833 } else if ((c
->modrm_rm
& 7) == 5 && c
->modrm_mod
== 0) {
834 if (ctxt
->mode
== X86EMUL_MODE_PROT64
)
837 modrm_ea
+= c
->regs
[c
->modrm_rm
];
838 switch (c
->modrm_mod
) {
840 if (c
->modrm_rm
== 5)
841 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
844 modrm_ea
+= insn_fetch(s8
, 1, c
->eip
);
847 modrm_ea
+= insn_fetch(s32
, 4, c
->eip
);
851 op
->addr
.mem
.ea
= modrm_ea
;
856 static int decode_abs(struct x86_emulate_ctxt
*ctxt
,
857 struct x86_emulate_ops
*ops
,
860 struct decode_cache
*c
= &ctxt
->decode
;
861 int rc
= X86EMUL_CONTINUE
;
864 switch (c
->ad_bytes
) {
866 op
->addr
.mem
.ea
= insn_fetch(u16
, 2, c
->eip
);
869 op
->addr
.mem
.ea
= insn_fetch(u32
, 4, c
->eip
);
872 op
->addr
.mem
.ea
= insn_fetch(u64
, 8, c
->eip
);
879 static void fetch_bit_operand(struct decode_cache
*c
)
883 if (c
->dst
.type
== OP_MEM
&& c
->src
.type
== OP_REG
) {
884 mask
= ~(c
->dst
.bytes
* 8 - 1);
886 if (c
->src
.bytes
== 2)
887 sv
= (s16
)c
->src
.val
& (s16
)mask
;
888 else if (c
->src
.bytes
== 4)
889 sv
= (s32
)c
->src
.val
& (s32
)mask
;
891 c
->dst
.addr
.mem
.ea
+= (sv
>> 3);
894 /* only subword offset */
895 c
->src
.val
&= (c
->dst
.bytes
<< 3) - 1;
898 static int read_emulated(struct x86_emulate_ctxt
*ctxt
,
899 struct x86_emulate_ops
*ops
,
900 unsigned long addr
, void *dest
, unsigned size
)
903 struct read_cache
*mc
= &ctxt
->decode
.mem_read
;
906 int n
= min(size
, 8u);
908 if (mc
->pos
< mc
->end
)
911 rc
= ops
->read_emulated(addr
, mc
->data
+ mc
->end
, n
,
912 &ctxt
->exception
, ctxt
->vcpu
);
913 if (rc
!= X86EMUL_CONTINUE
)
918 memcpy(dest
, mc
->data
+ mc
->pos
, n
);
923 return X86EMUL_CONTINUE
;
926 static int pio_in_emulated(struct x86_emulate_ctxt
*ctxt
,
927 struct x86_emulate_ops
*ops
,
928 unsigned int size
, unsigned short port
,
931 struct read_cache
*rc
= &ctxt
->decode
.io_read
;
933 if (rc
->pos
== rc
->end
) { /* refill pio read ahead */
934 struct decode_cache
*c
= &ctxt
->decode
;
935 unsigned int in_page
, n
;
936 unsigned int count
= c
->rep_prefix
?
937 address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) : 1;
938 in_page
= (ctxt
->eflags
& EFLG_DF
) ?
939 offset_in_page(c
->regs
[VCPU_REGS_RDI
]) :
940 PAGE_SIZE
- offset_in_page(c
->regs
[VCPU_REGS_RDI
]);
941 n
= min(min(in_page
, (unsigned int)sizeof(rc
->data
)) / size
,
945 rc
->pos
= rc
->end
= 0;
946 if (!ops
->pio_in_emulated(size
, port
, rc
->data
, n
, ctxt
->vcpu
))
951 memcpy(dest
, rc
->data
+ rc
->pos
, size
);
956 static u32
desc_limit_scaled(struct desc_struct
*desc
)
958 u32 limit
= get_desc_limit(desc
);
960 return desc
->g
? (limit
<< 12) | 0xfff : limit
;
963 static void get_descriptor_table_ptr(struct x86_emulate_ctxt
*ctxt
,
964 struct x86_emulate_ops
*ops
,
965 u16 selector
, struct desc_ptr
*dt
)
967 if (selector
& 1 << 2) {
968 struct desc_struct desc
;
969 memset (dt
, 0, sizeof *dt
);
970 if (!ops
->get_cached_descriptor(&desc
, NULL
, VCPU_SREG_LDTR
,
974 dt
->size
= desc_limit_scaled(&desc
); /* what if limit > 65535? */
975 dt
->address
= get_desc_base(&desc
);
977 ops
->get_gdt(dt
, ctxt
->vcpu
);
980 /* allowed just for 8 bytes segments */
981 static int read_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
982 struct x86_emulate_ops
*ops
,
983 u16 selector
, struct desc_struct
*desc
)
986 u16 index
= selector
>> 3;
990 get_descriptor_table_ptr(ctxt
, ops
, selector
, &dt
);
992 if (dt
.size
< index
* 8 + 7)
993 return emulate_gp(ctxt
, selector
& 0xfffc);
994 addr
= dt
.address
+ index
* 8;
995 ret
= ops
->read_std(addr
, desc
, sizeof *desc
, ctxt
->vcpu
,
1001 /* allowed just for 8 bytes segments */
1002 static int write_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
1003 struct x86_emulate_ops
*ops
,
1004 u16 selector
, struct desc_struct
*desc
)
1007 u16 index
= selector
>> 3;
1011 get_descriptor_table_ptr(ctxt
, ops
, selector
, &dt
);
1013 if (dt
.size
< index
* 8 + 7)
1014 return emulate_gp(ctxt
, selector
& 0xfffc);
1016 addr
= dt
.address
+ index
* 8;
1017 ret
= ops
->write_std(addr
, desc
, sizeof *desc
, ctxt
->vcpu
,
1023 /* Does not support long mode */
1024 static int load_segment_descriptor(struct x86_emulate_ctxt
*ctxt
,
1025 struct x86_emulate_ops
*ops
,
1026 u16 selector
, int seg
)
1028 struct desc_struct seg_desc
;
1030 unsigned err_vec
= GP_VECTOR
;
1032 bool null_selector
= !(selector
& ~0x3); /* 0000-0003 are null */
1035 memset(&seg_desc
, 0, sizeof seg_desc
);
1037 if ((seg
<= VCPU_SREG_GS
&& ctxt
->mode
== X86EMUL_MODE_VM86
)
1038 || ctxt
->mode
== X86EMUL_MODE_REAL
) {
1039 /* set real mode segment descriptor */
1040 set_desc_base(&seg_desc
, selector
<< 4);
1041 set_desc_limit(&seg_desc
, 0xffff);
1048 /* NULL selector is not valid for TR, CS and SS */
1049 if ((seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
|| seg
== VCPU_SREG_TR
)
1053 /* TR should be in GDT only */
1054 if (seg
== VCPU_SREG_TR
&& (selector
& (1 << 2)))
1057 if (null_selector
) /* for NULL selector skip all following checks */
1060 ret
= read_segment_descriptor(ctxt
, ops
, selector
, &seg_desc
);
1061 if (ret
!= X86EMUL_CONTINUE
)
1064 err_code
= selector
& 0xfffc;
1065 err_vec
= GP_VECTOR
;
1067 /* can't load system descriptor into segment selecor */
1068 if (seg
<= VCPU_SREG_GS
&& !seg_desc
.s
)
1072 err_vec
= (seg
== VCPU_SREG_SS
) ? SS_VECTOR
: NP_VECTOR
;
1078 cpl
= ops
->cpl(ctxt
->vcpu
);
1083 * segment is not a writable data segment or segment
1084 * selector's RPL != CPL or segment selector's RPL != CPL
1086 if (rpl
!= cpl
|| (seg_desc
.type
& 0xa) != 0x2 || dpl
!= cpl
)
1090 if (!(seg_desc
.type
& 8))
1093 if (seg_desc
.type
& 4) {
1099 if (rpl
> cpl
|| dpl
!= cpl
)
1102 /* CS(RPL) <- CPL */
1103 selector
= (selector
& 0xfffc) | cpl
;
1106 if (seg_desc
.s
|| (seg_desc
.type
!= 1 && seg_desc
.type
!= 9))
1109 case VCPU_SREG_LDTR
:
1110 if (seg_desc
.s
|| seg_desc
.type
!= 2)
1113 default: /* DS, ES, FS, or GS */
1115 * segment is not a data or readable code segment or
1116 * ((segment is a data or nonconforming code segment)
1117 * and (both RPL and CPL > DPL))
1119 if ((seg_desc
.type
& 0xa) == 0x8 ||
1120 (((seg_desc
.type
& 0xc) != 0xc) &&
1121 (rpl
> dpl
&& cpl
> dpl
)))
1127 /* mark segment as accessed */
1129 ret
= write_segment_descriptor(ctxt
, ops
, selector
, &seg_desc
);
1130 if (ret
!= X86EMUL_CONTINUE
)
1134 ops
->set_segment_selector(selector
, seg
, ctxt
->vcpu
);
1135 ops
->set_cached_descriptor(&seg_desc
, 0, seg
, ctxt
->vcpu
);
1136 return X86EMUL_CONTINUE
;
1138 emulate_exception(ctxt
, err_vec
, err_code
, true);
1139 return X86EMUL_PROPAGATE_FAULT
;
1142 static void write_register_operand(struct operand
*op
)
1144 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1145 switch (op
->bytes
) {
1147 *(u8
*)op
->addr
.reg
= (u8
)op
->val
;
1150 *(u16
*)op
->addr
.reg
= (u16
)op
->val
;
1153 *op
->addr
.reg
= (u32
)op
->val
;
1154 break; /* 64b: zero-extend */
1156 *op
->addr
.reg
= op
->val
;
1161 static inline int writeback(struct x86_emulate_ctxt
*ctxt
,
1162 struct x86_emulate_ops
*ops
)
1165 struct decode_cache
*c
= &ctxt
->decode
;
1167 switch (c
->dst
.type
) {
1169 write_register_operand(&c
->dst
);
1173 rc
= ops
->cmpxchg_emulated(
1174 linear(ctxt
, c
->dst
.addr
.mem
),
1181 rc
= ops
->write_emulated(
1182 linear(ctxt
, c
->dst
.addr
.mem
),
1187 if (rc
!= X86EMUL_CONTINUE
)
1191 write_sse_reg(ctxt
, &c
->dst
.vec_val
, c
->dst
.addr
.xmm
);
1199 return X86EMUL_CONTINUE
;
1202 static inline void emulate_push(struct x86_emulate_ctxt
*ctxt
,
1203 struct x86_emulate_ops
*ops
)
1205 struct decode_cache
*c
= &ctxt
->decode
;
1207 c
->dst
.type
= OP_MEM
;
1208 c
->dst
.bytes
= c
->op_bytes
;
1209 c
->dst
.val
= c
->src
.val
;
1210 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], -c
->op_bytes
);
1211 c
->dst
.addr
.mem
.ea
= register_address(c
, c
->regs
[VCPU_REGS_RSP
]);
1212 c
->dst
.addr
.mem
.seg
= VCPU_SREG_SS
;
1215 static int emulate_pop(struct x86_emulate_ctxt
*ctxt
,
1216 struct x86_emulate_ops
*ops
,
1217 void *dest
, int len
)
1219 struct decode_cache
*c
= &ctxt
->decode
;
1221 struct segmented_address addr
;
1223 addr
.ea
= register_address(c
, c
->regs
[VCPU_REGS_RSP
]);
1224 addr
.seg
= VCPU_SREG_SS
;
1225 rc
= read_emulated(ctxt
, ops
, linear(ctxt
, addr
), dest
, len
);
1226 if (rc
!= X86EMUL_CONTINUE
)
1229 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], len
);
1233 static int emulate_popf(struct x86_emulate_ctxt
*ctxt
,
1234 struct x86_emulate_ops
*ops
,
1235 void *dest
, int len
)
1238 unsigned long val
, change_mask
;
1239 int iopl
= (ctxt
->eflags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1240 int cpl
= ops
->cpl(ctxt
->vcpu
);
1242 rc
= emulate_pop(ctxt
, ops
, &val
, len
);
1243 if (rc
!= X86EMUL_CONTINUE
)
1246 change_mask
= EFLG_CF
| EFLG_PF
| EFLG_AF
| EFLG_ZF
| EFLG_SF
| EFLG_OF
1247 | EFLG_TF
| EFLG_DF
| EFLG_NT
| EFLG_RF
| EFLG_AC
| EFLG_ID
;
1249 switch(ctxt
->mode
) {
1250 case X86EMUL_MODE_PROT64
:
1251 case X86EMUL_MODE_PROT32
:
1252 case X86EMUL_MODE_PROT16
:
1254 change_mask
|= EFLG_IOPL
;
1256 change_mask
|= EFLG_IF
;
1258 case X86EMUL_MODE_VM86
:
1260 return emulate_gp(ctxt
, 0);
1261 change_mask
|= EFLG_IF
;
1263 default: /* real mode */
1264 change_mask
|= (EFLG_IOPL
| EFLG_IF
);
1268 *(unsigned long *)dest
=
1269 (ctxt
->eflags
& ~change_mask
) | (val
& change_mask
);
1274 static void emulate_push_sreg(struct x86_emulate_ctxt
*ctxt
,
1275 struct x86_emulate_ops
*ops
, int seg
)
1277 struct decode_cache
*c
= &ctxt
->decode
;
1279 c
->src
.val
= ops
->get_segment_selector(seg
, ctxt
->vcpu
);
1281 emulate_push(ctxt
, ops
);
1284 static int emulate_pop_sreg(struct x86_emulate_ctxt
*ctxt
,
1285 struct x86_emulate_ops
*ops
, int seg
)
1287 struct decode_cache
*c
= &ctxt
->decode
;
1288 unsigned long selector
;
1291 rc
= emulate_pop(ctxt
, ops
, &selector
, c
->op_bytes
);
1292 if (rc
!= X86EMUL_CONTINUE
)
1295 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)selector
, seg
);
1299 static int emulate_pusha(struct x86_emulate_ctxt
*ctxt
,
1300 struct x86_emulate_ops
*ops
)
1302 struct decode_cache
*c
= &ctxt
->decode
;
1303 unsigned long old_esp
= c
->regs
[VCPU_REGS_RSP
];
1304 int rc
= X86EMUL_CONTINUE
;
1305 int reg
= VCPU_REGS_RAX
;
1307 while (reg
<= VCPU_REGS_RDI
) {
1308 (reg
== VCPU_REGS_RSP
) ?
1309 (c
->src
.val
= old_esp
) : (c
->src
.val
= c
->regs
[reg
]);
1311 emulate_push(ctxt
, ops
);
1313 rc
= writeback(ctxt
, ops
);
1314 if (rc
!= X86EMUL_CONTINUE
)
1320 /* Disable writeback. */
1321 c
->dst
.type
= OP_NONE
;
1326 static int emulate_popa(struct x86_emulate_ctxt
*ctxt
,
1327 struct x86_emulate_ops
*ops
)
1329 struct decode_cache
*c
= &ctxt
->decode
;
1330 int rc
= X86EMUL_CONTINUE
;
1331 int reg
= VCPU_REGS_RDI
;
1333 while (reg
>= VCPU_REGS_RAX
) {
1334 if (reg
== VCPU_REGS_RSP
) {
1335 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
],
1340 rc
= emulate_pop(ctxt
, ops
, &c
->regs
[reg
], c
->op_bytes
);
1341 if (rc
!= X86EMUL_CONTINUE
)
1348 int emulate_int_real(struct x86_emulate_ctxt
*ctxt
,
1349 struct x86_emulate_ops
*ops
, int irq
)
1351 struct decode_cache
*c
= &ctxt
->decode
;
1358 /* TODO: Add limit checks */
1359 c
->src
.val
= ctxt
->eflags
;
1360 emulate_push(ctxt
, ops
);
1361 rc
= writeback(ctxt
, ops
);
1362 if (rc
!= X86EMUL_CONTINUE
)
1365 ctxt
->eflags
&= ~(EFLG_IF
| EFLG_TF
| EFLG_AC
);
1367 c
->src
.val
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
1368 emulate_push(ctxt
, ops
);
1369 rc
= writeback(ctxt
, ops
);
1370 if (rc
!= X86EMUL_CONTINUE
)
1373 c
->src
.val
= c
->eip
;
1374 emulate_push(ctxt
, ops
);
1375 rc
= writeback(ctxt
, ops
);
1376 if (rc
!= X86EMUL_CONTINUE
)
1379 c
->dst
.type
= OP_NONE
;
1381 ops
->get_idt(&dt
, ctxt
->vcpu
);
1383 eip_addr
= dt
.address
+ (irq
<< 2);
1384 cs_addr
= dt
.address
+ (irq
<< 2) + 2;
1386 rc
= ops
->read_std(cs_addr
, &cs
, 2, ctxt
->vcpu
, &ctxt
->exception
);
1387 if (rc
!= X86EMUL_CONTINUE
)
1390 rc
= ops
->read_std(eip_addr
, &eip
, 2, ctxt
->vcpu
, &ctxt
->exception
);
1391 if (rc
!= X86EMUL_CONTINUE
)
1394 rc
= load_segment_descriptor(ctxt
, ops
, cs
, VCPU_SREG_CS
);
1395 if (rc
!= X86EMUL_CONTINUE
)
1403 static int emulate_int(struct x86_emulate_ctxt
*ctxt
,
1404 struct x86_emulate_ops
*ops
, int irq
)
1406 switch(ctxt
->mode
) {
1407 case X86EMUL_MODE_REAL
:
1408 return emulate_int_real(ctxt
, ops
, irq
);
1409 case X86EMUL_MODE_VM86
:
1410 case X86EMUL_MODE_PROT16
:
1411 case X86EMUL_MODE_PROT32
:
1412 case X86EMUL_MODE_PROT64
:
1414 /* Protected mode interrupts unimplemented yet */
1415 return X86EMUL_UNHANDLEABLE
;
1419 static int emulate_iret_real(struct x86_emulate_ctxt
*ctxt
,
1420 struct x86_emulate_ops
*ops
)
1422 struct decode_cache
*c
= &ctxt
->decode
;
1423 int rc
= X86EMUL_CONTINUE
;
1424 unsigned long temp_eip
= 0;
1425 unsigned long temp_eflags
= 0;
1426 unsigned long cs
= 0;
1427 unsigned long mask
= EFLG_CF
| EFLG_PF
| EFLG_AF
| EFLG_ZF
| EFLG_SF
| EFLG_TF
|
1428 EFLG_IF
| EFLG_DF
| EFLG_OF
| EFLG_IOPL
| EFLG_NT
| EFLG_RF
|
1429 EFLG_AC
| EFLG_ID
| (1 << 1); /* Last one is the reserved bit */
1430 unsigned long vm86_mask
= EFLG_VM
| EFLG_VIF
| EFLG_VIP
;
1432 /* TODO: Add stack limit check */
1434 rc
= emulate_pop(ctxt
, ops
, &temp_eip
, c
->op_bytes
);
1436 if (rc
!= X86EMUL_CONTINUE
)
1439 if (temp_eip
& ~0xffff)
1440 return emulate_gp(ctxt
, 0);
1442 rc
= emulate_pop(ctxt
, ops
, &cs
, c
->op_bytes
);
1444 if (rc
!= X86EMUL_CONTINUE
)
1447 rc
= emulate_pop(ctxt
, ops
, &temp_eflags
, c
->op_bytes
);
1449 if (rc
!= X86EMUL_CONTINUE
)
1452 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)cs
, VCPU_SREG_CS
);
1454 if (rc
!= X86EMUL_CONTINUE
)
1460 if (c
->op_bytes
== 4)
1461 ctxt
->eflags
= ((temp_eflags
& mask
) | (ctxt
->eflags
& vm86_mask
));
1462 else if (c
->op_bytes
== 2) {
1463 ctxt
->eflags
&= ~0xffff;
1464 ctxt
->eflags
|= temp_eflags
;
1467 ctxt
->eflags
&= ~EFLG_RESERVED_ZEROS_MASK
; /* Clear reserved zeros */
1468 ctxt
->eflags
|= EFLG_RESERVED_ONE_MASK
;
1473 static inline int emulate_iret(struct x86_emulate_ctxt
*ctxt
,
1474 struct x86_emulate_ops
* ops
)
1476 switch(ctxt
->mode
) {
1477 case X86EMUL_MODE_REAL
:
1478 return emulate_iret_real(ctxt
, ops
);
1479 case X86EMUL_MODE_VM86
:
1480 case X86EMUL_MODE_PROT16
:
1481 case X86EMUL_MODE_PROT32
:
1482 case X86EMUL_MODE_PROT64
:
1484 /* iret from protected mode unimplemented yet */
1485 return X86EMUL_UNHANDLEABLE
;
1489 static inline int emulate_grp1a(struct x86_emulate_ctxt
*ctxt
,
1490 struct x86_emulate_ops
*ops
)
1492 struct decode_cache
*c
= &ctxt
->decode
;
1494 return emulate_pop(ctxt
, ops
, &c
->dst
.val
, c
->dst
.bytes
);
1497 static inline void emulate_grp2(struct x86_emulate_ctxt
*ctxt
)
1499 struct decode_cache
*c
= &ctxt
->decode
;
1500 switch (c
->modrm_reg
) {
1502 emulate_2op_SrcB("rol", c
->src
, c
->dst
, ctxt
->eflags
);
1505 emulate_2op_SrcB("ror", c
->src
, c
->dst
, ctxt
->eflags
);
1508 emulate_2op_SrcB("rcl", c
->src
, c
->dst
, ctxt
->eflags
);
1511 emulate_2op_SrcB("rcr", c
->src
, c
->dst
, ctxt
->eflags
);
1513 case 4: /* sal/shl */
1514 case 6: /* sal/shl */
1515 emulate_2op_SrcB("sal", c
->src
, c
->dst
, ctxt
->eflags
);
1518 emulate_2op_SrcB("shr", c
->src
, c
->dst
, ctxt
->eflags
);
1521 emulate_2op_SrcB("sar", c
->src
, c
->dst
, ctxt
->eflags
);
1526 static inline int emulate_grp3(struct x86_emulate_ctxt
*ctxt
,
1527 struct x86_emulate_ops
*ops
)
1529 struct decode_cache
*c
= &ctxt
->decode
;
1530 unsigned long *rax
= &c
->regs
[VCPU_REGS_RAX
];
1531 unsigned long *rdx
= &c
->regs
[VCPU_REGS_RDX
];
1534 switch (c
->modrm_reg
) {
1535 case 0 ... 1: /* test */
1536 emulate_2op_SrcV("test", c
->src
, c
->dst
, ctxt
->eflags
);
1539 c
->dst
.val
= ~c
->dst
.val
;
1542 emulate_1op("neg", c
->dst
, ctxt
->eflags
);
1545 emulate_1op_rax_rdx("mul", c
->src
, *rax
, *rdx
, ctxt
->eflags
);
1548 emulate_1op_rax_rdx("imul", c
->src
, *rax
, *rdx
, ctxt
->eflags
);
1551 emulate_1op_rax_rdx_ex("div", c
->src
, *rax
, *rdx
,
1555 emulate_1op_rax_rdx_ex("idiv", c
->src
, *rax
, *rdx
,
1559 return X86EMUL_UNHANDLEABLE
;
1562 return emulate_de(ctxt
);
1563 return X86EMUL_CONTINUE
;
1566 static inline int emulate_grp45(struct x86_emulate_ctxt
*ctxt
,
1567 struct x86_emulate_ops
*ops
)
1569 struct decode_cache
*c
= &ctxt
->decode
;
1571 switch (c
->modrm_reg
) {
1573 emulate_1op("inc", c
->dst
, ctxt
->eflags
);
1576 emulate_1op("dec", c
->dst
, ctxt
->eflags
);
1578 case 2: /* call near abs */ {
1581 c
->eip
= c
->src
.val
;
1582 c
->src
.val
= old_eip
;
1583 emulate_push(ctxt
, ops
);
1586 case 4: /* jmp abs */
1587 c
->eip
= c
->src
.val
;
1590 emulate_push(ctxt
, ops
);
1593 return X86EMUL_CONTINUE
;
1596 static inline int emulate_grp9(struct x86_emulate_ctxt
*ctxt
,
1597 struct x86_emulate_ops
*ops
)
1599 struct decode_cache
*c
= &ctxt
->decode
;
1600 u64 old
= c
->dst
.orig_val64
;
1602 if (((u32
) (old
>> 0) != (u32
) c
->regs
[VCPU_REGS_RAX
]) ||
1603 ((u32
) (old
>> 32) != (u32
) c
->regs
[VCPU_REGS_RDX
])) {
1604 c
->regs
[VCPU_REGS_RAX
] = (u32
) (old
>> 0);
1605 c
->regs
[VCPU_REGS_RDX
] = (u32
) (old
>> 32);
1606 ctxt
->eflags
&= ~EFLG_ZF
;
1608 c
->dst
.val64
= ((u64
)c
->regs
[VCPU_REGS_RCX
] << 32) |
1609 (u32
) c
->regs
[VCPU_REGS_RBX
];
1611 ctxt
->eflags
|= EFLG_ZF
;
1613 return X86EMUL_CONTINUE
;
1616 static int emulate_ret_far(struct x86_emulate_ctxt
*ctxt
,
1617 struct x86_emulate_ops
*ops
)
1619 struct decode_cache
*c
= &ctxt
->decode
;
1623 rc
= emulate_pop(ctxt
, ops
, &c
->eip
, c
->op_bytes
);
1624 if (rc
!= X86EMUL_CONTINUE
)
1626 if (c
->op_bytes
== 4)
1627 c
->eip
= (u32
)c
->eip
;
1628 rc
= emulate_pop(ctxt
, ops
, &cs
, c
->op_bytes
);
1629 if (rc
!= X86EMUL_CONTINUE
)
1631 rc
= load_segment_descriptor(ctxt
, ops
, (u16
)cs
, VCPU_SREG_CS
);
1635 static int emulate_load_segment(struct x86_emulate_ctxt
*ctxt
,
1636 struct x86_emulate_ops
*ops
, int seg
)
1638 struct decode_cache
*c
= &ctxt
->decode
;
1642 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
1644 rc
= load_segment_descriptor(ctxt
, ops
, sel
, seg
);
1645 if (rc
!= X86EMUL_CONTINUE
)
1648 c
->dst
.val
= c
->src
.val
;
1653 setup_syscalls_segments(struct x86_emulate_ctxt
*ctxt
,
1654 struct x86_emulate_ops
*ops
, struct desc_struct
*cs
,
1655 struct desc_struct
*ss
)
1657 memset(cs
, 0, sizeof(struct desc_struct
));
1658 ops
->get_cached_descriptor(cs
, NULL
, VCPU_SREG_CS
, ctxt
->vcpu
);
1659 memset(ss
, 0, sizeof(struct desc_struct
));
1661 cs
->l
= 0; /* will be adjusted later */
1662 set_desc_base(cs
, 0); /* flat segment */
1663 cs
->g
= 1; /* 4kb granularity */
1664 set_desc_limit(cs
, 0xfffff); /* 4GB limit */
1665 cs
->type
= 0x0b; /* Read, Execute, Accessed */
1667 cs
->dpl
= 0; /* will be adjusted later */
1671 set_desc_base(ss
, 0); /* flat segment */
1672 set_desc_limit(ss
, 0xfffff); /* 4GB limit */
1673 ss
->g
= 1; /* 4kb granularity */
1675 ss
->type
= 0x03; /* Read/Write, Accessed */
1676 ss
->d
= 1; /* 32bit stack segment */
1682 emulate_syscall(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1684 struct decode_cache
*c
= &ctxt
->decode
;
1685 struct desc_struct cs
, ss
;
1689 /* syscall is not available in real mode */
1690 if (ctxt
->mode
== X86EMUL_MODE_REAL
||
1691 ctxt
->mode
== X86EMUL_MODE_VM86
)
1692 return emulate_ud(ctxt
);
1694 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1696 ops
->get_msr(ctxt
->vcpu
, MSR_STAR
, &msr_data
);
1698 cs_sel
= (u16
)(msr_data
& 0xfffc);
1699 ss_sel
= (u16
)(msr_data
+ 8);
1701 if (is_long_mode(ctxt
->vcpu
)) {
1705 ops
->set_cached_descriptor(&cs
, 0, VCPU_SREG_CS
, ctxt
->vcpu
);
1706 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1707 ops
->set_cached_descriptor(&ss
, 0, VCPU_SREG_SS
, ctxt
->vcpu
);
1708 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1710 c
->regs
[VCPU_REGS_RCX
] = c
->eip
;
1711 if (is_long_mode(ctxt
->vcpu
)) {
1712 #ifdef CONFIG_X86_64
1713 c
->regs
[VCPU_REGS_R11
] = ctxt
->eflags
& ~EFLG_RF
;
1715 ops
->get_msr(ctxt
->vcpu
,
1716 ctxt
->mode
== X86EMUL_MODE_PROT64
?
1717 MSR_LSTAR
: MSR_CSTAR
, &msr_data
);
1720 ops
->get_msr(ctxt
->vcpu
, MSR_SYSCALL_MASK
, &msr_data
);
1721 ctxt
->eflags
&= ~(msr_data
| EFLG_RF
);
1725 ops
->get_msr(ctxt
->vcpu
, MSR_STAR
, &msr_data
);
1726 c
->eip
= (u32
)msr_data
;
1728 ctxt
->eflags
&= ~(EFLG_VM
| EFLG_IF
| EFLG_RF
);
1731 return X86EMUL_CONTINUE
;
1735 emulate_sysenter(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1737 struct decode_cache
*c
= &ctxt
->decode
;
1738 struct desc_struct cs
, ss
;
1742 /* inject #GP if in real mode */
1743 if (ctxt
->mode
== X86EMUL_MODE_REAL
)
1744 return emulate_gp(ctxt
, 0);
1746 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1747 * Therefore, we inject an #UD.
1749 if (ctxt
->mode
== X86EMUL_MODE_PROT64
)
1750 return emulate_ud(ctxt
);
1752 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1754 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_CS
, &msr_data
);
1755 switch (ctxt
->mode
) {
1756 case X86EMUL_MODE_PROT32
:
1757 if ((msr_data
& 0xfffc) == 0x0)
1758 return emulate_gp(ctxt
, 0);
1760 case X86EMUL_MODE_PROT64
:
1761 if (msr_data
== 0x0)
1762 return emulate_gp(ctxt
, 0);
1766 ctxt
->eflags
&= ~(EFLG_VM
| EFLG_IF
| EFLG_RF
);
1767 cs_sel
= (u16
)msr_data
;
1768 cs_sel
&= ~SELECTOR_RPL_MASK
;
1769 ss_sel
= cs_sel
+ 8;
1770 ss_sel
&= ~SELECTOR_RPL_MASK
;
1771 if (ctxt
->mode
== X86EMUL_MODE_PROT64
1772 || is_long_mode(ctxt
->vcpu
)) {
1777 ops
->set_cached_descriptor(&cs
, 0, VCPU_SREG_CS
, ctxt
->vcpu
);
1778 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1779 ops
->set_cached_descriptor(&ss
, 0, VCPU_SREG_SS
, ctxt
->vcpu
);
1780 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1782 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_EIP
, &msr_data
);
1785 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_ESP
, &msr_data
);
1786 c
->regs
[VCPU_REGS_RSP
] = msr_data
;
1788 return X86EMUL_CONTINUE
;
1792 emulate_sysexit(struct x86_emulate_ctxt
*ctxt
, struct x86_emulate_ops
*ops
)
1794 struct decode_cache
*c
= &ctxt
->decode
;
1795 struct desc_struct cs
, ss
;
1800 /* inject #GP if in real mode or Virtual 8086 mode */
1801 if (ctxt
->mode
== X86EMUL_MODE_REAL
||
1802 ctxt
->mode
== X86EMUL_MODE_VM86
)
1803 return emulate_gp(ctxt
, 0);
1805 setup_syscalls_segments(ctxt
, ops
, &cs
, &ss
);
1807 if ((c
->rex_prefix
& 0x8) != 0x0)
1808 usermode
= X86EMUL_MODE_PROT64
;
1810 usermode
= X86EMUL_MODE_PROT32
;
1814 ops
->get_msr(ctxt
->vcpu
, MSR_IA32_SYSENTER_CS
, &msr_data
);
1816 case X86EMUL_MODE_PROT32
:
1817 cs_sel
= (u16
)(msr_data
+ 16);
1818 if ((msr_data
& 0xfffc) == 0x0)
1819 return emulate_gp(ctxt
, 0);
1820 ss_sel
= (u16
)(msr_data
+ 24);
1822 case X86EMUL_MODE_PROT64
:
1823 cs_sel
= (u16
)(msr_data
+ 32);
1824 if (msr_data
== 0x0)
1825 return emulate_gp(ctxt
, 0);
1826 ss_sel
= cs_sel
+ 8;
1831 cs_sel
|= SELECTOR_RPL_MASK
;
1832 ss_sel
|= SELECTOR_RPL_MASK
;
1834 ops
->set_cached_descriptor(&cs
, 0, VCPU_SREG_CS
, ctxt
->vcpu
);
1835 ops
->set_segment_selector(cs_sel
, VCPU_SREG_CS
, ctxt
->vcpu
);
1836 ops
->set_cached_descriptor(&ss
, 0, VCPU_SREG_SS
, ctxt
->vcpu
);
1837 ops
->set_segment_selector(ss_sel
, VCPU_SREG_SS
, ctxt
->vcpu
);
1839 c
->eip
= c
->regs
[VCPU_REGS_RDX
];
1840 c
->regs
[VCPU_REGS_RSP
] = c
->regs
[VCPU_REGS_RCX
];
1842 return X86EMUL_CONTINUE
;
1845 static bool emulator_bad_iopl(struct x86_emulate_ctxt
*ctxt
,
1846 struct x86_emulate_ops
*ops
)
1849 if (ctxt
->mode
== X86EMUL_MODE_REAL
)
1851 if (ctxt
->mode
== X86EMUL_MODE_VM86
)
1853 iopl
= (ctxt
->eflags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1854 return ops
->cpl(ctxt
->vcpu
) > iopl
;
1857 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt
*ctxt
,
1858 struct x86_emulate_ops
*ops
,
1861 struct desc_struct tr_seg
;
1864 u16 io_bitmap_ptr
, perm
, bit_idx
= port
& 0x7;
1865 unsigned mask
= (1 << len
) - 1;
1868 ops
->get_cached_descriptor(&tr_seg
, &base3
, VCPU_SREG_TR
, ctxt
->vcpu
);
1871 if (desc_limit_scaled(&tr_seg
) < 103)
1873 base
= get_desc_base(&tr_seg
);
1874 #ifdef CONFIG_X86_64
1875 base
|= ((u64
)base3
) << 32;
1877 r
= ops
->read_std(base
+ 102, &io_bitmap_ptr
, 2, ctxt
->vcpu
, NULL
);
1878 if (r
!= X86EMUL_CONTINUE
)
1880 if (io_bitmap_ptr
+ port
/8 > desc_limit_scaled(&tr_seg
))
1882 r
= ops
->read_std(base
+ io_bitmap_ptr
+ port
/8, &perm
, 2, ctxt
->vcpu
,
1884 if (r
!= X86EMUL_CONTINUE
)
1886 if ((perm
>> bit_idx
) & mask
)
1891 static bool emulator_io_permited(struct x86_emulate_ctxt
*ctxt
,
1892 struct x86_emulate_ops
*ops
,
1898 if (emulator_bad_iopl(ctxt
, ops
))
1899 if (!emulator_io_port_access_allowed(ctxt
, ops
, port
, len
))
1902 ctxt
->perm_ok
= true;
1907 static void save_state_to_tss16(struct x86_emulate_ctxt
*ctxt
,
1908 struct x86_emulate_ops
*ops
,
1909 struct tss_segment_16
*tss
)
1911 struct decode_cache
*c
= &ctxt
->decode
;
1914 tss
->flag
= ctxt
->eflags
;
1915 tss
->ax
= c
->regs
[VCPU_REGS_RAX
];
1916 tss
->cx
= c
->regs
[VCPU_REGS_RCX
];
1917 tss
->dx
= c
->regs
[VCPU_REGS_RDX
];
1918 tss
->bx
= c
->regs
[VCPU_REGS_RBX
];
1919 tss
->sp
= c
->regs
[VCPU_REGS_RSP
];
1920 tss
->bp
= c
->regs
[VCPU_REGS_RBP
];
1921 tss
->si
= c
->regs
[VCPU_REGS_RSI
];
1922 tss
->di
= c
->regs
[VCPU_REGS_RDI
];
1924 tss
->es
= ops
->get_segment_selector(VCPU_SREG_ES
, ctxt
->vcpu
);
1925 tss
->cs
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
1926 tss
->ss
= ops
->get_segment_selector(VCPU_SREG_SS
, ctxt
->vcpu
);
1927 tss
->ds
= ops
->get_segment_selector(VCPU_SREG_DS
, ctxt
->vcpu
);
1928 tss
->ldt
= ops
->get_segment_selector(VCPU_SREG_LDTR
, ctxt
->vcpu
);
1931 static int load_state_from_tss16(struct x86_emulate_ctxt
*ctxt
,
1932 struct x86_emulate_ops
*ops
,
1933 struct tss_segment_16
*tss
)
1935 struct decode_cache
*c
= &ctxt
->decode
;
1939 ctxt
->eflags
= tss
->flag
| 2;
1940 c
->regs
[VCPU_REGS_RAX
] = tss
->ax
;
1941 c
->regs
[VCPU_REGS_RCX
] = tss
->cx
;
1942 c
->regs
[VCPU_REGS_RDX
] = tss
->dx
;
1943 c
->regs
[VCPU_REGS_RBX
] = tss
->bx
;
1944 c
->regs
[VCPU_REGS_RSP
] = tss
->sp
;
1945 c
->regs
[VCPU_REGS_RBP
] = tss
->bp
;
1946 c
->regs
[VCPU_REGS_RSI
] = tss
->si
;
1947 c
->regs
[VCPU_REGS_RDI
] = tss
->di
;
1950 * SDM says that segment selectors are loaded before segment
1953 ops
->set_segment_selector(tss
->ldt
, VCPU_SREG_LDTR
, ctxt
->vcpu
);
1954 ops
->set_segment_selector(tss
->es
, VCPU_SREG_ES
, ctxt
->vcpu
);
1955 ops
->set_segment_selector(tss
->cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
1956 ops
->set_segment_selector(tss
->ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
1957 ops
->set_segment_selector(tss
->ds
, VCPU_SREG_DS
, ctxt
->vcpu
);
1960 * Now load segment descriptors. If fault happenes at this stage
1961 * it is handled in a context of new task
1963 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ldt
, VCPU_SREG_LDTR
);
1964 if (ret
!= X86EMUL_CONTINUE
)
1966 ret
= load_segment_descriptor(ctxt
, ops
, tss
->es
, VCPU_SREG_ES
);
1967 if (ret
!= X86EMUL_CONTINUE
)
1969 ret
= load_segment_descriptor(ctxt
, ops
, tss
->cs
, VCPU_SREG_CS
);
1970 if (ret
!= X86EMUL_CONTINUE
)
1972 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ss
, VCPU_SREG_SS
);
1973 if (ret
!= X86EMUL_CONTINUE
)
1975 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ds
, VCPU_SREG_DS
);
1976 if (ret
!= X86EMUL_CONTINUE
)
1979 return X86EMUL_CONTINUE
;
1982 static int task_switch_16(struct x86_emulate_ctxt
*ctxt
,
1983 struct x86_emulate_ops
*ops
,
1984 u16 tss_selector
, u16 old_tss_sel
,
1985 ulong old_tss_base
, struct desc_struct
*new_desc
)
1987 struct tss_segment_16 tss_seg
;
1989 u32 new_tss_base
= get_desc_base(new_desc
);
1991 ret
= ops
->read_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
1993 if (ret
!= X86EMUL_CONTINUE
)
1994 /* FIXME: need to provide precise fault address */
1997 save_state_to_tss16(ctxt
, ops
, &tss_seg
);
1999 ret
= ops
->write_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2001 if (ret
!= X86EMUL_CONTINUE
)
2002 /* FIXME: need to provide precise fault address */
2005 ret
= ops
->read_std(new_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2007 if (ret
!= X86EMUL_CONTINUE
)
2008 /* FIXME: need to provide precise fault address */
2011 if (old_tss_sel
!= 0xffff) {
2012 tss_seg
.prev_task_link
= old_tss_sel
;
2014 ret
= ops
->write_std(new_tss_base
,
2015 &tss_seg
.prev_task_link
,
2016 sizeof tss_seg
.prev_task_link
,
2017 ctxt
->vcpu
, &ctxt
->exception
);
2018 if (ret
!= X86EMUL_CONTINUE
)
2019 /* FIXME: need to provide precise fault address */
2023 return load_state_from_tss16(ctxt
, ops
, &tss_seg
);
2026 static void save_state_to_tss32(struct x86_emulate_ctxt
*ctxt
,
2027 struct x86_emulate_ops
*ops
,
2028 struct tss_segment_32
*tss
)
2030 struct decode_cache
*c
= &ctxt
->decode
;
2032 tss
->cr3
= ops
->get_cr(3, ctxt
->vcpu
);
2034 tss
->eflags
= ctxt
->eflags
;
2035 tss
->eax
= c
->regs
[VCPU_REGS_RAX
];
2036 tss
->ecx
= c
->regs
[VCPU_REGS_RCX
];
2037 tss
->edx
= c
->regs
[VCPU_REGS_RDX
];
2038 tss
->ebx
= c
->regs
[VCPU_REGS_RBX
];
2039 tss
->esp
= c
->regs
[VCPU_REGS_RSP
];
2040 tss
->ebp
= c
->regs
[VCPU_REGS_RBP
];
2041 tss
->esi
= c
->regs
[VCPU_REGS_RSI
];
2042 tss
->edi
= c
->regs
[VCPU_REGS_RDI
];
2044 tss
->es
= ops
->get_segment_selector(VCPU_SREG_ES
, ctxt
->vcpu
);
2045 tss
->cs
= ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
2046 tss
->ss
= ops
->get_segment_selector(VCPU_SREG_SS
, ctxt
->vcpu
);
2047 tss
->ds
= ops
->get_segment_selector(VCPU_SREG_DS
, ctxt
->vcpu
);
2048 tss
->fs
= ops
->get_segment_selector(VCPU_SREG_FS
, ctxt
->vcpu
);
2049 tss
->gs
= ops
->get_segment_selector(VCPU_SREG_GS
, ctxt
->vcpu
);
2050 tss
->ldt_selector
= ops
->get_segment_selector(VCPU_SREG_LDTR
, ctxt
->vcpu
);
2053 static int load_state_from_tss32(struct x86_emulate_ctxt
*ctxt
,
2054 struct x86_emulate_ops
*ops
,
2055 struct tss_segment_32
*tss
)
2057 struct decode_cache
*c
= &ctxt
->decode
;
2060 if (ops
->set_cr(3, tss
->cr3
, ctxt
->vcpu
))
2061 return emulate_gp(ctxt
, 0);
2063 ctxt
->eflags
= tss
->eflags
| 2;
2064 c
->regs
[VCPU_REGS_RAX
] = tss
->eax
;
2065 c
->regs
[VCPU_REGS_RCX
] = tss
->ecx
;
2066 c
->regs
[VCPU_REGS_RDX
] = tss
->edx
;
2067 c
->regs
[VCPU_REGS_RBX
] = tss
->ebx
;
2068 c
->regs
[VCPU_REGS_RSP
] = tss
->esp
;
2069 c
->regs
[VCPU_REGS_RBP
] = tss
->ebp
;
2070 c
->regs
[VCPU_REGS_RSI
] = tss
->esi
;
2071 c
->regs
[VCPU_REGS_RDI
] = tss
->edi
;
2074 * SDM says that segment selectors are loaded before segment
2077 ops
->set_segment_selector(tss
->ldt_selector
, VCPU_SREG_LDTR
, ctxt
->vcpu
);
2078 ops
->set_segment_selector(tss
->es
, VCPU_SREG_ES
, ctxt
->vcpu
);
2079 ops
->set_segment_selector(tss
->cs
, VCPU_SREG_CS
, ctxt
->vcpu
);
2080 ops
->set_segment_selector(tss
->ss
, VCPU_SREG_SS
, ctxt
->vcpu
);
2081 ops
->set_segment_selector(tss
->ds
, VCPU_SREG_DS
, ctxt
->vcpu
);
2082 ops
->set_segment_selector(tss
->fs
, VCPU_SREG_FS
, ctxt
->vcpu
);
2083 ops
->set_segment_selector(tss
->gs
, VCPU_SREG_GS
, ctxt
->vcpu
);
2086 * Now load segment descriptors. If fault happenes at this stage
2087 * it is handled in a context of new task
2089 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ldt_selector
, VCPU_SREG_LDTR
);
2090 if (ret
!= X86EMUL_CONTINUE
)
2092 ret
= load_segment_descriptor(ctxt
, ops
, tss
->es
, VCPU_SREG_ES
);
2093 if (ret
!= X86EMUL_CONTINUE
)
2095 ret
= load_segment_descriptor(ctxt
, ops
, tss
->cs
, VCPU_SREG_CS
);
2096 if (ret
!= X86EMUL_CONTINUE
)
2098 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ss
, VCPU_SREG_SS
);
2099 if (ret
!= X86EMUL_CONTINUE
)
2101 ret
= load_segment_descriptor(ctxt
, ops
, tss
->ds
, VCPU_SREG_DS
);
2102 if (ret
!= X86EMUL_CONTINUE
)
2104 ret
= load_segment_descriptor(ctxt
, ops
, tss
->fs
, VCPU_SREG_FS
);
2105 if (ret
!= X86EMUL_CONTINUE
)
2107 ret
= load_segment_descriptor(ctxt
, ops
, tss
->gs
, VCPU_SREG_GS
);
2108 if (ret
!= X86EMUL_CONTINUE
)
2111 return X86EMUL_CONTINUE
;
2114 static int task_switch_32(struct x86_emulate_ctxt
*ctxt
,
2115 struct x86_emulate_ops
*ops
,
2116 u16 tss_selector
, u16 old_tss_sel
,
2117 ulong old_tss_base
, struct desc_struct
*new_desc
)
2119 struct tss_segment_32 tss_seg
;
2121 u32 new_tss_base
= get_desc_base(new_desc
);
2123 ret
= ops
->read_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2125 if (ret
!= X86EMUL_CONTINUE
)
2126 /* FIXME: need to provide precise fault address */
2129 save_state_to_tss32(ctxt
, ops
, &tss_seg
);
2131 ret
= ops
->write_std(old_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2133 if (ret
!= X86EMUL_CONTINUE
)
2134 /* FIXME: need to provide precise fault address */
2137 ret
= ops
->read_std(new_tss_base
, &tss_seg
, sizeof tss_seg
, ctxt
->vcpu
,
2139 if (ret
!= X86EMUL_CONTINUE
)
2140 /* FIXME: need to provide precise fault address */
2143 if (old_tss_sel
!= 0xffff) {
2144 tss_seg
.prev_task_link
= old_tss_sel
;
2146 ret
= ops
->write_std(new_tss_base
,
2147 &tss_seg
.prev_task_link
,
2148 sizeof tss_seg
.prev_task_link
,
2149 ctxt
->vcpu
, &ctxt
->exception
);
2150 if (ret
!= X86EMUL_CONTINUE
)
2151 /* FIXME: need to provide precise fault address */
2155 return load_state_from_tss32(ctxt
, ops
, &tss_seg
);
2158 static int emulator_do_task_switch(struct x86_emulate_ctxt
*ctxt
,
2159 struct x86_emulate_ops
*ops
,
2160 u16 tss_selector
, int reason
,
2161 bool has_error_code
, u32 error_code
)
2163 struct desc_struct curr_tss_desc
, next_tss_desc
;
2165 u16 old_tss_sel
= ops
->get_segment_selector(VCPU_SREG_TR
, ctxt
->vcpu
);
2166 ulong old_tss_base
=
2167 ops
->get_cached_segment_base(VCPU_SREG_TR
, ctxt
->vcpu
);
2170 /* FIXME: old_tss_base == ~0 ? */
2172 ret
= read_segment_descriptor(ctxt
, ops
, tss_selector
, &next_tss_desc
);
2173 if (ret
!= X86EMUL_CONTINUE
)
2175 ret
= read_segment_descriptor(ctxt
, ops
, old_tss_sel
, &curr_tss_desc
);
2176 if (ret
!= X86EMUL_CONTINUE
)
2179 /* FIXME: check that next_tss_desc is tss */
2181 if (reason
!= TASK_SWITCH_IRET
) {
2182 if ((tss_selector
& 3) > next_tss_desc
.dpl
||
2183 ops
->cpl(ctxt
->vcpu
) > next_tss_desc
.dpl
)
2184 return emulate_gp(ctxt
, 0);
2187 desc_limit
= desc_limit_scaled(&next_tss_desc
);
2188 if (!next_tss_desc
.p
||
2189 ((desc_limit
< 0x67 && (next_tss_desc
.type
& 8)) ||
2190 desc_limit
< 0x2b)) {
2191 emulate_ts(ctxt
, tss_selector
& 0xfffc);
2192 return X86EMUL_PROPAGATE_FAULT
;
2195 if (reason
== TASK_SWITCH_IRET
|| reason
== TASK_SWITCH_JMP
) {
2196 curr_tss_desc
.type
&= ~(1 << 1); /* clear busy flag */
2197 write_segment_descriptor(ctxt
, ops
, old_tss_sel
,
2201 if (reason
== TASK_SWITCH_IRET
)
2202 ctxt
->eflags
= ctxt
->eflags
& ~X86_EFLAGS_NT
;
2204 /* set back link to prev task only if NT bit is set in eflags
2205 note that old_tss_sel is not used afetr this point */
2206 if (reason
!= TASK_SWITCH_CALL
&& reason
!= TASK_SWITCH_GATE
)
2207 old_tss_sel
= 0xffff;
2209 if (next_tss_desc
.type
& 8)
2210 ret
= task_switch_32(ctxt
, ops
, tss_selector
, old_tss_sel
,
2211 old_tss_base
, &next_tss_desc
);
2213 ret
= task_switch_16(ctxt
, ops
, tss_selector
, old_tss_sel
,
2214 old_tss_base
, &next_tss_desc
);
2215 if (ret
!= X86EMUL_CONTINUE
)
2218 if (reason
== TASK_SWITCH_CALL
|| reason
== TASK_SWITCH_GATE
)
2219 ctxt
->eflags
= ctxt
->eflags
| X86_EFLAGS_NT
;
2221 if (reason
!= TASK_SWITCH_IRET
) {
2222 next_tss_desc
.type
|= (1 << 1); /* set busy flag */
2223 write_segment_descriptor(ctxt
, ops
, tss_selector
,
2227 ops
->set_cr(0, ops
->get_cr(0, ctxt
->vcpu
) | X86_CR0_TS
, ctxt
->vcpu
);
2228 ops
->set_cached_descriptor(&next_tss_desc
, 0, VCPU_SREG_TR
, ctxt
->vcpu
);
2229 ops
->set_segment_selector(tss_selector
, VCPU_SREG_TR
, ctxt
->vcpu
);
2231 if (has_error_code
) {
2232 struct decode_cache
*c
= &ctxt
->decode
;
2234 c
->op_bytes
= c
->ad_bytes
= (next_tss_desc
.type
& 8) ? 4 : 2;
2236 c
->src
.val
= (unsigned long) error_code
;
2237 emulate_push(ctxt
, ops
);
2243 int emulator_task_switch(struct x86_emulate_ctxt
*ctxt
,
2244 u16 tss_selector
, int reason
,
2245 bool has_error_code
, u32 error_code
)
2247 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2248 struct decode_cache
*c
= &ctxt
->decode
;
2252 c
->dst
.type
= OP_NONE
;
2254 rc
= emulator_do_task_switch(ctxt
, ops
, tss_selector
, reason
,
2255 has_error_code
, error_code
);
2257 if (rc
== X86EMUL_CONTINUE
) {
2258 rc
= writeback(ctxt
, ops
);
2259 if (rc
== X86EMUL_CONTINUE
)
2263 return (rc
== X86EMUL_UNHANDLEABLE
) ? -1 : 0;
2266 static void string_addr_inc(struct x86_emulate_ctxt
*ctxt
, unsigned seg
,
2267 int reg
, struct operand
*op
)
2269 struct decode_cache
*c
= &ctxt
->decode
;
2270 int df
= (ctxt
->eflags
& EFLG_DF
) ? -1 : 1;
2272 register_address_increment(c
, &c
->regs
[reg
], df
* op
->bytes
);
2273 op
->addr
.mem
.ea
= register_address(c
, c
->regs
[reg
]);
2274 op
->addr
.mem
.seg
= seg
;
2277 static int em_push(struct x86_emulate_ctxt
*ctxt
)
2279 emulate_push(ctxt
, ctxt
->ops
);
2280 return X86EMUL_CONTINUE
;
2283 static int em_das(struct x86_emulate_ctxt
*ctxt
)
2285 struct decode_cache
*c
= &ctxt
->decode
;
2287 bool af
, cf
, old_cf
;
2289 cf
= ctxt
->eflags
& X86_EFLAGS_CF
;
2295 af
= ctxt
->eflags
& X86_EFLAGS_AF
;
2296 if ((al
& 0x0f) > 9 || af
) {
2298 cf
= old_cf
| (al
>= 250);
2303 if (old_al
> 0x99 || old_cf
) {
2309 /* Set PF, ZF, SF */
2310 c
->src
.type
= OP_IMM
;
2313 emulate_2op_SrcV("or", c
->src
, c
->dst
, ctxt
->eflags
);
2314 ctxt
->eflags
&= ~(X86_EFLAGS_AF
| X86_EFLAGS_CF
);
2316 ctxt
->eflags
|= X86_EFLAGS_CF
;
2318 ctxt
->eflags
|= X86_EFLAGS_AF
;
2319 return X86EMUL_CONTINUE
;
2322 static int em_call_far(struct x86_emulate_ctxt
*ctxt
)
2324 struct decode_cache
*c
= &ctxt
->decode
;
2329 old_cs
= ctxt
->ops
->get_segment_selector(VCPU_SREG_CS
, ctxt
->vcpu
);
2332 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
2333 if (load_segment_descriptor(ctxt
, ctxt
->ops
, sel
, VCPU_SREG_CS
))
2334 return X86EMUL_CONTINUE
;
2337 memcpy(&c
->eip
, c
->src
.valptr
, c
->op_bytes
);
2339 c
->src
.val
= old_cs
;
2340 emulate_push(ctxt
, ctxt
->ops
);
2341 rc
= writeback(ctxt
, ctxt
->ops
);
2342 if (rc
!= X86EMUL_CONTINUE
)
2345 c
->src
.val
= old_eip
;
2346 emulate_push(ctxt
, ctxt
->ops
);
2347 rc
= writeback(ctxt
, ctxt
->ops
);
2348 if (rc
!= X86EMUL_CONTINUE
)
2351 c
->dst
.type
= OP_NONE
;
2353 return X86EMUL_CONTINUE
;
2356 static int em_ret_near_imm(struct x86_emulate_ctxt
*ctxt
)
2358 struct decode_cache
*c
= &ctxt
->decode
;
2361 c
->dst
.type
= OP_REG
;
2362 c
->dst
.addr
.reg
= &c
->eip
;
2363 c
->dst
.bytes
= c
->op_bytes
;
2364 rc
= emulate_pop(ctxt
, ctxt
->ops
, &c
->dst
.val
, c
->op_bytes
);
2365 if (rc
!= X86EMUL_CONTINUE
)
2367 register_address_increment(c
, &c
->regs
[VCPU_REGS_RSP
], c
->src
.val
);
2368 return X86EMUL_CONTINUE
;
2371 static int em_imul(struct x86_emulate_ctxt
*ctxt
)
2373 struct decode_cache
*c
= &ctxt
->decode
;
2375 emulate_2op_SrcV_nobyte("imul", c
->src
, c
->dst
, ctxt
->eflags
);
2376 return X86EMUL_CONTINUE
;
2379 static int em_imul_3op(struct x86_emulate_ctxt
*ctxt
)
2381 struct decode_cache
*c
= &ctxt
->decode
;
2383 c
->dst
.val
= c
->src2
.val
;
2384 return em_imul(ctxt
);
2387 static int em_cwd(struct x86_emulate_ctxt
*ctxt
)
2389 struct decode_cache
*c
= &ctxt
->decode
;
2391 c
->dst
.type
= OP_REG
;
2392 c
->dst
.bytes
= c
->src
.bytes
;
2393 c
->dst
.addr
.reg
= &c
->regs
[VCPU_REGS_RDX
];
2394 c
->dst
.val
= ~((c
->src
.val
>> (c
->src
.bytes
* 8 - 1)) - 1);
2396 return X86EMUL_CONTINUE
;
2399 static int em_rdtsc(struct x86_emulate_ctxt
*ctxt
)
2401 unsigned cpl
= ctxt
->ops
->cpl(ctxt
->vcpu
);
2402 struct decode_cache
*c
= &ctxt
->decode
;
2405 if (cpl
> 0 && (ctxt
->ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_TSD
))
2406 return emulate_gp(ctxt
, 0);
2407 ctxt
->ops
->get_msr(ctxt
->vcpu
, MSR_IA32_TSC
, &tsc
);
2408 c
->regs
[VCPU_REGS_RAX
] = (u32
)tsc
;
2409 c
->regs
[VCPU_REGS_RDX
] = tsc
>> 32;
2410 return X86EMUL_CONTINUE
;
2413 static int em_mov(struct x86_emulate_ctxt
*ctxt
)
2415 struct decode_cache
*c
= &ctxt
->decode
;
2416 c
->dst
.val
= c
->src
.val
;
2417 return X86EMUL_CONTINUE
;
2420 static int em_movdqu(struct x86_emulate_ctxt
*ctxt
)
2422 struct decode_cache
*c
= &ctxt
->decode
;
2423 memcpy(&c
->dst
.vec_val
, &c
->src
.vec_val
, c
->op_bytes
);
2424 return X86EMUL_CONTINUE
;
2427 #define D(_y) { .flags = (_y) }
2428 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2429 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2430 .check_perm = (_p) }
2432 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2433 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2434 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2435 #define II(_f, _e, _i) \
2436 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2437 #define IIP(_f, _e, _i, _p) \
2438 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2439 .check_perm = (_p) }
2440 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2442 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2443 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2445 #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2446 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2447 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2450 static struct opcode group1
[] = {
2454 static struct opcode group1A
[] = {
2455 D(DstMem
| SrcNone
| ModRM
| Mov
| Stack
), N
, N
, N
, N
, N
, N
, N
,
2458 static struct opcode group3
[] = {
2459 D(DstMem
| SrcImm
| ModRM
), D(DstMem
| SrcImm
| ModRM
),
2460 D(DstMem
| SrcNone
| ModRM
| Lock
), D(DstMem
| SrcNone
| ModRM
| Lock
),
2461 X4(D(SrcMem
| ModRM
)),
2464 static struct opcode group4
[] = {
2465 D(ByteOp
| DstMem
| SrcNone
| ModRM
| Lock
), D(ByteOp
| DstMem
| SrcNone
| ModRM
| Lock
),
2469 static struct opcode group5
[] = {
2470 D(DstMem
| SrcNone
| ModRM
| Lock
), D(DstMem
| SrcNone
| ModRM
| Lock
),
2471 D(SrcMem
| ModRM
| Stack
),
2472 I(SrcMemFAddr
| ModRM
| ImplicitOps
| Stack
, em_call_far
),
2473 D(SrcMem
| ModRM
| Stack
), D(SrcMemFAddr
| ModRM
| ImplicitOps
),
2474 D(SrcMem
| ModRM
| Stack
), N
,
2477 static struct group_dual group7
= { {
2478 N
, N
, DI(ModRM
| SrcMem
| Priv
, lgdt
), DI(ModRM
| SrcMem
| Priv
, lidt
),
2479 DI(SrcNone
| ModRM
| DstMem
| Mov
, smsw
), N
,
2480 DI(SrcMem16
| ModRM
| Mov
| Priv
, lmsw
),
2481 DI(SrcMem
| ModRM
| ByteOp
| Priv
| NoAccess
, invlpg
),
2483 D(SrcNone
| ModRM
| Priv
| VendorSpecific
), N
,
2484 N
, D(SrcNone
| ModRM
| Priv
| VendorSpecific
),
2485 DI(SrcNone
| ModRM
| DstMem
| Mov
, smsw
), N
,
2486 DI(SrcMem16
| ModRM
| Mov
| Priv
, lmsw
), N
,
2489 static struct opcode group8
[] = {
2491 D(DstMem
| SrcImmByte
| ModRM
), D(DstMem
| SrcImmByte
| ModRM
| Lock
),
2492 D(DstMem
| SrcImmByte
| ModRM
| Lock
), D(DstMem
| SrcImmByte
| ModRM
| Lock
),
2495 static struct group_dual group9
= { {
2496 N
, D(DstMem64
| ModRM
| Lock
), N
, N
, N
, N
, N
, N
,
2498 N
, N
, N
, N
, N
, N
, N
, N
,
2501 static struct opcode group11
[] = {
2502 I(DstMem
| SrcImm
| ModRM
| Mov
, em_mov
), X7(D(Undefined
)),
2505 static struct gprefix pfx_0f_6f_0f_7f
= {
2506 N
, N
, N
, I(Sse
, em_movdqu
),
2509 static struct opcode opcode_table
[256] = {
2512 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2515 D(ImplicitOps
| Stack
| No64
), N
,
2518 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2521 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2525 D6ALU(Lock
), N
, I(ByteOp
| DstAcc
| No64
, em_das
),
2533 X8(I(SrcReg
| Stack
, em_push
)),
2535 X8(D(DstReg
| Stack
)),
2537 D(ImplicitOps
| Stack
| No64
), D(ImplicitOps
| Stack
| No64
),
2538 N
, D(DstReg
| SrcMem32
| ModRM
| Mov
) /* movsxd (x86/64) */ ,
2541 I(SrcImm
| Mov
| Stack
, em_push
),
2542 I(DstReg
| SrcMem
| ModRM
| Src2Imm
, em_imul_3op
),
2543 I(SrcImmByte
| Mov
| Stack
, em_push
),
2544 I(DstReg
| SrcMem
| ModRM
| Src2ImmByte
, em_imul_3op
),
2545 D2bv(DstDI
| Mov
| String
), /* insb, insw/insd */
2546 D2bv(SrcSI
| ImplicitOps
| String
), /* outsb, outsw/outsd */
2550 G(ByteOp
| DstMem
| SrcImm
| ModRM
| Group
, group1
),
2551 G(DstMem
| SrcImm
| ModRM
| Group
, group1
),
2552 G(ByteOp
| DstMem
| SrcImm
| ModRM
| No64
| Group
, group1
),
2553 G(DstMem
| SrcImmByte
| ModRM
| Group
, group1
),
2554 D2bv(DstMem
| SrcReg
| ModRM
), D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2556 I2bv(DstMem
| SrcReg
| ModRM
| Mov
, em_mov
),
2557 I2bv(DstReg
| SrcMem
| ModRM
| Mov
, em_mov
),
2558 D(DstMem
| SrcNone
| ModRM
| Mov
), D(ModRM
| SrcMem
| NoAccess
| DstReg
),
2559 D(ImplicitOps
| SrcMem16
| ModRM
), G(0, group1A
),
2561 X8(D(SrcAcc
| DstReg
)),
2563 D(DstAcc
| SrcNone
), I(ImplicitOps
| SrcAcc
, em_cwd
),
2564 I(SrcImmFAddr
| No64
, em_call_far
), N
,
2565 DI(ImplicitOps
| Stack
, pushf
), DI(ImplicitOps
| Stack
, popf
), N
, N
,
2567 I2bv(DstAcc
| SrcMem
| Mov
| MemAbs
, em_mov
),
2568 I2bv(DstMem
| SrcAcc
| Mov
| MemAbs
, em_mov
),
2569 I2bv(SrcSI
| DstDI
| Mov
| String
, em_mov
),
2570 D2bv(SrcSI
| DstDI
| String
),
2572 D2bv(DstAcc
| SrcImm
),
2573 I2bv(SrcAcc
| DstDI
| Mov
| String
, em_mov
),
2574 I2bv(SrcSI
| DstAcc
| Mov
| String
, em_mov
),
2575 D2bv(SrcAcc
| DstDI
| String
),
2577 X8(I(ByteOp
| DstReg
| SrcImm
| Mov
, em_mov
)),
2579 X8(I(DstReg
| SrcImm
| Mov
, em_mov
)),
2581 D2bv(DstMem
| SrcImmByte
| ModRM
),
2582 I(ImplicitOps
| Stack
| SrcImmU16
, em_ret_near_imm
),
2583 D(ImplicitOps
| Stack
),
2584 D(DstReg
| SrcMemFAddr
| ModRM
| No64
), D(DstReg
| SrcMemFAddr
| ModRM
| No64
),
2585 G(ByteOp
, group11
), G(0, group11
),
2587 N
, N
, N
, D(ImplicitOps
| Stack
),
2588 D(ImplicitOps
), DI(SrcImmByte
, intn
),
2589 D(ImplicitOps
| No64
), DI(ImplicitOps
, iret
),
2591 D2bv(DstMem
| SrcOne
| ModRM
), D2bv(DstMem
| ModRM
),
2594 N
, N
, N
, N
, N
, N
, N
, N
,
2597 D2bv(SrcImmUByte
| DstAcc
), D2bv(SrcAcc
| DstImmUByte
),
2599 D(SrcImm
| Stack
), D(SrcImm
| ImplicitOps
),
2600 D(SrcImmFAddr
| No64
), D(SrcImmByte
| ImplicitOps
),
2601 D2bv(SrcNone
| DstAcc
), D2bv(SrcAcc
| ImplicitOps
),
2604 DI(ImplicitOps
| Priv
, hlt
), D(ImplicitOps
),
2605 G(ByteOp
, group3
), G(0, group3
),
2607 D(ImplicitOps
), D(ImplicitOps
), D(ImplicitOps
), D(ImplicitOps
),
2608 D(ImplicitOps
), D(ImplicitOps
), G(0, group4
), G(0, group5
),
2611 static struct opcode twobyte_table
[256] = {
2613 N
, GD(0, &group7
), N
, N
,
2614 N
, D(ImplicitOps
| VendorSpecific
), D(ImplicitOps
| Priv
), N
,
2615 DI(ImplicitOps
| Priv
, invd
), DI(ImplicitOps
| Priv
, wbinvd
), N
, N
,
2616 N
, D(ImplicitOps
| ModRM
), N
, N
,
2618 N
, N
, N
, N
, N
, N
, N
, N
, D(ImplicitOps
| ModRM
), N
, N
, N
, N
, N
, N
, N
,
2620 D(ModRM
| DstMem
| Priv
| Op3264
), D(ModRM
| DstMem
| Priv
| Op3264
),
2621 D(ModRM
| SrcMem
| Priv
| Op3264
), D(ModRM
| SrcMem
| Priv
| Op3264
),
2623 N
, N
, N
, N
, N
, N
, N
, N
,
2625 D(ImplicitOps
| Priv
), II(ImplicitOps
, em_rdtsc
, rdtsc
),
2626 D(ImplicitOps
| Priv
), N
,
2627 D(ImplicitOps
| VendorSpecific
), D(ImplicitOps
| Priv
| VendorSpecific
),
2629 N
, N
, N
, N
, N
, N
, N
, N
,
2631 X16(D(DstReg
| SrcMem
| ModRM
| Mov
)),
2633 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2638 N
, N
, N
, GP(SrcMem
| DstReg
| ModRM
| Mov
, &pfx_0f_6f_0f_7f
),
2643 N
, N
, N
, GP(SrcReg
| DstMem
| ModRM
| Mov
, &pfx_0f_6f_0f_7f
),
2647 X16(D(ByteOp
| DstMem
| SrcNone
| ModRM
| Mov
)),
2649 D(ImplicitOps
| Stack
), D(ImplicitOps
| Stack
),
2650 N
, D(DstMem
| SrcReg
| ModRM
| BitOp
),
2651 D(DstMem
| SrcReg
| Src2ImmByte
| ModRM
),
2652 D(DstMem
| SrcReg
| Src2CL
| ModRM
), N
, N
,
2654 D(ImplicitOps
| Stack
), D(ImplicitOps
| Stack
),
2655 N
, D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2656 D(DstMem
| SrcReg
| Src2ImmByte
| ModRM
),
2657 D(DstMem
| SrcReg
| Src2CL
| ModRM
),
2658 D(ModRM
), I(DstReg
| SrcMem
| ModRM
, em_imul
),
2660 D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2661 D(DstReg
| SrcMemFAddr
| ModRM
), D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2662 D(DstReg
| SrcMemFAddr
| ModRM
), D(DstReg
| SrcMemFAddr
| ModRM
),
2663 D(ByteOp
| DstReg
| SrcMem
| ModRM
| Mov
), D(DstReg
| SrcMem16
| ModRM
| Mov
),
2666 G(BitOp
, group8
), D(DstMem
| SrcReg
| ModRM
| BitOp
| Lock
),
2667 D(DstReg
| SrcMem
| ModRM
), D(DstReg
| SrcMem
| ModRM
),
2668 D(ByteOp
| DstReg
| SrcMem
| ModRM
| Mov
), D(DstReg
| SrcMem16
| ModRM
| Mov
),
2670 D2bv(DstMem
| SrcReg
| ModRM
| Lock
),
2671 N
, D(DstMem
| SrcReg
| ModRM
| Mov
),
2672 N
, N
, N
, GD(0, &group9
),
2673 N
, N
, N
, N
, N
, N
, N
, N
,
2675 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2677 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
,
2679 N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
, N
2693 static unsigned imm_size(struct decode_cache
*c
)
2697 size
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2703 static int decode_imm(struct x86_emulate_ctxt
*ctxt
, struct operand
*op
,
2704 unsigned size
, bool sign_extension
)
2706 struct decode_cache
*c
= &ctxt
->decode
;
2707 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2708 int rc
= X86EMUL_CONTINUE
;
2712 op
->addr
.mem
.ea
= c
->eip
;
2713 /* NB. Immediates are sign-extended as necessary. */
2714 switch (op
->bytes
) {
2716 op
->val
= insn_fetch(s8
, 1, c
->eip
);
2719 op
->val
= insn_fetch(s16
, 2, c
->eip
);
2722 op
->val
= insn_fetch(s32
, 4, c
->eip
);
2725 if (!sign_extension
) {
2726 switch (op
->bytes
) {
2734 op
->val
&= 0xffffffff;
2743 x86_decode_insn(struct x86_emulate_ctxt
*ctxt
, void *insn
, int insn_len
)
2745 struct x86_emulate_ops
*ops
= ctxt
->ops
;
2746 struct decode_cache
*c
= &ctxt
->decode
;
2747 int rc
= X86EMUL_CONTINUE
;
2748 int mode
= ctxt
->mode
;
2749 int def_op_bytes
, def_ad_bytes
, dual
, goffset
, simd_prefix
;
2750 bool op_prefix
= false;
2751 struct opcode opcode
, *g_mod012
, *g_mod3
;
2752 struct operand memop
= { .type
= OP_NONE
};
2755 c
->fetch
.start
= c
->eip
;
2756 c
->fetch
.end
= c
->fetch
.start
+ insn_len
;
2758 memcpy(c
->fetch
.data
, insn
, insn_len
);
2759 ctxt
->cs_base
= seg_base(ctxt
, ops
, VCPU_SREG_CS
);
2762 case X86EMUL_MODE_REAL
:
2763 case X86EMUL_MODE_VM86
:
2764 case X86EMUL_MODE_PROT16
:
2765 def_op_bytes
= def_ad_bytes
= 2;
2767 case X86EMUL_MODE_PROT32
:
2768 def_op_bytes
= def_ad_bytes
= 4;
2770 #ifdef CONFIG_X86_64
2771 case X86EMUL_MODE_PROT64
:
2780 c
->op_bytes
= def_op_bytes
;
2781 c
->ad_bytes
= def_ad_bytes
;
2783 /* Legacy prefixes. */
2785 switch (c
->b
= insn_fetch(u8
, 1, c
->eip
)) {
2786 case 0x66: /* operand-size override */
2788 /* switch between 2/4 bytes */
2789 c
->op_bytes
= def_op_bytes
^ 6;
2791 case 0x67: /* address-size override */
2792 if (mode
== X86EMUL_MODE_PROT64
)
2793 /* switch between 4/8 bytes */
2794 c
->ad_bytes
= def_ad_bytes
^ 12;
2796 /* switch between 2/4 bytes */
2797 c
->ad_bytes
= def_ad_bytes
^ 6;
2799 case 0x26: /* ES override */
2800 case 0x2e: /* CS override */
2801 case 0x36: /* SS override */
2802 case 0x3e: /* DS override */
2803 set_seg_override(c
, (c
->b
>> 3) & 3);
2805 case 0x64: /* FS override */
2806 case 0x65: /* GS override */
2807 set_seg_override(c
, c
->b
& 7);
2809 case 0x40 ... 0x4f: /* REX */
2810 if (mode
!= X86EMUL_MODE_PROT64
)
2812 c
->rex_prefix
= c
->b
;
2814 case 0xf0: /* LOCK */
2817 case 0xf2: /* REPNE/REPNZ */
2818 case 0xf3: /* REP/REPE/REPZ */
2819 c
->rep_prefix
= c
->b
;
2825 /* Any legacy prefix after a REX prefix nullifies its effect. */
2833 if (c
->rex_prefix
& 8)
2834 c
->op_bytes
= 8; /* REX.W */
2836 /* Opcode byte(s). */
2837 opcode
= opcode_table
[c
->b
];
2838 /* Two-byte opcode? */
2841 c
->b
= insn_fetch(u8
, 1, c
->eip
);
2842 opcode
= twobyte_table
[c
->b
];
2844 c
->d
= opcode
.flags
;
2847 dual
= c
->d
& GroupDual
;
2848 c
->modrm
= insn_fetch(u8
, 1, c
->eip
);
2851 if (c
->d
& GroupDual
) {
2852 g_mod012
= opcode
.u
.gdual
->mod012
;
2853 g_mod3
= opcode
.u
.gdual
->mod3
;
2855 g_mod012
= g_mod3
= opcode
.u
.group
;
2857 c
->d
&= ~(Group
| GroupDual
);
2859 goffset
= (c
->modrm
>> 3) & 7;
2861 if ((c
->modrm
>> 6) == 3)
2862 opcode
= g_mod3
[goffset
];
2864 opcode
= g_mod012
[goffset
];
2865 c
->d
|= opcode
.flags
;
2868 if (c
->d
& Prefix
) {
2869 if (c
->rep_prefix
&& op_prefix
)
2870 return X86EMUL_UNHANDLEABLE
;
2871 simd_prefix
= op_prefix
? 0x66 : c
->rep_prefix
;
2872 switch (simd_prefix
) {
2873 case 0x00: opcode
= opcode
.u
.gprefix
->pfx_no
; break;
2874 case 0x66: opcode
= opcode
.u
.gprefix
->pfx_66
; break;
2875 case 0xf2: opcode
= opcode
.u
.gprefix
->pfx_f2
; break;
2876 case 0xf3: opcode
= opcode
.u
.gprefix
->pfx_f3
; break;
2878 c
->d
|= opcode
.flags
;
2881 c
->execute
= opcode
.u
.execute
;
2882 c
->check_perm
= opcode
.check_perm
;
2883 c
->intercept
= opcode
.intercept
;
2886 if (c
->d
== 0 || (c
->d
& Undefined
))
2889 if (!(c
->d
& VendorSpecific
) && ctxt
->only_vendor_specific_insn
)
2892 if (mode
== X86EMUL_MODE_PROT64
&& (c
->d
& Stack
))
2895 if (c
->d
& Op3264
) {
2896 if (mode
== X86EMUL_MODE_PROT64
)
2905 /* ModRM and SIB bytes. */
2907 rc
= decode_modrm(ctxt
, ops
, &memop
);
2908 if (!c
->has_seg_override
)
2909 set_seg_override(c
, c
->modrm_seg
);
2910 } else if (c
->d
& MemAbs
)
2911 rc
= decode_abs(ctxt
, ops
, &memop
);
2912 if (rc
!= X86EMUL_CONTINUE
)
2915 if (!c
->has_seg_override
)
2916 set_seg_override(c
, VCPU_SREG_DS
);
2918 memop
.addr
.mem
.seg
= seg_override(ctxt
, ops
, c
);
2920 if (memop
.type
== OP_MEM
&& c
->ad_bytes
!= 8)
2921 memop
.addr
.mem
.ea
= (u32
)memop
.addr
.mem
.ea
;
2923 if (memop
.type
== OP_MEM
&& c
->rip_relative
)
2924 memop
.addr
.mem
.ea
+= c
->eip
;
2927 * Decode and fetch the source operand: register, memory
2930 switch (c
->d
& SrcMask
) {
2934 decode_register_operand(ctxt
, &c
->src
, c
, 0);
2943 memop
.bytes
= (c
->d
& ByteOp
) ? 1 :
2949 rc
= decode_imm(ctxt
, &c
->src
, 2, false);
2952 rc
= decode_imm(ctxt
, &c
->src
, imm_size(c
), true);
2955 rc
= decode_imm(ctxt
, &c
->src
, imm_size(c
), false);
2958 rc
= decode_imm(ctxt
, &c
->src
, 1, true);
2961 rc
= decode_imm(ctxt
, &c
->src
, 1, false);
2964 c
->src
.type
= OP_REG
;
2965 c
->src
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2966 c
->src
.addr
.reg
= &c
->regs
[VCPU_REGS_RAX
];
2967 fetch_register_operand(&c
->src
);
2974 c
->src
.type
= OP_MEM
;
2975 c
->src
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
2976 c
->src
.addr
.mem
.ea
=
2977 register_address(c
, c
->regs
[VCPU_REGS_RSI
]);
2978 c
->src
.addr
.mem
.seg
= seg_override(ctxt
, ops
, c
),
2982 c
->src
.type
= OP_IMM
;
2983 c
->src
.addr
.mem
.ea
= c
->eip
;
2984 c
->src
.bytes
= c
->op_bytes
+ 2;
2985 insn_fetch_arr(c
->src
.valptr
, c
->src
.bytes
, c
->eip
);
2988 memop
.bytes
= c
->op_bytes
+ 2;
2993 if (rc
!= X86EMUL_CONTINUE
)
2997 * Decode and fetch the second source operand: register, memory
3000 switch (c
->d
& Src2Mask
) {
3005 c
->src2
.val
= c
->regs
[VCPU_REGS_RCX
] & 0x8;
3008 rc
= decode_imm(ctxt
, &c
->src2
, 1, true);
3015 rc
= decode_imm(ctxt
, &c
->src2
, imm_size(c
), true);
3019 if (rc
!= X86EMUL_CONTINUE
)
3022 /* Decode and fetch the destination operand: register or memory. */
3023 switch (c
->d
& DstMask
) {
3025 decode_register_operand(ctxt
, &c
->dst
, c
,
3026 c
->twobyte
&& (c
->b
== 0xb6 || c
->b
== 0xb7));
3029 c
->dst
.type
= OP_IMM
;
3030 c
->dst
.addr
.mem
.ea
= c
->eip
;
3032 c
->dst
.val
= insn_fetch(u8
, 1, c
->eip
);
3037 if ((c
->d
& DstMask
) == DstMem64
)
3040 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
3042 fetch_bit_operand(c
);
3043 c
->dst
.orig_val
= c
->dst
.val
;
3046 c
->dst
.type
= OP_REG
;
3047 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
3048 c
->dst
.addr
.reg
= &c
->regs
[VCPU_REGS_RAX
];
3049 fetch_register_operand(&c
->dst
);
3050 c
->dst
.orig_val
= c
->dst
.val
;
3053 c
->dst
.type
= OP_MEM
;
3054 c
->dst
.bytes
= (c
->d
& ByteOp
) ? 1 : c
->op_bytes
;
3055 c
->dst
.addr
.mem
.ea
=
3056 register_address(c
, c
->regs
[VCPU_REGS_RDI
]);
3057 c
->dst
.addr
.mem
.seg
= VCPU_SREG_ES
;
3061 /* Special instructions do their own operand decoding. */
3063 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3068 return (rc
== X86EMUL_UNHANDLEABLE
) ? -1 : 0;
3071 static bool string_insn_completed(struct x86_emulate_ctxt
*ctxt
)
3073 struct decode_cache
*c
= &ctxt
->decode
;
3075 /* The second termination condition only applies for REPE
3076 * and REPNE. Test if the repeat string operation prefix is
3077 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3078 * corresponding termination condition according to:
3079 * - if REPE/REPZ and ZF = 0 then done
3080 * - if REPNE/REPNZ and ZF = 1 then done
3082 if (((c
->b
== 0xa6) || (c
->b
== 0xa7) ||
3083 (c
->b
== 0xae) || (c
->b
== 0xaf))
3084 && (((c
->rep_prefix
== REPE_PREFIX
) &&
3085 ((ctxt
->eflags
& EFLG_ZF
) == 0))
3086 || ((c
->rep_prefix
== REPNE_PREFIX
) &&
3087 ((ctxt
->eflags
& EFLG_ZF
) == EFLG_ZF
))))
3094 x86_emulate_insn(struct x86_emulate_ctxt
*ctxt
)
3096 struct x86_emulate_ops
*ops
= ctxt
->ops
;
3098 struct decode_cache
*c
= &ctxt
->decode
;
3099 int rc
= X86EMUL_CONTINUE
;
3100 int saved_dst_type
= c
->dst
.type
;
3101 int irq
; /* Used for int 3, int, and into */
3103 ctxt
->decode
.mem_read
.pos
= 0;
3105 if (ctxt
->mode
== X86EMUL_MODE_PROT64
&& (c
->d
& No64
)) {
3106 rc
= emulate_ud(ctxt
);
3110 /* LOCK prefix is allowed only with some instructions */
3111 if (c
->lock_prefix
&& (!(c
->d
& Lock
) || c
->dst
.type
!= OP_MEM
)) {
3112 rc
= emulate_ud(ctxt
);
3116 if ((c
->d
& SrcMask
) == SrcMemFAddr
&& c
->src
.type
!= OP_MEM
) {
3117 rc
= emulate_ud(ctxt
);
3122 && ((ops
->get_cr(0, ctxt
->vcpu
) & X86_CR0_EM
)
3123 || !(ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_OSFXSR
))) {
3124 rc
= emulate_ud(ctxt
);
3128 if ((c
->d
& Sse
) && (ops
->get_cr(0, ctxt
->vcpu
) & X86_CR0_TS
)) {
3129 rc
= emulate_nm(ctxt
);
3133 if (unlikely(ctxt
->guest_mode
) && c
->intercept
) {
3134 rc
= ops
->intercept(ctxt
, c
->intercept
,
3135 X86_ICPT_PRE_EXCEPT
);
3136 if (rc
!= X86EMUL_CONTINUE
)
3140 /* Privileged instruction can be executed only in CPL=0 */
3141 if ((c
->d
& Priv
) && ops
->cpl(ctxt
->vcpu
)) {
3142 rc
= emulate_gp(ctxt
, 0);
3146 /* Do instruction specific permission checks */
3147 if (c
->check_perm
) {
3148 rc
= c
->check_perm(ctxt
);
3149 if (rc
!= X86EMUL_CONTINUE
)
3153 if (unlikely(ctxt
->guest_mode
) && c
->intercept
) {
3154 rc
= ops
->intercept(ctxt
, c
->intercept
,
3155 X86_ICPT_POST_EXCEPT
);
3156 if (rc
!= X86EMUL_CONTINUE
)
3160 if (c
->rep_prefix
&& (c
->d
& String
)) {
3161 /* All REP prefixes have the same first termination condition */
3162 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) == 0) {
3168 if ((c
->src
.type
== OP_MEM
) && !(c
->d
& NoAccess
)) {
3169 rc
= read_emulated(ctxt
, ops
, linear(ctxt
, c
->src
.addr
.mem
),
3170 c
->src
.valptr
, c
->src
.bytes
);
3171 if (rc
!= X86EMUL_CONTINUE
)
3173 c
->src
.orig_val64
= c
->src
.val64
;
3176 if (c
->src2
.type
== OP_MEM
) {
3177 rc
= read_emulated(ctxt
, ops
, linear(ctxt
, c
->src2
.addr
.mem
),
3178 &c
->src2
.val
, c
->src2
.bytes
);
3179 if (rc
!= X86EMUL_CONTINUE
)
3183 if ((c
->d
& DstMask
) == ImplicitOps
)
3187 if ((c
->dst
.type
== OP_MEM
) && !(c
->d
& Mov
)) {
3188 /* optimisation - avoid slow emulated read if Mov */
3189 rc
= read_emulated(ctxt
, ops
, linear(ctxt
, c
->dst
.addr
.mem
),
3190 &c
->dst
.val
, c
->dst
.bytes
);
3191 if (rc
!= X86EMUL_CONTINUE
)
3194 c
->dst
.orig_val
= c
->dst
.val
;
3198 if (unlikely(ctxt
->guest_mode
) && c
->intercept
) {
3199 rc
= ops
->intercept(ctxt
, c
->intercept
,
3200 X86_ICPT_POST_MEMACCESS
);
3201 if (rc
!= X86EMUL_CONTINUE
)
3206 rc
= c
->execute(ctxt
);
3207 if (rc
!= X86EMUL_CONTINUE
)
3218 emulate_2op_SrcV("add", c
->src
, c
->dst
, ctxt
->eflags
);
3220 case 0x06: /* push es */
3221 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_ES
);
3223 case 0x07: /* pop es */
3224 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_ES
);
3228 emulate_2op_SrcV("or", c
->src
, c
->dst
, ctxt
->eflags
);
3230 case 0x0e: /* push cs */
3231 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_CS
);
3235 emulate_2op_SrcV("adc", c
->src
, c
->dst
, ctxt
->eflags
);
3237 case 0x16: /* push ss */
3238 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_SS
);
3240 case 0x17: /* pop ss */
3241 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_SS
);
3245 emulate_2op_SrcV("sbb", c
->src
, c
->dst
, ctxt
->eflags
);
3247 case 0x1e: /* push ds */
3248 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_DS
);
3250 case 0x1f: /* pop ds */
3251 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_DS
);
3255 emulate_2op_SrcV("and", c
->src
, c
->dst
, ctxt
->eflags
);
3259 emulate_2op_SrcV("sub", c
->src
, c
->dst
, ctxt
->eflags
);
3263 emulate_2op_SrcV("xor", c
->src
, c
->dst
, ctxt
->eflags
);
3267 emulate_2op_SrcV("cmp", c
->src
, c
->dst
, ctxt
->eflags
);
3269 case 0x40 ... 0x47: /* inc r16/r32 */
3270 emulate_1op("inc", c
->dst
, ctxt
->eflags
);
3272 case 0x48 ... 0x4f: /* dec r16/r32 */
3273 emulate_1op("dec", c
->dst
, ctxt
->eflags
);
3275 case 0x58 ... 0x5f: /* pop reg */
3277 rc
= emulate_pop(ctxt
, ops
, &c
->dst
.val
, c
->op_bytes
);
3279 case 0x60: /* pusha */
3280 rc
= emulate_pusha(ctxt
, ops
);
3282 case 0x61: /* popa */
3283 rc
= emulate_popa(ctxt
, ops
);
3285 case 0x63: /* movsxd */
3286 if (ctxt
->mode
!= X86EMUL_MODE_PROT64
)
3287 goto cannot_emulate
;
3288 c
->dst
.val
= (s32
) c
->src
.val
;
3290 case 0x6c: /* insb */
3291 case 0x6d: /* insw/insd */
3292 c
->src
.val
= c
->regs
[VCPU_REGS_RDX
];
3294 case 0x6e: /* outsb */
3295 case 0x6f: /* outsw/outsd */
3296 c
->dst
.val
= c
->regs
[VCPU_REGS_RDX
];
3299 case 0x70 ... 0x7f: /* jcc (short) */
3300 if (test_cc(c
->b
, ctxt
->eflags
))
3301 jmp_rel(c
, c
->src
.val
);
3303 case 0x80 ... 0x83: /* Grp1 */
3304 switch (c
->modrm_reg
) {
3325 emulate_2op_SrcV("test", c
->src
, c
->dst
, ctxt
->eflags
);
3327 case 0x86 ... 0x87: /* xchg */
3329 /* Write back the register source. */
3330 c
->src
.val
= c
->dst
.val
;
3331 write_register_operand(&c
->src
);
3333 * Write back the memory destination with implicit LOCK
3336 c
->dst
.val
= c
->src
.orig_val
;
3339 case 0x8c: /* mov r/m, sreg */
3340 if (c
->modrm_reg
> VCPU_SREG_GS
) {
3341 rc
= emulate_ud(ctxt
);
3344 c
->dst
.val
= ops
->get_segment_selector(c
->modrm_reg
, ctxt
->vcpu
);
3346 case 0x8d: /* lea r16/r32, m */
3347 c
->dst
.val
= c
->src
.addr
.mem
.ea
;
3349 case 0x8e: { /* mov seg, r/m16 */
3354 if (c
->modrm_reg
== VCPU_SREG_CS
||
3355 c
->modrm_reg
> VCPU_SREG_GS
) {
3356 rc
= emulate_ud(ctxt
);
3360 if (c
->modrm_reg
== VCPU_SREG_SS
)
3361 ctxt
->interruptibility
= KVM_X86_SHADOW_INT_MOV_SS
;
3363 rc
= load_segment_descriptor(ctxt
, ops
, sel
, c
->modrm_reg
);
3365 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3368 case 0x8f: /* pop (sole member of Grp1a) */
3369 rc
= emulate_grp1a(ctxt
, ops
);
3371 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3372 if (c
->dst
.addr
.reg
== &c
->regs
[VCPU_REGS_RAX
])
3375 case 0x98: /* cbw/cwde/cdqe */
3376 switch (c
->op_bytes
) {
3377 case 2: c
->dst
.val
= (s8
)c
->dst
.val
; break;
3378 case 4: c
->dst
.val
= (s16
)c
->dst
.val
; break;
3379 case 8: c
->dst
.val
= (s32
)c
->dst
.val
; break;
3382 case 0x9c: /* pushf */
3383 c
->src
.val
= (unsigned long) ctxt
->eflags
;
3384 emulate_push(ctxt
, ops
);
3386 case 0x9d: /* popf */
3387 c
->dst
.type
= OP_REG
;
3388 c
->dst
.addr
.reg
= &ctxt
->eflags
;
3389 c
->dst
.bytes
= c
->op_bytes
;
3390 rc
= emulate_popf(ctxt
, ops
, &c
->dst
.val
, c
->op_bytes
);
3392 case 0xa6 ... 0xa7: /* cmps */
3393 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3395 case 0xa8 ... 0xa9: /* test ax, imm */
3397 case 0xae ... 0xaf: /* scas */
3402 case 0xc3: /* ret */
3403 c
->dst
.type
= OP_REG
;
3404 c
->dst
.addr
.reg
= &c
->eip
;
3405 c
->dst
.bytes
= c
->op_bytes
;
3406 goto pop_instruction
;
3407 case 0xc4: /* les */
3408 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_ES
);
3410 case 0xc5: /* lds */
3411 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_DS
);
3413 case 0xcb: /* ret far */
3414 rc
= emulate_ret_far(ctxt
, ops
);
3416 case 0xcc: /* int3 */
3419 case 0xcd: /* int n */
3422 rc
= emulate_int(ctxt
, ops
, irq
);
3424 case 0xce: /* into */
3425 if (ctxt
->eflags
& EFLG_OF
) {
3430 case 0xcf: /* iret */
3431 rc
= emulate_iret(ctxt
, ops
);
3433 case 0xd0 ... 0xd1: /* Grp2 */
3436 case 0xd2 ... 0xd3: /* Grp2 */
3437 c
->src
.val
= c
->regs
[VCPU_REGS_RCX
];
3440 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3441 register_address_increment(c
, &c
->regs
[VCPU_REGS_RCX
], -1);
3442 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) != 0 &&
3443 (c
->b
== 0xe2 || test_cc(c
->b
^ 0x5, ctxt
->eflags
)))
3444 jmp_rel(c
, c
->src
.val
);
3446 case 0xe3: /* jcxz/jecxz/jrcxz */
3447 if (address_mask(c
, c
->regs
[VCPU_REGS_RCX
]) == 0)
3448 jmp_rel(c
, c
->src
.val
);
3450 case 0xe4: /* inb */
3453 case 0xe6: /* outb */
3454 case 0xe7: /* out */
3456 case 0xe8: /* call (near) */ {
3457 long int rel
= c
->src
.val
;
3458 c
->src
.val
= (unsigned long) c
->eip
;
3460 emulate_push(ctxt
, ops
);
3463 case 0xe9: /* jmp rel */
3465 case 0xea: { /* jmp far */
3468 memcpy(&sel
, c
->src
.valptr
+ c
->op_bytes
, 2);
3470 if (load_segment_descriptor(ctxt
, ops
, sel
, VCPU_SREG_CS
))
3474 memcpy(&c
->eip
, c
->src
.valptr
, c
->op_bytes
);
3478 jmp
: /* jmp rel short */
3479 jmp_rel(c
, c
->src
.val
);
3480 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3482 case 0xec: /* in al,dx */
3483 case 0xed: /* in (e/r)ax,dx */
3484 c
->src
.val
= c
->regs
[VCPU_REGS_RDX
];
3486 c
->dst
.bytes
= min(c
->dst
.bytes
, 4u);
3487 if (!emulator_io_permited(ctxt
, ops
, c
->src
.val
, c
->dst
.bytes
)) {
3488 rc
= emulate_gp(ctxt
, 0);
3491 if (!pio_in_emulated(ctxt
, ops
, c
->dst
.bytes
, c
->src
.val
,
3493 goto done
; /* IO is needed */
3495 case 0xee: /* out dx,al */
3496 case 0xef: /* out dx,(e/r)ax */
3497 c
->dst
.val
= c
->regs
[VCPU_REGS_RDX
];
3499 c
->src
.bytes
= min(c
->src
.bytes
, 4u);
3500 if (!emulator_io_permited(ctxt
, ops
, c
->dst
.val
,
3502 rc
= emulate_gp(ctxt
, 0);
3505 ops
->pio_out_emulated(c
->src
.bytes
, c
->dst
.val
,
3506 &c
->src
.val
, 1, ctxt
->vcpu
);
3507 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3509 case 0xf4: /* hlt */
3510 ctxt
->vcpu
->arch
.halt_request
= 1;
3512 case 0xf5: /* cmc */
3513 /* complement carry flag from eflags reg */
3514 ctxt
->eflags
^= EFLG_CF
;
3516 case 0xf6 ... 0xf7: /* Grp3 */
3517 rc
= emulate_grp3(ctxt
, ops
);
3519 case 0xf8: /* clc */
3520 ctxt
->eflags
&= ~EFLG_CF
;
3522 case 0xf9: /* stc */
3523 ctxt
->eflags
|= EFLG_CF
;
3525 case 0xfa: /* cli */
3526 if (emulator_bad_iopl(ctxt
, ops
)) {
3527 rc
= emulate_gp(ctxt
, 0);
3530 ctxt
->eflags
&= ~X86_EFLAGS_IF
;
3532 case 0xfb: /* sti */
3533 if (emulator_bad_iopl(ctxt
, ops
)) {
3534 rc
= emulate_gp(ctxt
, 0);
3537 ctxt
->interruptibility
= KVM_X86_SHADOW_INT_STI
;
3538 ctxt
->eflags
|= X86_EFLAGS_IF
;
3541 case 0xfc: /* cld */
3542 ctxt
->eflags
&= ~EFLG_DF
;
3544 case 0xfd: /* std */
3545 ctxt
->eflags
|= EFLG_DF
;
3547 case 0xfe: /* Grp4 */
3549 rc
= emulate_grp45(ctxt
, ops
);
3551 case 0xff: /* Grp5 */
3552 if (c
->modrm_reg
== 5)
3556 goto cannot_emulate
;
3559 if (rc
!= X86EMUL_CONTINUE
)
3563 rc
= writeback(ctxt
, ops
);
3564 if (rc
!= X86EMUL_CONTINUE
)
3568 * restore dst type in case the decoding will be reused
3569 * (happens for string instruction )
3571 c
->dst
.type
= saved_dst_type
;
3573 if ((c
->d
& SrcMask
) == SrcSI
)
3574 string_addr_inc(ctxt
, seg_override(ctxt
, ops
, c
),
3575 VCPU_REGS_RSI
, &c
->src
);
3577 if ((c
->d
& DstMask
) == DstDI
)
3578 string_addr_inc(ctxt
, VCPU_SREG_ES
, VCPU_REGS_RDI
,
3581 if (c
->rep_prefix
&& (c
->d
& String
)) {
3582 struct read_cache
*r
= &ctxt
->decode
.io_read
;
3583 register_address_increment(c
, &c
->regs
[VCPU_REGS_RCX
], -1);
3585 if (!string_insn_completed(ctxt
)) {
3587 * Re-enter guest when pio read ahead buffer is empty
3588 * or, if it is not used, after each 1024 iteration.
3590 if ((r
->end
!= 0 || c
->regs
[VCPU_REGS_RCX
] & 0x3ff) &&
3591 (r
->end
== 0 || r
->end
!= r
->pos
)) {
3593 * Reset read cache. Usually happens before
3594 * decode, but since instruction is restarted
3595 * we have to do it here.
3597 ctxt
->decode
.mem_read
.end
= 0;
3598 return EMULATION_RESTART
;
3600 goto done
; /* skip rip writeback */
3607 if (rc
== X86EMUL_PROPAGATE_FAULT
)
3608 ctxt
->have_exception
= true;
3609 if (rc
== X86EMUL_INTERCEPTED
)
3610 return EMULATION_INTERCEPTED
;
3612 return (rc
== X86EMUL_UNHANDLEABLE
) ? EMULATION_FAILED
: EMULATION_OK
;
3616 case 0x01: /* lgdt, lidt, lmsw */
3617 switch (c
->modrm_reg
) {
3619 unsigned long address
;
3621 case 0: /* vmcall */
3622 if (c
->modrm_mod
!= 3 || c
->modrm_rm
!= 1)
3623 goto cannot_emulate
;
3625 rc
= kvm_fix_hypercall(ctxt
->vcpu
);
3626 if (rc
!= X86EMUL_CONTINUE
)
3629 /* Let the processor re-execute the fixed hypercall */
3631 /* Disable writeback. */
3632 c
->dst
.type
= OP_NONE
;
3635 rc
= read_descriptor(ctxt
, ops
, c
->src
.addr
.mem
,
3636 &size
, &address
, c
->op_bytes
);
3637 if (rc
!= X86EMUL_CONTINUE
)
3639 realmode_lgdt(ctxt
->vcpu
, size
, address
);
3640 /* Disable writeback. */
3641 c
->dst
.type
= OP_NONE
;
3643 case 3: /* lidt/vmmcall */
3644 if (c
->modrm_mod
== 3) {
3645 switch (c
->modrm_rm
) {
3647 rc
= kvm_fix_hypercall(ctxt
->vcpu
);
3650 goto cannot_emulate
;
3653 rc
= read_descriptor(ctxt
, ops
, c
->src
.addr
.mem
,
3656 if (rc
!= X86EMUL_CONTINUE
)
3658 realmode_lidt(ctxt
->vcpu
, size
, address
);
3660 /* Disable writeback. */
3661 c
->dst
.type
= OP_NONE
;
3665 c
->dst
.val
= ops
->get_cr(0, ctxt
->vcpu
);
3668 ops
->set_cr(0, (ops
->get_cr(0, ctxt
->vcpu
) & ~0x0eul
) |
3669 (c
->src
.val
& 0x0f), ctxt
->vcpu
);
3670 c
->dst
.type
= OP_NONE
;
3672 case 5: /* not defined */
3674 rc
= X86EMUL_PROPAGATE_FAULT
;
3677 emulate_invlpg(ctxt
->vcpu
,
3678 linear(ctxt
, c
->src
.addr
.mem
));
3679 /* Disable writeback. */
3680 c
->dst
.type
= OP_NONE
;
3683 goto cannot_emulate
;
3686 case 0x05: /* syscall */
3687 rc
= emulate_syscall(ctxt
, ops
);
3690 emulate_clts(ctxt
->vcpu
);
3692 case 0x09: /* wbinvd */
3693 kvm_emulate_wbinvd(ctxt
->vcpu
);
3695 case 0x08: /* invd */
3696 case 0x0d: /* GrpP (prefetch) */
3697 case 0x18: /* Grp16 (prefetch/nop) */
3699 case 0x20: /* mov cr, reg */
3700 switch (c
->modrm_reg
) {
3705 rc
= X86EMUL_PROPAGATE_FAULT
;
3708 c
->dst
.val
= ops
->get_cr(c
->modrm_reg
, ctxt
->vcpu
);
3710 case 0x21: /* mov from dr to reg */
3711 if ((ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_DE
) &&
3712 (c
->modrm_reg
== 4 || c
->modrm_reg
== 5)) {
3714 rc
= X86EMUL_PROPAGATE_FAULT
;
3717 ops
->get_dr(c
->modrm_reg
, &c
->dst
.val
, ctxt
->vcpu
);
3719 case 0x22: /* mov reg, cr */
3720 if (ops
->set_cr(c
->modrm_reg
, c
->src
.val
, ctxt
->vcpu
)) {
3721 emulate_gp(ctxt
, 0);
3722 rc
= X86EMUL_PROPAGATE_FAULT
;
3725 c
->dst
.type
= OP_NONE
;
3727 case 0x23: /* mov from reg to dr */
3728 if ((ops
->get_cr(4, ctxt
->vcpu
) & X86_CR4_DE
) &&
3729 (c
->modrm_reg
== 4 || c
->modrm_reg
== 5)) {
3731 rc
= X86EMUL_PROPAGATE_FAULT
;
3735 if (ops
->set_dr(c
->modrm_reg
, c
->src
.val
&
3736 ((ctxt
->mode
== X86EMUL_MODE_PROT64
) ?
3737 ~0ULL : ~0U), ctxt
->vcpu
) < 0) {
3738 /* #UD condition is already handled by the code above */
3739 emulate_gp(ctxt
, 0);
3740 rc
= X86EMUL_PROPAGATE_FAULT
;
3744 c
->dst
.type
= OP_NONE
; /* no writeback */
3748 msr_data
= (u32
)c
->regs
[VCPU_REGS_RAX
]
3749 | ((u64
)c
->regs
[VCPU_REGS_RDX
] << 32);
3750 if (ops
->set_msr(ctxt
->vcpu
, c
->regs
[VCPU_REGS_RCX
], msr_data
)) {
3751 emulate_gp(ctxt
, 0);
3752 rc
= X86EMUL_PROPAGATE_FAULT
;
3755 rc
= X86EMUL_CONTINUE
;
3759 if (ops
->get_msr(ctxt
->vcpu
, c
->regs
[VCPU_REGS_RCX
], &msr_data
)) {
3760 emulate_gp(ctxt
, 0);
3761 rc
= X86EMUL_PROPAGATE_FAULT
;
3764 c
->regs
[VCPU_REGS_RAX
] = (u32
)msr_data
;
3765 c
->regs
[VCPU_REGS_RDX
] = msr_data
>> 32;
3767 rc
= X86EMUL_CONTINUE
;
3769 case 0x34: /* sysenter */
3770 rc
= emulate_sysenter(ctxt
, ops
);
3772 case 0x35: /* sysexit */
3773 rc
= emulate_sysexit(ctxt
, ops
);
3775 case 0x40 ... 0x4f: /* cmov */
3776 c
->dst
.val
= c
->dst
.orig_val
= c
->src
.val
;
3777 if (!test_cc(c
->b
, ctxt
->eflags
))
3778 c
->dst
.type
= OP_NONE
; /* no writeback */
3780 case 0x80 ... 0x8f: /* jnz rel, etc*/
3781 if (test_cc(c
->b
, ctxt
->eflags
))
3782 jmp_rel(c
, c
->src
.val
);
3784 case 0x90 ... 0x9f: /* setcc r/m8 */
3785 c
->dst
.val
= test_cc(c
->b
, ctxt
->eflags
);
3787 case 0xa0: /* push fs */
3788 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_FS
);
3790 case 0xa1: /* pop fs */
3791 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_FS
);
3795 c
->dst
.type
= OP_NONE
;
3796 /* only subword offset */
3797 c
->src
.val
&= (c
->dst
.bytes
<< 3) - 1;
3798 emulate_2op_SrcV_nobyte("bt", c
->src
, c
->dst
, ctxt
->eflags
);
3800 case 0xa4: /* shld imm8, r, r/m */
3801 case 0xa5: /* shld cl, r, r/m */
3802 emulate_2op_cl("shld", c
->src2
, c
->src
, c
->dst
, ctxt
->eflags
);
3804 case 0xa8: /* push gs */
3805 emulate_push_sreg(ctxt
, ops
, VCPU_SREG_GS
);
3807 case 0xa9: /* pop gs */
3808 rc
= emulate_pop_sreg(ctxt
, ops
, VCPU_SREG_GS
);
3812 emulate_2op_SrcV_nobyte("bts", c
->src
, c
->dst
, ctxt
->eflags
);
3814 case 0xac: /* shrd imm8, r, r/m */
3815 case 0xad: /* shrd cl, r, r/m */
3816 emulate_2op_cl("shrd", c
->src2
, c
->src
, c
->dst
, ctxt
->eflags
);
3818 case 0xae: /* clflush */
3820 case 0xb0 ... 0xb1: /* cmpxchg */
3822 * Save real source value, then compare EAX against
3825 c
->src
.orig_val
= c
->src
.val
;
3826 c
->src
.val
= c
->regs
[VCPU_REGS_RAX
];
3827 emulate_2op_SrcV("cmp", c
->src
, c
->dst
, ctxt
->eflags
);
3828 if (ctxt
->eflags
& EFLG_ZF
) {
3829 /* Success: write back to memory. */
3830 c
->dst
.val
= c
->src
.orig_val
;
3832 /* Failure: write the value we saw to EAX. */
3833 c
->dst
.type
= OP_REG
;
3834 c
->dst
.addr
.reg
= (unsigned long *)&c
->regs
[VCPU_REGS_RAX
];
3837 case 0xb2: /* lss */
3838 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_SS
);
3842 emulate_2op_SrcV_nobyte("btr", c
->src
, c
->dst
, ctxt
->eflags
);
3844 case 0xb4: /* lfs */
3845 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_FS
);
3847 case 0xb5: /* lgs */
3848 rc
= emulate_load_segment(ctxt
, ops
, VCPU_SREG_GS
);
3850 case 0xb6 ... 0xb7: /* movzx */
3851 c
->dst
.bytes
= c
->op_bytes
;
3852 c
->dst
.val
= (c
->d
& ByteOp
) ? (u8
) c
->src
.val
3855 case 0xba: /* Grp8 */
3856 switch (c
->modrm_reg
& 3) {
3869 emulate_2op_SrcV_nobyte("btc", c
->src
, c
->dst
, ctxt
->eflags
);
3871 case 0xbc: { /* bsf */
3873 __asm__ ("bsf %2, %0; setz %1"
3874 : "=r"(c
->dst
.val
), "=q"(zf
)
3876 ctxt
->eflags
&= ~X86_EFLAGS_ZF
;
3878 ctxt
->eflags
|= X86_EFLAGS_ZF
;
3879 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3883 case 0xbd: { /* bsr */
3885 __asm__ ("bsr %2, %0; setz %1"
3886 : "=r"(c
->dst
.val
), "=q"(zf
)
3888 ctxt
->eflags
&= ~X86_EFLAGS_ZF
;
3890 ctxt
->eflags
|= X86_EFLAGS_ZF
;
3891 c
->dst
.type
= OP_NONE
; /* Disable writeback. */
3895 case 0xbe ... 0xbf: /* movsx */
3896 c
->dst
.bytes
= c
->op_bytes
;
3897 c
->dst
.val
= (c
->d
& ByteOp
) ? (s8
) c
->src
.val
:
3900 case 0xc0 ... 0xc1: /* xadd */
3901 emulate_2op_SrcV("add", c
->src
, c
->dst
, ctxt
->eflags
);
3902 /* Write back the register source. */
3903 c
->src
.val
= c
->dst
.orig_val
;
3904 write_register_operand(&c
->src
);
3906 case 0xc3: /* movnti */
3907 c
->dst
.bytes
= c
->op_bytes
;
3908 c
->dst
.val
= (c
->op_bytes
== 4) ? (u32
) c
->src
.val
:
3911 case 0xc7: /* Grp9 (cmpxchg8b) */
3912 rc
= emulate_grp9(ctxt
, ops
);
3915 goto cannot_emulate
;
3918 if (rc
!= X86EMUL_CONTINUE
)